KR102800421B1 - Electric device configured to support high speed interface for expanding neural network - Google Patents

Abstract

An electronic device configured to support a neural network according to the present disclosure includes a neuron array including a plurality of neurons, a row address encoder configured to receive a plurality of spike signals from the plurality of neurons and output a plurality of request signals in response to the received plurality of spike signals, and a row arbiter tree configured to receive the plurality of request signals from the row address encoder and output a plurality of response signals in response to the received plurality of request signals, wherein the row arbiter tree includes a first arbiter configured to arbitrate first and second request signals among the plurality of request signals, a first latch circuit configured to store a state of the first arbiter, a second arbiter configured to arbitrate third and fourth request signals among the plurality of request signals, a second latch circuit configured to store a state of the second arbiter, and a third arbiter configured to transmit a response signal to the first and second arbiters based on information stored in the first and second latch circuits.

Description

{ELECTRIC DEVICE CONFIGURED TO SUPPORT HIGH SPEED INTERFACE FOR EXPANDING NEURAL NETWORK}

The present invention relates to neural networks, and more particularly, to an electronic device configured to support a high-speed interface for neural network expansion.

There is increasing interest in artificial intelligence technology that processes information by applying human thinking, reasoning, and learning processes to electronic devices. For example, research is being conducted on signal processing between neurons or synapses that mimic the human brain. Spike-based neural networks were developed based on a method of learning and inferring based on input spikes. However, in order to mimic high human intelligence, a large number of neurons are required, but there are limitations in integrating a large number of neurons into a single semiconductor chip due to area, power consumption, or process issues.

An object of the present invention is to provide an electronic device configured to support a high-speed interface for neural network extension with improved reliability and improved performance.

An electronic device configured to support a neural network according to one embodiment of the present disclosure comprises: a neuron array including a plurality of neurons; a row address encoder configured to receive a plurality of spike signals from the plurality of neurons and to output a plurality of request signals in response to the received plurality of spike signals; and a row arbiter tree configured to receive the plurality of request signals from the row address encoder and to output a plurality of response signals in response to the received plurality of request signals, wherein the row arbiter tree comprises: a first arbiter configured to arbitrate first and second request signals among the plurality of request signals; a first latch circuit configured to store a state of the first arbiter; a second arbiter configured to arbitrate third and fourth request signals among the plurality of request signals; a second latch circuit configured to store a state of the second arbiter; and a third arbiter configured to transmit a response signal to the first and second arbiters based on information stored in the first and second latch circuits.

In one embodiment, the row address encoder: generates the first request signal in response to a spike signal received from neurons located in a first row among the plurality of neurons, among the plurality of spike signals; generates the second request signal in response to a spike signal received from neurons located in a second row among the plurality of neurons, among the plurality of spike signals; generates the third request signal in response to a spike signal received from neurons located in a third row among the plurality of neurons, among the plurality of spike signals; and generates the fourth request signal in response to a spike signal received from neurons located in a fourth row among the plurality of neurons, among the plurality of spike signals.

In one embodiment, the row address encoder is configured to, in response to the plurality of response signals, output a row signal indicating information about a row of neurons among the plurality of neurons corresponding to the plurality of response signals.

In one embodiment, the first arbiter is further configured to receive one of the first and second request signals before receiving the first request signal among the first and second request signals and outputting a first response signal to the first request signal among the plurality of response signals, and the second arbiter is further configured to receive one of the third and fourth request signals before receiving the third request signal among the third and fourth request signals and outputting a third response signal corresponding to the third request signal among the plurality of response signals.

In one embodiment, the circuit further comprises a third latch circuit configured to store a state of the third arbiter.

In one embodiment, the row address encoder is further configured to sequentially output the plurality of spike signals received from the plurality of neurons as row signals in response to the plurality of response signals.

In one embodiment, the apparatus further comprises a column address encoder configured to receive the plurality of spike signals from the plurality of neurons and to output a plurality of request signals in response to the received plurality of spike signals; and a column arbiter tree configured to receive the plurality of request signals from the column address encoder and to output a plurality of response signals in response to the received plurality of request signals from the column address encoder.

In one embodiment, the column address encoder is configured to, in response to the plurality of response signals received from the column arbiter tree, output a column signal indicating information about a column of neurons among the plurality of neurons corresponding to the plurality of response signals.

According to one embodiment of the present disclosure, an electronic device configured to support a neural network includes: a neuron array including a plurality of neurons; and an interface circuit configured to transmit a plurality of spike signals generated from the plurality of neurons in parallel to an external device, wherein the interface circuit includes: a row arbiter tree configured to arbitrate a plurality of request signals corresponding to the plurality of spike signals, wherein the row arbiter tree includes: a first arbiter configured to return a first token in response to first and second request signals among the plurality of request signals; and a second arbiter configured to return a second token in response to third and fourth request signals among the plurality of request signals, wherein a spike signal corresponding to a request signal for which the first token is returned among the first and second request signals is transmitted to the external device through a first path, and a spike signal corresponding to a request signal for which the second token is returned among the third and fourth request signals is transmitted to the external device through a second path implemented in parallel with the first path.

In one embodiment, the interface circuit further comprises a row address encoder configured to transmit the plurality of spike signals in parallel to the external device through the first and second paths based on arbitration of the row arbiter tree.

In one embodiment, the row arbiter tree further comprises: a first latch circuit configured to store a state of the first arbiter; and a second latch circuit configured to store a state of the second arbiter.

In one embodiment, the row address encoder is further configured to identify a return order of the first and second tokens based on information stored in the first and second latch circuits.

According to the present disclosure, an electronic device is provided that is configured to support a high-speed interface for neural network extension with improved reliability and improved performance.

FIG. 1 is a diagram for explaining the operation of a neural network according to one embodiment of the present disclosure.
FIG. 2 is a block diagram showing an electronic device based on the Address-Event-Representative (AER) protocol that implements the neural network of FIG. 1.
Figure 3 is a block diagram showing the structure of the row arbiter tree of Figure 2.
Figure 4 is a block diagram showing the structure of the row arbiter tree of Figure 2.
FIG. 5 is a diagram for explaining the multi-token and multi-path used in the row arbiter tree of FIG. 3.
Figure 6 is a block diagram showing the structure of a row arbiter tree using multi-tokens and multi-paths of Figure 5.
FIG. 7 is a block diagram showing an electronic device according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to such an extent that a person skilled in the art can easily practice the present disclosure.

Hereinafter, with reference to the attached drawings, preferred embodiments of the present disclosure will be described in more detail. In order to facilitate an overall understanding in describing the present disclosure, similar reference numerals are used for similar components in the drawings, and redundant descriptions of similar components are omitted.

The modules in the drawings or detailed description below may be connected to other components other than those depicted in the drawings or described in the detailed description. The connection between the modules or components may be direct or indirect, respectively. The connection between the modules or components may be a connection by communication or a physical connection, respectively.

Components described with reference to terms such as unit, module, layer, etc. used in the detailed description may be implemented in the form of software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, MEMS (Micro Electro Mechanical Systems), passive components, or a combination thereof.

According to the present disclosure, an electronic device configured to drive a spike-based neural network may include a plurality of neurons. Each of the plurality of neurons may generate a spike signal, and the generated spike signals may be transmitted to the outside. At this time, the electronic device according to the present disclosure may prevent a decrease in the transmission speed of the plurality of spike signals generated from the plurality of neurons. For example, the neural network may include a plurality of neurons connected in parallel with a complex structure. Accordingly, the plurality of spike signals generated from the plurality of neurons may also be continuously generated in a parallel form. In a conventional neural network-based electronic device, an AER (Address-Event-Representative) circuit is used to serialize the plurality of spike signals and transmit the serialized signals to the outside. In this case, a decrease in the transmission speed occurs because the plurality of spike signals generated in a parallel form are converted to a serial form. On the other hand, the electronic device according to the present disclosure may provide a high-speed AER interface technique for expanding neurons between neural networks while minimizing distortion related to the transmission of the plurality of spikes.

FIG. 1 is a diagram for explaining the operation of a neural network according to an embodiment of the present disclosure. Referring to FIG. 1, a neural network (NN) may include a first layer (L1), a second layer (L2), and synapses (S). In one embodiment, the neural network (NN) may be a spiking neural network based on spike signals. However, the scope of the present disclosure is not limited thereto, and the neural network (NN) may be configured to support various neural networks or machine learning.

The first layer (L1) may include a plurality of axons (A1 to An), and the second layer (L2) may include a plurality of neurons (N1 to Nm). Synapses (S) may be configured to connect the plurality of axons (A1 to An) and the plurality of neurons (N1 to Nm). Here, each of m and n may be any natural number, and m and n may be the same number or different numbers.

Each of the axons (A1 to An) included in the first layer (L1) can output a spike signal. The synapses (S) can transmit spike signals with weighted synaptic weights to the neurons (N1 to Nm) included in the second layer (L2) based on the output spike signals. Even if a spike signal is output from one axon, the spike signal transmitted from each of the synapses (S) to the neurons (N1 to Nm) can vary depending on the synaptic weight, which is the connection strength of each of the synapses (S). For example, when the synaptic weight of the first synapse is greater than the synaptic weight of the second synapse, the neuron connected to the first synapse can receive a spike signal with a larger value than the neuron connected to the second synapse.

Each of the neurons (N1 to Nm) included in the second layer (L2) can receive a spike signal transmitted from the synapses (S). Each of the neurons (N1 to Nm) receiving the spike signal can output a neuron spike based on the received spike signal. For example, when the accumulated value of the spike signal received by the second neuron (N2) becomes greater than a threshold value, the second neuron (N2) can output a neuron spike.

For example, as illustrated in FIG. 1, when the second axon (A2) outputs a spike signal, the synapses (S) connected to the second axon (A2) can transmit the spike signal to the neurons (N1 to Nm). The transmitted spike signal may vary depending on the synaptic weight of each of the synapses (S) connected to the second axon (A2). When a spike signal is transmitted to the second neuron (N2) from the synapse (S22) connecting the second axon (A2) and the second neuron (N2), and the accumulated spike signal value of the second neuron (N2) becomes greater than a threshold value according to the transmitted spike signal, the second neuron (N2) can output a neuron spike.

As illustrated in FIG. 1, in the embodiments of the present disclosure, a layer including axons (A1 to An) may be a layer prior to a layer including neurons (N1 to Nm). Additionally, a layer including neurons (N1 to N) may be a layer subsequent to a layer including axons (A1 to An). Accordingly, spike signals output from axons (A1 to An) are transmitted to neurons (N1 to Nm) of the next layer according to weighted synaptic weights, and the neurons (N1 to Nm) can output neuron spikes based on the transmitted spike signals.

Although not illustrated in FIG. 1, spike signals may be transmitted to neurons in the next layer based on the output of the neuron spike in the second layer (L2). For example, when a spike signal is transmitted from the second layer (L2) to the third layer, axons in the second layer (L2) may output spike signals based on the output of the neuron spike, and spike signals with synaptic weights may be transmitted to neurons in the third layer based on the output spike signals. Neurons in the third layer may output neuron spikes when the accumulated value of the transmitted spike signals is greater than a threshold value. That is, one layer may include both axons and neurons, or may include either axons or neurons.

FIG. 2 is a block diagram showing an electronic device based on the Address-Event-Representative (AER) protocol that implements the neural network of FIG. 1. Referring to FIGS. 1 and 2, the electronic device (100) may include a neuron array (110), a row address encoder (120), a row arbiter tree (130), a column address encoder (140), and a column arbiter tree (150).

In one embodiment, the electronic device (100) of FIG. 2 may be configured to support a communication structure based on the Address-Event-Representative (AER) protocol. The AER protocol is a point-to-point protocol that can asynchronously transmit spike information of a neuron in which a spike has been fired to another neuron. By transmitting information about a spike fired from one neuron to another neuron, synaptic connections by the synapses (S) of FIG. 1 can be implemented. The transmitted information may include information about the timing at which the spike was fired and the address of the neuron in which the spike was fired.

In one embodiment, in the electronic device (100) of FIG. 2, the remaining components (e.g., row address encoder (120), row arbiter tree (130), column address encoder (140), and column arbiter tree (150)) excluding the neuron array (110) may refer to an interface circuit or AER interface circuit configured to transmit spike signals generated in the neuron array (110) to the outside of the electronic device (100) or to another electronic device.

The neuron array (110) may include a plurality of neurons (N11 to N44). In order to improve the integration of the electronic device (100), the plurality of neurons (N11 to N44) may be arranged in the row direction and the column direction, respectively. For the simplicity of the drawing, the plurality of neurons (N11 to N4) of FIG. 2 are illustrated as being arranged in four rows and four columns, but the scope of the present disclosure is not limited thereto. The number of neurons included in the neuron array (11), the number of rows in which the neurons are arranged, and the number of columns may be increased or decreased. In one embodiment, the neuron array (110) may have various arrangements different from the arrangement illustrated in FIG. 2.

Each of the plurality of neurons (N11 to N44) included in the neuron array (110) may be a neuron (for example, one of N1 to Nm) of FIG. 1 or one of the axons (A1 to An) of FIG. 1, and may output a spike signal. The process of outputting the spike signal may be implemented by outputting the address of the neuron block in which the spike is fired. The output address may include an address for a row and an address for a column. In one embodiment, the address for a row may be processed sequentially with priority over the address for a column. Alternatively, the address for a column may be processed sequentially with priority over the address for a row. Alternatively, the address for a row and the address for a column may be processed simultaneously or in parallel.

For example, a plurality of neurons (N11 to N44) included in a neuron array (110) can output spike signals. Spike signals output from the plurality of neurons (N11 to N44) can be provided to a row address encoder (120) and a column address encoder (140). The row address encoder (120) can sequentially process spike signals output from the plurality of neurons (N11 to N44) using a row arbiter tree (130) to output a row signal (SIG_row). The column address encoder (140) can sequentially process spike signals output from the plurality of neurons (N11 to N44) using a column arbiter tree (150) to output a column signal (SIG_col).

For example, the row address encoder (120) can output a first request signal in response to a spike signal fired from neurons (e.g., N11, N12, N13, N14) located in a first row among a plurality of neurons (N11 to N44), can output a second request signal in response to a spike signal fired from neurons (e.g., N21, N22, N23, N24) located in a second row among a plurality of neurons (N11 to N44), can output a third request signal in response to a spike signal fired from neurons (e.g., N31, N32, N33, N34) located in a third row among a plurality of neurons (N11 to N44), and can output a fourth request signal in response to a spike signal fired from neurons (e.g., N41, N42, N43, N44) located in a fourth row among a plurality of neurons (N11 to N44). can. The row address encoder (120) can provide the generated request signal to the row arbiter tree (130), and the row arbiter tree (130) can provide a response signal corresponding to the request signal to the row address encoder (120) in response to the request signal. The row address encoder (120) can output a row signal (SIG_row) based on information about the row of neurons corresponding to the received request signal.

Similarly, the column address encoder (140) can output a first request signal in response to a spike signal fired from neurons located in a first column (e.g., N11, N21, N31, N41) among the plurality of neurons (N11 to N44), can output a second request signal in response to a spike signal fired from neurons located in a second column (e.g., N12, N22, N32, N42) among the plurality of neurons (N11 to N44), can output a third request signal in response to a spike signal fired from neurons located in a third column (e.g., N13, N23, N33, N43) among the plurality of neurons (N11 to N44), and can output a fourth request signal in response to a spike signal fired from neurons located in a fourth column (e.g., N14, N24, N34, N44) among the plurality of neurons (N11 to N44). The column address encoder (140) can provide the generated request signal to the column arbiter tree (150), and the column arbiter tree (150) can provide a response signal corresponding to the request signal to the column small encoder (14) in response to the request signal. The column address encoder (140) can output a column signal (SIG_col) based on information about the columns of neurons corresponding to the received request signal.

In one embodiment, a neuron or a position of a neuron that outputs a spike signal can be determined based on a row signal (SIG_row) and a column signal (SIG_col), and a spike signal with a weight reflected thereon can be provided to another neuron (e.g., other neurons included in the electronic device (100) or neurons included in another electronic device) through a synapse (S) corresponding to the determined neuron or position of the neuron.

In one embodiment, the row arbiter tree (130) may play a role of arbitrating spike signals so that the row signal (SIG_row) is output according to the output order of the spike signals provided from the row address encoder (120). The column arbiter tree (150) may play a role of arbitrating spike signals so that the column signal (SIG_col) is output according to the output order of the spike signals provided from the column address encoder (140). In order to concisely describe the embodiments of the present disclosure below, the structure of the row arbiter tree (130) will be primarily described. In one embodiment, the structures of the row arbiter tree (130) and the column arbiter tree (150) may be similar to each other.

FIG. 3 is a block diagram showing the structure of the row arbiter tree of FIG. 2. For the sake of simplicity of the drawing and convenience of explanation, unnecessary components (e.g., row address encoders) for explaining the row arbiter tree are omitted, and it is assumed that the row arbiter tree directly receives a request for outputting a spike signal from the neurons (N11 to N41) and directly provides a response to the request. However, the scope of the present disclosure is not limited thereto, and the spike signals output from the neurons (N11 to N41) may be provided to the row address encoder (120), and the row address encoder (120) may provide a request for outputting spike signals to the row arbiter tree and receive a response from the row arbiter tree.

The row arbiter tree (10) can be configured to receive requests from the first to fourth neurons (N11, N21, N31, N41) and output corresponding responses according to the reception order or firing order of spike signals.

For example, the row arbiter tree (10) may include first to third arbiters (ABT1 to ABT3). The first arbiter (ABT1) may be connected to the first and second neurons (N11, N21), the second arbiter (ABT2) may be connected to the third and fourth neurons (N31, N41), and the third arbiter (ABT3) may be connected to the first and second arbiters (ABT1, ABT2).

Each of the first to third arbiters (ABT1, ABT2, ABT3) may be configured to mediate operation priorities for corresponding components according to the reception order or generation order of the received signals. For example, the first arbiter (ABT1) may receive response signals from the first and second neurons (N11, N21). The first arbiter (ABT1) may be configured to provide operation priorities to a neuron that fires first among the first and second neurons (N11, N21). The second arbiter (ABT2) may be configured to provide operation priorities to a neuron that fires first among the third and fourth neurons (N31, N41). The third arbiter (ABT3) may be configured to provide operation priorities to an arbiter that outputs a spike signal first among the first and second arbiters (ABT1, ABT2).

That is, by connecting the first to third arbiters (ABT1, ABT2, ABT3) in a tree structure, the operation priority (e.g., the output order of spike signals fired from the first to fourth neurons (N11 to N41)) for the first to fourth neurons (N11 to N412) can be mediated.

As a more detailed example, it is assumed that the first neuron (N11) among the first to fourth neurons (N11 to N41) fires first. In this case, a request signal corresponding to the first neuron (N11) can be provided to the first arbiter (ABT1). In response to the request signal corresponding to the first neuron (N11), the first arbiter (ABT1) can store information indicating that the first neuron (N11) fired a spike signal (hereinafter, referred to as “the position of the first neuron (N11)” for convenience of explanation) and output the request signal. In one embodiment, the configuration in which the first arbiter (ABT1) stores information on the position of the first neuron (N11) can be implemented by maintaining a path along which the first arbiter (ABT1) receives a response signal and transmits the response signal so as to correspond to the first neuron (N11).

A request signal output from the first arbiter (ABT1) is provided to the third arbiter (ABT3). The third arbiter (ABT3) can return a token (TK) in response to the request signal received from the first arbiter (ABT1). For example, the return of the token (TK) can be implemented by the third arbiter (ABT3) transmitting a response signal including information about the token (TK) to the first arbiter (ABT1). The first arbiter (ABT1) can provide the received response signal to the first neuron (N11) in response to the response signal received from the third arbiter (ABT3). The first neuron (N11) can provide the fired spike signal to the outside or to another neuron in response to the response signal received from the first arbiter (ABT1). Alternatively, in response to the response signal, the row address encoder (120) may output a corresponding row signal (SIG_row).

As described above, the row arbiter tree (10) can mediate the operation priority (e.g., the output order of spike signals fired from the first to fourth neurons (N11 to N41)) for the first to fourth neurons (N11 to N412). However, when the number of neurons corresponding to the row arbiter tree (10) increases (i.e., when the number of request signals input to the row arbiter tree (10) increases), the number of arbiters and the number of arbiter stages included in the row arbiter tree (10) also increase. In this case, the time for a response signal (or token) to be returned to one request signal may increase. In addition, until a response signal (or token) to one request signal is returned, specific neurons must wait in a specific state (e.g., a reset state), and request signals corresponding to other neurons also cannot be provided to the row arbiter tree (10).

That is, according to the structure of the row arbiter tree (10) of Fig. 3, request signals for other neurons cannot be processed until a response signal corresponding to one request signal is returned, and thus the overall signal processing time increases. In addition, if spike signals are fired from other neurons while a request signal for a specific neuron is being processed, the firing order of other neurons cannot be maintained, and therefore, distortion of signal processing occurs.

FIG. 4 is a block diagram showing the structure of the row arbiter tree of FIG. 2. Referring to FIG. 2 and FIG. 4, the row arbiter tree (130) may include first to third arbiters (ABT1, ABT2, ABT3) and first to third latches (LAT1, LAT2, LAT3).

For the sake of brevity of the drawing and convenience of explanation, unnecessary components (e.g., row address encoders) for describing the row arbiter tree are omitted, and it is assumed that the row arbiter tree directly receives a request for outputting a spike signal from the neurons (N11 to N41) and directly provides a response to the request. However, the scope of the present disclosure is not limited thereto, and the spike signals output from the neurons (N11 to N41) may be provided to the row address encoder (120), and the row address encoder (120) may provide a request for outputting spike signals to the row arbiter tree and receive a response from the row arbiter tree.

The row arbiter tree (10) can be configured to receive requests from the first to fourth neurons (N11, N21, N31, N41) and output corresponding responses according to the reception order or firing order of spike signals.

For example, the row arbiter tree (10) may include first to third arbiters (ABT1 to ABT3). The first arbiter (ABT1) may be connected to the first and second neurons (N11, N21), and the second arbiter (ABT2) may be connected to the third and fourth neurons (N31, N41).

In one embodiment, unlike the row arbiter tree (10) of FIG. 3, in the row arbiter tree (130) of FIG. 4, the first arbiter (ABT1) can exchange a request signal and a response signal with the first latch (LAT1), and the second arbiter (ABT2) can exchange a request signal and a response signal with the second latch (LAT2). The third arbiter (ABT3) can be connected to the first and second latches (LAT1, LAT2), and can exchange a request signal and a response signal with the third latch (LAT3). That is, in the tree structure of the arbiters (ABT1, ABT2, ABT3) included in the row arbiter tree (130) of FIG. 4, the first to third latches (LAT1, LAT2, LAT3) can be added.

The first to third latches (LAT1, LAT2, LAT3) may be configured to store the states of the first to third arbiters (ABT1, ABT2, ABT3). For example, the first latch (LAT1) may be configured to store the state of the first arbiter (ABT1), the second latch (LAT2) may be configured to store the state of the second arbiter (ABT2), and the third latch (LAT3) may be configured to store the state of the third arbiter (ABT3). In this case, unlike the row arbiter tree (10) of FIG. 3, in the row arbiter tree (130) of FIG. 4, each of the first to third arbiters (ABT1, ABT2, ABT3) does not need to store its own state (i.e., the position of the neuron from which the request signal is received), and can receive a response signal for another neuron before a response signal is received in a subsequent stage.

As a more detailed example, it is assumed that a spike signal is fired from the first neuron (N11). In this case, a request signal corresponding to the first neuron (N11) can be transmitted to the first arbiter (ABT1). The first arbiter (ABT1) can store information about the position of the first neuron (N11) in the first latch (LAT1) in response to the request signal corresponding to the first neuron (N11). Thereafter, the first arbiter (ABT1) switches to a state in which it can receive the request signal corresponding to the second neuron (N21). That is, the first arbiter (ABT1) can receive the request signal corresponding to the second neuron (N21) without receiving or outputting a response signal to the request signal corresponding to the first neuron (N11) by storing the current state (i.e., information about the position of the first neuron (N11)) in the first latch (LAT1).

A request signal may be provided to the third arbiter (ABT3) based on the information stored in the first latch (LAT1). The third arbiter (ABT3) may store the state of the third arbiter (ABT3) in the third latch (LAT3) in response to the request signal provided from the first latch (LAT1). In one embodiment, when the third arbiter (ABT3) is a final stage, the third arbiter (ABT3) may provide a response signal to the first latch (LAT1) in response to the request signal. The first latch (LAT1) may provide the response signal to the first neuron (N11) based on the stored state information of the first arbiter (ABT1) in response to the response signal received from the third arbiter (ABT3).

As described above, when the first latch (LAT1) is configured to store the state of the first arbiter (ABT1), the second latch (LAT2) is configured to store the state of the second arbiter (ABT2), and the third latch (LAT3) is configured to store the state of the third arbiter (ABT3), each of the first to third arbiters (ABT1, ABT2, ABT3) can only determine the order of input request signals and receive request signals from other neurons before receiving an additional response signal. In addition, the plurality of neurons (N11, N21, N31, N41) do not need to wait in a reset state until receiving a response signal from the row arbiter tree (130). That is, through the structure of the row arbiter tree (130) of Fig. 4, parallel processing of spike signals fired from multiple neurons (N11, N21, N31, N41) is possible, and the firing order of spike signals fired from multiple neurons (N11, N21, N31, N41) can be normally identified.

FIG. 5 is a diagram for explaining the multi-token and multi-path used in the row arbiter tree of FIG. 3. FIG. 6 is a block diagram showing the structure of the row arbiter tree using the multi-token and multi-path of FIG. 5.

Referring to FIGS. 2, 4, 5, and 6, the row arbiter tree (130-1) can mediate operations for multiple neurons (N11 to N41) using multi-tokens and multi-paths.

For example, the row arbiter tree (10) described with reference to FIG. 3 arbitrates actions for multiple neurons (N11 to N41) using one token (TK). In this case, the neuron that fires first among the multiple neurons (N11 to N41) uses the entire structure of the row arbiter tree (10) (e.g., winner takes all).

On the other hand, as shown in FIGS. 5 and 6, when the row arbiter tree (130-1) uses multi-tokens and multi-paths, it can simultaneously or in parallel arbitrate not only the action for the initially fired neuron, but also the actions for neurons fired at later points in time.

For example, as illustrated in FIG. 6, the row arbiter tree (130-1) may include first to third arbiters (ABT1, ABT2, ABT3) and first to third latches (LAT1, LAT2, LAT3). The first arbiter (ABT1) may be configured to arbitrate spike signals fired from the first and second neurons (N11, N21). The second arbiter (ABT2) may be configured to arbitrate spike signals fired from the third and fourth neurons (N31, N41). The third arbiter (ABT3) may be configured to arbitrate outputs from the first and second arbiters (ABT1, ABT2).

Unlike the structure of the row arbiter tree (10) of Fig. 2, in the row arbiter tree (130-1) of Fig. 6, token return (TK) can be performed for each of the first to third arbiters (ABT1, ABT2, ABT3). For example, the first arbiter (ABT1) can directly perform token (TK) return in response to a request signal for the first and second neurons (N11, N21). In this case, the first arbiter (ABT1) can receive a request signal for other neurons without receiving a response signal from a subsequent stage (e.g., a third arbiter (ABT3). In one embodiment, the state (or operation result) of the first arbiter (ABT1) can be stored in a plurality of latch circuits (LAT1 to LAT3). The state of the first arbiter (ABT1) stored in the plurality of latch circuits (LAT1 to LAT3) can be transferred to the next stage (e.g., a third arbiter (ABT3)). The next stage (e.g., the third arbiter (ABT3)) can perform token (TK) return based on the information stored in the plurality of latch circuits (LAT1 to LAT3). That is, the row arbiter tree (130-1) uses a plurality of tokens (TK1 to TKn) (or individual tokens) for each of the plurality of arbiters (ABT1 to ABT3), thereby performing a row arbiter tree (130-1). In the arbiter tree (130-1), a plurality of request signals can be processed simultaneously or in parallel. In addition, the return order of the plurality of tokens (TK1 to TKn) can be determined or identified based on the information stored in the plurality of latch circuits (LAT1 to LAT3). In one embodiment, the row address encoder (120) can identify the return order (i.e., the occurrence order or transmission order of the corresponding spike signals) of the plurality of tokens (TK1 to TKn) based on the information stored in the plurality of latch circuits (LAT1 to LAT3).

In one embodiment, a row arbiter tree (130-1) using a plurality of tokens (TK1 to TKn) described above can manage a plurality of paths (e.g., a first path, a second path, a third path). In one embodiment, each of the plurality of paths (e.g., the first path, the second path, and the third path) can mean a path through which a request signal (Req), a response signal (Ack), and an address (e.g., an address corresponding to a location of a corresponding neuron) are transmitted and received.

A plurality of paths (e.g., a first path, a second path, and a third path) may correspond to a plurality of tokens (TK1 to TKn), and spike signals fired from the plurality of neurons (N11 to N41) may be transmitted to the outside through the plurality of paths (e.g., a first path, a second path, and a third path) according to the spike signal firing order of the plurality of neurons (N11 to N41) based on the state information stored in the plurality of latches (LAT1 to LAT3). That is, since the electronic device (100) according to the present disclosure can transmit and receive spike signals through a plurality of paths, not a single transmission path, the transmission speed of the spike signal may be improved.

In one embodiment, although not shown in the drawing, the number of the plurality of tokens and the number of the plurality of paths may be equal to each other. Or, the number of the plurality of tokens may be greater than the number of the plurality of paths. In this case, each of the plurality of paths may be configured to output a spike signal corresponding to at least one or more tokens.

FIG. 7 is a block diagram showing an electronic device according to an embodiment of the present disclosure. Referring to FIG. 7, the electronic device (1000) may include a neural processor (1100), a processor (1200), a random access memory (RAM) (1300), and a storage device (1400). The neural processor (1100) may perform inference or prediction operations based on various neural network algorithms under the control of the processor (1200). For example, the neural processor (1100) may include a calculation unit or an accelerator for processing operations based on a neural network. The neural processor (1100) may receive various types of input data from the RAM (1300) or the storage device (1400), and may perform neural learning or infer various data based on the received input data. In one embodiment, the neural processor (1100) may be configured to drive a neural network (NN) as described with reference to FIGS. 1 to 6 or may include an electronic device (100) as described with reference to FIGS. 1 to 6. Alternatively, the neural processor (1100) may include a plurality of electronic devices (100) as described with reference to FIGS. 1 to 6, and each of the electronic devices included in the neural processor (1100) may transmit and receive signals based on the operations described with reference to FIGS. 1 to 6.

The processor (1200) can perform various operations required for the operation of the electronic device (1000). For example, the processor (1200) can execute firmware, software, or program codes loaded into the RAM (1300). The processor (1200) can control the electronic device (1000) by executing the firmware, software, or program codes loaded into the RAM (1300). The processor (1200) can store the results of the executions in the RAM (1300) or a storage device (1400).

RAM (1300) can store data to be processed by the neural processor (1100) or processor (1200), various program codes or instructions that can be executed by the neural processor (1100) or processor (1200), or data processed by the neural processor (1100) or processor (1200). RAM (1300) can include SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

The storage device (1400) can store data or information required for the neural processor (1100) or the processor (1200) to perform operations. The storage device (1400) can store data processed by the neural processor (1100) or the processor (1200). The storage device (1400) can store software, firmware, program codes, or instructions that can be executed by the neural processor (1100) or the processor (1200). The storage device (1400) can be a volatile memory such as a DRAM, an SRAM, or a nonvolatile memory such as a flash memory.

As described above, the neural network performs learning and inference based on spike signals. However, in order to simulate the advanced intelligence of humans, a large number of neurons are required, and accordingly, the performance of artificial intelligence based on the neural network can be improved by extending the neural network through an external interface. As an example, the neural network can be extended using the Address-Event-Representative (AER) interface. Since the AER interface processes spike signals based on events, it consumes little power, and since it serializes and transmits spike signals, it can use minimal hardware resources. However, since the AER interface serializes and outputs spike signals that occur in parallel on the neural network, there is a problem of distorting information about the occurrence time or occurrence order of spike signals.

According to the present disclosure, an electronic device configured to support a high-speed interface for neural network expansion can be configured to maximize a speed of transmitting signals to the outside while minimizing distortion of the generation time or generation order of spike signals generated from a plurality of neurons. According to the present disclosure, an arbiter tree included in the electronic device can minimize signal transmission delay through a separate latch, secure a plurality of tokens indicating the generation order of spike signals to maintain information about the generation order of spike signals, and secure a plurality of signal transmission paths for transmitting and receiving signals to the outside, thereby improving a signal transmission speed.

The above-described contents are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that are simply designed or can be easily changed. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the claims described below as well as the equivalents of the claims of this disclosure.

NN: Neural Network
A1~An: Multiple axons
N1~Nm: Multiple neurons
L1: First layer
L2: Second layer
S: Synapse
100: Electronic devices
110: Neuron Array
120: Row address encoder
130: Row Arbiter Tree
140: Column address encoder
150: Ten Arbiter Trees

Claims (12)

In an electronic device configured to support a neural network,
A neuron array comprising multiple neurons;
A row address encoder configured to receive a plurality of spike signals from the plurality of neurons and output a plurality of request signals in response to the received plurality of spike signals; and
A row arbiter tree configured to receive the plurality of request signals from the row address encoder and to arbitrate the received plurality of request signals,
The above row arbiter tree is:
A first arbiter configured to return a first token in response to first and second request signals among the plurality of request signals;
A first latch circuit configured to store the state of the first arbiter;
A second arbiter configured to return a second token in response to third and fourth request signals among the plurality of request signals;
a second latch circuit configured to store the state of the second arbiter; and
An electronic device comprising a third arbiter configured to return a third token to the first and second arbiters based on information stored in the first and second latch circuits.
In paragraph 1,
The above row address encoder is:
Generating the first request signal in response to a spike signal received from neurons located in a first row among the plurality of neurons, among the plurality of spike signals;
Generating the second request signal in response to a spike signal received from neurons located in a second row among the plurality of neurons, among the plurality of spike signals;
Generating the third request signal in response to a spike signal received from neurons located in a third row among the plurality of neurons among the plurality of spike signals;
An electronic device that generates the fourth request signal in response to a spike signal received from neurons located in a fourth row among the plurality of neurons among the plurality of spike signals.
In paragraph 1,
An electronic device wherein the row address encoder is configured to output, in response to the first and second tokens, a row signal indicating information about a row of neurons among the plurality of neurons corresponding to the plurality of response signals.


delete In paragraph 1,
An electronic device further comprising a third latch circuit configured to store a state of the third arbiter.
In paragraph 1,
An electronic device wherein the row address encoder is further configured to sequentially output the plurality of spike signals received from the plurality of neurons as row signals in response to the first and second tokens.
In paragraph 1,
A column address encoder configured to receive the plurality of spike signals from the plurality of neurons and output the plurality of request signals in response to the received plurality of spike signals; and
An electronic device further comprising a column arbiter tree configured to receive the plurality of request signals from the column address encoder and output a plurality of response signals in response to the plurality of request signals received from the column address encoder.
In paragraph 7,
An electronic device wherein the column address encoder is configured to output a column signal indicating information about a column of neurons corresponding to the plurality of response signals among the plurality of neurons, in response to the plurality of response signals received from the column arbiter tree.
delete delete delete In paragraph 1,
An electronic device wherein the above row address encoder is further configured to identify a return order of the first and second tokens based on information stored in the first and second latch circuits.

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