KR102787588B1 - High electron mobility transister with recess thin oxide layer - Google Patents

Abstract

The main purpose of the present invention is to provide a high electron mobility transistor having a recess oxide film and a method for manufacturing the same, which increases surface bonding properties and reduces leakage current by removing an oxide film that naturally occurs in a recess etching process when forming a recess for a gate electrode and artificially forming a more stable oxide film.
In order to achieve the above-described object, a high electron mobility transistor having a recessed oxide film according to one embodiment of the present invention may include a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a fine oxide film layer artificially formed on a surface of a recess for a gate electrode formed by etching on the barrier layer; and a gate electrode formed on the fine oxide film layer.

Description

High electron mobility transistor with recessed oxide layer and its manufacturing method {HIGH ELECTRON MOBILITY TRANSISTER WITH RECESS THIN OXIDE LAYER}

The present invention relates to a high electron mobility transistor having a recessed oxide film and a method for manufacturing the same, and more specifically, to a high electron mobility transistor in which a recessed oxide film is artificially formed when forming a gate electrode of the high electron mobility transistor and a method for manufacturing the same.

Due to the development of ultra-high frequency band wireless communication technology, the use of high-voltage transistors operating in high-speed switching environments or high-voltage environments is increasing. The recently introduced III-V group compound semiconductor transistors are not only suitable for ultra-high frequency band wireless communication because they enable high-speed switching operations compared to conventional silicon-based transistors, but also have the advantage of being usable in high-voltage environments due to the high-voltage characteristics of the material itself, and are thus attracting attention from the industry.

In particular, in the case of a high electron mobility transistor (HEMT) using a group III-V compound semiconductor, the mobility of electrons can be increased by utilizing a two-dimensional electron gas (2DEG) generated at the interface between different materials, making it suitable for wireless communications in the ultra-high frequency band.

Among the materials used in high-electron-mobility transistors using group III-V compound semiconductors, GaN is being utilized as a semiconductor for high-power, high-frequency communications based on its excellent material properties. However, despite its excellent material properties, it faces various problems in terms of reliability and characteristics. Among them, surface traps are a problem caused by the technical limitations of epi growth, and are pointed out as a technical problem that must be solved for the commercialization of GaN transistors.

There are representative methods for improving surface traps, such as wet surface treatment methods using various solutions and dry surface treatment methods using various gas and plasma conditions. Existing methods for improving surface traps generally utilize methods for etching oxide films formed by natural oxidation. However, even after etching the oxide film, the surface is not stable and easily re-oxidized, so existing methods have limitations in the degree of surface improvement.

U.S. Patent Publication No. 2010-0171150 (Published on July 8, 2010)

The present invention has been developed to solve such conventional problems, and its main purpose is to provide a high electron mobility transistor having a recess oxide film and a manufacturing method thereof, which improves surface bonding properties and reduces leakage current by removing an oxide film naturally occurring in a recess etching process when forming a recess for a gate electrode and artificially forming a more stable oxide film.

In order to achieve the above-described object, a high electron mobility transistor having a recessed oxide film according to one embodiment of the present invention may include a substrate, a channel layer formed on the substrate, a barrier layer formed on the channel layer, a fine oxide film layer artificially formed on a surface of a recess for a gate electrode formed by etching on the barrier layer; and a gate electrode formed on the fine oxide film layer.

In addition, it may include a fine oxide film layer artificially formed on the surface of a recess for an ohmic electrode formed by etching on the barrier layer; and a source electrode and a drain electrode formed on the fine oxide film layer.

In addition, the recess for the gate electrode and the recess for the ohmic electrode can be formed simultaneously, and the fine oxide film layer formed on the surface of the recess for the gate electrode and the recess for the ohmic electrode can also be formed simultaneously.

In addition, the fine oxide film layer formed on the surface of the recess for the gate electrode can be formed after removing the oxide film layer naturally occurring in the etching process of the recess for the gate electrode.

In addition, the fine oxide film layer formed on the surface of the recess for the ohmic electrode can be formed after removing the oxide film layer naturally occurring in the etching process of the recess for the ohmic electrode.

Additionally, the fine oxide film layer may include either Ga ₂ O ₃ or Al ₂ O ₃ or both.

A method for manufacturing a high electron mobility transistor having a recessed oxide film according to another embodiment of the present invention may include the steps of: preparing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer; etching and forming a recess for a gate electrode on the barrier layer; removing an oxide film naturally formed on a surface of the recess for the gate electrode in the etching process; artificially forming a fine oxide film layer on the surface of the recess for the gate electrode; and forming a gate electrode on the fine oxide film layer.

In addition, the step of forming the barrier layer may include a step of etching and forming a recess for an ohmic electrode on the barrier layer; a step of removing an oxide film naturally formed on the surface of the recess for the ohmic electrode in the etching process; a step of artificially forming a fine oxide film layer on the surface of the recess for the ohmic electrode; and a step of forming a source electrode and a drain electrode on the fine oxide film layer.

In addition, the recess for the gate electrode and the recess for the ohmic electrode can be formed simultaneously, and the fine oxide film layer formed on the surface of the recess for the gate electrode and the recess for the ohmic electrode can also be formed simultaneously.

Additionally, the fine oxide film layer may include either Ga ₂ O ₃ or Al ₂ O ₃ or both.

Additionally, the step of artificially forming the above fine oxide film layer can be performed through an oxygen plasma process or an oxygen heat treatment process.

According to the present invention configured as described above, by forming a fine oxide film under the gate electrode, damage to the gate surface caused by the recess etching process can be minimized. As a result, the gate electrode bonding at the recess surface for the gate electrode can be increased and the leakage current can be reduced, thereby improving the channel layer control performance of the high electron mobility transistor.

In addition, according to the present invention, a fine oxide film is formed not only on the gate electrode but also on the recess surface for the ohmic electrode including the source electrode and the drain electrode, thereby improving the surface bonding of the source electrode and the drain electrode.

In addition, according to the present invention, since the recess for the gate electrode and the recess for the ohmic electrode are formed simultaneously through a single etching process, the gap between the gate electrode and the ohmic electrode that are finally formed is precisely aligned through the self-alignment effect. As a result, the deterioration of transistor uniformity caused by foot misalignment of the gate electrode can be minimized.

Figure 1 is a drawing of a high electron mobility transistor in which a gate electrode is formed without forming a recess on a barrier layer.
FIG. 2 is a drawing of a high electron mobility transistor having a gate electrode formed on a recess having a fine oxide film according to one embodiment of the present invention.
FIG. 3 is a drawing illustrating a state in which a channel layer, a barrier layer, and a first photosensitive film are deposited on a substrate according to one embodiment of the present invention.
Figure 4 is a drawing showing a state in which a recess for a gate electrode and a recess for an ohmic electrode are etched and formed in Figure 3.
Figure 5 is a drawing showing a state in which a fine oxide film is artificially formed in Figure 4.
Figure 6 is a drawing showing a state in which the first photosensitive film in Figure 5 has been removed.
Figure 7 is a drawing showing a state in which a second photosensitive film is applied and patterned in Figure 6.
Figure 8 is a drawing showing the state in which a metal layer for an ohmic electrode is deposited in Figure 7.
Figure 9 is a drawing showing a state in which the second photosensitive film and metal layer in Figure 8 have been removed.
Figure 10 is a drawing showing a state in which a third photosensitive film is applied and patterned in Figure 9.
Figure 11 is a drawing showing the state in which a metal layer for a gate electrode is deposited in Figure 10.
Figure 12 is a drawing showing a state in which the third photosensitive film and metal layer in Figure 11 have been removed.

Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Regardless of the reference numerals used in the drawings, identical or similar components will be given the same reference numerals and redundant descriptions thereof will be omitted. In addition, when describing embodiments disclosed in this specification, if it is determined that a detailed description of a related known technology may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted.

Terms that include ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, each step described may be performed regardless of the listed order, except in cases where it must be performed in the listed order due to a special causal relationship.

In this application, it should be understood that terms such as “comprises” or “has” are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Hereinafter, a high electron mobility transistor having a recessed oxide film and a manufacturing method thereof according to one embodiment of the present invention will be described in detail with reference to the attached drawings.

The high electron mobility transistor (HEMT), which is the subject of the present invention, is known as a heterojunction FET (HFET) or a modulation-doped FET (MODFET), and is a type of field effect transistor (FET) in which a heterojunction is formed between a channel layer composed of a III-V group compound semiconductor element and a barrier layer having a lower electron affinity than the channel layer. The high electron mobility transistor can operate at a higher frequency than a general transistor, reaching millimeter frequencies, and is applicable to high-frequency and high-power products such as power amplifiers between mobile phone base stations and phased array lasers in military applications, and is therefore one of the semiconductor devices on which research and development has been most actively conducted recently.

FIG. 1 is a diagram of a high electron mobility transistor having a gate electrode formed on a barrier layer without forming a recess, and FIG. 2 is a diagram of a high electron mobility transistor having a gate electrode formed on a recess having a fine oxide film according to an embodiment of the present invention. The core technical ideas of the present invention will be described in detail by comparing them with prior art with reference to FIGS. 1 and 2.

As illustrated in FIG. 1, a compound semiconductor device including a high electron mobility transistor can be basically formed by sequentially stacking a buffer layer (20), a channel layer (30), and a barrier layer (40) on a substrate (10). The stacking process of each layer can be performed by one or a combination of various epitaxial growth processes such as LPE, VPE, MOVPE, MOCVD, and MBE, and some layers may be omitted depending on the epitaxial process.

As mentioned above, the high electron mobility transistor has the advantage of being suitable for wireless communications in the ultra-high frequency band, as a two-dimensional electron gas (2DEG) is formed at the interface between heterogeneous materials between the channel layer (30) and the barrier layer (40), and this can be used to increase the mobility of electrons.

Since the above buffer layer (20), channel layer (30), and barrier layer (40) are formed according to various epitaxial processes, they are formed very smoothly on the layer surfaces. For example, the surface of the barrier layer (40) that is epitaxially grown at the very end also becomes smooth with almost no damage, and when a T-shaped gate electrode (80) is formed thereon, excellent surface bonding can be maintained between the barrier layer (40) and the gate electrode (80). However, in this case, the gap between the interface of the channel layer (30) and the barrier layer (40) where 2DEG is formed and the gate electrode (80) increases by the thickness (t1) of the barrier layer (40), so that the control performance for electron movement is lowered. In order to reinforce this, a higher voltage must be applied to the gate electrode, and as a result, a problem of more leakage current also occurs.

In order to solve these problems, a technology has been used to form a recess of a certain depth in a barrier layer (40) as illustrated in FIG. 2 and to form a gate electrode (80) inside the recess. When a gate electrode (80) having a recess is used in this way, the gap between the interface of the channel layer (30) and the barrier layer (40) where 2DEG is formed and the gate electrode (80) becomes as close as the thickness (t2) of the recess, thereby improving the control performance for electron movement.

In contrast, the etching process for forming a recess for the gate electrode (80) damages the recess surface, creating a very rough surface. Therefore, when the gate electrode (80) is formed on this rough surface, the surface bonding property is reduced, and as a result, a low-quality Schottky junction is formed, which causes a problem in that the leakage current increases. Furthermore, in the etching process for forming the recess, an unstable and low-quality oxide film, for example, an oxide film made of GaO _x , is naturally formed on the surface of the recess. This low-quality oxide film has the problem of lowering the surface bonding property of the gate electrode (80), thereby further deteriorating the performance of the channel layer.

The present invention has been developed to minimize the side effects resulting from the formation of such a recess, and thereby improves the surface bonding properties with the gate electrode (80) by artificially forming a fine oxide film layer (50) with excellent surface quality on a rough recess surface generated by an etching process for forming a recess for a gate electrode. The fine oxide film layer (50) can be formed after removing a low-quality oxide film naturally formed on the surface of the recess during the etching process for forming the recess. As a result, not only can the control performance of the channel layer by the gate electrode (80) be improved, but also the gap between the feet of the gate electrode (80) can be made narrower, thereby forming a gate electrode (80) suitable for high-frequency wireless communications.

In addition, according to one embodiment of the present invention, a fine oxide film layer artificially formed on the surface of the recess for an ohmic electrode formed by etching on the barrier layer (40) can be formed. When the source electrode and the drain electrode are formed on the fine oxide film layer formed on the surface of the recess for an ohmic electrode, excellent ohmic bonding characteristics can be obtained, which contributes to improving the performance of a high electron mobility transistor. At this time, the fine oxide film layer formed on the surface of the recess for an ohmic electrode can be formed after removing a low-quality oxide film layer naturally occurring in the etching process of the recess for an ohmic electrode.

In addition, the recess for the gate electrode and the recess for the ohmic electrode can be formed simultaneously, and the fine oxide film layer formed on the surface of the recess for the gate electrode and the recess for the ohmic electrode can also be formed simultaneously. In this way, by simultaneously forming the fine oxide film layer on the surface of the recess for the gate electrode and the recess for the ohmic electrode through a single process, not only can the process cost be reduced, but also uniform fine oxide film characteristics can be obtained. The process of forming the recess for the ohmic electrode and the fine oxide film will be described later with reference to FIGS. 3 to 12.

As described above, in the etching process for forming the recess, an unstable and low-quality oxide film, for example, an oxide film composed of GaO _x , is naturally formed on the surface of the recess. In contrast, after the low-quality oxide film naturally formed on the surface of the recess is removed in the etching process, a fine oxide film artificially formed on the surface of the recess according to the present invention may include either Ga ₂ O ₃ or Al ₂ O ₃ , or both.

Typically, the channel layer (30) is composed of GaN among III-V group compounds, and the barrier layer (40) can be composed of AlGaN among III-V group compounds. When a surface treatment process such as oxygen plasma treatment or oxygen heat treatment is performed on the surface of a recess formed through an etching process in the barrier layer (40), a cation component among the constituent elements of AlGaN forms a fine oxide film layer made of Ga ₂ O ₃ , Al ₂ O ₃ , etc. through bonding with oxygen. These fine oxide film layers are denser and have superior surface quality than the naturally occurring oxide film, GaO _X , thereby improving surface bonding with the gate electrode (80).

Hereinafter, a method for manufacturing a high electron mobility transistor having a recessed oxide film according to one embodiment of the present invention will be described in detail with reference to the attached FIGS. 3 to 12.

First, FIG. 3 shows a state in which a buffer layer (20), a channel layer (30), and a barrier layer (40) are deposited on a substrate (10) according to one embodiment of the present invention, and a first photosensitive film (100) is applied on the barrier layer (40).

Compound semiconductor devices including the high electron mobility transistor which is the subject of the present invention can basically be sequentially laminated with a buffer layer (20), a channel layer (30), and a barrier layer (40) on a substrate (10). The lamination process of each layer can be performed by one or a combination of various epitaxial growth processes such as LPE, VPE, MOVPE, MOCVD, and MBE, and some layers can be omitted depending on the epitaxial process.

The above substrate (10) may be an insulating substrate such as glass, sapphire, or quartz, or may be a semiconductor material substrate such as silicon, silicon carbide, indium-phosphorus, silicon-germanium, gallium-arsenide, or gallium-nitrogen, or may be a diamond substrate with excellent heat dissipation properties. In addition, various materials suitable for laminating semiconductor materials may be used.

The above buffer layer (20) reduces the lattice mismatch between the substrate (10) and the channel layer (30), which is a semiconductor element formed on the substrate (10), and is formed of a material that traps defects (e.g., dislocations), thereby suppressing the diffusion of defects. The above buffer layer (20) may be composed of a compound of two materials including In, Ga, Al, etc. and N.

The above channel layer (30) may be a semiconductor element having a uniform composition that is not doped with impurities and formed using an epitaxial growth technique. The channel layer (30) may include a 2DEG (2-dimensional electron gas) region, which is a region where movement of charges (electrons) occurs in a high electron mobility transistor element, between the channel layer (30) and the barrier layer (40).

In one embodiment, the channel layer (30) may be formed by combining group III-V compound semiconductor elements, and the number and form thereof may vary. For example, representative binary compounds may include gallium-nitrogen (GaN), gallium-arsenide (GaAs), indium-phosphorus (InP), aluminum-arsenide (AlAs), indium-arsenide (InAs), and indium-tin (In-Sb), and representative ternary compounds may include aluminum-gallium-nitrogen (AlGaN), indium-gallium-nitrogen (InGaN), aluminum-gallium-arsenide (AlGaAs), indium-gallium-arsenide (InGaAs), indium-gallium-phosphorus (InGaP), indium-aluminum-phosphorus (InAlP), indium-gallium-phosphorus (InGaP), indium-aluminum-arsenide (InAlAs).

The above barrier layer (40) has a larger band gap energy than the channel layer (30), and acts as a barrier to charge flow to enable the formation of a 2DEG (2-dimensional electron gas) region in which charges (electrons) move between the channel layer (30) and the barrier layer (40). In addition, the barrier layer (40) can form a Schottky junction (a junction between a semiconductor channel layer and a metal connected to the semiconductor channel layer) necessary for forming a transistor requiring a high operating speed between the gate electrode and the channel layer (30).

The above first photosensitive film (100) is applied on the barrier layer (40) for a photolithography process.

Typically, the photolithography process consists of five steps: photoresist coating, exposure, development, etching, and stripping.

The above coating process is a process of coating a photosensitive film with a certain thickness on the deposition surface to be etched.

The above exposure process is a process of changing the properties of a photosensitive film by exposing the film to light such as UV light. At this time, a mask with a desired pattern is used to create areas of the photosensitive film that are exposed to light and areas that are not exposed to light.

The above development process is a process in which the photosensitive film is divided into a portion exposed to light and a portion not exposed to light, and then the unwanted portion is selectively removed through a developer using a dedicated removal solution, acetone, O ₂ plasma treatment, etc. to pattern it. Depending on the properties of the photosensitive film, it is divided into a positive process in which a pattern identical to the pattern of the photosensitive film not exposed to light (mask pattern) remains during the development step, and a negative process in which a pattern identical to the pattern of the photosensitive film exposed to light (non-mask pattern) remains.

The above etching process is a process of patterning a photosensitive film and then shaving off the deposited material along the patterned shape. At this time, the photosensitive film acts as an etching protective layer that protects the lower part of the deposited material from being etched. The etching process is divided into wet etching and dry etching depending on the state of the material causing the etching reaction. Wet etching is a method of etching through a chemical reaction using a solution, and dry etching is a method of removing a specific area using a reactive gas, ions, etc., and is also called plasma etching.

The above-mentioned stripping process removes the photoresist film remaining on the patterned deposition surface after the etching process is completed, thereby finally completing the deposition material of the desired shape. The method for removing the photoresist film is comprised of a dry cleaning process such as ashing using oxygen plasma, a wet cleaning process using an organic stripper, or a combination of these.

FIG. 4 shows a state after the coating, exposure, development, and etching processes for the first photosensitive film (100) are completed during the photolithography process. First, as in FIG. 3, the first photosensitive film (100) is coated with a constant thickness over the entire length of the barrier layer (40). The coated first photosensitive film (100) is patterned through the exposure process so that only the positions where the gate electrode and the ohmic electrode recesses are to be formed remain. Subsequently, when the unpatterned first photosensitive film (100) is removed through the development process, only the patterned first photosensitive film (100) remains.

Thereafter, when an etching process is performed using the first photosensitive film (100) as an etching protection layer, a recess for a gate electrode having a narrow width is formed in the center, and recesses for ohmic electrodes having a wider width are formed on both sides of the recess for the gate electrode. Typically, the recess on the left becomes the recess for the source electrode, and the recess on the right becomes the recess for the drain electrode.

According to one embodiment of the present invention, since the recess for the gate electrode and the recess for the ohmic electrode are formed simultaneously through a single etching process, the gap between the finally formed gate electrode and the ohmic electrode is precisely aligned through the self-alignment effect. As a result, the deterioration of transistor uniformity caused by foot misalignment of the gate electrode can be minimized. As shown in FIG. 12 described below, the gate electrode and the ohmic electrode may be formed of different metal materials through different lamination processes, or may be formed through a single lamination process using the same metal. In either case, if the recess for the gate electrode and the recess for the ohmic electrode are formed simultaneously as shown in FIG. 4, the gap between each electrode can be precisely controlled due to the self-alignment effect.

After the etching process of FIG. 4 is completed, an unstable and low-quality oxide film is naturally formed on the recess surface of the barrier layer (40). The recess surface of the barrier layer (40) formed during a wet or dry etching process is not only rougher than the surface of the existing barrier layer (40) formed through epitaxial growth due to the chemical reaction during the etching process, but also naturally forms an oxide film in the form of GaO _X by combining with oxygen. If a gate electrode or ohmic electrode is formed on this unstable and low-quality oxide film, the surface bonding property deteriorates, and as a result, the control performance of the channel layer deteriorates.

According to the present invention, a naturally occurring low-quality oxide film is removed through a separate etching process. This etching process is performed using an HCl, HF-based solution, and at this time, the first photosensitive film (100) does not react with the etching solution and is therefore not removed, and only the low-quality oxide film formed on the surface of the recess for the gate electrode and the recess for the ohmic electrode is selectively removed. This etching process is one of the main technical components of the present invention and is a preliminary process for obtaining a recess surface having a high-quality fine oxide film.

FIG. 5 shows another main configuration of the present invention, in which a fine oxide film layer (50) is artificially formed in FIG. 4. This fine oxide film layer (50) is composed of Ga ₂ O ₃ , Al ₂ O _{3 ,} etc., and is not only chemically stable, but also can have excellent surface quality because it is formed through a surface treatment process.

To explain in more detail, the barrier layer (40) can be composed of AlGaN among group III-V compounds, and when a surface treatment process such as oxygen plasma treatment or oxygen heat treatment is performed, a fine oxide film layer composed of Ga ₂ O ₃ , Al ₂ O ₃ , etc. is formed through bonding of the cationic components among the constituent elements of AlGaN with oxygen. These fine oxide film layers are denser and have superior surface quality than the naturally occurring oxide film, GaO _X , thereby improving surface bonding with the gate electrode (80).

The above oxygen plasma surface treatment is a plasma treatment using oxygen as an active gas on the surface of the barrier layer (40) in a vacuum state, thereby removing foreign substances remaining on the surface of the barrier layer (40) and at the same time forming a dense and high-quality fine oxide film layer (50) through the combination of oxygen and the semiconductor element forming the surface of the barrier layer (40).

Instead of this oxygen plasma treatment, a general oxygen heat treatment method may be used. This oxygen heat treatment may use a rapid heat treatment method such as RTA (Rapid Thermal Annealing), or a high-temperature oxygen heat treatment method using a furnace, oven, etc. Any oxygen heat treatment method that heats the recessed surface of the barrier layer (40) to a high temperature to increase the reaction speed with oxygen and form a denser fine oxide film layer (50) may be used.

Fig. 6 shows a state in which the first photosensitive film (100) is removed in Fig. 5. That is, the unnecessary first photosensitive film (100) is removed by the lift-off method through the peeling process. As a result, the horizontal surface of the barrier layer (40) coated by the first photosensitive film (100) is exposed to the outside, and the gate electrode recess and the ohmic electrode recess, where the fine oxide film layer (50) is formed, are also exposed to the outside. Since the horizontal surface of the barrier layer (40) is formed through epitaxial growth, it has excellent surface quality. In response, the surfaces of the gate electrode recess and the ohmic electrode recess can also have dense and excellent surface quality due to the fine oxide film layer (50).

FIG. 7 shows a state after the coating, exposure, and development processes for the second photosensitive film (110) are completed during the photolithography process. First, the second photosensitive film (110) is coated with a constant thickness over the entire length of the barrier layer (40). The coated second photosensitive film (110) is patterned through the exposure process so that only the positions where the ohmic electrode is to be deposited remain. Subsequently, when the unpatterned second photosensitive film (110) is removed through the development process, only the patterned second photosensitive film (110) remains. At this time, as shown in FIG. 7, the second photosensitive film (110) is patterned so that the recess for the gate electrode located in the center remains. As a result, in the subsequent deposition process, only the ohmic electrode, that is, the source electrode and the drain electrode, are deposited and formed within the recess for the ohmic electrode.

According to another embodiment of the present invention, the second photosensitive film (110) can be patterned so that it is exposed to the outside up to the recess for the gate electrode. This allows the gate electrode, source electrode, and drain electrode to be all made of the same metal and deposited simultaneously.

FIG. 8 shows a state in which the metal layer (60) for the ohmic electrode is deposited with a constant thickness in FIG. 7. The metal layer (60) for the ohmic electrode is deposited with a constant thickness not only at the recess position for the ohmic electrode but also on the horizontal surface of the barrier layer (40). The deposition of the metal layer (60) for the ohmic electrode can be performed by one or a combination of various deposition processes, such as PVD (Physical Vapor Deposition) such as sputtering, electron beam, and thermal evaporation, and CVD (Chemical Vapor Deposition) such as LPCVD, MOCVD, PECVD, and ALCVD.

The metal layer (60) for the ohmic electrode may be formed in the form of a laminate or alloy of one or more materials from among Si, Ti, Al, Mo, Pt, Cr, Pd, Ni, Au, TiN, TaN, Cu, W, TiW, etc. In addition, according to the present embodiment, the source electrode and the drain electrode constituting the ohmic electrode may be formed using the same metal through a single process.

FIG. 9 shows a state in which the second photosensitive film (110) and the metal layer (60) for the ohmic electrode are removed in FIG. 8. That is, the second photosensitive film (110) and the metal layer (60) for the ohmic electrode, which are not patterned through the etching and peeling process, are lifted off in a lift-off manner. As a result, the source electrode and the drain electrode (60) are formed so as to be positioned inside the recess for the ohmic electrode. At this time, the source electrode and the drain electrode (60) are in contact with the fine oxide film layer (50) having excellent surface quality, so that they exhibit excellent surface bonding properties and ohmic contact performance. In addition, the surface of the recess for the gate electrode is also exposed to the outside, so that the gate electrode can be formed through a subsequent deposition process.

FIG. 10 shows a state in which the third photosensitive film (120) is applied and patterned in FIG. 9. In other words, it shows a state after the application, exposure, and development processes for the third photosensitive film (120) are completed in the photolithography process. First, the third photosensitive film (120) is applied with a constant thickness over the entire length of the barrier layer (40). The applied third photosensitive film (120) is patterned through an exposure process so that only the position where the gate electrode is to be deposited remains. Subsequently, when the unpatterned third photosensitive film (120) is removed through a development process, only the patterned third photosensitive film (120) remains. As a result, a recess for the gate electrode with a fine oxide film layer (50) formed in the center is exposed to the outside.

Fig. 11 shows a state in which a metal layer (70) for a gate electrode is deposited in Fig. 10. The metal layer (70) for a gate electrode is deposited with a constant thickness not only at the recess position for the gate electrode but also on the horizontal surface of the barrier layer (40) and the surface of the ohmic electrode. The deposition of the metal layer (70) for a gate electrode can be performed by one or a combination of various deposition processes, such as PVD (Physical Vapor Deposition) such as sputtering, electron beam, and thermal evaporation, and CVD (Chemical Vapor Deposition) such as LPCVD, MOCVD, PECVD, and ALCVD.

The metal layer (70) for the gate electrode may be formed in the form of a laminate or alloy of one or more materials such as Ti, Al, Mo, Pt, Cr, Pd, Ni, Au, TiN, TaN, Cu, W, TiW, etc. In addition, according to another embodiment of the present invention, the process of forming the gate electrode may be performed simultaneously with the process of forming the ohmic electrode described with reference to FIG. 9. In this case, the gate electrode and the ohmic electrode may be formed using the same metal through a single process.

Finally, Fig. 12 shows a state in which the third photosensitive film (120) and the metal layer (70) for the gate electrode are removed in Fig. 11. That is, the third photosensitive film (120) and the metal layer (70) for the gate electrode, which are not patterned through the etching and peeling process, are lifted off in a lift-off manner. As a result, the gate electrode (70) is formed so as to be positioned inside the recess for the gate electrode. At this time, the gate electrode (70) is in contact with the fine oxide film layer (50) having excellent surface quality, and thus exhibits excellent surface bonding properties and short-circuit contact performance.

In this way, according to the present invention, by forming a recess for a gate electrode so that the distance between the gate electrode and the channel layer (30) can be positioned close, control is possible even with a low gate voltage and a technical effect of reducing leakage current is exhibited. On the other hand, when forming a recess for a gate electrode, there was a problem that the surface bonding between the gate electrode and the barrier layer (40) was deteriorated due to a rough recess surface and a low-quality oxide film naturally occurring in the etching process. Accordingly, the present invention solves the problem of deterioration of surface bonding due to the formation of a recess for a gate electrode by forming a dense and high-quality fine oxide film layer (50) on the recess surface through a separate oxygen plasma treatment or oxygen heat treatment process. This fine oxide film layer (50) can also be formed on the recess surface for an ohmic electrode to ensure excellent ohmic contact performance.

The technical features disclosed in each embodiment of the present invention are not limited to that embodiment, and, unless they are mutually incompatible, the technical features disclosed in each embodiment may be combined and applied to different embodiments.

Therefore, each embodiment will focus on explaining each technical feature, but unless each technical feature is incompatible with each other, it can be applied in combination with each other.

The present invention is not limited to the above-described embodiments and the attached drawings, and various modifications and variations are possible from the viewpoint of those skilled in the art to which the present invention pertains. Therefore, the scope of the present invention should be determined not only by the claims of this specification but also by the equivalents of these claims.

10: Substrate
20: Buffer layer
30: Channel layer
40: Barrier layer
50: Fine oxide film
60: Ohmic metal layer, source electrode and drain electrode
70: Metal layer for gate, gate electrode
100, 110, 120: 1st photosensitive film, 2nd photosensitive film, 3rd photosensitive film

Claims (11)

substrate;
A channel layer formed on the above substrate;
A barrier layer formed on the channel layer and having a recess for a gate electrode, a recess for a source electrode, and a recess for a drain electrode;
A fine oxide film layer artificially formed on the surface of the recess for the gate electrode, the recess for the source electrode, and the recess for the drain electrode;
A gate electrode formed on a fine oxide film layer located in a recess for the gate electrode;
A source electrode formed on a fine oxide film layer located in a recess for the source electrode; and
A drain electrode formed on a fine oxide film layer located in the recess for the above drain electrode.
Including,
The above source electrode and the fine oxide film layer located in the recess for the above source electrode overlap in the vertical direction,
A high electron mobility transistor having a recess oxide film, wherein the drain electrode and the fine oxide film layer positioned in the recess for the drain electrode are overlapped in the vertical direction. delete In claim 1,
The recess for the gate electrode, the recess for the source electrode and the recess for the drain electrode are formed simultaneously,
A high electron mobility transistor having a recess oxide film, characterized in that the fine oxide film layers formed on the surfaces of the recess for the gate electrode, the recess for the source electrode, and the recess for the drain electrode are formed simultaneously. delete In claim 1,
A high electron mobility transistor having a recess oxide film, characterized in that the fine oxide film layer formed on the surface of the recess for the gate electrode, the surface of the recess for the source electrode, and the surface of the recess for the drain electrode is formed after removing an oxide film layer that naturally occurs during an etching process of the recess for the gate electrode, the recess for the source electrode, and the recess for the drain electrode. In claim 1,
A high electron mobility transistor having a recessed oxide film, characterized in that the above fine oxide film layer includes one or both of Ga ₂ O ₃ and Al ₂ O _{3 .} Steps to prepare the substrate;
A step of forming a channel layer on the above substrate;
A step of forming a barrier layer on the above channel layer;
A step of etching and forming a recess for a gate electrode, a recess for a source electrode, and a recess for a drain electrode on the barrier layer;
A step of removing an oxide film naturally formed on the surface of each of the recess for the gate electrode, the recess for the source electrode, and the recess for the drain electrode in the etching process;
A step of artificially forming a fine oxide film layer on the recess surface for the gate electrode, the recess surface for the source electrode, and the recess surface for the drain electrode;
A step of forming a metal layer for an ohmic electrode on a fine oxide film layer formed on the surface of the recess for the source electrode and a fine oxide film layer formed on the surface of the recess for the drain electrode, thereby forming a source electrode on the fine oxide film layer formed on the surface of the recess for the source electrode and forming a drain electrode on the fine oxide film layer formed on the surface of the recess for the drain electrode; and
A step of forming a metal layer for a gate electrode on a fine oxide film layer formed on the recessed surface for the gate electrode, thereby forming a gate electrode on the fine oxide film layer formed on the recessed surface for the gate electrode.
A method for manufacturing a high electron mobility transistor having a recessed film including: delete delete In claim 7,
A method for manufacturing a high electron mobility transistor having a recessed oxide film, characterized in that the fine oxide film layer includes one or both of Ga ₂ O ₃ and Al ₂ O _{3 .} In claim 7,
The step of artificially forming the above fine oxide film layer is:
A method for manufacturing a high electron mobility transistor having a recessed oxide film characterized by being formed through an oxygen plasma process or an oxygen heat treatment process.

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