KR102783442B1 - Display device and driving method therof - Google Patents

Abstract

Embodiments relate to a display device and a driving method thereof, including a display panel including a display area and a non-display area, a first gate driver arranged in a left non-display area of the display panel and supplying a first scan signal to a left gate line of the display panel, a first source driver transmitting a first control signal to the first gate driver, a second gate driver arranged in a right non-display area of the display panel and supplying a second scan signal to a right gate line of the display panel, a second source driver transmitting a second control signal to the second gate driver, and a timing controller supplying the first and second control signals, wherein the first gate driver supplies the first scan signal according to the first control signal, the second gate driver supplies the second scan signal according to the second control signal, and the supply of the first scan signal and the supply of the second scan signal are not simultaneous.

Description

DISPLAY DEVICE AND DRIVING METHOD THEROF

The present invention relates to a display device and a driving method, and more particularly, to a display device that controls the timing of a signal supplied to a display panel and a driving method thereof.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and various types of flat panel display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs) are being utilized.

Recently, in response to the demand for high resolution and large size of display devices, development of large-area display panels has been carried out. In the case of such large-area display panels, the stability of image quality in the center of the screen is deteriorated and defects are likely to occur due to signals being supplied simultaneously to the left and right sides of the screen.

The present invention is intended to solve the above problems, and provides a method for dispersing a signal concentrated in the center of a display panel and a display device driven according to the method.

According to one embodiment, a display device may include a display panel including a display area and a non-display area, a first gate driver arranged in a left non-display area of the display panel and supplying a first scan signal to a left gate line of the display panel, a first source driver transmitting a first control signal to the first gate driver, a second gate driver arranged in a right non-display area of the display panel and supplying a second scan signal to a right gate line of the display panel, a second source driver transmitting a second control signal to the second gate driver, and a timing controller supplying the first and second control signals, wherein the first gate driver supplies the first scan signal according to the first control signal, the second gate driver supplies the second scan signal according to the second control signal, and the supply of the first scan signal and the supply of the second scan signal are not simultaneous.

The first control signal includes a first output cancel signal, the second control signal includes a second output cancel signal, and a falling point in time of the first output cancel signal may be different from a falling point in time of the second output cancel signal.

The first control signal includes a first output cancel signal, the second control signal includes a second output cancel signal, and the rising point of the first output cancel signal is the same as the rising point of the second output cancel signal, but the level high section of the first output cancel signal can be different from the level high section of the second output cancel signal.

The first control signal includes a first output erase signal, the second control signal includes a second output erase signal, and a time at which the first source driver applies the first output erase signal to the first gate driver may be different from a time at which the second source driver applies the second output erase signal to the second gate driver.

The first source driving unit may include a first buffer that controls input and output of the first output cancel signal, and the second source driving unit may include a second buffer that controls input and output of the second output cancel signal.

The first control signal includes a first start pulse, the second control signal includes a second start pulse, and a time at which the first source driver applies the first start pulse to the first gate driver may be different from a time at which the second source driver applies the second start pulse to the second gate driver.

The first source driving unit may include a first buffer that controls input and output of the first start pulse, and the second source driving unit may include a second buffer that controls input and output of the second start pulse.

It further includes a switching element connected to the timing control unit, an input terminal of the switching element is connected to the timing control unit, and an output terminal of the switching element can be switched with either one of the first source driving unit and the second source driving unit.

The above switching element can be connected to the first source driving unit for a preset time and then connected to the second source driving unit.

A method for driving a display device according to one embodiment includes the steps of supplying a first control signal to a first source driver, supplying the first control signal to a first gate driver arranged in a left non-display area of a display panel, supplying a first scan signal to a gate line arranged on the left side of the display panel in response to the first control signal, supplying a second control signal to a second source driver, supplying the second control signal to a second gate driver arranged in a right non-display area of the display panel, and supplying a second scan signal to a gate line arranged on the right side of the display panel in response to the second control signal, wherein the supply of the first scan signal and the supply of the second scan signal may be asynchronous.

The first control signal includes a first output cancel signal, the second control signal includes a second output cancel signal, and a falling point in time of the first output cancel signal may be different from a falling point in time of the second output cancel signal.

The first control signal includes a first output cancel signal, the second control signal includes a second output cancel signal, and the rising point of the first output cancel signal is the same as the rising point of the second output cancel signal, but the level high section of the first output cancel signal can be different from the level high section of the second output cancel signal.

The first control signal includes a first output erase signal, the second control signal includes a second output erase signal, and the timing of applying the first output erase signal to the first gate driver may be different from the timing of applying the second output erase signal to the second gate driver.

The first output erase signal may be input/output controlled by a first buffer included in the first source driving unit, and the second output erase signal may be input/output controlled by a second buffer included in the second source driving unit.

The first control signal includes a first start pulse, the second control signal includes a second start pulse, and the timing at which the first start pulse is applied to the first gate driver may be different from the timing at which the second start pulse is applied to the second gate driver.

The first start pulse may be input/output controlled by a first buffer included in the first source driving unit, and the second start pulse may be input/output controlled by a second buffer included in the second source driving unit.

The first control signal is supplied to the first source driving unit while the switching element is connected to the first source driving unit, the second control signal is supplied to the second source driving unit while the switching element is connected to the second source driving unit, and the switching element can be connected to the second source driving unit after being connected to the first source driving unit for a preset period of time.

According to the present invention, by alternately providing signals to the left and right of the display panel, it is possible to disperse the load concentrated in the center of a large-area display device.

In addition, according to the present invention, the image quality in the central portion of the display device can be improved.

Figure 1 is a block diagram showing the configuration of a display device according to one embodiment of the present invention.
Figure 2 is a drawing showing a display device according to the present invention.
FIG. 3 is a drawing for explaining the structure of a pixel according to one embodiment of the present invention.
FIG. 4 is a structural diagram showing the connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to the first embodiment of the present invention.
FIG. 5 illustrates a timing diagram of a control signal transmitted to a gate driver through a source driver illustrated in FIG. 4 and a scan signal supplied from the gate driver to a gate line.
FIG. 6 is a drawing for explaining the signal flow of a display device according to the first embodiment of the present invention.
FIG. 7 is a structural diagram showing the connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to a second embodiment of the present invention.
FIG. 8 illustrates a timing diagram of a control signal transmitted to a gate driver through a source driver illustrated in FIG. 7 and a scan signal supplied from the gate driver to a gate line.
FIG. 9 is a drawing for explaining the signal flow of a display device according to the second embodiment of the present invention.
FIG. 10 is a structural diagram showing the connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to a third embodiment of the present invention.
Figure 11 illustrates a timing diagram of a control signal transmitted to a gate driver through a source driver illustrated in Figure 10 and a scan signal supplied from the gate driver to a gate line.
FIG. 12 is a drawing for explaining the signal flow of a display device according to a third embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. In the present specification, when a component (or region, layer, portion, etc.) is referred to as being "on," "connected," or "coupled" to another component, it means that it can be directly connected/coupled to the other component, or a third component may be arranged between them.

Identical drawing reference numerals refer to identical components. Also, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively explaining the technical contents. "And/or" includes all combinations of one or more that the associated components can define.

Although the terms first, second, etc. may be used to describe various components, the components are not limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the present embodiments, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The singular expression includes the plural expression unless the context clearly indicates otherwise.

The terms "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

It should be understood that the terms "include" or "have", etc., are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Figure 1 is a block diagram showing the configuration of a display device according to one embodiment of the present invention.

Referring to FIG. 1, the display device (1) includes a timing control unit (10), a gate driving unit (20), a data driving unit (30), a power supply unit (40), and a display panel (50).

The timing control unit (10) can receive an image signal (RGB) and a control signal (CS) from the outside. The image signal (RGB) can include a plurality of grayscale data. The control signal (CS) can include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

The timing control unit (10) processes the image signal (RGB) and the control signal (CS) to be suitable for the operating conditions of the display panel (50), and can generate and output image data (DATA), a gate drive control signal (CONT1), a data drive control signal (CONT2), and a power supply control signal (CONT3).

The gate driver (20) can be connected to pixels (or pixels, PX) of the display panel (50) through a plurality of first gate lines (GL1 to GLn). The gate driver (20) can generate gate signals based on a gate driving control signal (CONT1) output from the timing control unit (10). The gate driver (20) can provide the generated gate signals to the pixels (PX) through the plurality of first gate lines (GL1 to GLn).

In various embodiments, the gate driver (20) may be further connected to the pixels (PX) of the display panel (50) through a plurality of second gate lines (GL21 to GL2m). The gate driver (20) may provide a sensing signal to the pixels (PX) through the plurality of second gate lines (GL21 to GL2m). The sensing signal may be supplied to measure the characteristics of the driving transistor and/or the light-emitting element provided inside the pixels (PX).

The data driving unit (30) can be connected to pixels (PX) of the display panel (50) through a plurality of data lines (DL1 to DLn). The data driving unit (30) can generate data signals based on image data (DATA) and a data driving signal (CONT2) output from the timing control unit (10). The data driving unit (30) can provide the generated data signals to pixels (PX) through a plurality of data lines (DL1 to DLn).

In various embodiments, the data driving unit (30) may be further connected to the pixels (PX) of the display panel (50) through a plurality of sensing lines (or, reference lines) (SL1 to SLm). The data driving unit (30) may provide a reference voltage (or, sensing voltage, initialization voltage) to the pixels (PX) through the plurality of sensing lines (SL1 to SLm), or sense the state of the pixels (PX) based on an electrical signal fed back from the pixels (PX).

The power supply unit (40) can be connected to the pixels (PX) of the display panel (50) through a plurality of power lines (PL1, PL2). The power supply unit (40) can generate a driving voltage supplied to the display panel (50) based on a power supply control signal (CONT3). The driving voltage can include, for example, a high potential driving voltage (ELVDD) and a low potential driving voltage (ELVSS). The power supply unit (40) can provide the generated driving voltages (ELVDD, ELVSS) to the pixels (PX) through the corresponding power lines (PL1, PL2).

A plurality of pixels (PX) are arranged on the display panel (50). The pixels (PX) may be arranged in a matrix form on the display panel (50), for example.

Each pixel (PX) can be electrically connected to a corresponding gate line and data line. These pixels (PX) can emit light with a brightness corresponding to a gate signal and a data signal supplied through the first gate lines (GL1 to GLn) and the data lines (DL1 to DLn).

Each pixel (PX) can display any one of the first to third colors. For example, each pixel (PX) can display any one of the colors red, green, and blue. For another example, each pixel (PX) can display any one of the colors cyan, magenta, and yellow. For another example, the pixels (PX) can be configured to display any one of four or more colors. For example, each pixel (PX) can display any one of the colors red, green, blue, and white.

The timing control unit (10), the gate driver (20), the data driver (30), and the power supply unit (40) may each be configured as separate integrated circuits (ICs) or may be configured as integrated circuits in which at least a portion is integrated. For example, at least one of the data driver (30) and the power supply unit (40) may be configured as an integrated circuit integrated with the timing control unit (10).

In addition, although the gate driver (20) and the data driver (30) are illustrated as separate components from the display panel (50) in FIG. 1, at least one of the gate driver (20) and the data driver (30) may be implemented in an in-panel manner in which it is formed integrally with the display panel (50). For example, the gate driver (20) may be formed integrally with the display panel (50) in accordance with a gate in panel (GIP) manner.

Figure 2 is a drawing showing a display device according to the present invention.

Referring to FIG. 2, a display panel (50) having a rectangular shape is shown, and the display panel (50) includes a plurality of pixels (PX) arranged in the form of rows and columns therein. The plurality of pixels (PX) include, for example, four sub-pixels, and each of the four sub-pixels may be a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel.

In addition, the display device (1) includes a plurality of gate driving units (G-IC) (20). In one embodiment, the plurality of gate driving units (20) include a first gate driving unit (G-IC, Left) and a second gate driving unit (G-IC, Right). The first gate driving unit (G-IC, Left) may be arranged in a left non-display area of the display panel (50) to supply a scan signal (SSL1) to the left gate lines of the display panel (50), and the second gate driving unit (G-IC, Right) may be arranged in a right non-display area of the display panel (50) to supply a scan signal (SSL2) to the right gate lines of the display panel (50).

The display panel (50) may be implemented in a gate-in-panel (GIP) manner in which a plurality of gate drivers (20) are arranged internally. That is, the plurality of gate drivers (20) may be implemented as a plurality of gate driver ICs and attached to the left and right sides of the display panel (50), respectively.

In addition, the display device (1) includes a data driving IC (or source driving IC, S-IC) (30). The source driving IC (30) can be attached to the bottom of the display panel (50), and a plurality of them can be attached in the horizontal direction of the display panel (50). Such a source driving IC (30) can be implemented in a COF (Chip on Film) method arranged in a flexible PCB (FPCB), a COG (Chip on Glass) method arranged on a glass substrate constituting the display panel (50), etc.

For example, in the embodiment illustrated in FIG. 2, the source driving IC (30) is implemented in a COF manner, and the FPCB connects the display panel (50) and the source driving unit (S-PCB) through pad connections. The source driving IC (30) can transmit a control signal (e.g., an output mute signal (Mute), a start pulse (VSP), a source IC driving voltage, EVDD, VREF, etc.) provided from a control PCB (C-PCB) to the display panel (50).

The source driving unit (S-PCB) is connected to the display panel (50) through the FPCB from the lower part of the display panel (50), and can be connected to the control PCB (C-PCB) through an FPC (Flexible Plat Cable) connection. This source driving unit (S-PCB) is directly connected to the source driving IC (30) and transmits a control signal to the gate driving unit (10).

In one embodiment, the source driver (S-PCB) includes a first source driver (S-PCB, Left) and a second source driver (S-PCB, Right). The first source driver (S-PCB, Left) is arranged at the lower left of the display panel (50) and can transmit a control signal (CONT1) to the first gate driver (G-IC, Left). In addition, the second source driver (S-PCB, Right) is arranged at the lower right of the display panel (50) and can transmit a control signal (CONT2) to the second gate driver (G-IC, Right). That is, the source driver (S-PCB) provides a connection between the control PCB (C-PCB) and the left and right gate drivers (20) through the leftmost or rightmost source driver IC (30).

In Fig. 2, an example is shown in which one source driving unit (S-PCB) is arranged at each of the left and right lower sides of the display panel (50), but the present invention is not limited thereto. For example, a plurality of source driving units (S-PCB) may be arranged at each of the left and right lower sides of the display panel (50).

In addition, the source driver (S-PCB) receives a control signal (e.g., an output mute signal (Mute), a start pulse (VSP), a source IC driving voltage, EVDD, VREF, etc.) from the control PCB (C-PCB) and transmits it to the display panel (50). For example, a gate driver IC driving voltage, a gate high voltage (VGH), a gate low voltage (VGL), etc. can be transmitted from the control PCB (C-PCB) to the gate driver (30) through the source driver (S-PCB).

The control PCB (C-PCB) is arranged at the bottom of the display panel (50) and is connected to the source driver (S-PCB) via a cable (FPC). The control PCB (C-PCB) may include a timing control unit (TCON) (10), a power supply unit (40), and a memory. The description of the timing control unit (10) and the power supply unit (40) is the same as the description referring to FIG. 1. In addition, an area is required for calculating an algorithm for each frame of output image data to be output, storing compensation data, and storing various parameters required for calculating the algorithm or various parameters for tuning, and therefore, a volatile memory and/or a nonvolatile memory may be arranged on the control PCB (C-PCB).

FIG. 3 is a drawing for explaining the structure of a pixel according to an embodiment of the present invention.

Referring to FIG. 3, one pixel includes four sub-pixels (R, W, G, B), and each sub-pixel is connected to a gate driver IC (G-IC), a scan line (SCAN), and a sensing line (SENSE), and is connected to a source driver IC (S-IC) and a reference line (Reference).

In addition, each sub-pixel receives a data voltage (VDATA) from a source driving IC (S-IC) through a DAC (Digital Analog Converter). In addition, a sensing voltage (VSEN) output from each sub-pixel is provided to the source driving IC (S-IC) through an ADC (Analog Digital Converter). In addition, each sub-pixel is connected to a high-potential driving voltage (ELVDD) and a low-potential driving voltage (ELVSS).

Each sub-pixel includes a scan TFT (S-TFT), a driving TFT (D-TFT), and a sensing TFT (SS-TFT). Additionally, each sub-pixel includes a storage capacitor (CST) and an organic light-emitting diode (OLED).

A first electrode (e.g., a source electrode) of a scan transistor (S-TFT) is connected to a data line (DATA, DL), and a data voltage (VDATA) is output from a source driving IC (S-IC) and applied to the data line via a DAC. A second electrode (e.g., a drain electrode) of the scan transistor (S-TFT) is connected to one end of a storage capacitor (CST) and is connected to a gate electrode of a driving TFT (D-TFT). The gate electrode of the scan transistor (S-TFT) is connected to a scan line (or gate line (GL)). That is, the scan transistor (S-TFT) is turned on when a gate signal of a gate-on level is applied through the scan line (SCAN), and transmits a data signal applied through the data line (DATA) to one end of the storage capacitor (CST).

One end of a storage capacitor (CST) is connected to a third electrode (e.g., a drain electrode) of a scan TFT (S-TFT). The other end of the storage capacitor (CST) is configured to receive a high-potential driving voltage (ELVDD). The storage capacitor (CST) can charge a voltage corresponding to a difference between a voltage applied to one end and the high-potential driving voltage (ELVDD) applied to the other end. In addition, the storage capacitor (CST) can also charge a voltage corresponding to a difference between a voltage applied to one end and a reference voltage (VREF) applied to the other end through a switch (SPRE) and a sensing TFT (SS-TFT).

A first electrode (e.g., a source electrode) of a driving transistor (D-TFT) is configured to receive a high-potential driving voltage (ELVDD), and a second electrode (e.g., a drain electrode) is connected to a first electrode (e.g., an anode electrode) of a light-emitting element (OLED). A third electrode (e.g., a gate electrode) of the driving transistor (D-TFT) is connected to one end of a storage capacitor (CST). The driving transistor (D-TFT) is turned on when a voltage of a gate-on level is applied, and can control an amount of driving current flowing through the light-emitting element (OLED) in response to the voltage provided to the gate electrode. That is, the current is determined by a voltage difference of Vgs of the driving TFT (D-TFT) (or a storage voltage of the storage capacitor (CST)) and is applied to the light-emitting element (OLED).

A first electrode (e.g., a source electrode) of a sensing TFT (SS-TFT) is connected to a reference line (REFERENCE), a second electrode (e.g., a drain electrode) is connected to the other end of a storage capacitor (CST), and a third electrode (e.g., a gate electrode) is connected to a sensing line (SENSE). That is, the sensing TFT (SS-TFT) is turned on by a sensing signal (SENSE) output from a gate driving IC (G-IC) and applies a reference voltage (VREF) to the other end of the storage capacitor (CST). If both the switch (SPRE) and the switch (SAM) are turned off and the sensing TFT (SS-TFT) is turned on, the storage voltage of the storage capacitor (CST) is transferred to the capacitor of the reference line, and the sensing voltage (VSEN) is stored in the capacitor of the reference line.

If the switch (SPRE) is turned off and the switch (SAM) is turned on, the voltage (VSEN) stored in the reference line capacitor is output to the source driving IC (S-IC) through the ADC. This output voltage is soon used as a voltage for sensing and sampling the deterioration of the corresponding sub-pixel. In other words, it is possible to sense and sample a voltage for compensating the corresponding sub-pixel. Specifically, the characteristics of the driving TFT (D-TFT) are divided into two: mobility and threshold voltage, and compensation can be implemented by sensing the mobility and threshold voltage of the driving TFT (D-TFT). In addition, the characteristics of the corresponding sub-pixel can also be determined by the deterioration of the light-emitting element (OLED), and it is also necessary to sense and compensate for the degree of deterioration of the light-emitting element (OLED).

The light emitting element (OLED) outputs light corresponding to the driving current. The light emitting element (OLED) can output light corresponding to any one color of red, white, green, and blue. The light emitting element (OLED) may be an organic light emitting diode (OLED), or an ultra-small inorganic light emitting diode having a size in the micro to nano scale range, but the present invention is not limited thereto. Hereinafter, the technical idea of the present invention will be described with reference to an embodiment in which the light emitting element (LD) is composed of an organic light emitting diode.

Although FIG. 3 illustrates an example in which the switching transistor (S-TFT), the driving transistor (D-TFT), and the sensing transistor (SS-TFT) are NMOS transistors, the present invention is not limited thereto. For example, at least some or all of the transistors constituting each pixel (PX) may be configured as PMOS transistors. In various embodiments, each of the switching transistor (ST) and the driving transistor (DT) may be implemented as a low temperature poly silicon (LTPS) thin film transistor, an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor.

In addition, in the description referring to FIG. 3, four sub-pixels are depicted as sharing one reference line (REFERENCE). However, this is not limited to the present invention, and a different number of sub-pixels may share one reference line (REFERENCE), and each sub-pixel may be connected to one reference line (REFERENCE). In this specification, for the convenience of explanation, four sub-pixels are depicted as sharing one reference line (REFERENCE), as illustrated in FIG. 3, and it should be understood that this is an example.

FIGS. 4 to 6 are diagrams showing a display device and its signal flow according to a first embodiment of the present invention. First, FIG. 4 is a structural diagram showing a connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to the first embodiment of the present invention.

Referring to FIG. 4 together with FIGS. 1 to 3, the timing control unit (10) supplies an output mute signal (Mute) to the source driver (S-PCB). The output mute signal (Mute) may be a signal that controls the output of a scan signal provided to a gate line. For example, when the output mute signal (Mute) is supplied from the timing control unit (10) to the source driver (S-PCB) and the gate driver (G-IC) receives the output mute signal (Mute) through the source driver (S-PCB), the gate driver (G-IC) may not output a scan signal to the gate line. That is, the gate driver (G-IC) may output a scan signal to the gate line when the level of the output mute signal (Mute) changes from high to low. The application time of the scan signal may be the same as the falling time of the output mute signal (Mute).

The source driver (S-PCB) includes a first source driver (S-PCB, Left) and a second source driver (S-PCB, Right). The first source driver (S-PCB, Left) may be arranged at the lower left of the display panel (50), and the second source driver (S-PCB, Right) may be arranged at the lower right of the display panel (50). The timing control unit (10) supplies first and second output mute signals (Mute) to the first and second source drivers (S-PCBs). Specifically, the timing control unit (10) may supply a first output mute signal (Mute_L) to the first source driver (S-PCB, Left) and a second output mute signal (Mute_R) to the second source driver (S-PCB, Right).

The gate driver (G-IC) includes a first gate driver (G-IC, Left) and a second gate driver (G-IC, Right). The first gate driver (G-IC, Left) may be disposed in a left non-display area of the display panel (50), and the second gate driver (G-IC, Right) may be disposed in a right non-display area of the display panel (10). The source driver (S-PCB) may transmit an output mute signal (Mute) to the gate driver (G-IC). For example, the first source driver (S-PCB, Left) transmits a first output mute signal (Mute_L) to the first gate driver (G-IC, Left), and the second source driver (S-PCB, Right) transmits a second output mute signal (Mute_R) to the second gate driver (G-IC, Right).

The gate driver (G-IC) can supply a scan signal to a gate line in response to an output mute signal (Mute) transmitted from a source driver (S-PCB). The gate driver (G-IC) can include a level shifter and a gate output unit. The level shifter can receive the output mute signal (Mute) from the source driver (S-PCB) and generate a plurality of scan clock signals (SCCLK#). The plurality of scan clock signals (SCCLK#) generated by the level shifter can be supplied to the gate output unit. The gate output unit can receive the scan clock signal (SCCLK#) supplied from the level shifter and sequentially output a gate signal (or scan signal) to the gate line. For example, a first gate driver (G-IC, Left) may include a first level shifter (Left) and a first gate output unit (Left), and a second gate driver (G-IC, Right) may include a second level shifter (Right) and a second gate output unit (Right).

In one embodiment, the first gate driver (G-IC, Left) may apply a first scan signal (SCAN_L) to the left gate line of the display panel (50) in response to the first output erase signal (Mute_L), and the second gate driver (G-IC, Right) may apply a second scan signal (SCAN_R) to the right gate line of the display panel (50) in response to the second output erase signal (Mute_R). For example, the first and second gate drivers (G-IC) may supply scan signals to the left and right gate lines of the display panel (50) when the levels of the first and second output erase signals (Mute) change from high to low. Specifically, the first scan signal (SCAN_L) may be applied from the first gate driver (G-IC, Left) to the left gate line when the level of the first output mute signal (Mute) changes from a high level to a low level, and the second scan signal (SCAN_R) may be applied from the second gate driver (G-IC, Right) to the right gate line when the level of the second output mute signal (Mute) changes from a high level to a low level.

As in the embodiment illustrated in FIG. 5, the point in time when the first scan signal (SCAN_L) changes to the low level and the point in time when the second scan signal (SCAN_R) changes to the high level may be the same. In this case, the section between the point in time when the first scan signal (SCAN_L) changes to the high level and the point in time when the second scan signal (SCAN_R) changes to the high level may be defined as a delay. Alternatively, the second scan signal (SCAN_R) may change to the high level before the first scan signal (SCAN_L) changes to the low level after changing to the high level. That is, in this case, the high level section of the first scan signal (SCAN_L) and the high level section of the second scan signal (SCAN_R) may overlap each other. In this case, the delay may be relatively small. Alternatively, after a predetermined time has passed since the first scan signal (SCAN_L) changed to a low level, the second scan signal (SCAN_R) may change to a high level. That is, in this case, a gap corresponding to a predetermined time may exist between the high level section of the first scan signal (SCAN_L) and the high level section of the second scan signal (SCAN_R). In this case, the delay may be relatively large.

As described above, the time at which the first scan signal (SCAN_R) changes from a high level to a low level may be different from the time at which the second scan signal (SCAN_L) changes to a high level.

In one embodiment, the level high section of the second output erase signal (Mute_R) provided from the timing control unit (10) may be implemented to be longer than the level high section of the first output erase signal (Mute_L). That is, even if the first and second output erase signals (Mute) are supplied simultaneously from the timing control unit (10), the application timing of the first scan signal (SCAN_L) output from the first gate driver (G-IC) and the application timing of the second scan signal (SCAN_R) output from the second gate driver (G-IC) may be different due to the difference in the level high section between the first output erase signal (Mute_L) and the second output erase signal (Mute_R). For example, the second scan signal (SCAN_R) may be output from the second gate driver (G-IC, Right) after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left).

Accordingly, by asynchronously applying the first scan signal (SCAN_L) and the second scan signal (SCAN_R) to the display panel (50), the load concentrated in the center of the display panel (50) can be distributed compared to when the first and second scan signals are applied simultaneously.

FIG. 5 illustrates a timing diagram of an output erase signal transmitted to a gate driver through a source driver illustrated in FIG. 4 and a scan signal supplied to a gate line from the gate driver.

Referring to FIG. 5 together with FIGS. 1 to 4, the timing control unit (10) supplies a first output erase signal (Mute_L) to the first source driver (S-PCB, Left) and supplies a second output erase signal (Mute_R) to the second source driver (S-PCB, Right). The first gate driver (G-IC, Left) receives the first output erase signal (Mute_L) from the first source driver (S-PCB, Left) and outputs a first scan signal (SCAN_L) to the left gate line of the display panel (50), and the second source driver (G-IC, Right) receives the second output erase signal (Mute_R) from the second source driver (S-PCB, Right) and outputs a second scan signal (SCAN_R) to the right gate line of the display panel (50). For example, the first and second gate drivers (G-IC) can supply scan signals to the left and right gate lines of the display panel (50) when the levels of the first and second output erase signals (Mute) change from high to low. Specifically, the first scan signal (SCAN_L) can be applied from the first gate driver (G-IC, Left) to the left gate line when the first output erase signal (Mute) changes from a high level to a low level, and the second scan signal (SCAN_R) can be applied from the second gate driver (G-IC, Right) to the right gate line when the second output erase signal (Mute) changes from a high level to a low level.

In one embodiment, the time at which the first scan signal (SCAN_L) changes to a low level and the time at which the second scan signal (SCAN_R) changes to a high level may be the same. Alternatively, the second scan signal (SCAN_R) may change to a high level after a time period has elapsed since the first scan signal (SCAN_L) changes to a low level.

In one embodiment, a level high section of a second output erase signal (Mute_R) provided from a timing control unit (10) may be implemented to be longer than a level high section of a first output erase signal (Mute_L). That is, even if the first and second output erase signals (Mute) are supplied simultaneously from the timing control unit (10), the application time of the first scan signal (SCAN_L) output from the first gate driver (G-IC) and the application time of the second scan signal (SCAN_R) output from the second gate driver (G-IC) may be different due to the difference in the level high section between the first output erase signal (Mute_L) and the second output erase signal (Mute_R).

For example, after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left), the second scan signal (SCAN_R) can be output from the second gate driver (G-IC, Right).

Accordingly, since the first scan signal (SCAN_L) and the second scan signal (SCAN_R) are applied asynchronously to the display panel (50), the load concentrated in the center of the display panel (50) can be distributed compared to when the first and second scan signals are applied simultaneously.

FIG. 6 is a drawing for explaining the signal flow of a display device according to the first embodiment of the present invention.

Referring to FIG. 6 together with FIGS. 1 to 5, the output mute signal (Mute) generated and output from the timing control unit (10) may be transmitted to the gate drivers (G-ICs) disposed in the left non-display area and the right non-display area of the display panel (50) through the source drivers (S-PCBs) formed on the left and right sides of the display panel (50). For example, when the output mute signal (Mute) is transmitted to the first gate driver (G-IC, Left) disposed on the left side of the display panel (50), the first gate driver (G-IC, Left) may not output a scan signal to the left gate line of the display panel (50). In addition, when the output mute signal (Mute) is transmitted to the second gate driver (G-IC, Right) disposed on the right side of the display panel (50), the second gate driver (G-IC, Right) may not output a scan signal to the right gate line of the display panel (50). That is, the gate driver (G-IC) can output a scan signal to the gate line when the level of the output mute signal (Mute) changes from high to low.

In the present embodiment, the level high section of the second output signal (Mute_R) provided to the second gate driver (G-IC, Right) is formed longer than the level high section of the first output signal (Mute_L) provided to the first gate driver (G-IC, Left), so that the second scan signal (SCAN_R) can be output after the first scan signal (SCAN_L) is output. Accordingly, by preventing the first scan signal (SCAN_L) and the second scan signal (SCAN_R) from being applied to the display panel (50) at the same time, the image quality in the central portion of the display device (1) shown in FIG. 6 can be improved.

FIGS. 7 to 9 are diagrams showing a display device and its signal flow according to a second embodiment of the present invention. First, FIG. 7 is a structural diagram showing the connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to a second embodiment of the present invention.

Referring to FIG. 7, the configuration may be the same as that of the display device (1) according to the first embodiment of the present invention, except that a buffer is placed in the source driving unit (S-PCB).

Referring to FIG. 7 together with FIGS. 1 to 4, the timing control unit (10) supplies a start pulse (VSP) to the source driving unit (S-PCB). The start pulse (VSP) may be a signal for generating a scan signal provided to a gate line. For example, when the start pulse (VSP) is supplied from the timing control unit (10) to the source driving unit (S-PCB), the gate driving unit (G-IC) may sequentially output a scan signal to the gate line when the start pulse (VSP) is received through the source driving unit (S-PCB). The application time of the scan signal may be the same as the falling time of the start pulse (VSP).

The source driver (S-PCB) includes a first source driver (S-PCB, Left) and a second source driver (S-PCB, Right), and the first and second source drivers (S-PCBs) each include a buffer that controls input and output of a start pulse (VSP) applied to a gate driver (G-IC). The timing control unit (10) simultaneously supplies the first and second start pulses (VSP) to the first and second source drivers (S-PCBs). Specifically, the timing control unit (10) can supply the first start pulse (VSP) to the first source driver (S-PCB, Left) and the second start pulse (VSP) to the second source driver (S-PCB, Right).

The gate driver (G-IC) includes a first gate driver (G-IC, Left) and a second gate driver (G-IC, Right), and the source driver (S-PCB) transmits a start pulse (VSP) to the first and second gate drivers (G-IC). In one embodiment, the buffer (Left) of the first source driver (S-PCB, Left) may transmit the first start pulse (VSP) to the first gate driver (G-IC), and the buffer (Right) of the second source driver (S-PCB, Right) may transmit the second start pulse (VSP) to the second gate driver (G-IC). In this case, the buffers of the first and second source drivers (S-PCB) may control input/output of the first and second start pulses (VSP) and transmit them to the first and second gate drivers (G-IC), respectively. Specifically, after the buffer (Left) of the first source driver (S-PCB) applies a first start pulse (VPS) to the first gate driver (G-IC, Left), the buffer (Right) of the second source driver (S-PCB) can apply a second start pulse (VSP) to the second gate driver (G-IC, Right).

That is, even if the first and second start pulses (VSP) are supplied simultaneously from the timing control unit (10) to the first and second source driving units (S-PCB), the timings at which the first and second start pulses (VSP) are input to the first and second gate driving units (G-IC) can be different, respectively, by the buffers of the first and second source driving units (S-PCB). For example, the second start pulse (VSP) can be input to the second gate driving unit (G-IC, Right) after the first start pulse (VSP) is input to the first gate driving unit (G-IC, Left). Accordingly, the second scan signal (SCAN_R) can be output from the second gate driving unit (G-IC, Right) after the first scan signal (SCAN_L) is output from the first gate driving unit (G-IC, Left).

Accordingly, by preventing the first scan signal (SCAN_L) and the second scan signal (SCAN_R) from being applied simultaneously to the display panel (50), the load concentrated in the center of the display panel (50) can be dispersed compared to when the scan signals are applied simultaneously to the left gate line and the right gate line.

FIG. 8 illustrates a timing diagram of a start pulse transmitted to a gate driver through a source driver illustrated in FIG. 7 and a scan signal supplied from the gate driver to a gate line.

Referring to FIG. 8 together with FIGS. 1 to 3 and FIG. 7, the timing control unit (10) supplies a first start pulse (VSP) to the first source driving unit (S-PCB, Left) and supplies a second start pulse (VSP) to the second source driving unit (S-PCB, Right). The first gate driving unit (G-IC, Left) receives the first start pulse (VSP_L) from the first source driving unit (S-PCB, Left) and outputs a first scan signal (SCAN_L) to the left gate line of the display panel (50), and the second source driving unit (G-IC, Right) receives the second start pulse (VSP_R) from the second source driving unit (S-PCB, Right) and outputs a second scan signal (SCAN_R) to the right gate line of the display panel (50). For example, the first and second gate drivers (G-IC) can supply scan signals to the left and right gate lines of the display panel (50) when the levels of the first and second start pulses (VSP) change from high to low. Specifically, the first scan signal (SCAN_L) can be applied from the first gate driver (G-IC, Left) to the left gate line when the first start pulse (VSP_L) changes from the high level to the low level, and the second scan signal (SCAN_R) can be applied from the second gate driver (G-IC, Right) to the right gate line when the second start pulse (VSP) changes from the high level to the low level.

As in the embodiment illustrated in FIG. 8, the point in time when the first scan signal (SCAN_L) changes to the low level and the point in time when the second scan signal (SCAN_R) changes to the high level may be the same. In this case, the section between the point in time when the first scan signal (SCAN_L) changes to the high level and the point in time when the second scan signal (SCAN_R) changes to the high level may be defined as a delay. Alternatively, the second scan signal (SCAN_R) may change to the high level before the first scan signal (SCAN_L) changes to the low level after changing to the high level. That is, in this case, the high level section of the first scan signal (SCAN_L) and the high level section of the second scan signal (SCAN_R) may overlap each other. In this case, the delay may be relatively small. Alternatively, after a predetermined time has passed since the first scan signal (SCAN_L) changed to a low level, the second scan signal (SCAN_R) may change to a high level. That is, in this case, a gap corresponding to a predetermined time may exist between the high level section of the first scan signal (SCAN_L) and the high level section of the second scan signal (SCAN_R). In this case, the delay may be relatively large.

As described above, the time at which the first scan signal (SCAN_R) changes from a high level to a low level may be different from the time at which the second scan signal (SCAN_L) changes to a high level.

That is, in the present embodiment, the supply timing of the first scan signal (SCAN_L) output from the first gate driver (G-IC, Left) and the supply timing of the second scan signal (SCAN_R) output from the second gate driver (G-IC, Right) can be controlled using a buffer.

In one embodiment, the first and second start pulses (VSP) supplied from the timing control unit (10) have the same level high section and can be provided simultaneously to the first and second source driving units (S-PCB). The first and second source driving units (S-PCB) can each include a buffer that controls the input/output timing of the first and second start pulses (VSP) transmitted to the first and second gate driving units (G-IC). That is, even if the first and second output mute signals (Mute) are supplied simultaneously from the timing control unit (10), the application timing of the first scan signal (SCAN_L) output from the first gate driver (G-IC) and the application timing of the second scan signal (SCAN_R) output from the second gate driver (G-IC) may be different due to the difference in output timing between the first start pulse (VSP) output from the buffer of the first source driver (S-PCB, Left) and the second start pulse (VSP) output from the buffer of the second source driver (S-PCB, Right). For example, the second scan signal (SCAN_R) may be output from the second gate driver (G-IC, Right) after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left).

Accordingly, by preventing the first scan signal (SCAN_L) and the second scan signal (SCAN_R) from being applied simultaneously to the display panel (50), the load concentrated in the center of the display panel (50) can be dispersed compared to when the scan signals are applied simultaneously to the left gate line and the right gate line.

FIG. 9 is a drawing for explaining the signal flow of a display device according to the second embodiment of the present invention.

Referring to FIG. 9 together with FIGS. 1 to 3, 7 and 8, a start signal (VSP) generated and output by a timing control unit (10) may pass through a buffer of a source driver (S-PCB) provided on the left and right sides of a display panel (50) and be transmitted to a gate driver (G-IC) disposed in a left non-display area and a right non-display area of the display panel (50), respectively. In this case, the application timing of the first start signal (VSP_L) transmitted to the first gate driver (G-IC, Left) disposed on the left side of the display panel (50) and the application timing of the second start signal (VSP_R) transmitted to the second gate driver (G-IC, Right) disposed on the right side of the display panel (50) may be set differently.

In the present embodiment, after the first start signal (VSP_L) is applied to the first gate driver (G-IC, Left), the second start signal (VSP_R) can be applied to the second gate driver (G-IC, Right). Accordingly, after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left), the second scan signal (SCAN_R) can be output from the second gate driver (G-IC, Right). Accordingly, by preventing the first scan signal (SCAN_L) and the second scan signal (SCAN_R) from being applied to the display panel (50) at the same time, the image quality in the central portion of the display device (1) shown in FIG. 9 can be improved.

FIGS. 10 to 12 are diagrams showing a display device and its signal flow according to a third embodiment of the present invention. First, FIG. 10 shows a structural diagram showing the connection relationship between a timing control unit, a source driver unit, and a gate driver unit according to a third embodiment of the present invention.

Referring to FIG. 10, the configuration may be the same as that of the display device (1) according to the first embodiment of the present invention, except that a switching element is placed between the timing control unit (10) and the source driving unit (S-PCB).

Referring to FIG. 10 together with FIGS. 1 to 4, the control PCB (C-PCB) further includes a switching element, and the timing control unit (10) supplies a start pulse (VSP) to the switching element (10). The start pulse (VSP) may be a signal for generating a scan signal provided to a gate line.

An input terminal of the switching element may be connected to a timing control unit (10), and an output terminal of the switching element may be connected to a source driving unit (S-PCB). In one embodiment, the source driving unit (S-PCB) may include a first source driving unit (S-PCB, Left) arranged at a lower left side of the display panel (50) and a second source driving unit (S-PCB, Right) arranged at a lower right side of the display panel (50). That is, the switching element may be connected to be switched with either the first source driving unit (S-PCB, Left) or the second source driving unit (S-PCB, Right). Specifically, the switching element may supply a start pulse (VSP) signal to the first source driving unit (S-PCB, Left) while being connected to the first source driving unit (S-PCB, Left), and may supply a start pulse (VSP) signal to the second source driving unit (S-PCB, Right) while being connected to the second source driving unit (S-PCB, Right).

The gate driver (G-IC) may include a first gate driver (G-IC, Left) and a second gate driver (G-IC, Right), and the first source driver (S-PCB, Left) or the second source driver (S-PCB, Right) may transmit a start pulse (VSP) to the first gate driver (G-IC, Left) or the second gate driver (G-IC, Right).

Specifically, while the switching element is connected to the first source driving unit (S-PCB, Left), the switching element supplies a start pulse (VSP) to the first source driving unit (S-PCB, Left), and the first source driving unit (S-PCB, Left) transmits the start pulse (VSP) to the first gate driving unit (G-IC, Left). In addition, while the switching element is connected to the second source driving unit (S-PCB, Right), the switching element supplies a start pulse (VSP) to the second source driving unit (S-PCB, Right), and the second source driving unit (S-PCB, Right) transmits the start pulse (VSP) to the second gate driving unit (G-IC, Right). That is, the start pulse (VSP) can be provided to the first gate driving unit (G-IC, Left) or the second gate driving unit (G-IC, Right) depending on the connection of the switching element. That is, the timing at which the start pulse (VSP) is input to the first and second gate drivers (G-IC) by the switching element can be different.

That is, by providing a start pulse (VSP) to the first gate driver (G-IC, Left) or the second gate driver (G-IC, Right) using the switching element, the first scan signal (SCAN_L) and the second scan signal (SCAN_R) may not be applied to the display panel (50) at the same time. For example, since the switching element is connected to the second source driver (S-PCB, Right) after a time has elapsed since it is disconnected from the first source driver (S-PCB, Left), the first scan signal (SCAN_L) may be output from the first gate driver (G-IC, Left), and the second scan signal (SCAN_R) may be output from the second gate driver (G-IC, Right) after a time has elapsed. Accordingly, the load concentrated on the center of the display panel (50) may be distributed compared to when the scan signal is applied to the left gate line and the right gate line simultaneously.

Figure 11 illustrates a timing diagram of a start pulse transmitted to a gate driver through a source driver illustrated in Figure 10 and a scan signal supplied from the gate driver to a gate line.

Referring to FIG. 11 together with FIGS. 1 to 3 and FIG. 10, the timing control unit (10) can output a start pulse (VSP) to a switching element. The switching element can be connected to a first source driving unit (S-PCB, Left) for a preset time and then connected to a second source driving unit (S-PCB, Right) to transmit the start pulse (VSP). For example, the switching element can supply a first start pulse (VSP_L) to the first source driving unit (S-PCB, Left) while being connected to the first source driving unit (S-PCB, Left), and can supply a second start pulse (VSP_R) to the second source driving unit (S-PCB, Right) while being connected to the second source driving unit (S-PCB, Right).

The first source driver (S-PCB, Left) or the second source driver (S-PCB, Right) can receive a start pulse (VSP) from the switching element and provide the start pulse (VSP) to the first gate driver (G-IC, Left) arranged in the left non-display area of the display panel (50), or can provide the start pulse (VSP) to the second gate driver (G-IC, Right) arranged in the right non-display area of the display panel (50).

Specifically, the first gate driver (G-IC, Left) may receive a first start pulse (VSP_L) from the first source driver (S-PCB, Left) and output a first scan signal (SCAN_L) to the left gate line of the display panel (50), and the second source driver (G-IC, Right) may receive a second start pulse (VSP_R) from the second source driver (S-PCB, Right) and output a second scan signal (SCAN_R) to the right gate line of the display panel (50).

In one embodiment, the first and second gate drivers (G-IC) can supply scan signals to the left and right gate lines of the display panel (50) when the level of the start pulse (VSP) changes from high to low. Specifically, the first scan signal (SCAN_L) can be applied from the first gate driver (G-IC, Left) to the left gate line when the first start pulse (VSP_L) changes from the high level to the low level, and the second scan signal (SCAN_R) can be applied from the second gate driver (G-IC, Right) to the right gate line when the second start pulse (VSP_R) changes from the high level to the low level.

That is, the timing of applying the first scan signal (SCAN_L) output from the first gate driver (G-IC, Left) and the timing of applying the second scan signal (SCAN_R) output from the second gate driver (G-IC, Right) can be made different by using a switching element. For example, the second scan signal (SCAN_R) can be output from the second gate driver (G-IC, Right) after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left).

As in the embodiment illustrated in FIG. 11, the switching element (SW) can be sequentially connected to the second source driving unit (S-PCB, Right) after being disconnected from the first source driving unit (S-PCB, Left). For example, while connected to the first source driving unit (S-PCB, Left), a first start pulse (VSP_L) can be supplied to the first source driving unit (S-PCB, Left) to output a first scan signal (SCAN_L), and while connected to the second source driving unit (S-PCB, Right) after being disconnected from the first source driving unit (S-PCB, Left), a second start pulse (VSP_R) can be supplied to the second source driving unit (S-PCB, Right) to output a second scan signal (SCAN_R). In this case, the interval between the point in time when the first scan signal (SCAN_L) changes to a high level and the point in time when the second scan signal (SCAN_R) changes to a high level can be defined as a delay.

Meanwhile, FIG. 11 illustrates a case where the switching element (SW) is disconnected from the first source driving unit (S-PCB, Left) and then continuously connected to the second source driving unit (S-PCB, Right). In this case, the delay may be relatively small. In another embodiment, the switching element (SW) may be connected to the second source driving unit (S-PCB, Right) after a predetermined time has elapsed since the connection with the first source driving unit (S-PCB, Left) has been disconnected. That is, in this case, a gap corresponding to a predetermined time may exist between the high level section of the first scan signal (SCAN_L) and the high level section of the second scan signal (SCAN_R). In this case, the delay may be relatively large.

Therefore, in the present embodiment, by not simultaneously applying the first scan signal (SCAN_L) and the second scan signal (SCAN_R) to the display panel (50) using a switching element, the load concentrated in the center of the display panel (50) can be dispersed compared to when the scan signals are simultaneously applied to the left gate line and the right gate line.

FIG. 12 is a drawing for explaining the signal flow of a display device according to a third embodiment of the present invention.

Referring to FIG. 12 together with FIGS. 1 to 3, FIGS. 10 and 11, a start signal (VSP) generated in a timing control unit (10) is output to a switching element of a control PCB (C-PCB). The switching element can be connected to a first source driving unit (S-PCB, Left) or a second source driving unit (S-PCB, Right) for a preset time. Specifically, the switching element can supply a start pulse (VSP) to the first source driving unit (S-PCB, Left) while being connected to the first source driving unit (S-PCB, Left), and can supply a start pulse (VSP) to the second source driving unit (S-PCB, Right) while being connected to the second source driving unit (S-PCB, Right). Additionally, the first source driver (S-PCB, Left) can transmit a start pulse (VSP) to the first gate driver (G-IC, Left), and the second source driver (S-PCB, Right) can transmit a start pulse (VSP) to the second gate driver (G-IC, Right).

That is, the application timing of the start signal (VSP) transmitted to the first gate driver (G-IC, Left) and the application timing of the start signal (VSP) transmitted to the second gate driver (G-IC, Right) can be set differently by the operation of the switching element.

In the present embodiment, after the start signal (VSP) is applied to the first gate driver (G-IC, Left), the start signal (VSP) can be applied to the second gate driver (G-IC, Right). Accordingly, after the first scan signal (SCAN_L) is output from the first gate driver (G-IC, Left), the second scan signal (SCAN_R) can be output from the second gate driver (G-IC, Right). Accordingly, by preventing the first scan signal (SCAN_L) and the second scan signal (SCAN_R) from being applied to the display panel (50) at the same time, the image quality in the central portion of the display device (1) shown in FIG. 9 can be improved.

Those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing its technical idea or essential characteristics. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

1: Display device
10: Timing Control Unit
20: Gate drive unit
30: Data Drive
40: Power supply
50: Display panel

Claims (17)

A display panel including a display area and a non-display area;
A first gate driver arranged in a left non-display area of the display panel and supplying a first scan signal from the left side of any gate line of the display panel;
A first source driver for transmitting a first control signal to the first gate driver;
A second gate driver arranged in a non-display area on the right side of the display panel and supplying a second scan signal from the right side of any gate line;
A second source driver for transmitting a second control signal to the second gate driver; and
A timing control unit for supplying the first and second control signals is included,
The first gate driver supplies the first scan signal according to the first control signal, and the second gate driver supplies the second scan signal according to the second control signal, and the supply timing of the first scan signal and the supply timing of the second scan signal are different.
A display device, wherein the first control signal includes a first output clear signal, the second control signal includes a second output clear signal, and a falling point of the first output clear signal is different from a falling point of the second output clear signal.

delete In the first paragraph,
The first control signal includes a first output cancel signal, and the second control signal includes a second output cancel signal.
A display device, wherein the rising point of the first output erase signal is the same as the rising point of the second output erase signal, but the level high section of the first output erase signal is different from the level high section of the second output erase signal.
In the first paragraph,
The first control signal includes a first output cancel signal, and the second control signal includes a second output cancel signal.
A display device, wherein the timing at which the first source driver applies the first output erase signal to the first gate driver is different from the timing at which the second source driver applies the second output erase signal to the second gate driver.
In paragraph 4,
A display device, wherein the first source driving unit includes a first buffer that controls input and output of the first output cancel signal, and the second source driving unit includes a second buffer that controls input and output of the second output cancel signal.


delete delete In the first paragraph,
Further comprising a switching element connected to the timing control unit,
A display device, wherein the input terminal of the switching element is connected to the timing control unit, and the output terminal of the switching element is switched with one of the first source driving unit and the second source driving unit.
In Article 8,
A display device, wherein the switching element is connected to the first source driving unit for a preset time and then connected to the second source driving unit.
A step of supplying a first control signal to a first source driving unit;
A step of supplying the first control signal to a first gate driver arranged in a left non-display area of the display panel;
A step of supplying a first scan signal from the left side of any gate line arranged on the left side of the display panel according to the first control signal;
A step of supplying a second control signal to a second source driving unit;
A step of supplying the second control signal to a second gate driver arranged in a non-display area on the right side of the display panel; and
In accordance with the second control signal, a step of supplying a second scan signal from the arbitrary gate line arranged on the right side of the display panel is included.
The supply time of the first scan signal and the supply time of the second scan signal are different,
A method for driving a display device, wherein the first control signal includes a first output clear signal, the second control signal includes a second output clear signal, and a falling point in time of the first output clear signal is different from a falling point in time of the second output clear signal.

delete In Article 10,
The first control signal includes a first output cancel signal, and the second control signal includes a second output cancel signal.
A method for driving a display device, wherein the rising point of the first output erase signal is the same as the rising point of the second output erase signal, but the level high section of the first output erase signal is different from the level high section of the second output erase signal.
In Article 10,
The first control signal includes a first output cancel signal, and the second control signal includes a second output cancel signal.
A method for driving a display device, wherein the timing at which the first output erase signal is applied to the first gate driver is different from the timing at which the second output erase signal is applied to the second gate driver.
In Article 13,
A method for driving a display device, wherein the input/output of the first output erase signal is controlled by a first buffer included in the first source driving unit, and the input/output of the second output erase signal is controlled by a second buffer included in the second source driving unit.


delete delete In Article 10,
A method for driving a display device, wherein the first control signal is supplied to the first source driving unit while the switching element is connected to the first source driving unit, the second control signal is supplied to the second source driving unit while the switching element is connected to the second source driving unit, and the switching element is connected to the first source driving unit for a preset period of time and then connected to the second source driving unit.