KR102774103B1 - The method for manufacturing the printed circuit board - Google Patents

Abstract

A printed circuit board according to an embodiment includes a first insulating portion including a cavity; a second insulating portion arranged on an upper surface of the first insulating portion; a third insulating portion arranged below a lower surface of the first insulating portion; and an electronic component arranged within the cavity, wherein the cavity includes a first portion on a surface facing the third insulating portion and a second portion on a surface opposite to the first portion, and a width of the first portion is greater than a width of the second portion.

Description

{THE METHOD FOR MANUFACTURING THE PRINTED CIRCUIT BOARD}

The present invention relates to a printed circuit board, and more particularly, to a printed circuit board with built-in electronic components and a method for manufacturing the same.

Unlike conventional printed circuit boards in which passive and active components share the surface of the printed circuit board, embedded printed circuit boards have components such as resistors and capacitors built into the board, allowing for free space on the surface of the printed circuit board, which allows for higher wiring density than conventional printed circuit boards, enabling the development of more compact electronic devices.

In addition, these embedded printed circuit boards have the effect of reducing problems such as impedance generation and signal delay caused by parasitic effects in electronic devices that use high-frequency signals, as the components are connected vertically, greatly reducing the wiring length.

The core technologies of these embedded printed circuit boards are the technology for embedding components inside the board and the technology for precisely connecting the embedded components and wiring circuits.

In general, embedded printed circuit boards are manufactured by performing a cavity forming process in which an insulating layer is formed and then a component mounting area is removed. Then, conventionally, a component is mounted in the formed cavity, and an additional insulating layer is laminated on top and bottom of the insulating layer on which the component is mounted, thereby manufacturing an embedded printed circuit board.

The present invention provides a printed circuit board having a novel structure and a method for manufacturing the same.

In addition, the embodiment provides a printed circuit board and a method for manufacturing the same that can minimize the chip shift phenomenon that occurs during the process of filling a resin within a cavity.

In an embodiment, a printed circuit board having an asymmetrical structure and an electronic component embedded therein and a method for manufacturing the same are provided.

In addition, the embodiment provides a printed circuit board with built-in electronic components and a method for manufacturing the same, which can improve the degree of design freedom while reducing the thickness of the board.

The technical problems to be achieved in the proposed embodiment are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

A printed circuit board according to an embodiment includes a first insulating portion including a cavity; a second insulating portion arranged on an upper surface of the first insulating portion; a third insulating portion arranged below a lower surface of the first insulating portion; and an electronic component arranged within the cavity, wherein the cavity includes a first portion on a surface facing the third insulating portion and a second portion on a surface opposite to the first portion, and a width of the first portion is greater than a width of the second portion.

Additionally, the second insulating part includes a first part disposed within the cavity, and a second part disposed over the first insulating part and the first part.

Additionally, the third insulating portion is disposed below the lower surface of the first insulating portion and below the lower surface of the first part of the second insulating portion.

Additionally, the width of the first portion has a range of 1.5 to 2.5 times the width of the second portion.

In addition, the first insulating portion includes at least one first insulating layer; a first circuit pattern embedded in a lower portion of the first insulating layer; a second circuit pattern protruding above an upper surface of the first insulating layer; and a first via disposed within the first insulating layer and connecting the first and second circuit patterns.

Additionally, the first insulating layer includes a prepreg including glass fiber.

In addition, the second insulating portion includes a second insulating layer disposed inside the cavity and on the first insulating layer; a third circuit pattern disposed on an upper surface of the second insulating layer; and a second via disposed within the second insulating layer and connecting the second and third circuit patterns, wherein the second insulating layer includes an insulating material different from that of the first insulating layer.

Additionally, the second insulating layer is composed of RCC (Resin Coated Cu).

In addition, the third insulating portion includes a third insulating layer disposed under the first insulating layer; a third via disposed within the third insulating layer; and a fourth circuit pattern disposed under a lower surface of the third insulating layer; and the third insulating layer includes an insulating material different from the first and second insulating layers.

Additionally, the third insulating layer includes ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric).

Additionally, the third insulating layer has a thickness smaller than each of the first insulating layer and the second insulating layer.

In addition, the third via includes a first sub-third via that vertically overlaps the electronic component and is directly connected to a terminal of the electronic component, and a second sub-third via that is positioned at a position that does not vertically overlap the electronic component, and the first sub-third via has a width smaller than a width of the second sub-third via.

Additionally, the electronic element includes first and second electronic elements that are arranged at a set interval from each other within the cavity.

Meanwhile, a method for manufacturing a printed circuit board according to an embodiment includes a step of forming a first insulating portion; a step of forming a cavity penetrating the first insulating portion; a step of forming a film layer on one surface of the first insulating portion; a step of attaching an electronic component on the film layer exposed through the cavity; a step of forming a second insulating portion filling the cavity on the first insulating portion; a step of removing the film layer; and a step of forming a third insulating portion below the first insulating portion and the second insulating portion arranged in the cavity, wherein the cavity includes a first portion of a surface facing the film layer and a second portion of a surface opposite to the first portion, a width of the first portion is greater than a width of the second portion, and an insulating material constituting the second insulating portion is introduced through the second portion of the cavity.

In addition, the second insulating portion includes a first part disposed within the cavity, and a second part disposed above the first insulating portion and the first part, and the third insulating portion is disposed below a lower surface of the first insulating portion and a lower surface of the first part of the second insulating portion.

Additionally, the width of the first portion has a range of 1.5 to 2.5 times the width of the second portion.

According to an embodiment, a printed circuit board includes a first insulating portion in which a cavity in which an electronic component is placed is formed. At this time, the cavity has an asymmetrical structure with respect to a horizontal line in the center. Specifically, the cavity has a width of one side (e.g., the upper side) into which an insulating material filling the cavity is injected is greater than a width of the opposite side. Accordingly, when the cavity is filled with an insulating material, the insulating material can be filled from edges on both sides of the electronic component, thereby preventing the phenomenon in which the position of the electronic component moves due to resin flow. In other words, in the embodiment, an electronic component is placed in a cavity in which the upper and lower sides have different widths. In addition, in the embodiment, a resin is injected into a portion having a relatively small width to form an insulating portion in which the electronic component is embedded. Accordingly, the interconnectivity between a pad and a via hole can be improved by preventing shifting of the electronic component, and the reliability and durability of the product can be secured while reducing process issues and securing yields by minimizing connection failures.

In addition, according to an embodiment, the printed circuit board is arranged so that the circuit pattern or pad is embedded in the first insulating portion. Accordingly, since the circuit pattern or pad is embedded in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and the degree of design freedom can be improved. In addition, since the first insulating portion uses a prepreg containing glass fiber, it is possible to minimize panel breakage or warping that occurs when manufacturing a thin substrate.

In addition, according to an embodiment, the printed circuit board has a second insulating portion arranged under the first insulating portion. At this time, the second insulating portion forms an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric), which is a photosensitive insulating material) in an area in direct contact with the first insulating portion. According to this, in the embodiment, the thickness of the insulating layer of the second insulating portion can be reduced compared to the prior art, and the degree of design freedom can be improved.

In addition, according to an embodiment, by forming the second insulating portion on the area in direct contact with the first insulating portion using a film-type resin, a small via can be formed, and thus a fine pattern can be implemented.

FIG. 1a and FIG. 1b are drawings for explaining a printed circuit board according to a comparative example.
Figure 2 is a drawing for explaining the structure of a printed circuit board according to an embodiment.
Figures 3 to 15 are drawings for explaining the manufacturing method of the printed circuit board of Figure 2 in process order.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components among the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention can be interpreted as having a meaning that can be generally understood by a person having ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, can have their meanings interpreted in consideration of the contextual meaning of the related technology. In addition, terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and (or) at least one (or more) of B, C", it may include one or more of all combinations that can be combined with A, B, C. In addition, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the terms. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

Also, when it is described as being formed or arranged "above or below" each component, above or below includes not only the cases where the two components are in direct contact with each other, but also the cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above or below", it can include the meaning of the downward direction as well as the upward direction based on one component.

FIG. 1a and FIG. 1b are drawings for explaining a printed circuit board according to a comparative example.

The printed circuit board according to FIGS. 1a and 1b includes a first insulating layer (1), a second insulating layer (2), a circuit pattern (3), and a via (4).

The first insulating layer (1) and the second insulating layer (2) have a mutually laminated structure and include a cavity (Ca) in which electronic elements (6, 7) are arranged.

And, a circuit pattern (3) is arranged on at least one of the surfaces of the first insulating layer (1) and the second insulating layer (2).

Additionally, vias (4) are arranged within the first insulating layer (1) and the second insulating layer (2) to electrically connect circuit patterns arranged in different layers.

At this time, in the case of a printed circuit board with built-in electronic components, a process of removing the area where the electronic components (6, 7) are to be inserted by processing the area with a laser is necessary in order to insert the electronic components inside the board. And, this process is called cavity processing.

In addition, when a cavity (Ca) is formed in the first insulating layer (1) and the second insulating layer (2) as described above, a carrier film (5) that blocks one side of the cavity (Ca) is placed.

The carrier film (5) closes one side of the cavity (Ca) so that the electronic element (6, 7) can be fixedly placed within the cavity (Ca).

And, with the carrier film (5) placed, a process of filling the cavity (Ca) with an insulating material by filling the upper portion of the cavity (Ca) with an insulating material is performed.

At this time, in the printed circuit board in the comparative example according to Fig. 1a, the width of the surface on which the carrier film (5) is arranged centered on both sides of the cavity (Ca) is narrower than the width of the opposite surface. In other words, the width of the portion where the insulating material filling the cavity (Ca) is injected is larger than the width of the opposite portion.

In addition, in the case of the cavity (Ca) in the comparative example according to Fig. 1b, the cavity (Ca) has a symmetrical structure in which the upper and lower widths are the same, and accordingly, the inner wall of the cavity (Ca) has a shape that is substantially close to vertical.

At this time, in the case of the cavity (Ca) of the comparative example in FIGS. 1A and 1B as above, when pressure is applied during the lamination process of the insulating material, a larger amount of insulating material may be injected in the direction where the electronic element (6, 7) is located than in the edge region of the cavity (Ca), and a shift problem occurs in which the electronic element (6, 7) moves from the initial position toward the center due to the flow of the insulating material.

In other words, when the cavity (Ca) of the comparative example is laminated with an insulating material, a large amount of resin flows to both sides of the electronic element (6, 7) rather than the center due to the shape characteristics of the cavity (Ca), and a problem occurs in which the position of the electronic element (6, 7) fixed by the carrier film (5) shifts due to the resin flow.

In addition, when the position of the electronic element (6, 7) shifts, a misalignment occurs in the pad or via connected to the electronic element (6, 7), which causes a fatal problem in the reliability of the electrical connection.

Figure 2 is a drawing for explaining the structure of a printed circuit board according to an embodiment.

Referring to FIG. 2, the printed circuit board may include a first insulating portion, a second insulating portion, and a third insulating portion. The first insulating portion may include a central insulating layer, the second insulating portion may include an upper insulating layer disposed over the first insulating portion, and the third insulating portion may include a lower insulating layer disposed under the first insulating portion.

The first insulating portion includes an insulating layer in which electronic elements (300a, 300b) are embedded. To this end, the first insulating portion may include a first insulating layer (110) and a second insulating layer (125). In addition, a cavity (C) in which the electronic elements (300) are placed may be formed in the first insulating layer (110) and the second insulating layer (125). At this time, the first insulating portion may also be referred to as a core insulating portion, and accordingly, the first insulating layer (110) and the second insulating layer (125) may be referred to as core insulating layers.

The first insulating layer (110) and the second insulating layer (125) are substrates on which electric circuits capable of changing wiring are formed, and may include all of a print, wiring board, and insulating substrate made of an insulating material capable of forming at least one circuit pattern on the surface.

The first insulating layer (110) and the second insulating layer (125) may include glass or plastic. In detail, the first insulating layer (110) and the second insulating layer (125) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

At this time, a plurality of circuit patterns can be arranged on the surfaces of the first insulating layer (110) and the second insulating layer (125).

A first circuit pattern (105) may be embedded in the lower part of the first insulating layer (110). A second circuit pattern (120) may be arranged on the upper surface of the first insulating layer (110). In addition, a third circuit pattern (135) may be arranged on the upper surface of the second insulating layer (125). At this time, when the first insulating layer (110) and the second insulating layer (125) are viewed as one insulating layer, the circuit pattern arranged on the lower part is arranged to be embedded in the insulating layer, and the circuit pattern arranged on the upper part is arranged to be protruded on the insulating layer. That is, as shown in FIGS. 1A and 1B, in the printed circuit board of the comparative example, the circuit patterns arranged on the upper and lower parts with the insulating layer as the center are both formed to protrude from the upper and lower surfaces of the insulating layer. In contrast, in the embodiment, the first circuit pattern (105) may be embedded in the lower part of the first insulating layer (110). Accordingly, in the embodiment, the thickness of the insulating layer (to be described later, 150) disposed under the first insulating layer (110) can be reduced by the thickness of the first circuit pattern (105). That is, since the insulating layer is basically disposed while covering the circuit pattern, the thickness of the circuit pattern is determined by the basic offset thickness. On the other hand, in the embodiment, since the first circuit pattern (105) is disposed buried under the first insulating layer (110), the thickness of the insulating layer to be later laminated under the first insulating layer (110) can be reduced by about 12 to 18 ㎛ compared to the prior art.

In addition, the first circuit pattern (105), the second circuit pattern (120), and the third circuit pattern (135) are wirings that transmit electrical signals and may be formed of a metal material having high electrical conductivity. To this end, the first circuit pattern (105), the second circuit pattern (120), and the third circuit pattern (135) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern (105), the second circuit pattern (120), and the third circuit pattern (135) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern (105), the second circuit pattern (120), and the third circuit pattern (135) can be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern (105), the second circuit pattern (120), and the third circuit pattern (135) can be manufactured using conventional printed circuit board manufacturing processes such as the additive process, the subtractive process, the MSAP (Modified Semi Additive Process), and the SAP (Semi Additive Process), and a detailed description thereof is omitted here.

A first via (115) is formed within a first insulating layer (110). In addition, a second via (130) is formed within a second insulating layer (125). The first via (115) and the second via (130) electrically connect circuit patterns arranged in different layers to each other. The first via (115) can electrically connect the first circuit pattern (105) and the second circuit pattern (120). In addition, the second via (130) can electrically connect the second circuit pattern (120) and the third circuit pattern (135).

The first via (115) and the second via (130) may penetrate only one of the first insulating layer (110) and the second insulating layer (125), or alternatively, may be formed to commonly penetrate at least two insulating layers among the plurality of insulating layers. Accordingly, the first via (115) and the second via (130) electrically connect circuit patterns disposed on the surfaces of different insulating layers to each other.

The first via (115) and the second via (130) can be formed by filling the interior of a through hole (not shown) penetrating at least one of the first insulating layer (110) and the second insulating layer (125) with a conductive material.

The above through hole can be formed by any one of mechanical, laser and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling and routing can be used, and when the through hole is formed by laser processing, a UV or _CO2 laser method can be used, and when the through hole is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. can be used to open at least one of the plurality of insulating layers.

Meanwhile, the processing by the laser is a cutting method that focuses optical energy on a surface to melt and vaporize part of the material, thereby forming a desired shape. It can easily process complex shapes using a computer program, and can also process composite materials that are difficult to cut using other methods.

In addition, the processing using the laser has the advantage of a cutting diameter of at least 0.005 mm and a wide range of processable thicknesses.

For the above laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a _CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper layer and the insulating layer, and the _CO2 laser is a laser that can process only the insulating layer.

When the above through hole is formed, the inside of the through hole can be filled with a conductive material to form a first via (115) and a second via (130). The metal material forming the first via (115) and the second via (130) can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

Electronic elements (300a, 300b) may be embedded in a cavity (C) commonly formed in the first insulating layer (110) and the second insulating layer (125). That is, a first electronic element (300a) and a second electronic element (300b) may be embedded in the cavity (C) at a set distance from each other.

The above electronic components (300a, 300b) may be electronic parts such as chips, and may be divided into active components and passive components. In addition, the active components are components that actively utilize nonlinear portions, and the passive components refer to components that do not utilize nonlinear characteristics even though both linear and nonlinear characteristics exist. In addition, the passive components may include transistors, IC semiconductor chips, and the like, and the passive components may include capacitors, resistors, inductors, and the like. The passive components are mounted on a typical printed circuit board to increase the signal processing speed of the active component semiconductor chip, or to perform a filtering function, and the like.

The above electronic components (300a, 300b) may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smartphone, the electronic components (300a, 300b) may be control components.

Terminals (310a, 310b) may be formed on the lower surfaces of the electronic components (300a, 300b), respectively. At this time, the lower surfaces of the terminals (310a, 310b) may be arranged on the same plane as the lower surface of the first insulating layer (110). The lower surfaces of the terminals (310a, 310b) may be arranged on the same plane as the lower surface of the first circuit pattern (105). Meanwhile, the upper surfaces of the electronic components (300a, 300b) may be arranged on the same plane as the upper surface of the second insulating layer (125). Preferably, the upper surfaces of the electronic components (300a, 300b) may be arranged lower than the upper surface of the second insulating layer (125). That is, the cavity (C) may have the same thickness as the electronic component (300a, 300b), and may have a thickness greater than the thickness of the electronic component (300a, 300b) in order to improve reliability. Preferably, the cavity (C) may have a thickness greater than the thickness of the electronic component (300a, 300b) by about 10 ㎛. Accordingly, the upper surface of the electronic component (300a, 300b) may be positioned lower than the upper surface of the second insulating layer (125). In addition, the width of the cavity (C) may have a width greater than the total width of the electronic component (300a, 300b) in order to ensure stable placement of the electronic component (300a, 300b).

Here, the first insulating portion has a structure in which the first circuit pattern (105) is embedded in the lower part of the first insulating layer (110), rather than a structure in which the first circuit pattern (105) protrudes from the lower surface of the first insulating layer (110) as compared to the existing structure. This can be achieved by a differentiated manufacturing process in the embodiment, rather than a general printed circuit board manufacturing process. This will be described in more detail below.

According to an embodiment, a printed circuit board includes a first insulating portion having a cavity formed in which an electronic component is arranged. Then, a circuit pattern or a pad is disposed so as to be embedded in the first insulating portion. Accordingly, since the circuit pattern or pad is disposed so as to be embedded in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to a conventional one, and the degree of design freedom can be improved. In addition, since the first insulating portion uses a prepreg including glass fiber, it is possible to minimize panel breakage or warping that occurs when manufacturing a thin substrate.

Meanwhile, as described above, the cavity (C) in the embodiment may have an upper width smaller than a lower width. Preferably, the width of the portion where the insulating material filling the cavity (C) is laminated may be smaller than the width of the opposite portion. This will be described in more detail below.

A second insulating portion may be arranged on the first insulating portion, and a third insulating portion may be arranged below the first insulating portion. In this case, in one embodiment, the second insulating portion may be composed of a single insulating layer, and the third insulating portion may be composed of a plurality of insulating layers.

At this time, the insulating layer constituting the second insulating portion, some insulating layers constituting the third insulating portion, and the insulating layer constituting the first insulating portion may all be composed of different insulating materials. That is, as described above, the first insulating layer (110) and the second insulating layer (125) of the first insulating portion may be formed of a prepreg including glass fiber.

In contrast, the third insulating layer (140) constituting the second insulating portion may be composed of RCC (Resin Coated Cu). At this time, the third insulating layer (140) is disposed on the second insulating layer (125), while also being disposed within the cavity (C) formed in the second insulating layer (125) and the first insulating layer (110). That is, the third insulating layer (140) may be disposed on the second insulating layer (125) with a certain thickness while filling the cavity (C).

Here, the meaning that the third insulating layer (140) is placed on the second insulating layer (125) while filling the cavity (C) means that the second insulating part is laminated before the third insulating part placed below the first insulating part.

In other words, this means that the lamination of the insulating material within the cavity (C) was performed in the direction in which the second insulating portion is located.

At this time, the width of the portion of the cavity (C) facing the second insulating portion is smaller than the width of the portion facing the third insulating portion. In other words, the upper portion of the cavity (C) may have a first width (W1), and the lower portion of the cavity (C) may have a second width (W2) greater than the first width (W1).

As described above, in the embodiment, the width of the upper part of the cavity (C) is made smaller than the width of the lower part, and accordingly, the second insulating part filling the cavity (C) is laminated from the upper part where the width is smaller. Accordingly, the space at the lower part of the cavity (C) is relatively larger than the space at the upper part, and accordingly, the insulating material forming the second insulating part is slowly filled from the edge area of the cavity (C), and accordingly, the electronic element (300a, 300b) can be prevented from moving toward the center due to the resin flow.

At this time, the second width (W2) is set to have a range of 1.5 to 2.5 times the first width (W1). If the second width (W2) is smaller than 1.5 times the first width (W1), the flow direction of the resin cannot be formed in the edge area of the cavity (C), and thus, a problem of shifting of the electronic component may occur. In addition, if the second width (W2) is larger than 2.5 times the first width (W1), the area of the cavity (C) increases, and thus, waste of the insulating material for filling the cavity (C) may occur. In addition, if the second width (W2) is larger than 2.5 times the first width (W1), a bend may occur on the upper surface of the third insulating layer (140) as described below, and thus, a problem of reliability may occur.

In addition, as described above, the third insulating layer (140) should be disposed on the second insulating layer (125) with a uniform thickness while stably filling the cavity (C). At this time, a certain curvature may be formed on the upper surface of the third insulating layer (140) depending on the area of the cavity (C). This is because the thickness of the third insulating layer (140) in the area where the cavity (C) exists and the other area are different from each other. Accordingly, in the embodiment, the third insulating layer (140) is formed in the RCC type as described above, thereby solving the above problems and manufacturing a reliable substrate.

A fourth circuit pattern (145) may be arranged on the upper surface of the third insulating layer (140). In addition, a third via may be arranged through the third insulating layer (140). The third via may electrically connect the third circuit pattern (135) arranged on the second insulating layer (125) and the fourth circuit pattern (145) arranged on the third insulating layer (140).

In addition, a first external insulating layer (170) may be arranged on the third insulating layer (140). In addition, a first external circuit pattern (175) may be arranged on the upper surface of the first external insulating layer (170), and a via (180) may be arranged within the first external insulating layer (170).

Meanwhile, a third insulating portion is arranged under the first insulating portion. Unlike the second insulating portion, the third insulating portion has a multiple insulating layer structure. Accordingly, in the embodiment, the first insulating portion on which the electronic elements (300a, 300b) are arranged may have a symmetrical structure, or may have an asymmetrical structure.

The third insulating member may include a fourth insulating layer (150) positioned under the first insulating layer (110) and a second outer insulating layer (170) positioned under the fourth insulating layer (150).

At this time, the fourth insulating layer (150) and the second outer insulating layer (170) may be formed of the same insulating material, or may be formed of different insulating materials.

Preferably, the fourth insulating layer (150) may be formed of a different insulating material than the second outer insulating layer (170).

The second outer insulating layer (170) may be formed of the same insulating material as the first insulating layer (110) and the second insulating layer (125).

The second outer insulating layer (170) may include glass fiber or plastic. In detail, the second outer insulating layer (170) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

And, the fourth insulating layer (150) can be formed of a film type resin. Preferably, the fourth insulating layer (150) can be formed of a film type prepreg. Preferably, the fourth insulating layer (150) can be formed of ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric), which is a photosensitive insulating material.

The fourth insulating layer (150) has a certain thickness and is arranged under the first insulating layer (110). At this time, the first insulating layer (110) does not have a circuit pattern protruding through the lower surface. That is, the first circuit pattern (105) is formed by being buried under the first insulating layer (110). Therefore, the fourth insulating layer (150) can be formed without considering the thickness of the circuit pattern. That is, a general insulating layer is arranged to cover the circuit pattern while providing stable interlayer insulation, and for this purpose, the final thickness can be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer (140), the thickness should be determined in consideration of the thickness of the third circuit pattern (135) arranged on the second insulating layer (125). That is, when the thickness of the third circuit pattern (135) is 12 μm, the thickness of the third insulating layer (140) can be 20 μm. In addition, when the thickness of the third insulating layer (140) is 10 ㎛, the thickness of the third insulating layer (140) may be 15 ㎛. On the other hand, the fourth insulating layer (150) may be formed without considering the thickness of the circuit pattern, and thus may be formed with a thin thickness of about 10 ㎛.

That is, the thickness of the fourth insulating layer (150) is smaller than the thicknesses of the first insulating layer (110), the second insulating layer (125), the third insulating layer (140), the first external insulating layer (170), and the second external insulating layer (170).

A fifth circuit pattern (160) may be arranged on the lower surface of the fourth insulating layer (150). In addition, a fourth via (155a) and a fifth via (155b) may be included within the fourth insulating layer (150).

At this time, the fifth circuit pattern (160) formed on the lower surface of the fourth insulating layer (150) may have a different line width from the other circuit patterns. Preferably, the fifth circuit pattern (160) may have a smaller line width than the circuit patterns arranged in other layers. In addition, the fifth circuit pattern (160) may have a smaller pitch than the circuit patterns arranged in other layers. This can be achieved by the physical properties of the fifth insulating layer (165).

Meanwhile, a fourth via (155a) and a fifth via (155b) are formed in the fourth insulating layer (150). The fourth via (155a) is a via directly connected to the terminal (310) of the electronic device (300), and the fifth insulating layer (165) is a via connected to the first circuit pattern (105). Preferably, the fourth via (155a) may overlap with the electronic device (300a, 300b) in the vertical direction, and the fifth via (155b) may not overlap with the electronic device (300) in the vertical direction. In addition, the fourth via (155a) and the fifth via (155b) may have different widths. That is, the width of the via formed in the fourth insulating layer (150) may be formed smaller than that of the via formed in other layers. At this time, if all vias arranged in the fourth insulating layer (150) are formed as small vias, a problem may occur in alignment with vias arranged in other layers. In contrast, if all vias arranged in the fourth insulating layer (150) are formed with the same width as vias arranged in other layers, the reliability of the vias connected to the terminals (310a, 310b) of the electronic device (300) may decrease. Accordingly, in the embodiment, the fourth via (155a) and the fifth via (155b) arranged in the same layer are formed with different widths according to their respective functions. That is, since the fifth via (155b) is connected to the vias of other layers, it may have the same width as the vias of the other layers. Accordingly, the fifth via (155b) may have a minimum width of 40 μm. Preferably, the fifth via (155b) may have a width of between 40 μm and 100 μm.

Meanwhile, the fourth via (155a) is formed as a small via as it is directly connected to the terminal (310a, 310b) of the electronic device (300a, 300b). Preferably, the fourth via (155a) has a smaller width than the fifth via (155b). For example, the fourth via (155a) may have a width of 10 μm to 35 μm. For example, the fourth via (155a) may have a width of 20 μm to 25 μm.

A protective layer (190) may be placed on the first and second outer insulating layers (170).

The protective layer (190) can be formed of at least one layer using one or more of SR (Solder Resist), oxide, and Au.

According to an embodiment, a printed circuit board includes a first insulating portion in which a cavity in which an electronic component is placed is formed. At this time, the cavity has an asymmetrical structure with respect to a horizontal line in the center. Specifically, the cavity has a width of one side (e.g., the upper side) into which an insulating material filling the cavity is injected, which is greater than a width of the opposite side. Accordingly, when the cavity is filled with an insulating material, the insulating material can be filled from edges on both sides of the electronic component, thereby preventing the phenomenon in which the position of the electronic component moves due to the resin flow. In other words, in the embodiment, an electronic component is placed in a cavity in which the upper and lower sides have different widths. In addition, in the embodiment, a resin is injected into a portion having a relatively small width to form an insulating portion in which the electronic component is embedded. Accordingly, the interconnectivity between a pad and a via hole can be improved by preventing shifting of the electronic component, and the reliability and durability of the product can be secured while reducing process issues and securing yields by minimizing connection failures.

In addition, according to an embodiment, the printed circuit board is arranged so that the circuit pattern or pad is embedded in the first insulating portion. Accordingly, since the circuit pattern or pad is embedded in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and the degree of design freedom can be improved. In addition, since the first insulating portion uses a prepreg containing glass fiber, it is possible to minimize panel breakage or warping that occurs when manufacturing a thin substrate.

In addition, according to an embodiment, the printed circuit board has a second insulating portion arranged under the first insulating portion. At this time, the second insulating portion forms an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric), which is a photosensitive insulating material) in an area in direct contact with the first insulating portion. According to this, in the embodiment, the thickness of the insulating layer of the second insulating portion can be reduced compared to the prior art, and the degree of design freedom can be improved.

In addition, according to an embodiment, by forming the second insulating portion on the area in direct contact with the first insulating portion using a film-type resin, a small via can be formed, and thus a fine pattern can be implemented.

Hereinafter, a manufacturing process of the printed circuit board illustrated in FIG. 2 will be described. The manufacturing method of the printed circuit board in the embodiment may include a first process for having a structure in which a first circuit pattern is embedded and arranged within a first insulating layer (110), a second process for arranging electronic components (300a, 300b) within a first insulating portion, and a third process for laminating second and third insulating portions above and below the first insulating portion, respectively.

Figures 3 to 15 are drawings for explaining the manufacturing method of the printed circuit board of Figure 2 in process order.

Referring to Fig. 3, first, a carrier board (CB) for manufacturing the first insulating part is prepared. The carrier board (CB) may be a substrate that serves as a basis for manufacturing a printed circuit board. The carrier board (CB) may have a structure in which a metal layer (20) is formed on both sides with a support substrate (10) as the center.

Carrier board (CB) is a general support substrate and can use CCL (Copper Claded Laminate).

Meanwhile, the surface of the metal layer (20) of the carrier board (CB) may be subjected to surface treatment to facilitate subsequent separation from the first insulating portion.

Next, referring to Fig. 5, a first circuit pattern (105) is formed on a carrier board (CB). The first circuit pattern (105) can be formed on each of both sides of the carrier board (CB).

The first circuit pattern (105) can be formed by plating a metal material on the metal layer (20) using the metal layer (20) as a seed layer. Alternatively, the first circuit pattern (105) can be formed by forming a plating layer (not shown) on the metal layer (20) and etching the formed plating layer.

The first circuit pattern (105) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern (105) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern (105) may be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern (105) can be manufactured using conventional printed circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed description thereof is omitted here.

Next, referring to Fig. 6, a first insulating layer (110) is formed on the metal layer (20) on which the first circuit pattern (105) is formed. At this time, a copper layer may be present on the first insulating layer (110).

The above first insulating layer (110) can be formed of a prepreg containing glass fiber.

Preferably, the first insulating layer (110) may include glass or plastic. In detail, the first insulating layer (110) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

And, a first via (115) can be formed within the first insulating layer (110).

The first via (115) above can be formed by filling the inside of a through hole (not shown) penetrating the first insulating layer (110) with a conductive material. The through hole can be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used, and when the through hole is formed by laser processing, a UV or CO ₂ laser method can be used, and when the through hole is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. can be used to open at least one of the plurality of insulating layers.

Meanwhile, the processing by the laser is a cutting method that focuses optical energy on a surface to melt and vaporize part of the material, thereby forming a desired shape. It can easily process complex shapes using a computer program, and can also process composite materials that are difficult to cut using other methods.

In addition, the processing using the laser has the advantage of a cutting diameter of at least 0.005 mm and a wide range of processable thicknesses.

For the above laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a _CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper layer and the insulating layer, and the _CO2 laser is a laser that can process only the insulating layer.

When the above through hole is formed, the inside of the through hole can be filled with a conductive material to form a first via (115). The metal material forming the first via (115) can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

Next, when the first via (115) is formed, a second circuit pattern (120) can be formed on the upper surface of the first insulating layer (110).

At this time, the formation process of the first insulating layer (110), the first via (115), and the second circuit pattern (120) can be performed simultaneously on both sides of the carrier board (CB).

Next, referring to FIG. 6, a second insulating layer (125) is laminated on the first insulating layer (110). Then, a second via (120) is formed in the second insulating layer (125). In addition, a third circuit pattern (135) is formed on the upper surface of the second insulating layer (125). At this time, the second insulating layer (125) may be formed of a prepreg including the same glass fiber as the first insulating layer (110).

At this time, the formation process of the second insulating layer (125), the second via (120), and the third circuit pattern (135) can be performed simultaneously on both sides of the carrier board (CB).

Next, referring to FIG. 7, a process of separating the first insulating portions formed at the upper and lower portions from the carrier board (CB) may be performed. Accordingly, in the embodiment, a plurality of first insulating portions may be manufactured simultaneously in one process. In addition, according to the embodiment, a first circuit pattern (105) may be embedded in the lower portion of the first insulating layer (110). A second circuit pattern (120) may be arranged on the upper surface of the first insulating layer (110). In addition, a third circuit pattern (135) may be arranged on the upper surface of the second insulating layer (125). At this time, when the first insulating layer (110) and the second insulating layer (125) are viewed as one insulating layer, the circuit pattern arranged at the lower portion is arranged while being embedded in the insulating layer, and the circuit pattern arranged at the upper portion is arranged while protruding on the insulating layer. That is, in the past, both the circuit patterns arranged at the upper and lower portions were formed while protruding from the upper and lower surfaces of the insulating layer. In contrast, in the embodiment, the first circuit pattern (105) can be embedded in the lower portion of the first insulating layer (110). Accordingly, in the embodiment, the thickness of the fourth insulating layer (150) disposed under the first insulating layer (110) can be reduced by the thickness of the first circuit pattern (105). That is, since the insulating layer is basically disposed while covering the circuit pattern, the thickness of the circuit pattern is determined by the basic offset thickness. In contrast, in the embodiment, since the first circuit pattern (105) is embedded in the lower portion of the first insulating layer (110), the thickness of the insulating layer to be laminated under the first insulating layer (110) in the future can be reduced by about 12 to 18 ㎛ compared to the prior art.

When the first insulating portion is manufactured, a cavity (C) can be formed in the first insulating portion. The cavity (C) can be formed by commonly penetrating the first insulating layer (110) and the second insulating layer (125). That is, the cavity (C) can have the same thickness as the electronic device (300), and can have a thickness greater than the thickness of the electronic device (300a, 300b) in order to improve reliability. Preferably, the cavity (C) can have a thickness greater than the thickness of the electronic device (300a, 300b) by about 10 ㎛. Therefore, the upper surface of the electronic device (300) can be positioned lower than the upper surface of the second insulating layer (125). In addition, the width of the cavity (C) may be larger than the width of the electronic components (300a, 300b) for stable placement of the electronic components (300). The cavity (C) may be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used, and when it is formed by laser processing, a UV or CO ₂ laser method may be used, and when it is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. may be used to open the first insulating layer (110) and the second insulating layer (125).

At this time, the width of the portion of the cavity (C) facing the second insulating portion is smaller than the width of the portion facing the third insulating portion. In other words, the upper portion of the cavity (C) may have a first width (W1), and the lower portion of the cavity (C) may have a second width (W2) greater than the first width (W1).

As described above, in the embodiment, the width of the upper part of the cavity (C) is made smaller than the width of the lower part, and accordingly, the second insulating part filling the cavity (C) is laminated from the upper part where the width is smaller. Accordingly, the space at the lower part of the cavity (C) is relatively larger than the space at the upper part, and accordingly, the insulating material forming the second insulating part is slowly filled from the edge area of the cavity (C), and accordingly, the electronic element (300a, 300b) can be prevented from moving toward the center due to the resin flow.

At this time, the second width (W2) is set to have a range of 1.5 to 2.5 times the first width (W1). If the second width (W2) is smaller than 1.5 times the first width (W1), the flow direction of the resin cannot be formed in the edge area of the cavity (C), and thus, a problem of shifting of the electronic component may occur. In addition, if the second width (W2) is larger than 2.5 times the first width (W1), the area of the cavity (C) increases, and thus, waste of the insulating material for filling the cavity (C) may occur. In addition, furthermore, if the second width (W2) is larger than 2.5 times the first width (W1), a bend may occur on the upper surface of the third insulating layer (140) as described below, and thus, a problem of reliability may occur.

Here, the portion having the first width (W1) means the surface opposite to the surface on which the film layer (A) is later placed. And, the portion having the second width (W2) larger than the first width (W1) means the surface on which the film layer (A) is later placed (or attached).

Next, referring to FIG. 8, a film layer (A) is formed on the lower surface of the first insulating layer (110). The film layer (A) is attached to the lower surface of the first insulating layer (110), and thus can be arranged to cover the lower portion of the cavity (C). The film layer (A) can be arranged to cover one surface of the cavity (C) in order to arrange and fix an electronic device (300) within the cavity (C). The film layer (A) can use a polyimide film, but is not limited thereto.

Preferably, the film layer (A) can be attached to a portion having a relatively large width among the upper and lower portions of the cavity (C). That is, the upper portion of the cavity (C) has a first width (W1), and the lower portion of the cavity (C) has a second width (W2) larger than the first width (W1), and accordingly, the film layer (A) closes the lower portion of the cavity (C) having the large width and can be attached to the lower surface of the first insulating layer (110).

Next, referring to FIG. 9, electronic components (300a, 300b) are attached on the film layer (A) exposed through one surface of the cavity (C). The electronic components (300a, 300b) may be electronic components such as chips, and may be divided into active components and passive components. In addition, the active components are components that actively utilize nonlinear portions, and the passive components refer to components that do not utilize nonlinear characteristics even though both linear and nonlinear characteristics exist. In addition, the passive components may include transistors, IC semiconductor chips, and the like, and the passive components may include capacitors, resistors, inductors, and the like. The passive components are mounted on a typical printed circuit board in order to increase the signal processing speed of the active component semiconductor chip, or to perform a filtering function, and the like.

The above electronic components (300a, 300b) may vary depending on the application to which the printed circuit board is applied. For example, when applied to a NAND flash memory product applied to a smartphone, the electronic components (300a, 300b) may be control components.

A terminal (310a, 310b) may be formed on the lower surface of the electronic component (300a, 300b). At this time, the lower surface of the terminal (310a, 310b) may be arranged on the same plane as the lower surface of the first insulating layer (110). The lower surface of the terminal (310a, 310b) may be arranged on the same plane as the lower surface of the first circuit pattern (105). Meanwhile, the upper surface of the electronic component (300a, 300b) may be arranged on the same plane as the upper surface of the second insulating layer (125). Preferably, the upper surface of the electronic component (300a, 300b) may be arranged lower than the upper surface of the second insulating layer (125). That is, the cavity (C) may have the same thickness as the electronic component (300a, 300b), and may have a thickness greater than the thickness of the electronic component (300a, 300b) in order to improve reliability. Preferably, the cavity (C) may have a thickness greater than the thickness of the electronic component (300a, 300b) by about 10 ㎛. Accordingly, the upper surface of the electronic component (300a, 300b) may be positioned lower than the upper surface of the second insulating layer (125). In addition, the width of the cavity (C) may have a width greater than the width of the electronic component (300a, 300b) in order to ensure stable placement of the electronic component (300a, 300b).

However, the embodiment is not limited thereto, and the electronic components (300a, 300b) may be attached on the film layer (A) such that the terminals (310a, 310b) face upward. Here, what is important is that the film layer (A) in the present embodiment is arranged to close one side of a cavity (C) having a relatively large width, and an insulating material filling the cavity (C) is laminated on the other side of the cavity (C) having a relatively small width.

Next, referring to FIG. 10, a second insulating portion is formed on the first insulating portion. That is, when the process of arranging the electronic components (300a, 300b) is completed, a third insulating layer (140) is formed on the second insulating layer (125). The third insulating layer (140) may be composed of RCC (Resin Coated Cu). At this time, the third insulating layer (140) is arranged on the second insulating layer (125), while also being arranged in the cavity (C) formed in the second insulating layer (125) and the first insulating layer (110). That is, the third insulating layer (140) may be arranged on the second insulating layer (125) with a certain thickness while filling the cavity (C).

That is, as described above, the third insulating layer (140) should be placed on the second insulating layer (125) with a uniform thickness while stably filling the cavity (C). At this time, a certain curvature may be formed on the upper surface of the third insulating layer (140) depending on the area of the cavity (C). This is because the thickness of the third insulating layer (140) in the area where the cavity (C) exists and the other area are different from each other. Accordingly, in the embodiment, the third insulating layer (140) is formed in the RCC type as described above, thereby solving the above-described problem and manufacturing a reliable substrate.

In addition, the third insulating layer (140) is laminated through the other surface of the cavity (C) having a relatively small width as described above, thereby solving the shift problem of the electronic elements (300a, 300b) attached on the film layer (A) due to the flow of the resin constituting the third insulating layer (140).

In addition, a copper-coated coating layer (141) may be formed on the third insulating layer (140). The coating layer (141) may be a metal layer for forming a fourth circuit pattern (145) later.

Next, as shown in Fig. 11, when the formation of the third insulating layer (140) is completed, the film layer (A) attached under the second insulating layer (125) is removed.

Next, referring to FIG. 12, a fourth insulating layer (150) is formed under the first insulating layer (110). At this time, the fourth insulating layer (150) may be formed of an insulating material different from the first insulating layer (110), the second insulating layer (125), and the third insulating layer (140). Preferably, the fourth insulating layer (150) may be formed of a film-type resin. Preferably, the fourth insulating layer (150) may be formed of a film-type prepreg. Preferably, the fourth insulating layer (150) may be formed of an ABF (Aginomoto Build-up Film) or a PID (Photo Imagable Dielectric), which is a photosensitive insulating material.

The fourth insulating layer (150) has a certain thickness and is arranged under the first insulating layer (110). At this time, the first insulating layer (110) does not have a circuit pattern protruding through the lower surface. That is, the first circuit pattern (105) is formed by being buried under the first insulating layer (110). Therefore, the fourth insulating layer (150) can be formed without considering the thickness of the circuit pattern. That is, a general insulating layer is arranged to cover the circuit pattern while providing stable interlayer insulation, and for this purpose, the final thickness can be determined based on the thickness of the circuit pattern. For example, in the case of the third insulating layer (140), the thickness should be determined in consideration of the thickness of the third circuit pattern (135) arranged on the second insulating layer (125). That is, when the thickness of the third circuit pattern (135) is 12 μm, the thickness of the third insulating layer (140) can be 20 μm. In addition, when the thickness of the third insulating layer (140) is 10 ㎛, the thickness of the third insulating layer (140) may be 15 ㎛. On the other hand, the fourth insulating layer (150) may be formed without considering the thickness of the circuit pattern, and thus may be formed with a thin thickness of about 10 ㎛.

That is, the thickness of the fourth insulating layer (150) may be smaller than each of the thicknesses of the first insulating layer (110), the second insulating layer (125), and the third insulating layer (140).

Next, a fifth circuit pattern (160) can be formed on the lower surface of the fourth insulating layer (150). In addition, a fourth via (155a) and a fifth via (155b) can be formed within the fourth insulating layer (150).

At this time, the fifth circuit pattern (160) formed on the lower surface of the fourth insulating layer (150) may have a different line width from the other circuit patterns. Preferably, the fifth circuit pattern (160) may have a smaller line width than the circuit patterns arranged in other layers. In addition, the fifth circuit pattern (160) may have a smaller pitch than the circuit patterns arranged in other layers. This may be achieved by the physical properties of the fifth insulating layer (165).

Meanwhile, a fourth via (155a) and a fifth via (155b) are formed in the fourth insulating layer (150). The fourth via (155a) is a via directly connected to a terminal (310a, 310b) of an electronic device (300a, 300b), and the fifth via (155b) is a via connected to the first circuit pattern (105). Preferably, the fourth via (155a) may overlap with the electronic device (300a, 300b) in the vertical direction, and the fifth via (155b) may not overlap with the electronic device (300a, 300b) in the vertical direction. In addition, the fourth via (155a) and the fifth via (155b) may have different widths. That is, the width of the via formed in the fourth insulating layer (150) may be formed smaller than the vias formed in other layers. At this time, if all the vias arranged in the fourth insulating layer (150) are formed as small vias, a problem may occur in alignment with the vias arranged in other layers. In contrast, if all the vias arranged in the fourth insulating layer (150) are formed with the same width as the vias arranged in other layers, the reliability of the vias connected to the terminal (310) of the electronic device (300) may be reduced. Accordingly, in the embodiment, the fourth via (155a) and the fifth via (155b) arranged in the same layer are formed with different widths according to their respective functions. That is, since the fifth via (155b) is connected to the vias of other layers, it may have the same width as the vias of the other layers. For example, the fifth via (155b) may have a minimum width of 40 μm. Preferably, the fifth via (155b) may have a width of between 40 μm and 100 μm.

Meanwhile, the fourth via (155a) is formed as a small via as it is directly connected to the terminal (310a, 310b) of the electronic device (300a, 300b). Preferably, the fourth via (155a) has a smaller width than the fifth via (155b). For example, the fourth via (155a) may have a width of 10 μm to 35 μm. For example, the fourth via (155a) may have a width of 20 μm to 25 μm.

Next, referring to Fig. 13, the first and second external insulating layers (170) are laminated above the third insulating layer (140) and below the fourth insulating layer (150), respectively. At this time, a metal layer (171) may be formed on the surfaces of the first and second external insulating layers (170).

Next, referring to FIG. 14, a process of forming the sixth via (180) of the first and second external insulating layers (170) can be performed. In addition, a process of forming the first and second external circuit patterns (175) on the surfaces of the first and second external insulating layers (170) can be performed using the metal layer (171).

Next, referring to FIG. 15, a process of forming a first protective layer (215) on the first and second outer insulating layers (170) and placing a second protective layer (220) under the seventh insulating layer (195) can be performed.

The first protective layer (215) and the second protective layer (220) can be formed of at least one layer using one or more of SR (Solder Resist), oxide, and Au.

According to an embodiment, a printed circuit board includes a first insulating portion in which a cavity in which an electronic component is placed is formed. At this time, the cavity has an asymmetrical structure with respect to a horizontal line in the center. Specifically, the cavity has a width of one side (e.g., the upper side) into which an insulating material filling the cavity is injected is greater than a width of the opposite side. Accordingly, when the cavity is filled with an insulating material, the insulating material can be filled from edges on both sides of the electronic component, thereby preventing the phenomenon in which the position of the electronic component moves due to resin flow. In other words, in the embodiment, an electronic component is placed in a cavity in which the upper and lower sides have different widths. In addition, in the embodiment, a resin is injected into a portion having a relatively small width to form an insulating portion in which the electronic component is embedded. Accordingly, the interconnectivity between a pad and a via hole can be improved by preventing shifting of the electronic component, and the reliability and durability of the product can be secured while reducing process issues and securing yields by minimizing connection failures.

In addition, according to an embodiment, the printed circuit board is arranged so that the circuit pattern or pad is embedded in the first insulating portion. Accordingly, since the circuit pattern or pad is embedded in the first insulating portion, the thickness of the printed circuit board can be reduced by the thickness of the circuit pattern compared to the prior art, and the degree of design freedom can be improved. In addition, since the first insulating portion uses a prepreg containing glass fiber, it is possible to minimize panel breakage or warping that occurs when manufacturing a thin substrate.

In addition, according to an embodiment, the printed circuit board has a second insulating portion arranged under the first insulating portion. At this time, the second insulating portion forms an insulating layer using a film-type resin (for example, ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric), which is a photosensitive insulating material) in an area in direct contact with the first insulating portion. According to this, in the embodiment, the thickness of the insulating layer of the second insulating portion can be reduced compared to the prior art, and the degree of design freedom can be improved.

In addition, according to an embodiment, by forming the second insulating portion on the area in direct contact with the first insulating portion using a film-type resin, a small via can be formed, and thus a fine pattern can be implemented.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

Although the above description focuses on examples, these are only examples and do not limit the examples, and those with ordinary knowledge in the field to which the examples belong will recognize that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, the differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.

Claims (16)

A first insulating member comprising a cavity;
A second insulating member arranged on the upper surface of the first insulating member;
A third insulating part arranged below the lower surface of the first insulating part; and
comprising at least one electronic element disposed within the cavity;
The above cavity includes an inclined surface so that the width in the horizontal direction becomes wider as it approaches the third insulating portion,
The second insulating portion includes a protrusion disposed within the cavity,
A circuit board in which the width of the protrusion increases in the horizontal direction as it approaches the third insulating portion.
delete In the first paragraph,
The third insulating part is,
Positioned below the lower surface of the first insulating part and the lower surface of the protrusion
Circuit board. In the first paragraph,
The first part of the surface facing the third insulating part,
Including a second part opposite to the first part,
The width of the above first part is,
Having a range of between 1.5 and 2.5 times the width of the second portion
Circuit board. In the first paragraph,
The above first insulating part,
At least one first insulating layer;
A first circuit pattern embedded in the lower portion of the first insulating layer;
A second circuit pattern protruding above the upper surface of the first insulating layer; and
A first via disposed within the first insulating layer and connecting the first and second circuit patterns.
Circuit board. In paragraph 5,
The first insulating layer comprises a prepreg comprising glass fibers.
Circuit board. In paragraph 5,
The above second insulating part,
A second insulating layer disposed inside the cavity and over the first insulating layer;
A third circuit pattern disposed on the upper surface of the second insulating layer; and
A second via is disposed within the second insulating layer and connects the second and third circuit patterns,
The second insulating layer comprises an insulating material different from that of the first insulating layer.
Circuit board. In Article 7,
The second insulating layer is,
Composed of RCC (Resin Coated Cu)
Circuit board. In Article 7,
The third insulating part is,
A third insulating layer disposed under the first insulating layer;
a third via disposed within the third insulating layer; and
A fourth circuit pattern is disposed below the lower surface of the third insulating layer;
The third insulating layer is,
Including an insulating material other than the first and second insulating layers
Circuit board. In Article 9,
The third insulating layer is,
Containing ABF (Aginomoto Build-up Film) or PID (Photo Imagable Dielectric)
Circuit board. In Article 9,
The third insulating layer is,
having a thickness smaller than the thickness of each of the first insulating layer and the second insulating layer;
Circuit board. In Article 9,
The above third via,
A first sub-third via that overlaps the electronic component in a vertical direction and is directly connected to a terminal of the electronic component,
Including a second sub-third via arranged at a position that does not vertically overlap with the electronic component;
The above first sub-third via,
Having a width smaller than the width of the second sub-third via
Circuit board. In the first paragraph,
The above electronic components,
Including first and second electronic elements spaced apart from each other within the cavity.
Circuit board. Step of forming a first insulating part;
A step of forming a cavity penetrating the first insulating portion;
A step of forming a film layer on one surface of the first insulating part;
A step of attaching an electronic component on the film layer exposed through the cavity;
A step of forming a second insulating part filling the cavity on the first insulating part;
a step of removing the above film layer; and
A step of forming a third insulating member under the first insulating member and the second insulating member arranged within the cavity is included.
The above cavity is,
The above cavity includes an inclined surface so that the width in the horizontal direction becomes wider as it approaches the third insulating portion,
The second insulating portion includes a protrusion disposed within the cavity,
The width of the above protrusion becomes wider in the horizontal direction as it approaches the third insulating portion.
The insulating material forming the second insulating portion is introduced into the cavity to form the protrusion.
Method for manufacturing a circuit board. In Article 14,
The third insulating part is,
Positioned below the lower surface of the first insulating part and the lower surface of the protrusion
Method for manufacturing a circuit board. In Article 14,
A first portion of the surface facing the above film layer,
Including a second part opposite to the first part above;
The width of the above first part is,
Having a range of between 1.5 and 2.5 times the width of the second portion
Method for manufacturing a circuit board.

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