KR102756447B1 - Electronic device, panel, and gate driving circuit including oxide semiconductor - Google Patents

Abstract

Embodiments of the present invention relate to an electronic device, a panel, and a gate driving circuit, and more specifically, a gate driving circuit built into a panel includes a diode, and the diode may include a first electrode positioned on a substrate, a buffer layer disposed while covering the first electrode, a first oxide semiconductor disposed on the buffer layer and electrically connected to the first electrode through a buffer layer hole of the buffer layer, a second oxide semiconductor disposed on the first oxide semiconductor, an interlayer insulating film disposed on the second oxide semiconductor, and a second electrode disposed on the interlayer insulating film and electrically connected to the second oxide semiconductor through the first interlayer insulating film hole of the interlayer insulating film. According to embodiments of the present invention, a gate driving circuit having excellent leakage current blocking performance and an electronic device and a panel including the same can be provided.

Description

ELECTRONIC DEVICE, PANEL, AND GATE DRIVING CIRCUIT INCLUDING OXIDE SEMICONDUCTOR

Embodiments of the present invention relate to electronic devices, panels and gate driving circuits.

As the information society develops, the demand for various electronic devices such as display devices and lighting devices is increasing in various forms. These electronic devices may include a panel on which data lines and gate lines are arranged, a data driver for driving the data lines, and a gate driver for driving the gate lines.

To reduce the number of gate driver chips for driving gate lines arranged on a panel, GIP (Gate In Panel) technology was developed, which embeds gate driver circuits in the panel.

When the gate drive circuits are arranged in the non-active area of the panel in the GIP type, a problem of unexpected leakage current occurring within the gate drive circuits may occur. When such leakage current occurs, the gate drive circuits cannot operate normally. Accordingly, electronic devices such as display devices and lighting devices may also operate abnormally.

An object of embodiments of the present invention is to provide a gate driving circuit capable of blocking leakage current, and an electronic device and panel including the same.

In addition, another object of embodiments of the present invention is to provide a gate driving circuit having a small-area leakage current blocking structure, and an electronic device and panel including the same.

In addition, another object of embodiments of the present invention is to provide a gate driving circuit including a diode having excellent leakage current blocking performance, and an electronic device and panel including the same.

In addition, another object of the embodiments of the present invention is to provide an electronic device, panel and gate driving circuit including a transistor having a structure linked to a diode having excellent leakage current blocking performance.

In one aspect, embodiments of the present invention can provide an electronic device including a panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of subpixels are arranged, a data driver for driving the plurality of data lines, and a gate driver for driving the plurality of gate lines.

The gate driver may include a plurality of gate driving circuits arranged in a non-active region of the panel.

Each of the multiple gate drive circuits may include a diode.

The diode may include a first electrode positioned on a substrate, a buffer layer disposed while covering the first electrode, a first oxide semiconductor disposed on the buffer layer and electrically connected to the first electrode through a buffer layer hole of the buffer layer, a second oxide semiconductor disposed on the first oxide semiconductor, an interlayer insulating film disposed on the second oxide semiconductor, and a second electrode disposed on the interlayer insulating film and electrically connected to the second oxide semiconductor through the first interlayer insulating film hole of the interlayer insulating film.

The first oxide semiconductor may be composed of a P-type oxide semiconductor, and the second oxide semiconductor may be composed of an N-type oxide semiconductor.

Alternatively, the first oxide semiconductor may be composed of an N-type oxide semiconductor, and the second oxide semiconductor may be composed of a P-type oxide semiconductor.

The transistor arranged on the panel includes a third oxide semiconductor composed of the same material as the first oxide semiconductor, and a fourth oxide semiconductor composed of the same material as the second oxide semiconductor, and among the third oxide semiconductor and the fourth oxide semiconductor, the oxide semiconductor closer to the gate electrode of the transistor may be an N-type oxide semiconductor.

The transistors arranged on the panel may be transistors arranged in the active area of the panel, transistors arranged in the non-active area of the panel, or transistors arranged in both the active area and the non-active area of the panel.

The buffer layer hole and the first interlayer insulating film hole can overlap.

Alternatively, the buffer layer hole and the first interlayer insulating film hole may have different locations.

The first oxide semiconductor and the second oxide semiconductor form a channel, and forward current can flow between the first electrode and the second electrode of the diode. The first oxide semiconductor and the second oxide semiconductor do not form a channel, and reverse current can be blocked between the first electrode and the second electrode of the diode.

Transistors can be arranged on the panel, the stacked structure of the transistors being similar to the stacked structure of the diodes in the gate driving circuit arranged in the non-active region.

The transistor may include a third oxide semiconductor disposed on the buffer layer and composed of the same material as the first oxide semiconductor, a fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor, a source electrode contacting one end of the fourth oxide semiconductor and composed of the same material as the second electrode, and a drain electrode contacting the other end of the fourth oxide semiconductor and composed of the same material as the second electrode.

Among the third oxide semiconductor and the fourth oxide semiconductor, a channel may be formed in the fourth oxide semiconductor, and no channel may be formed in the third oxide semiconductor.

The transistors may be transistors arranged in the active area and/or the non-active area of the panel.

The transistors may be included in each of a plurality of gate driving circuits arranged in a non-active area of the panel. Additionally, the transistors may be arranged in subpixels arranged in an active area of the panel.

The panel may further include a subpattern arranged to overlap the third oxide semiconductor of the transistor with a buffer layer therebetween.

The subpattern may be composed of the same material as the first electrode of the diode.

The sub-pattern may be a voltage wiring.

Alternatively, the sub-pattern may be a floating or light shield to which a specific voltage is applied.

The subpattern can be electrically connected to the source electrode or the drain electrode.

The subpattern can be electrically connected to the gate electrode.

The second oxide semiconductor can have a thickness of 50 Å or more.

The second oxide semiconductor and the fourth oxide semiconductor of the transistor formed therewith can have a thickness in the range of 50 Å to 500 Å.

In another aspect, embodiments of the present invention may provide a panel in which a plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged in an active area, a plurality of gate driving circuits for driving the plurality of gate lines are arranged in a non-active area, and each of the plurality of gate driving circuits includes a diode.

Each diode in the gate driving circuit arranged on the panel may include a first electrode positioned on a substrate, a buffer layer arranged while covering the first electrode, a first oxide semiconductor arranged on the buffer layer and electrically connected to the first electrode through a buffer layer hole of the buffer layer, a second oxide semiconductor arranged on the first oxide semiconductor, an interlayer insulating film arranged on the second oxide semiconductor, and a second electrode arranged on the interlayer insulating film and electrically connected to the second oxide semiconductor through the first interlayer insulating film hole of the interlayer insulating film.

The first oxide semiconductor may be composed of a P-type oxide semiconductor, and the second oxide semiconductor may be composed of an N-type oxide semiconductor.

Alternatively, the first oxide semiconductor may be composed of an N-type oxide semiconductor, and the second oxide semiconductor may be composed of a P-type oxide semiconductor.

The transistor arranged on the panel includes a third oxide semiconductor composed of the same material as the first oxide semiconductor, and a fourth oxide semiconductor composed of the same material as the second oxide semiconductor, and an active layer closer to the gate electrode of the transistor among the third oxide semiconductor and the fourth oxide semiconductor may be an N-type oxide semiconductor.

In another aspect, at least one of the transistors in the gate driving circuit and the transistors in the subpixel may include a third oxide semiconductor disposed on the buffer layer and composed of the same material as the first oxide semiconductor, a fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor, a source electrode contacting one end of the fourth oxide semiconductor and composed of the same material as the second electrode, and a drain electrode contacting the other end of the fourth oxide semiconductor and composed of the same material as the second electrode.

In another aspect, embodiments of the present invention can provide a gate driving circuit including a pull-up transistor outputting a gate signal corresponding to a first level voltage to a gate line, a pull-down transistor outputting a gate signal corresponding to a second level voltage to the gate line, and a control switch circuit controlling a gate node of the pull-up transistor and a gate node of the pull-down transistor.

A control switch circuit of a gate driving circuit may include a diode, and the diode may include a first electrode positioned on a substrate, a buffer layer disposed while covering the first electrode, a first oxide semiconductor disposed on the buffer layer and electrically connected to the first electrode through a buffer layer hole of the buffer layer, a second oxide semiconductor disposed on the first oxide semiconductor, an interlayer insulating film disposed on the second oxide semiconductor, and a second electrode disposed on the interlayer insulating film and electrically connected to the second oxide semiconductor through the first interlayer insulating film hole of the interlayer insulating film.

The first oxide semiconductor may be composed of a P-type oxide semiconductor, and the second oxide semiconductor may be composed of an N-type oxide semiconductor.

Alternatively, the first oxide semiconductor may be composed of an N-type oxide semiconductor, and the second oxide semiconductor may be composed of a P-type oxide semiconductor.

At least one of the transistors, pull-up transistors and pull-down transistors included in the control switch circuit may include a third oxide semiconductor disposed on a buffer layer and composed of the same material as the first oxide semiconductor, a fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor, a source electrode contacting one end of the fourth oxide semiconductor and composed of the same material as the second electrode, and a drain electrode contacting the other end of the fourth oxide semiconductor and composed of the same material as the second electrode.

According to the embodiments of the present invention described above, a gate driving circuit capable of blocking leakage current and an electronic device and panel including the same can be provided.

In addition, according to embodiments of the present invention, a gate driving circuit having a small-area leakage current blocking structure and an electronic device and panel including the same can be provided.

In addition, according to embodiments of the present invention, a gate driving circuit including a diode having excellent leakage current blocking performance, and an electronic device and panel including the same can be provided.

In addition, according to embodiments of the present invention, an electronic device, panel, and gate driving circuit including a transistor having a structure linked to a diode having excellent leakage current blocking performance can be provided.

FIG. 1 is a schematic system configuration diagram of an electronic device according to embodiments of the present invention.
FIG. 2 is an example of a system implementation diagram of an electronic device according to embodiments of the present invention.
FIG. 3 is a drawing showing the structure of a subpixel when the panel according to embodiments of the present invention is an OLED (Organic Light Emitting Diode) panel.
FIG. 4 is a drawing showing the structure of a subpixel when the panel according to embodiments of the present invention is an LCD (Liquid Crystal Display) panel.
FIG. 5 is a schematic diagram illustrating a gate driving circuit arranged on a panel according to embodiments of the present invention.
FIG. 6 is a drawing for explaining a leakage current blocking transistor in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIG. 7 is a plan view of a leakage current blocking transistor in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIG. 8 is a graph of IV characteristics of a leakage current blocking transistor in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIG. 9 is a diagram showing a change in threshold voltage distribution of a leakage current blocking transistor in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIG. 10 is a drawing for explaining a phenomenon of leakage current generation due to a change in threshold voltage distribution of a leakage current blocking transistor in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIGS. 11 and 12 are cross-sectional views and plan views of a leakage current blocking diode in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIGS. 13 and 14 are cross-sectional views and plan views respectively of a leakage current blocking diode in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIG. 15 is an equivalent circuit of a leakage current blocking diode in a gate driving circuit arranged in a panel according to embodiments of the present invention.
FIGS. 16 and 17 are plan views showing a leakage current blocking diode in a non-active region and a transistor in a non-active region in a panel according to embodiments of the present invention.
FIGS. 18 and 19 are plan views showing a leakage current blocking diode in a non-active region and a transistor in an active region in a panel according to embodiments of the present invention.
FIGS. 20 to 24 are drawings showing various types of sub-patterns arranged under a transistor arranged in an active region or a transistor arranged in a non-active region, according to the stacked structure of a leakage current blocking diode in a gate driving circuit arranged on a panel according to embodiments of the present invention.
FIG. 25 is a graph showing the relationship between the mobility and thickness of a second oxide semiconductor of a leakage current blocking diode in a gate driving circuit arranged in a panel according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When adding reference numerals to components in each drawing, the same components may have the same numerals as much as possible even if they are shown in different drawings. In addition, when describing the present invention, if it is determined that a specific description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, when describing components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. When it is described that a component is "connected," "coupled," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but that other components may be "interposed" between each component, or that each component may be "connected," "coupled," or "connected" through another component.

FIG. 1 is a schematic system configuration diagram of an electronic device according to embodiments of the present invention.

Electronic devices according to embodiments of the present invention may include display devices, lighting devices, light-emitting devices, etc. In the following, for convenience of explanation, the description will focus on display devices. However, the description below may be equally applied to various other electronic devices, such as lighting devices and light-emitting devices.

An electronic device according to embodiments of the present invention may include a panel (PNL) that displays an image or outputs light, and a driving circuit for driving the panel (PNL).

The panel (PNL) may have a plurality of data lines (DL) and a plurality of gate lines (GL) arranged in a matrix type, and a plurality of subpixels (SP) defined by the plurality of data lines (DL) and the plurality of gate lines (GL).

In a panel (PNL), a plurality of data lines (DL) and a plurality of gate lines (GL) may be arranged to cross each other. For example, a plurality of gate lines (GL) may be arranged in rows or columns, and a plurality of data lines (DL) may be arranged in columns or rows. In the following, for convenience of explanation, it is assumed that a plurality of gate lines (GL) are arranged in rows and a plurality of data lines (DL) are arranged in columns.

In addition to a plurality of data lines (DL) and a plurality of gate lines (GL), other types of signal lines may be arranged on the panel (PNL) depending on the subpixel structure, etc. Driving voltage lines, reference voltage lines, or common voltage lines may be further arranged.

The panel (PNL) can be of various types, such as an LCD (Liquid Crystal Display) panel or an OLED (Organic Light Emitting Diode) panel.

The types of signal wires arranged on the panel (PNL) may vary depending on the subpixel structure, panel type (e.g., LCD panel, OLED panel, etc.). In addition, in this specification, signal wires may be a concept that includes electrodes to which signals are applied.

A panel (PNL) may include an active area (A/A) where an image (video) is displayed, and a non-active area (N/A) which is an area surrounding the active area and where no image is displayed. Here, the non-active area (N/A) is also called a bezel area.

A number of subpixels (SP) are arranged in the active area (A/A) for image display.

In the non-active area (N/A), a pad portion for electrically connecting a data driver (DDR) may be arranged, and a plurality of data link lines may be arranged for connection between the pad portion and a plurality of data lines (DL). Here, the plurality of data link lines may be portions in which a plurality of data lines (DL) extend into the non-active area (N/A), or may be separate patterns electrically connected to the plurality of data lines (DL).

In addition, in the non-active area (N/A), gate drive-related wirings may be arranged to transmit a voltage (signal) required for gate driving to the gate driver (GDR) through a pad portion to which the data driver (DDR) is electrically connected. For example, the gate drive-related wirings may include clock wirings for transmitting a clock signal, gate voltage wirings for transmitting gate voltages (VGH, VGL), gate drive control signal wirings for transmitting various control signals required for scan signal generation, etc. These gate drive-related wirings are arranged in the non-active area (N/A), unlike the gate lines (GL) arranged in the active area (A/A).

The driving circuit may include a data driver (DDR) that drives a plurality of data lines (DL), a gate driver (GDR) that drives a plurality of gate lines (GL), and a controller (CTR) that controls the data driver (DDR) and the gate driver (GDR).

A data driver (DDR) can drive multiple data lines (DL) by outputting data voltages to multiple data lines (DL).

A gate driver (GDR) can drive multiple gate lines (GL) by outputting scan signals to multiple gate lines (GL).

The controller (CTR) can control the driving operations of the data driver (DDR) and the gate driver (GDR) by supplying various control signals (DCS, GCS) necessary for the driving operations of the data driver (DDR) and the gate driver (GDR). In addition, the controller (CTR) can supply image data (DATA) to the data driver (DDR).

The controller (CTR) starts scanning according to the timing implemented in each frame, converts the input image data input from the outside into the data signal format used by the data driver (DDR), outputs the converted image data (DATA), and controls data driving at an appropriate time according to the scan.

The controller (CTR) receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, and a clock signal (CLK) from an external source (e.g., a host system) to control the data driver (DDR) and the gate driver (GDR), and generates various control signals and outputs them to the data driver (DDR) and the gate driver (GDR).

For example, the controller (CTR) outputs various gate control signals (GCS: Gate Control Signals) including a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC: Gate Shift Clock), and a gate output enable signal (GOE: Gate Output Enable) to control the gate driver (GDR).

Additionally, the controller (CTR) outputs various data control signals (DCS: Data Control Signals) including a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), and a source output enable signal (SOE: Source Output Enable) to control the data driver (DDR).

The controller (CTR) may be a timing controller used in conventional display technology, or may be a control device that can perform other control functions, including a timing controller.

The controller (CTR) may be implemented as a separate component from the data driver (DDR), or may be implemented as an integrated circuit integrated with the data driver (DDR).

The data driver (DDR) receives image data (DATA) from the controller (CTR) and supplies data voltages to a plurality of data lines (DL), thereby driving a plurality of data lines (DL). Here, the data driver (DDR) is also called a source driver.

The data driver (DDR) can exchange various signals with the controller (CTR) through various interfaces.

A gate driver (GDR) sequentially drives a plurality of gate lines (GL) by sequentially supplying scan signals to the plurality of gate lines (GL). Here, the gate driver (GDR) is also called a scan driver.

The gate driver (GDR) sequentially supplies scan signals of on voltage or off voltage to a plurality of gate lines (GL) under the control of the controller (CTR).

The data driver (DDR) converts image data (DATA) received from the controller (CTR) into an analog data voltage and supplies it to a number of data lines (DL) when a specific gate line is opened by the gate driver (GDR).

The data driver (DDR) may be located on only one side of the panel (PNL) (e.g., the upper or lower side), or in some cases, on both sides of the panel (PNL) (e.g., the upper and lower sides) depending on the driving method, panel design method, etc.

Gate drivers (GDRs) may be located on only one side of the panel (PNL) (e.g., left or right) or, in some cases, on both sides of the panel (PNL) (e.g., left and right sides) depending on the driving method, panel design method, etc.

A data driver (DDR) may be implemented by including one or more source driver integrated circuits (SDIC).

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. The data driver (DDR) may, in some cases, further include one or more analog to digital converters (ADC).

Each source driver integrated circuit (SDIC) may be connected to a bonding pad of a panel (PNL) as a TAB (Tape Automated Bonding) type or a COG (Chip On Glass) type, or may be directly placed on the panel (PNL). In some cases, each source driver integrated circuit (SDIC) may be placed while being integrated on the panel (PNL). In addition, each source driver integrated circuit (SDIC) may be implemented as a COF (Chip On Film) type. In this case, each source driver integrated circuit (SDIC) may be mounted on a circuit film and may be electrically connected to data lines (DL) on the panel (PNL) through the circuit film.

A gate driver (GDR) may include a plurality of gate driving circuits (GDCs), wherein the plurality of gate driving circuits (GDCs) may each correspond to a plurality of gate lines (GLs).

Each gate drive circuit (GDC) may include a shift register, a level shifter, etc.

Each gate driving circuit (GDC) can be connected to a bonding pad of the panel (PNL) as a TAB (Tape Automated Bonding) type or a COG (Chip On Glass) type. In addition, each gate driving circuit (GDC) can be implemented as a COF (Chip On Film) method. In this case, each gate driving circuit (GDC) is mounted on a circuit film and can be electrically connected to the gate lines (GL) of the panel (PNL) through the circuit film. In addition, each gate driving circuit (GDC) can be implemented as a GIP (Gate In Panel) type and built into the panel (PNL). That is, each gate driving circuit (GDC) can be formed directly on the panel (PNL).

FIG. 2 is an example of a system implementation diagram of an electronic device according to embodiments of the present invention.

Referring to FIG. 2, in an electronic device according to embodiments of the present invention, a data driver (DDR) may be implemented as a COF (Chip On Film) type among various types (TAB, COG, COF, etc.), and a gate driver (GDR) may be implemented as a GIP (Gate In Panel) type among various types (TAB, COG, COF, GIP, etc.).

A data driver (DDR) can be implemented with one or more source driver integrated circuits (SDICs). Figure 2 illustrates an example where a data driver (DDR) is implemented with multiple source driver integrated circuits (SDICs).

When the data driver (DDR) is implemented as a COF type, each source driver integrated circuit (SDIC) implementing the data driver (DDR) can be mounted on a source-side circuit film (SF).

One side of the source side circuit film (SF) can be electrically connected to a pad portion (a collection of pads) existing in a non-active area (N/A) of the panel (PNL).

On the source side circuit film (SF), wires can be arranged to electrically connect the source driver integrated circuit (SDIC) and the panel (PNL).

An electronic device may include one or more source printed circuit boards (SPCBs) for circuit connections between a plurality of source driver integrated circuits (SDICs) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

One or more source printed circuit boards (SPCBs) may be connected to the other side of a source side circuit film (SF) having a source driver integrated circuit (SDIC) mounted thereon.

That is, a source-side circuit film (SF) on which a source driver integrated circuit (SDIC) is mounted can have one side electrically connected to a non-active area (N/A) of a panel (PNL) and the other side electrically connected to a source printed circuit board (SPCB).

A controller (CTR) that controls the operations of a data driver (DDR) and a gate driver (GDR) can be placed on a control printed circuit board (CPCB).

In addition, a control printed circuit board (CPCB) may further include power management integrated circuits (PMICs) that supply various voltages or currents to the panel (PNL), data driver (DDR), and gate driver (GDR), or control various voltages or currents to be supplied.

The source printed circuit board (SPCB) and the control printed circuit board (CPCB) can be circuit-connected via at least one connecting member (CBL). Here, the connecting member (CBL) can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

One or more source printed circuit boards (SPCB) and control printed circuit boards (CPCB) may be implemented integrated into a single printed circuit board.

When the gate driver (GDR) is implemented as a GIP (Gate In Panel) type, a plurality of gate driving circuits (GDC) included in the gate driver (GDR) can be formed directly on the non-active area (N/A) of the panel (PNL).

Each of a plurality of gate driving circuits (GDC) can output a corresponding scan signal (SCAN) to a corresponding gate line (GL) arranged in an active area (A/A) in a panel (PNL).

A plurality of gate drive circuits (GDCs) arranged on a panel (PNL) can receive various signals (clock signal, high level gate voltage (VGH), low level gate voltage (VGL), start signal (VST), reset signal (RST), etc.) necessary for generating a scan signal through gate drive related wirings arranged in a non-active area (N/A).

The gate drive related wirings arranged in the non-active region (N/A) can be electrically connected to the source side circuit film (SF) arranged closest to a plurality of gate drive circuits (GDC).

FIG. 3 is a drawing showing the structure of a subpixel (SP) when the panel (PNL) according to embodiments of the present invention is an OLED (Organic Light Emitting Diode) panel.

Referring to FIG. 3, each subpixel (SP) in the panel (110), which is an OLED panel, may be implemented to include an organic light-emitting diode (OLED), a driving transistor (DRT) that drives the organic light-emitting diode (OLED), a switching transistor (O-SWT) electrically connected between a first node (N1) of the driving transistor (DRT) and a corresponding data line (DL), and a storage capacitor (Cst) electrically connected between the first node (N1) and a second node (N2) of the driving transistor (DRT).

An organic light-emitting diode (OLED) can be composed of an anode electrode, an organic light-emitting layer, and a cathode electrode.

According to the circuit example of FIG. 3, the anode electrode (also called pixel electrode) of the organic light-emitting diode (OLED) can be electrically connected to the second node (N2) of the driving transistor (DRT). A base voltage (EVSS) can be applied to the cathode electrode (also called common electrode) of the organic light-emitting diode (OLED).

Here, the base voltage (EVSS) may be, for example, the ground voltage or a voltage higher or lower than the ground voltage. In addition, the base voltage (EVSS) may vary depending on the driving state. For example, the base voltage (EVSS) during image driving and the base voltage (EVSS) during sensing driving may be set differently.

The driver transistor (DRT) drives the organic light-emitting diode (OLED) by supplying driving current to the OLED.

The driving transistor (DRT) may include a first node (N1), a second node (N2), and a third node (N3).

A first node (N1) of the driving transistor (DRT) may be a gate node and may be electrically connected to a source node or a drain node of a switching transistor (O-SWT). A second node (N2) of the driving transistor (DRT) may be a source node or a drain node and may be electrically connected to an anode electrode (or a cathode electrode) of an organic light emitting diode (OLED). A third node (N3) of the driving transistor (DRT) may be a drain node or a source node, may be applied with a driving voltage (EVDD), and may be electrically connected to a driving voltage line (DVL: Driving Voltage Line) that supplies the driving voltage (EVDD).

A storage capacitor (Cst) is electrically connected between a first node (N1) and a second node (N2) of a driving transistor (DRT), and can maintain a data voltage (Vdata) corresponding to an image signal voltage or a voltage corresponding thereto for one frame time (or a specified time).

A drain node or a source node of a switching transistor (O-SWT) is electrically connected to a corresponding data line (DL), a source node or a drain node of the switching transistor (O-SWT) is electrically connected to a first node (N1) of a driving transistor (DRT), and a gate node of the switching transistor (O-SWT) is electrically connected to a corresponding gate line so as to receive a scan signal (SCAN).

The switching transistor (O-SWT) can be turned on and off by receiving a scan signal (SCAN) as a gate node through the corresponding gate line.

These switching transistors (O-SWT) are turned on by a scan signal (SCAN) and can transmit the data voltage (Vdata) supplied from the corresponding data line (DL) to the first node (N1) of the driving transistor (DRT).

Meanwhile, the storage capacitor (Cst) may be an external capacitor intentionally designed outside the driving transistor (DRT), rather than a parasitic capacitor (e.g., Cgs, Cgd) that exists between the first node (N1) and the second node (N2) of the driving transistor (DRT).

Each of the driving transistor (DRT) and the switching transistor (O-SWT) can be either an n-type transistor or a p-type transistor.

Each subpixel structure illustrated in FIG. 3 is a 2T (Transistor) 1C (Capacitor) structure, which is merely an example for explanation, and may further include one or more transistors, or in some cases, one or more capacitors. Alternatively, each of a plurality of subpixels may have the same structure, or some of the plurality of subpixels may have different structures.

FIG. 4 is a drawing showing the structure of a subpixel (SP) when the panel (PNL) according to embodiments of the present invention is an LCD (Liquid Crystal Display) panel.

Referring to FIG. 4, each subpixel (SP) in the panel (110), which is an LCD panel, may include a pixel electrode (PXL) and a switching transistor (L-SWT), etc.

A switching transistor (L-SWT) is controlled by a scan signal (SCAN) and can be electrically connected between a data line (DL) and a pixel electrode (PXL).

The switching transistor (L-SWT) is turned on by the scan signal (SCAN) and transmits the data voltage (Vdata) supplied from the data line (DL) to the pixel electrode (PXL). The pixel electrode (PXL) to which the data voltage (Vdata) is applied can form an electric field with the common electrode (COM) to which the common voltage is applied. In other words, a capacitor can be formed between the pixel electrode (PXL) and the common electrode (COM).

FIG. 5 is a schematic diagram illustrating a gate driving circuit (GDC) arranged on a panel (PNL) according to embodiments of the present invention.

Referring to FIG. 5, each gate driving circuit (GDC) may include a pull-up transistor (Tup), a pull-down transistor (Tdown), and a control switch circuit (CSC).

The control switch circuit (CSC) is a circuit that controls the voltage of the Q node corresponding to the gate node of the pull-up transistor (Tup) and the voltage of the QB node corresponding to the gate node of the pull-down transistor (Tdown), and may include multiple switches (transistors).

A pull-up transistor (Tup) is a transistor that supplies a gate signal (Vgate) corresponding to a first level voltage (e.g., a high level voltage (VGH)) to a gate line (GL) through a gate signal output node (Nout). A pull-down transistor (Tdown) is a transistor that supplies a gate signal (Vgate) corresponding to a second level voltage (e.g., a low level voltage (VGL)) to a gate line (GL) through a gate signal output node (Nout). The pull-up transistor (Tup) and the pull-down transistor (Tdown) can be turned on at different timings.

A pull-up transistor (Tup) is electrically connected between a clock signal application node (Nclk) to which a clock signal (CLK) is applied and a gate signal output node (Nout) that is electrically connected to a gate line (GL), and is turned on or off by the voltage of the Q node.

The gate node of the pull-up transistor (Tup) is electrically connected to the Q node. The drain node or source node of the pull-up transistor (Tup) is electrically connected to the clock signal application node (Nclk). The source node or drain node of the pull-up transistor (Tup) is electrically connected to the gate signal output node (Nout) from which the gate signal (Vgate) is output.

The pull-up transistor (Tup) is turned on by the voltage of the Q node and outputs a gate signal (Vgate) having a high level voltage (VGH) in the high level section of the clock signal (CLK) to the gate signal output node (Nout).

The gate signal (Vgate) of the high level voltage (VGH) output to the gate signal output node (Nout) is supplied to the corresponding gate line (GL).

The pull-down transistor (Tdown) is electrically connected between the gate signal output node (Nout) and the base voltage node (Nvss), and is turned on or off by the voltage of the QB node.

The gate node of the pull-down transistor (Tdown) is electrically connected to the QB node. The drain node or source node of the pull-down transistor (Tdown) is electrically connected to the base voltage node (Nvss) and receives a base voltage (VSS) corresponding to a positive voltage. The source node or drain node of the pull-down transistor (Tdown) is electrically connected to the gate signal output node (Nout) from which the gate signal (Vgate) is output.

The pull-down transistor (Tdown) is turned on by the voltage of the QB node and outputs a gate signal (Vgate) of a low-level voltage (VGL) to a gate signal output node (Nout). Accordingly, the gate signal (Vgate) of the low-level voltage (VGL) can be supplied to the corresponding gate line (GL) through the gate signal output node (Nout). Here, the gate signal (Vgate) of the low-level voltage (VGL) can be, for example, a base voltage (VSS).

Meanwhile, the control switch circuit (CSC) may be composed of two or more transistors, etc., and has main nodes such as a Q node, a QB node, a set node (S, also called a start node), and a reset node (R). In some cases, the control switch circuit (CSC) may further have input nodes to which various voltages, such as a driving voltage (VDD), are input.

In the controlled switch circuit (CSC), the Q node is electrically connected to the gate node of the pull-up transistor (Tup), and charging and discharging are repeated.

In the controlled switch circuit (CSC), the QB node is electrically connected to the gate node of the pull-down transistor (Tdown), and charging and discharging are repeated.

In the control switch circuit (CSC), the set node (S) receives a set signal (SET) to instruct the start of gate driving of the corresponding gate driving circuit (GDC).

Here, the set signal (SET) applied to the set node (S) may be a start signal (VST) input from the outside of the gate driver (GDR), or may be a signal (carry signal) in which a gate signal (Vgate) output from a gate driving circuit (GDC) of a previous stage prior to the current gate driving circuit (GD) is fed back.

The reset signal (RST) applied to the reset node (R) in the control switch circuit (CSC) may be a reset signal for simultaneously initializing the gate driving circuits (GDC) of all stages, or may be a carry signal input from another stage (a previous or subsequent stage).

The control switch circuit (CSC) charges the Q node in response to a set signal (SET) and discharges the Q node in response to a reset signal (RST). The control switch circuit (CSC) may include an inverter circuit to charge or discharge each of the Q node and the QB node at different timings.

FIG. 6 is a drawing for explaining a leakage current blocking transistor (LCPT) in a gate driving circuit (GDC) disposed in a panel (PNL) according to embodiments of the present invention, FIG. 7 is a plan view of a leakage current blocking transistor (LCPT) in a gate driving circuit (GDC) disposed in a panel (PNL) according to embodiments of the present invention, and FIG. 8 is an I-V characteristic graph of a leakage current blocking transistor (LCPT) in a gate driving circuit (GDC) disposed in a panel (PNL) according to embodiments of the present invention.

Referring to FIG. 6, the control switch circuit (CSC) of each gate driving circuit (GDC) arranged on the panel (PNL) may include a leakage current blocking transistor (LCPT) to block leakage current.

Here, leakage current refers to an unwanted current that may occur within the gate drive circuit (GDC), and refers to current that flows unintentionally in a situation or circuit part where current should not flow. This leakage current may refer to current that flows in the reverse direction in a situation or circuit part where current should flow only in the forward direction.

For example, even though the transistor in the gate drive circuit (GDC) should be turned off, a change in the threshold voltage of the transistor may occur, causing it to be abnormally turned on, resulting in leakage current. In addition, a gate signal waveform for turning the transistor in the gate drive circuit (GDC) off may become abnormal, causing the transistor to be abnormally turned on, resulting in leakage current.

In this way, leakage current can occur in various situations and locations. For example, leakage current can occur in the signal input circuit or the inverter circuit in the gate drive circuit (GDC).

Accordingly, a leakage current blocking transistor (LCPT) may be included in a signal input circuit or an inverter circuit within a gate drive circuit (GDC).

The signal input circuit section may be a circuit section into which a set signal (SET) is input, or a circuit section into which a reset signal (RST) is input. The inverter circuit section may be a circuit section that controls the voltage state (charge/discharge state) of the Q node and the QB node.

Referring to FIGS. 6 and 7, a leakage current blocking transistor (LCPT) may include a source electrode (S), a drain electrode (D), a gate electrode (G), and the like, and may further include an active layer (ACT) for forming a channel.

Referring to FIG. 7, one end of the active layer (ACT) may be in direct contact with the source electrode (S) through a contact hole (CNT) or may be contacted through other connection pattern(s). Accordingly, one end of the active layer (ACT) may be electrically connected to the source electrode (S) through the contact hole (CNT). The other end of the active layer (ACT) may be in direct contact with the drain electrode (D) through the contact hole (CNT) or may be contacted through other connection pattern(s). Accordingly, the other end of the active layer (ACT) may be electrically connected to the drain electrode (D) through the contact hole (CNT). The gate electrode (G) may partially overlap the active layer (ACT) with a gate insulating film therebetween.

Referring to FIGS. 6 and 7, the gate electrode (G) of the leakage current blocking transistor (LCPT) can be electrically connected to the drain electrode (D). Here, the electrical connection between the gate electrode (G) and the drain electrode (D) is called a diode connection.

In this way, the gate electrode (G) of the leakage current blocking transistor (LCPT) can be electrically connected to the drain electrode (D), but the gate electrode (G) of the leakage current blocking transistor (LCPT) can also be electrically connected to the source electrode (S). In the following, for convenience of explanation, it is assumed as an example that the gate electrode (G) of the leakage current blocking transistor (LCPT) is electrically connected to the drain electrode (D).

By this diode connection, in the leakage current blocking transistor (LCPT), the source electrode (S) becomes one electrode (the first electrode), the gate electrode (G) and the drain electrode (D), which are connected to each other, become the other electrode (the second electrode), and an active layer (ACT) exists between the first electrode and the second electrode. Accordingly, the leakage current blocking transistor (LCPT) can play a role similar to a type of diode.

Therefore, the leakage current blocking transistor (LCPT) in the gate drive circuit (GDC) can have I-V characteristics that conduct forward current and block reverse current, similar to a diode, as illustrated in Fig. 8.

Referring to Fig. 7, the leakage current blocking transistor (LCPT) is effective to some extent in blocking leakage current, but since it is a transistor with three electrodes (S, D, G), it cannot help but have a certain area (x*y) based on the contact hole (CNT).

Therefore, the gate drive circuit (GDC) must be as large as the area (x*y) of the leakage current blocking transistor (LCPT) in order to have the leakage current blocking function. This may cause the bezel area to become larger or make it difficult to mount a high-density GIP (Gate In Panel) type gate drive circuit (GDC) on the panel (PNL).

FIG. 9 is a diagram showing a change in threshold voltage distribution of a leakage current blocking transistor (LCPT) in a gate driving circuit (GDC) disposed in a panel (PNL) according to embodiments of the present invention, and FIG. 10 is a diagram explaining a leakage current generation phenomenon due to a change in threshold voltage distribution of a leakage current blocking transistor (LCPT) in a gate driving circuit (GDC) disposed in a panel (PNL) according to embodiments of the present invention.

Referring to FIG. 9, the leakage current blocking transistors (LCPTs) in the gate drive circuit (GDC) may have their threshold voltage distribution (Vth distribution) shifted in the negative direction due to various factors (e.g., channel, insulating film, and process distribution, etc.). Here, the negative shift of the threshold voltage distribution may mean that the center value (average value) of the threshold voltage distribution moves in the negative direction and the standard deviation of the threshold voltage distribution increases.

The leakage current blocking transistors (LCPT) in the gate driving circuit (GDC) can be designed as oxide transistors. That is, the active layer (ACT) of the leakage current blocking transistors (LCPT) in the gate driving circuit (GDC) can be an oxide semiconductor.

Likewise, when the leakage current blocking transistors (LCPTs) in the gate drive circuit (GDC) are oxide transistors, the negative shift phenomenon of the threshold voltage distribution mentioned above can become more severe.

When a negative shift phenomenon of threshold voltage distribution occurs for leakage current blocking transistors (LCPTs) included in a plurality of gate drive circuits (GDCs), the I-V characteristics of the leakage current blocking transistors (LCPTs) change as shown in Fig. 10.

When the I-V characteristics change due to the negative shift of the threshold voltage distribution, leakage current blocking transistors (LCPTs) can generate reverse current. That is, leakage current blocking transistors (LCPTs) can induce leakage current instead of blocking it.

In other words, transistor-based leakage current blocking using leakage current blocking transistors (LCPTs) is likely to fail to operate normally due to variations in the threshold voltage distribution of the leakage current blocking transistors (LCPTs).

FIGS. 11 to 14 are cross-sectional views and plan views of a leakage current blocking diode (LCPD) in a gate drive circuit (GDC) arranged in a panel (PNL) according to embodiments of the present invention.

The gate driver (GDR) may include a plurality of gate driving circuits (GDCs) arranged in a non-active area (N/A) of the panel (PNL). That is, a plurality of gate driving circuits (GDCs) included in the gate driver (GDR) may be implemented as a GIP type and arranged in the panel (PNL).

Each of these multiple gate drive circuits (GDCs) may include a leakage current blocking diode (LCPD) to block leakage current.

A leakage current blocking diode (LCPD) can be located in the initial signal input circuit or the inverter circuit within each gate drive circuit (GDC).

Referring to FIGS. 11 to 14, a leakage current blocking diode (LCPD) may include a first electrode (E1) positioned on a substrate (SUB), a buffer layer (BUF) arranged to cover the first electrode (E1), a first oxide semiconductor (OSEM1) arranged on the buffer layer (BUF) and electrically connected to the first electrode (E1) through a buffer layer hole (BUF_CNT) of the buffer layer (BUF), a second oxide semiconductor (OSEM2) arranged on the first oxide semiconductor (OSEM1), an interlayer insulating film (ILD) arranged on the second oxide semiconductor (OSEM2), and a second electrode (E2) arranged on the interlayer insulating film (ILD) and electrically connected to the second oxide semiconductor (OSEM2) through the first interlayer insulating film hole (ILD_CNT) of the interlayer insulating film (ILD).

The first oxide semiconductor (OSEM1) may be composed of a P-type oxide semiconductor. The second oxide semiconductor (OSEM2) may be composed of an N-type oxide semiconductor.

Alternatively, the first oxide semiconductor (OSEM1) may be composed of an N-type oxide semiconductor. The second oxide semiconductor (OSEM2) may be composed of a P-type oxide semiconductor.

For example, the P-type oxide semiconductor may include one or more of CuOx, SnOx, NiOx, etc. The N-type oxide semiconductor may include one or more of IZO, IGZO, ITZO, etc.

The panel (PNL) may include a transistor having a structure corresponding to a leakage current blocking diode (LCPD). The transistor may include a third oxide semiconductor made of the same material as the first oxide semiconductor (OSEM1) and a fourth oxide semiconductor made of the same material as the second oxide semiconductor (OSEM2), and may be arranged in an active area (A/A) and/or a non-active area (N/A) of the panel (PNL).

When a transistor having a structure corresponding to a leakage current blocking diode (LCPD) has a top gate structure, in the leakage current blocking diode (LCPD), the first oxide semiconductor (OSEM1) must be composed of a P-type oxide semiconductor and the second oxide semiconductor (OSEM2) must be composed of an N-type oxide semiconductor. Therefore, in the transistor having a structure corresponding to the leakage current blocking diode (LCPD), the third oxide semiconductor must be composed of a P-type oxide semiconductor and the fourth oxide semiconductor must be composed of an N-type oxide semiconductor. If the first oxide semiconductor (OSEM1) and the third oxide semiconductor are composed of N-type oxide semiconductors and the second oxide semiconductor (OSEM2) and the fourth oxide semiconductor are composed of P-type oxide semiconductors, a conductive issue of the first and fourth oxide semiconductors may occur in the transistor having a structure corresponding to the leakage current blocking diode (LCPD), and the transistor having a structure corresponding to the leakage current blocking diode (LCPD) may not operate normally.

When a transistor having a structure corresponding to a leakage current blocking diode (LCPD) has a bottom gate structure, in the leakage current blocking diode (LCPD), the first oxide semiconductor (OSEM1) must be composed of an N-type oxide semiconductor and the second oxide semiconductor (OSEM2) must be composed of a P-type oxide semiconductor. Therefore, in the transistor having a structure corresponding to the leakage current blocking diode (LCPD), the third oxide semiconductor must be composed of an N-type oxide semiconductor and the fourth oxide semiconductor must be composed of a P-type oxide semiconductor. If the first oxide semiconductor (OSEM1) and the third oxide semiconductor are composed of P-type oxide semiconductors and the second oxide semiconductor (OSEM2) and the fourth oxide semiconductor are composed of N-type oxide semiconductors, a conductive issue of the first and fourth oxide semiconductors (ACT1, ACT2) may occur in the transistor having a structure corresponding to the leakage current blocking diode (LCPD), and the transistor having a structure corresponding to the leakage current blocking diode (LCPD) may not operate normally.

That is, the types (N-type, P-type) of the first oxide semiconductor (OSEM1) and the second oxide semiconductor (OSEM1) may vary depending on their proximity to the gate electrode of the transistor. More specifically, the transistor arranged on the panel includes a third oxide semiconductor composed of the same material as the first oxide semiconductor (OSEM1), and a fourth oxide semiconductor composed of the same material as the second oxide semiconductor (OSEM2), and among the third oxide semiconductor and the fourth oxide semiconductor, the oxide semiconductor closer to the gate electrode of the transistor may be an N-type oxide semiconductor.

As described above, the transistors arranged on the panel may have a top-gate structure and/or a bottom-gate structure, but for convenience of explanation, the following explanation will focus on an example having a top-gate structure.

Referring to FIGS. 11 and 13, a passivation layer (PAS) may be placed on a leakage current blocking diode (LCPD).

As illustrated in FIG. 11 and FIG. 12, in the leakage current blocking diode (LCPD), the buffer layer hole (BUF_CNT) and the first interlayer insulating hole (ILD_CNT) may have the same location. That is, the buffer layer hole (BUF_CNT) and the first interlayer insulating hole (ILD_CNT) may overlap.

As illustrated in FIG. 13 and FIG. 14, in a leakage current blocking diode (LCPD), the buffer layer hole (BUF_CNT) and the first interlayer insulating hole (ILD_CNT) may have different locations.

According to this, the first electrode (E1) can more stably contact the first oxide semiconductor (OSEM1), and the second electrode (E2) can more stably contact the second oxide semiconductor (OSEM2).

Meanwhile, the first oxide semiconductor (OSEM1) and the second oxide semiconductor (OSEM2) positioned between the first electrode (E1) and the second electrode (E20) can be formed by various deposition methods. For example, the first oxide semiconductor (OSEM1) and the second oxide semiconductor (OSEM2) can be formed continuously using, for example, a MOCVD (Metal-Organic Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method.

The MOCVD (Metal-Organic Chemical Vapor Deposition) method is a type of chemical vapor deposition (CVD) that forms a thin film by causing a decomposition reaction on the surface by flowing a raw material gas over a high-temperature substrate. It refers to cases where the raw material gas contains an organic metal complex, and is a technology that grows a semiconductor thin film by thermally decomposing the organic metal gas on a heated substrate. In the case of MOCVD, it is operated at a lower temperature than CVD that uses a halogen gas, and thin film control on the atomic order is possible, so a uniform film can be obtained.

In the case of the ALD (Atomic Layer Deposition) method, the reactant materials are separately supplied and the particles formed by the chemical reaction between the reactant gases are deposited on the substrate surface to form a thin film. This is a deposition method in which one reactant material undergoes chemical adsorption on the substrate where the thin film is to be deposited, and then a second or third gas is introduced and chemical adsorption occurs again on the substrate to deposit the thin film.

When the MOCVD method or ALD method described above is used, compared to general PVD (Physical Vapor Deposition) and other general CVD (Chemical Vapor Deposition) methods, the thin film productivity or growth rate can be increased, but the thin film coating property is excellent, and thus, fine thin film thickness control is possible. In other words, when the MOCVD method or ALD method is used, a thin film having excellent step coverage characteristics can be formed.

When the first oxide semiconductor (OSEM1) and the second oxide semiconductor (OSEM2) are formed continuously through MOCVD or ALD, the excellent step coverage characteristics of MOCVD or ALD allow the first oxide semiconductor (OSEM1) and the second oxide semiconductor (OSEM2) to be formed in a nearly vertical structure in the buffer layer hole (BUF-CNT), so that the area of the leakage current blocking diode (LCPD) can be significantly reduced.

According to the example of Fig. 12, the area corresponding to the leakage current blocking diode (LCPD) corresponds to a*b. According to the example of Fig. 14, the area corresponding to the leakage current blocking diode (LCPD) corresponds to c*d.

The area of the leakage current blocking diode (LCPD) of FIG. 12 and FIG. 14 is significantly smaller than the area (x*y) of the leakage current blocking transistor (LCPT) of FIG. 7. Therefore, there is an advantage in that the area occupied by the gate drive circuit (GDC) does not significantly increase when using the leakage current blocking diode (LCPD).

FIG. 15 is an equivalent circuit of a leakage current blocking diode (LCPD) in a gate driving circuit (GDC) arranged in a panel (PNL) according to embodiments of the present invention.

Referring to FIG. 15, a first oxide semiconductor (OSEM1) and a second oxide semiconductor (OSEM2) of a leakage current blocking diode (LCPD) form a channel, and a forward current can flow between a first electrode (E1) and a second electrode (E2) of the leakage current blocking diode (LCPD). A first oxide semiconductor (OSEM1) and a second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) do not form a channel, and a reverse current can be blocked between the first electrode (E1) and the second electrode (E2) of the leakage current blocking diode (LCPD).

In this way, since a leakage current blocking diode (LCPD) operates like a perfect diode, its leakage current blocking effect is superior to that of a leakage current blocking transistor (LCPT) with a diode connection.

The structure of the leakage current blocking diode (LCPD) also influences the structure of other transistors.

More specifically, the structure of the transistor (GIP-TR) included in the gate driving circuit (GDC) disposed in the non-active area (N/A) of the panel (PNL) may be affected by the structure of the leakage current blocking diode (LCPD) included in the gate driving circuit (GDC) disposed in the non-active area (N/A) of the panel (PNL).

Alternatively, the structure of a transistor (SP-TR) arranged in a subpixel (SP) arranged in an active area (A/A) of the panel (PNL) may be affected by the structure of a leakage current blocking diode (LCPD) included in a gate driving circuit (GDC) arranged in a non-active area (N/A) of the panel (PNL).

FIGS. 16 and 17 are plan views showing a leakage current blocking diode (LCPD) in a non-active region (N/A) and a transistor (GIP-TR) in a non-active region (N/A) in a panel (PNL) according to embodiments of the present invention. FIGS. 18 and 19 are plan views showing a leakage current blocking diode (LCPD) in a non-active region (N/A) and a transistor (SP-TR) in an active region (A/A) in a panel (PNL) according to embodiments of the present invention.

FIG. 16 and FIG. 18 illustrate a case in which the buffer layer hole (BUF_CNT) and the first interlayer insulating hole (ILD_CNT) have the same location in a leakage current blocking diode (LCPD), and FIG. 17 and FIG. 19 illustrate a case in which the buffer layer hole (BUF_CNT) and the first interlayer insulating hole (ILD_CNT) have different locations in a leakage current blocking diode (LCPD).

Referring to FIGS. 16 to 19, various transistors (GIP-TR, SP-TR) can be placed on the panel (PNL).

For example, as illustrated in FIGS. 16 and 17, a transistor (GIP-TR) included in a gate driving circuit (GDC) of a GIP type may be placed in a non-active area (N/A) of a panel (PNL). In addition, as illustrated in FIGS. 18 and 19, a transistor (SP-TR) in a subpixel (SP) may be placed in an active area (A/A) of the panel (PNL).

A transistor (GIP-TR) included in a gate drive circuit (GDC) of the GIP type may be a pull-up transistor (Tup) and/or a pull-down transistor (Tdown), and may also be a transistor in a control switch circuit (CSC).

The transistor (SP-TR) within the subpixel (SP) may be a driving transistor (DRT) and a switching transistor (O-SWT) within the subpixel (SP) of the OLED panel in Fig. 3. Alternatively, the transistor (SP-TR) within the subpixel (SP) may be a switching transistor (L-SWT) within the LCD panel in Fig. 4.

Referring to FIGS. 16 to 19, a transistor (GIP-TR) disposed in a non-active region (N/A) and/or a transistor (SP-TR) disposed in an active region (A/A) is configured to: a third oxide semiconductor (OSEM3) disposed on a buffer layer (BUF) and composed of the same material as a first oxide semiconductor (OSEM1); a fourth oxide semiconductor (OSEM4) disposed on the third oxide semiconductor (OSEM3) and composed of the same material as a second oxide semiconductor (OSEM2); a gate insulating film (GI) disposed on the fourth oxide semiconductor (OSEM4); a gate electrode (G) positioned on the gate insulating film (GI); an interlayer insulating film (ILD) disposed on the gate insulating film (GI) and the gate electrode (G); and a second interlayer insulating film hole (ILD_CNT_S) of the interlayer insulating film (ILD) disposed on the interlayer insulating film (ILD) and directly or indirectly connected to one end of the fourth oxide semiconductor (OSEM4). It may include a source electrode (S) made of the same material as the second electrode (E2), a drain electrode (D) arranged on an interlayer insulating film (ILD) and in direct or indirect contact with the other end of a fourth oxide semiconductor (OSEM4) through a third interlayer insulating film hole (ILD_CNT_D) of the interlayer insulating film (ILD), and made of the same material as the second electrode (E2).

Referring to FIGS. 16 to 19, with respect to channel formation of a transistor (GIP-TR) disposed in a non-active region (N/A) and/or a transistor (SP-TR) disposed in an active region (A/A), a portion overlapping the gate electrode (G) in the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4) corresponds to a channel area (CHA). In this channel area (CHA), an actual channel may be formed only in the fourth oxide semiconductor (OSEM4) among the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4), and no channel may be formed in the third oxide semiconductor (OSEM3).

Referring to FIGS. 16 and 17, a lower pattern (DP) may be placed under a transistor (GIP-TR) positioned in a non-active region (N/A) of a panel (PNL). That is, a lower pattern (DP) may be placed overlapping a third oxide semiconductor (OSEM3) of the transistor (GIP-TR) with a buffer layer (BUF) therebetween.

The subpattern (DP) disposed under the transistor (GIP-TR) disposed in the non-active region (N/A) can be composed of the same material as the first electrode (E1) of the leakage current blocking diode (LCPD). That is, the subpattern (DP) disposed under the transistor (GIP-TR) disposed in the non-active region (N/A) can be formed together with the first electrode (E1) of the leakage current blocking diode (LCPD).

In this way, by arranging the lower pattern (DP) under the transistor (GIP-TR) arranged in the non-active region (N/A), the threshold voltage, etc. of the transistor (GIP-TR) arranged in the non-active region (N/A) can be stabilized. For example, the lower pattern (DP) arranged under the transistor (GIP-TR) arranged in the non-active region (N/A) can prevent a negative shift in the threshold voltage of the transistor (GIP-TR) in the gate driving circuit (GDC). Accordingly, the gate driving circuit (GDC) can operate normally.

Referring to FIGS. 18 and 19, a lower pattern (DP) may be placed under a transistor (SP-TR) placed in an active area (A/A) of a panel (PNL). That is, a lower pattern (DP) may be placed overlapping a third oxide semiconductor (OSEM3) of a transistor (SP-TR) in a subpixel (SP) with a buffer layer (BUF) therebetween.

The sub-pattern (DP) disposed under the transistor (SP-TR) disposed in the active region (A/A) may be composed of the same material as the first electrode (E1) of the leakage current blocking diode (LCPD). That is, the sub-pattern (DP) disposed under the transistor (SP-TR) disposed in the active region (A/A) may be formed together with the first electrode (E1) of the leakage current blocking diode (LCPD).

In this way, by arranging the sub-pattern (DP) under the transistor (SP-TR) arranged in the active area (A/A), the threshold voltage, etc. of the transistor (SP-TR) arranged in the active area (A/A) can be stabilized. For example, the sub-pattern (DP) arranged under the transistor (SP-TR) arranged in the active area (A/A) can prevent a negative shift in the threshold voltage of the transistor (SP-TR) in the sub-pixel (SP). Accordingly, the sub-pixel (SP) can be driven normally.

The sub-pattern (DP) mentioned above is a pattern formed together with the formation of the first electrode (E1) of the leakage current blocking diode (LCPD).

FIGS. 20 to 24 are drawings showing various types of lower patterns (DPs) arranged under a transistor (SP-TR) arranged in an active region (A/A) or a transistor (GIP-TR) arranged in a non-active region (N/A), according to the stacked structure of a leakage current blocking diode (LCPD) in a gate driving circuit (GDC) arranged in a panel (PNL) according to embodiments of the present invention.

Referring to FIG. 20, the lower pattern (DP) may be a voltage wiring (VL) for transmitting various voltages.

By utilizing the sub-pattern (DP) formed together in the area of the transistor (GIP-TR, SP-TR) as a voltage wiring (VL) according to the formation of the first electrode (E1) of the leakage current blocking diode (LCPD), efficient panel production can be made possible.

Referring to FIG. 21, the lower pattern (DP) may be a floating or light shield (LS) to which a specific voltage is applied.

A lower pattern (DP) disposed below a transistor (SP-TR) disposed in an active area (A/A) can prevent a channel of a transistor (SP-TR) within a subpixel (SP) from being exposed to light. In this way, by preventing the channel of a transistor (SP-TR) within a subpixel (SP) from being exposed to light, an abnormal shift in a threshold voltage of a transistor (SP-TR) within a subpixel (SP) can be prevented.

A lower pattern (DP) disposed under a transistor (GIP-TR) disposed in a non-active region (N/A) can prevent a channel of the transistor (GIP-TR) in the gate driving circuit (GDC) from being exposed to light. In this way, by preventing the channel of the transistor (GIP-TR) in the gate driving circuit (GDC) from being exposed to light, an abnormal shift in the threshold voltage of the transistor (GIP-TR) in the gate driving circuit (GDC) can be prevented.

Referring to FIGS. 22 to 24, the lower pattern (DP) can be electrically connected to one of the source electrode (S), drain electrode (D), and gate electrode (G) of the transistor (GIP-TR, SP-TR).

Referring to FIG. 22, the lower pattern (DP) can be electrically connected to the source electrode (S) of the transistor (GIP-TR, SP-TR). Referring to FIG. 23, the lower pattern (DP) can be electrically connected to the drain electrode (D) of the transistor (GIP-TR, SP-TR).

The lower pattern (DP) is electrically connected to the source electrode (S) or drain electrode (D) of the transistor (GIP-TR, SP-TR), so that the transistor (GIP-TR, SP-TR) can operate stably.

For example, if a sub-pattern (DP) is placed in an area of a driving transistor (DRT) among the transistors (DRT, O-SWT) in a sub-pixel (SP) of an OLED panel of Fig. 3 and the sub-pattern (DP) is electrically connected to a source electrode (S) or a drain electrode (D) of the driving transistor (DRT), the driving transistor (DRT) can operate more stably.

Referring to FIG. 24, the lower pattern (DP) can be electrically connected to the gate electrode (G) of the transistor (GIP-TR, SP-TR). In this case, the lower pattern (DP) can function as an additional gate electrode (G') together with the gate electrode (G) positioned on the gate insulating film (GI). Accordingly, the transistor (GIP-TR, SP-TR) can have a structure having double gate electrodes (G, G').

As illustrated in FIGS. 22 to 24, a lower pattern (DP) electrically connected to one of the source electrode (S), drain electrode (D), and gate electrode (G) of a transistor (GIP-TR, SP-TR) may be a light shield (LS).

As illustrated in FIGS. 16 to 24, the transistors (GIP-TR, SP-TR) may have a junction structure of different types (P type, N type) of the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4). In some cases, among the different types (P type, N type) of the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4), the third oxide semiconductor (OSEM3) may not be formed and only the fourth oxide semiconductor (OSEM4) may be formed. That is, the transistors (GIP-TR, SP-TR) may include only one type (N type or P type) of the fourth oxide semiconductor (OSEM4) that is in contact with the source/drain electrodes (S/D).

However, when the transistor (GIP-TR, SP-TR) operates under a junction structure of a third oxide semiconductor (OSEM3) and a fourth oxide semiconductor (OSEM4) of different types (P type, N type), the device reliability (device stability) of the transistor (GIP-TR, SP-TR) can be improved in terms of threshold voltage characteristics compared to a case where it includes only one type (N type or P type) of the fourth oxide semiconductor (OSEM4).

To explain in more detail, when only one type (N-type or P-type) of the fourth oxide semiconductor (OSEM4) is included, the threshold voltage of the transistor (GIP-TR, SP-TR) shifts in an undesirable negative direction (or positive direction) that deteriorates the device performance, so that the device reliability (device performance) such as the on-off characteristics of the transistor (GIP-TR, SP-TR) may deteriorate.

There is a difference in how close the energy level of the conduction band of each of the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4) of different types (P type, N type) is positioned to the Fermi level. That is, the energy level of the conduction band of the N-type oxide semiconductor is formed close to the Fermi level, and the energy level of the conduction band of the P-type oxide semiconductor is formed farther from the Fermi level. Due to this phenomenon, a transistor (GIP-TR, SP-TR) having a junction structure of the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4) of different types (P type, N type) exhibits a characteristic in which the threshold voltage, which can be shifted in the negative direction, shifts in the positive direction due to the difference between the energy level of the conduction band of each of the third oxide semiconductor (OSEM3) and the fourth oxide semiconductor (OSEM4) of different types (P type, N type) and the Fermi level.

That is, when different types (P type, N type) of third oxide semiconductor (OSEM3) and fourth oxide semiconductor (OSEM4) are bonded to form a structure, the threshold voltage of the transistor (GIP-TR, SP-TR) is prevented from undesirably shifting in one direction (e.g., negative direction), so that the device reliability (performance) of the transistor (GIP-TR, SP-TR) can be improved.

In summary, when a transistor (GIP-TR, SP-TR) is formed by joining different types (P type, N type) of a third oxide semiconductor (OSEM3) and a fourth oxide semiconductor (OSEM4), there is a process advantage in that the transistor (GIP-TR, SP-TR) can be formed to correspond to the structure of a leakage current blocking diode (LCPD) compared to a transistor (GIP-TR, SP-TR) that includes only one type (N type or P type) of the fourth oxide semiconductor (OSEM4). That is, since the first and second oxide semiconductors (OSEM1, OSEM2) of the leakage current blocking diode (LCPD) and the third and fourth oxide semiconductors (OSEM3, OSEM4) of the transistor (GIP-TR, SP-TR) can be formed together in common, there may be process advantages such as a reduction in the number of mask processes, an increase in process speed, and an increase in process convenience. In addition to these process advantages, it can have a very important advantage of improving the device reliability (device performance) of transistors (GIP-TR, SP-TR) from the perspective of threshold voltage (threshold voltage distribution).

FIG. 25 is a graph showing the relationship (tendency) between the mobility and the thickness (T2) of the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) in the gate driving circuit (GDC) arranged in the panel (PNL) according to embodiments of the present invention.

Referring to Fig. 25, the second oxide semiconductor (OSEM2), which is an N-type oxide semiconductor, must also function as a channel of the transistor (GIP-TR, SP-TR), and therefore, must be set to an appropriate thickness (T2) for normal operation of the transistor (GIP-TR, SP-TR).

Once the desired mobility of the transistor (GIP-TR, SP-TR) is determined, the appropriate thickness (T2) of the second oxide semiconductor (OSEM2) must be determined.

As illustrated in FIG. 25, when the desired mobility of the transistor (GIP-TR, SP-TR) increases, the upper limit of the appropriate thickness (T2) of the second oxide semiconductor (OSEM2) may decrease. That is, the desired mobility of the transistor (GIP-TR, SP-TR) and the upper limit of the appropriate thickness (T2) of the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) corresponding to the same material as the fourth oxide semiconductor (OSEM4) among the first and fourth oxide semiconductors (ACT1, ACT2) of the transistor (GIP-TR, SP-TR) may be inversely proportional.

For example, the minimum thickness (T2) of the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) may be a value between 50Å and 80Å. In addition, if the thickness (T2) of the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) is too thick, carrier mobility may decrease.

For example, the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) may have a thickness (T2) of 50 Å or more. Accordingly, by way of example, the second oxide semiconductor (OSEM2) of the leakage current blocking diode (LCPD) and the fourth oxide semiconductor (OSEM4) formed together with the second oxide semiconductor (OSEM2) may have a thickness (T2) of 50 Å to 500 Å.

When a first oxide semiconductor (OSEM1) and a third oxide semiconductor (OSEM3) formed together with the same material as the first oxide semiconductor (OSEM1) and a fourth oxide semiconductor (OSEM4) formed together with the same material as the second oxide semiconductor (OSEM2) are continuously formed using a MOCVD or ALD method, they can have superior step coverage characteristics compared to those deposited using other general deposition methods.

And, when the first oxide semiconductor (OSEM1) and the third oxide semiconductor (OSEM3) formed together with the same material as the first oxide semiconductor, and the fourth oxide semiconductor (OSEM4) formed together with the second oxide semiconductor (OSEM2) and the same material are formed through MOCVD or ALD, a thin film having better thickness uniformity and composition uniformity and having a higher density can be formed compared to a case where the thin film is formed through other general deposition methods such as sputtering.

In addition, when the first oxide semiconductor (OSEM1) and the third oxide semiconductor (OSEM3) formed together with the same material as the first oxide semiconductor (OSEM1) and the fourth oxide semiconductor (OSEM4) formed together with the second oxide semiconductor (OSEM2) and the same material are formed through MOCVD or ALD, they can have a higher carrier concentration and a smaller thin film resistivity than when formed through other general deposition methods such as sputtering.

According to the embodiments of the present invention described above, a gate driving circuit (GDC) capable of blocking leakage current and an electronic device and panel (PNL) including the same can be provided.

In addition, according to embodiments of the present invention, a gate driving circuit (GDC) having a small-area leakage current blocking structure and an electronic device and panel (PNL) including the same can be provided.

In addition, according to embodiments of the present invention, a gate driving circuit (GDC) including a diode (LCPD) having excellent leakage current blocking performance, and an electronic device and panel (PNL) including the same can be provided.

In addition, according to embodiments of the present invention, an electronic device, a panel (PNL), and a gate driving circuit (GDC) including a transistor (GIP-TR, SP-TR) having a structure linked to a diode (LCPD) having excellent leakage current blocking performance can be provided.

The above description and the attached drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art will appreciate that various modifications and variations, such as combination, separation, substitution, and change of the configuration, may be made without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to explain it, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims (21)

A panel in which a plurality of data lines and a plurality of gate lines are arranged and a plurality of subpixels are arranged;
a data driver for driving the above-mentioned plurality of data lines; and
A gate driver for driving the above plurality of gate lines is included,
The above gate driver comprises a plurality of gate driving circuits arranged in a non-active area of the panel,
Each of the above multiple gate driving circuits,
A pull-up transistor that outputs a gate signal corresponding to the first level voltage to the gate line;
A pull-down transistor that outputs a gate signal corresponding to a second level voltage to the above gate line; and
It includes a control switch circuit that controls the gate node of the pull-up transistor and the gate node of the pull-down transistor,
The above control switch circuit comprises a diode, the diode comprising:
A first electrode positioned on the substrate,
A first oxide semiconductor disposed on a buffer layer that covers the first electrode and is electrically connected to the first electrode through a buffer layer hole of the buffer layer,
A second oxide semiconductor disposed on the first oxide semiconductor,
An electronic device comprising a second electrode disposed on an interlayer insulating film disposed on the second oxide semiconductor and electrically connected to the second oxide semiconductor through a first interlayer insulating film hole of the interlayer insulating film.
In the first paragraph,
The first oxide semiconductor is composed of a P-type oxide semiconductor, and the second oxide semiconductor is composed of an N-type oxide semiconductor, or
An electronic device wherein the first oxide semiconductor is composed of the N-type oxide semiconductor and the second oxide semiconductor is composed of the P-type oxide semiconductor.
In the first paragraph,
The transistors placed on the above panel are,
It includes a third oxide semiconductor composed of the same material as the first oxide semiconductor, and a fourth oxide semiconductor composed of the same material as the second oxide semiconductor.
An electronic device wherein among the third oxide semiconductor and the fourth oxide semiconductor, the oxide semiconductor closer to the gate electrode of the transistor is an N-type oxide semiconductor.
In the first paragraph,
An electronic device in which the above buffer layer hole and the above first interlayer insulating film hole overlap.
In the first paragraph,
An electronic device in which the above buffer layer hole and the above first interlayer insulating film hole have different positions.
In the first paragraph,
The first oxide semiconductor and the second oxide semiconductor form a channel, and a forward current flows between the first electrode and the second electrode of the diode.
An electronic device in which the first oxide semiconductor and the second oxide semiconductor do not form a channel, and reverse current is blocked between the first electrode and the second electrode of the diode.
In the first paragraph,
A transistor is placed on the above panel, and the transistor is
A third oxide semiconductor is disposed on the above buffer layer and is composed of the same material as the first oxide semiconductor;
A fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor;
A source electrode that is in contact with one end of the fourth oxide semiconductor and is composed of the same material as the second electrode;
An electronic device comprising a drain electrode in contact with the other end of the fourth oxide semiconductor and composed of the same material as the second electrode.
In Article 7,
An electronic device in which a channel is formed in the fourth oxide semiconductor among the third oxide semiconductor and the fourth oxide semiconductor.
In Article 7,
An electronic device in which the above transistor is included in each of the plurality of gate driving circuits arranged in the non-active region of the above panel.
In Article 7,
The above transistor is an electronic device arranged in the subpixel arranged in the active area of the above panel.
In Article 7,
An electronic device further comprising a sub-pattern disposed to overlap the third oxide semiconductor of the transistor with the buffer layer interposed therebetween, wherein the sub-pattern is composed of the same material as the first electrode of the diode.
In Article 11,
The above sub-pattern is an electronic device with voltage wiring.
In Article 11,
The above sub-pattern is an electronic device which is a light shield that is floating or to which a specific voltage is applied.
In Article 11,
The above sub-pattern is an electronic device electrically connected to the source electrode or the drain electrode.
In Article 11,
The above sub-pattern is an electronic device electrically connected to the gate electrode.
In the first paragraph,
An electronic device wherein the second oxide semiconductor has a thickness in the range of 50 Å to 500 Å.
A plurality of subpixels defined by a plurality of data lines and a plurality of gate lines are arranged in the active area,
A plurality of gate driving circuits for driving the above plurality of gate lines are arranged in a non-active region,
Each of the above multiple gate driving circuits,
A pull-up transistor that outputs a gate signal corresponding to the first level voltage to the gate line;
A pull-down transistor that outputs a gate signal corresponding to a second level voltage to the above gate line; and
It includes a control switch circuit that controls the gate node of the pull-up transistor and the gate node of the pull-down transistor,
The above control switch circuit comprises a diode, the diode comprising:
A first electrode positioned on the substrate,
A first oxide semiconductor disposed on a buffer layer that covers the first electrode and is electrically connected to the first electrode through a buffer layer hole of the buffer layer,
A second oxide semiconductor disposed on the first oxide semiconductor,
A panel including a second electrode disposed on an interlayer insulating film disposed on the second oxide semiconductor and electrically connected to the second oxide semiconductor through a first interlayer insulating film hole of the interlayer insulating film.
In Article 17,
At least one of the transistors in the gate driving circuit and the transistors in the subpixel,
A third oxide semiconductor is disposed on the above buffer layer and is composed of the same material as the first oxide semiconductor;
A fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor;
A source electrode that is in contact with one end of the fourth oxide semiconductor and is composed of the same material as the second electrode;
A panel including a drain electrode in contact with the other end of the fourth oxide semiconductor and composed of the same material as the second electrode.
In a gate driving circuit that drives a gate line arranged on a panel,
A pull-up transistor that outputs a gate signal corresponding to the first level voltage to the gate line;
A pull-down transistor that outputs a gate signal corresponding to a second level voltage to the above gate line; and
It includes a control switch circuit that controls the gate node of the pull-up transistor and the gate node of the pull-down transistor,
The above control switch circuit comprises a diode, the diode comprising:
A first electrode positioned on the substrate,
A first oxide semiconductor disposed on a buffer layer that covers the first electrode and is electrically connected to the first electrode through a buffer layer hole of the buffer layer,
A second oxide semiconductor disposed on the first oxide semiconductor,
A gate driving circuit including a second electrode disposed on an interlayer insulating film disposed on the second oxide semiconductor and electrically connected to the second oxide semiconductor through a first interlayer insulating film hole of the interlayer insulating film.
In Article 19,
The first oxide semiconductor is composed of a P-type oxide semiconductor, and the second oxide semiconductor is composed of an N-type oxide semiconductor, or
A gate driving circuit wherein the first oxide semiconductor is composed of the N-type oxide semiconductor, and the second oxide semiconductor is composed of the P-type oxide semiconductor.
In Article 19,
A transistor included in the above control switch circuit, at least one of the pull-up transistor and the pull-down transistor,
A third oxide semiconductor is disposed on the above buffer layer and is composed of the same material as the first oxide semiconductor;
A fourth oxide semiconductor disposed on the third oxide semiconductor and composed of the same material as the second oxide semiconductor;
A source electrode that is in contact with one end of the fourth oxide semiconductor and is composed of the same material as the second electrode;
A gate driving circuit including a drain electrode that is in contact with the other end of the fourth oxide semiconductor and is composed of the same material as the second electrode.

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