KR102753349B1 - High-electron-mobility transistor and method of manufacuring the same - Google Patents

Abstract

The present invention provides a HEMT device having a low-resistance access region and a method for manufacturing the same. A substrate and a portion of a transition layer below an access region of a HEMT device are etched, and a back protection layer and a back metal electrode are formed in the etched portion. By applying a voltage to the back metal electrode to increase the concentration of 2DEG, the resistance of the access region is reduced, thereby improving the drain current and transconductance, thereby improving the output characteristics and frequency characteristics of the device. In addition, when the HEMT device is in a turn-off state, by applying a voltage to the back metal electrode to deplete the 2DEG, the leakage current and power consumption can be reduced.

Description

{HIGH-ELECTRON-MOBILITY TRANSISTOR AND METHOD OF MANUFACURING THE SAME}

The present invention relates to a technology for reducing the internal resistance and improving the performance of a high electron mobility transistor (HEMT).

In a high electron mobility transistor (HEMT), a 2DEG (2-Dimensional Electron Gas) is generated near the heterojunction interface (interface between the semiconductor layer and the barrier layer) due to the band discontinuity and polarization resulting from the difference in band gaps when hetero semiconductors having different energy band gaps are joined. Electron movement between the source and drain electrodes occurs through the 2DEG layer and is controlled by the bias voltage applied to the gate electrode.

The concentration of electrons existing in the 2DEG layer is mainly determined by the materials used in the semiconductor layer and the barrier layer, and is partially affected by the charges existing inside or at the interface of the barrier layer or the dielectric layer existing over the barrier layer. However, the charges existing inside or at the interface of the barrier layer or the dielectric layer existing over the barrier layer are generally unintentionally generated during the process of the HEMT device, and thus it is very difficult to control the concentration of the 2DEG through this.

The resistance inside the HEMT device can be divided into the resistance of the access region between the gate and source and gate and drain electrodes, the resistance of the part under the gate electrode, and the source-drain contact resistance. As the resistance inside the HEMT device increases, the drain current and transconductance (the change in drain current according to the change in gate voltage) decrease. Therefore, it is necessary to lower the resistance inside the HEMT device to improve the drain current and transconductance, thereby improving the output and frequency characteristics of the device. In addition, the leakage current when a general HEMT is turned off causes heat generation and an increase in power consumption of the device. Therefore, when the HEMT device is turned off, by applying a voltage to the back metal electrode to deplete the 2DEG, the leakage current and power consumption of the device can be reduced.

According to previous reports, the resistance of the access region is determined by the concentration of 2DEG generated at the heterojunction, and in the case of a typical HEMT device, the concentration of 2DEG in the access region cannot be increased after the device fabrication is completed.

The purpose of the present invention is to improve the output and frequency characteristics of a HEMT device by reducing the resistance of an access region among the three internal resistances existing in the HEMT device.

In order to solve the above problem, in the present invention, a HEMT device is manufactured by etching a portion of a substrate (which may include a portion of a transition layer) below an access region and forming a dielectric film and a rear metal electrode in the etched portion. By applying a voltage to the rear metal electrode of the HEMT device manufactured in this manner to increase the concentration of 2DEG, the resistance of the access region can be reduced.

More specifically, a HEMT device is fabricated by etching a substrate under the source-gate and gate-drain regions of the HEMT device and forming a back metal electrode in the etched region. The HEMT device fabricated in this manner can improve the output and frequency characteristics of the device by applying voltage to the back metal electrode to increase the concentration of a two-dimensional electron gas layer (2DEG) existing in the source-gate and gate-drain regions and reduce the resistance inside the device, thereby providing a method for fabricating a HEMT device. In addition, the 2DEG can be depleted by applying voltage to the back metal electrode. By utilizing this, the leakage current of the device can be reduced and power consumption can be improved by depleting the 2DEG when the HEMT device is turned off.

The method for manufacturing a HEMT according to the present invention is as follows.

First, as in a general process, a transition layer is formed on a substrate made of a material such as silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, or diamond. A semiconductor layer is provided in contact with the transition layer. A barrier layer is provided in contact with the semiconductor layer, thereby forming a heterojunction with the semiconductor layer. A source region, a drain region, and a gate electrode are formed in the barrier layer. A protective layer is formed. The upper portions of the source electrode, the drain electrode, and the gate electrode covered with the protective layer are etched to open. A protective substrate is bonded to the protective layer, the source electrode, the drain electrode, and the gate electrode. Then, the substrate is thinned.

Next, in a process according to the features of the present invention, a portion below the access area of the HEMT device in the substrate and the transition layer is etched. A back protection layer is formed on the substrate and the transition layer. The remaining portion of the back protection layer except for the portion where the back metal electrode to be described later is to be formed is etched. A back metal electrode is formed in the back protection layer. The bonding material and the protective substrate are removed, thereby completing the HEMT device according to the present invention.

The configuration and operation of the present invention will become more clear through specific embodiments described later with reference to the drawings.

In the present invention, a HEMT device with lowered resistance in an access region is manufactured by etching a rear substrate and manufacturing a rear metal electrode, and applying voltage to the manufactured rear metal electrode to increase the 2DEG concentration. This reduces the internal resistance of the HEMT device, thereby improving the drain current and transconductance, and thus improving the output and frequency characteristics. As an additional effect, the 2DEG can be depleted by applying voltage to the rear metal electrode. By utilizing this, if the 2DEG is depleted only when the device is turned off, the leakage current of the device can be reduced, thereby improving the power consumption of the device.

FIG. 1 is a cross-sectional view illustrating a HEMT device having a low-resistance access region according to the present invention.
FIGS. 2 to 15 are cross-sectional views sequentially showing a method for manufacturing a HEMT device having a low-resistance access region according to the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become apparent by referring to the preferred embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments described below, but can be implemented in various other forms. The embodiments are provided only to completely disclose the present invention and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined by the description of the claims. In addition, the terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular forms also include the plural forms unless specifically stated otherwise. In addition, the terms "comprise", "comprising," etc., used in the specification are used in a meaning that does not exclude the presence or addition of one or more other components, steps, operations, and/or elements other than the mentioned components, steps, operations, and/or elements.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the embodiments, if a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

FIG. 1 is a cross-sectional view illustrating a HEMT device having a low-resistance access region according to one embodiment of the present invention.

Referring to FIG. 1, a HEMT device according to one embodiment of the present invention includes a transition layer (101), a semiconductor layer (102), and a barrier layer (103) sequentially formed on a substrate (105), source and drain electrodes (202) and a gate electrode (203) provided on the barrier layer (103), an isolation region (301), a protective layer (401), a back protective layer (402), and a back metal electrode (204).

Hereinafter, the detailed structure of a HEMT and its manufacturing method according to one embodiment of the present invention will be described in detail with reference to the attached drawings FIGS. 2 to 15.

Referring to Fig. 2, first, a substrate (100) is manufactured using a material such as silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, or diamond. However, the material of the substrate (100) is not limited to these.

A transition layer (101) is formed on a substrate (100). The transition layer (101) is a layer for alleviating the difference in lattice constant and thermal expansion coefficient between the substrate (100) and a semiconductor layer (102) to be described later. The transition layer (101) may be provided in a single-layer or multi-layer structure.

A semiconductor layer (102) is provided in contact with the transition layer (101). The semiconductor layer (102) may be a group III-V compound semiconductor including AlN, InN, GaN, AlGaN, InGaN, AlInN, AlGaInN, GaAs, etc. However, the semiconductor layer (102) is not limited to these, and other material layers may be used as long as a 2DEG layer can be formed inside the semiconductor layer (102). The thickness of the semiconductor layer (102) may be tens of micrometers or less. The 2DEG layer formed inside the semiconductor layer (102) may be a layer that electrically connects the source and drain electrodes (202). The semiconductor layer (102) may not be doped, and in some cases, a small amount of impurities may be added.

A barrier layer (103) is provided in contact with the semiconductor layer (102) and forms a heterojunction with the semiconductor layer (102). In some cases, the barrier layer (103) may include at least one of Al, Ga, In, and B among nitrides and may have a single-layer or multi-layer structure for increasing the electron concentration of the 2DEG layer. For example, the barrier layer (103) is formed as a single-layer or multi-layer structure including at least one of various nitrides such as InGaN, AlGaN, AlInGaN, AlInN, and AlN. The thickness of the barrier layer (103) may be tens of nanometers or less, and in some cases, the barrier layer (103) may be a layer to which a small amount of impurities is added or may not be added.

The semiconductor layer (102) and the barrier layer (103) may include semiconductor materials having different lattice constants, and the barrier layer (103) has a wider band gap than the semiconductor layer (102). A 2DEG layer is generated in the semiconductor layer (102) by the polarization occurring at the interface when the semiconductor layer (102) and the barrier layer (103) are heterojunctions and the band cutting occurring from the difference in the energy band gap. This 2DEG layer electrically connects the source and drain electrodes (202) in the HEMT device and is used as a channel through which electrons move.

Although not shown in the drawing, an interfacial layer may be formed between the semiconductor layer (102) and the barrier layer (103). This interfacial layer improves the electron concentration and electron mobility of the 2DEG layer by improving the interfacial characteristics of the semiconductor layer (102) and the barrier layer (103). This interfacial layer may be a material such as AlN having a thickness of several nanometers or less.

Referring to FIG. 3, conductive metal patterns (201) are formed on the barrier layer (103). These metal patterns (201) are used as drain and source electrodes (202) depending on their positions. These metal patterns (201) may be one or more of Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or alloys thereof. The deposition thickness of the metal patterns (201) may be several nanometers to several micrometers or less. The metal patterns (201) are diffused into the barrier layer (103) and the semiconductor layer (102) by rapid heat treatment described below, so that electrons can move from the source electrode (202) to the drain electrode (202) through the 2DEG layer of the semiconductor layer (102).

Referring to FIG. 4, a metal pattern (201 in FIG. 3) formed on a barrier layer (103) through rapid heat treatment is diffused into the barrier layer (103) and the semiconductor layer (102) to form an ohmic contact, thereby forming a source and drain region (202). Any method that allows the metal patterns (201) to form an alloy and diffuse into the semiconductor layer (102) and the barrier layer (103) may be applied. The heat treatment temperature may be about 1100°C or lower.

Referring to Fig. 5, an isolation region (300) is formed for isolation between devices. The isolation region (300) is formed by destroying the lattice structure using ion implantation outside the active region of the HEMT device. At this time, phosphorous can be used as the ion to be implanted, but other types of ions can also be used if they are possible for isolation of the device.

Referring to FIG. 6, a gate electrode (203) is formed on the barrier layer (103). The gate electrode (203) may be Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or an alloy thereof. Although not shown in the figure, the gate electrode (203) may be provided in a T-shape or a G-shape, such as one in which the width of the upper portion is larger than the width of the lower portion, in order to lower the resistance.

Referring to FIG. 7, a protective layer (401) covering the source and drain electrodes (202), the barrier layer (103), the gate electrode (203), and the isolation region (301) is formed. The protective layer (401) may be a single-layer or multi-layer structure including at least one of SiO, SiN, or a dielectric having a higher permittivity.

Referring to Fig. 8, the upper portion of the source and drain electrodes (202) and the gate electrode (203) covered with the protective layer (401) is etched to open the opening. The opening etching of the protective layer (401) can be performed by dry etching, wet etching, or a combination of dry and wet etching methods.

Referring to FIG. 9, a protective substrate (104) is bonded to the protective layer (401), the source and drain electrodes (202), and the gate electrode (203) using a bonding material (501). The protective substrate (104) is made of, but is not limited to, silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, or diamond. The bonding material (501) is made of, but is not limited to, BCB (Benzocyclobutene) or wax.

Referring to Fig. 10, the initially used substrate (100) is thinned to create a thinned substrate (105). Thinning is performed using a mechanical or chemical polishing method, and the thickness of the thinned substrate is 100 μm or less. This is to facilitate the rear substrate etching described later.

Referring to FIG. 11, a portion below the access area of the HEMT device is etched in the substrate (105) and the transition layer (101). The substrate is completely etched and removed, and a portion of the transition layer may remain. The thickness of the remaining transition layer should be such that defects caused by the etching do not affect the semiconductor layer (102), and is less than several hundred nm. The etching of the substrate (105) and the transition layer (101) may be dry etching, wet etching, or a combination of dry and wet etching methods.

Referring to FIG. 12, a back protection layer (402) is formed on the substrate (105) and the transition layer (101). The back protection layer (402) may have a single-layer or multi-layer structure including at least one of SiO, SiN, or a dielectric having a higher permittivity. The back protection layer (402) is formed to prevent electrons in the 2DEG from escaping through the back metal electrode, which will be described later.

Referring to Fig. 13, the remaining portion (403) of the back protection layer (402) except for the portion where the back metal electrode to be described later is to be formed is etched. The back protection layer (402) may be etched by dry etching, wet etching, or a combination of dry and wet etching methods. This is to minimize the deterioration of the output and frequency characteristics of the device due to the heat generated during the operation of the HEMT device not being released due to the back protection layer (402) due to the formation of the back protection layer (402).

Referring to FIG. 14, a rear metal electrode (204) is formed on the rear protective layer (402). The rear metal electrode (402) may be Ti, Al, Ni, Au, Pd, Cu, Co, Pt, or an alloy thereof. By applying voltage through the rear metal electrode (204), the electron concentration of the 2DEG layer can be improved, and by utilizing this, the resistance of the access region can be reduced.

Referring to FIG. 15, the bonding material (501) and the protective substrate (104) are removed to complete a HEMT device according to one embodiment of the present invention.

Although the present invention has been described in detail through preferred embodiments thereof so far, those skilled in the art will understand that the present invention can be implemented in specific forms other than those disclosed in the present specification without changing the technical idea or essential features thereof. For example, a method for manufacturing a HEMT device having a low-resistance access region according to one embodiment of the present invention has been described above with reference to FIGS. 2 to 15. However, the HEMT device of the present invention can be manufactured by various modified methods from the above-described method. In addition, the manufacturing process does not necessarily have to be performed in the order of FIGS. 2 to 15, and some processes may be omitted, added, or bypassed in the above-described process.

As such, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. In addition, the scope of protection of the present invention is determined by the claims described below rather than the detailed description above, and all changes or modified forms derived from the scope of the claims and their equivalent concepts should be interpreted as being included in the technical scope of the present invention.

100: substrate, 101: transition layer, 102: semiconductor layer, 103: barrier layer, 104: protective substrate, 105: thinned substrate, 201: metal pattern, 202: source and drain electrodes, 203: gate electrode, 204: back metal electrode, 301: isolation region, 401: protective layer, 402: back protective layer, 501: bonding material

Claims (8)

A method for manufacturing a high-electron-mobility transistor (HEMT) having an access region, which is a region between the gate and source and the gate and drain electrodes, wherein electron movement occurs through a two-dimensional electron gas layer (2DEG layer) formed between source and drain electrodes and is controlled by a bias voltage applied to a gate electrode,
A step of forming a high electron mobility transistor having a source electrode, a drain electrode, and a gate electrode on a substrate;
A step of forming a protective layer covering the source electrode, drain electrode, and gate electrode;
A step of etching the upper portion of the source electrode, drain electrode, and gate electrode covered with the protective layer to open them, and bonding a protective substrate to the protective layer, source electrode, drain electrode, and gate electrode;
A step of thinning the above substrate to create a thinned substrate;
A step of etching and removing a portion of the substrate below the access area of the high electron mobility transistor formed on the substrate, and forming a back protection layer on the back surface of the substrate;
A step of etching the remaining portion of the surface of the above rear protection layer except for the portion where the rear metal electrode is to be formed, and forming the rear metal electrode; and
A method for manufacturing a high electron mobility transistor, comprising the step of removing a protective substrate bonded to the above protective layer, the source electrode, the drain electrode, and the gate electrode. In the first paragraph, the protective substrate
A method for manufacturing a high electron mobility transistor made of a material selected from among silicon carbide (SiC), silicon (Si), gallium nitride (GaN), sapphire, and diamond. A method for manufacturing a high electron mobility transistor, wherein the thickness of the thinned substrate in the first paragraph is 100 μm or less. In the first paragraph, the rear protective layer
A method for manufacturing a high electron mobility transistor made of a material selected from among SiO, SiN, and dielectrics having a higher permittivity than these. A high-electron-mobility transistor (HEMT) in which electron movement occurs through a two-dimensional electron gas layer (2DEG layer) formed between source and drain electrodes and is controlled by a bias voltage applied to a gate electrode and has an access region, which is a region between the gate and source and the gate and drain electrodes,
A back protection layer formed by removing the substrate at the lower part of the access area of the high electron mobility transistor; and
Including a rear metal electrode formed on the rear protective layer,
A high electron mobility transistor, wherein when voltage is applied to the rear metal electrode, the concentration of the 2DEG layer increases and the resistance of the access region decreases. A high-electron-mobility transistor (HEMT) in which electron movement occurs through a two-dimensional electron gas layer (2DEG layer) formed between source and drain electrodes and is controlled by a bias voltage applied to a gate electrode and has an access region, which is a region between the gate and source and the gate and drain electrodes,
A back protection layer formed by removing the substrate at the lower part of the access area of the high electron mobility transistor; and
Including a rear metal electrode formed on the rear protective layer,
A high electron mobility transistor in which the 2DEG layer is depleted when voltage is applied to the rear metal electrode. In clause 5 or 6, the rear protective layer
A high electron mobility transistor fabricated from a material selected from among SiO, SiN, and dielectrics having higher permittivity than these. delete