KR102744389B1 - Inverting switching regulator using charge pump and operating method thereof - Google Patents

Abstract

An inverting switching regulator for generating a negative output voltage from a positive input voltage may include, according to an exemplary embodiment of the present disclosure, an inductor through which an inductor current passes from a first terminal to a second terminal, a flying capacitor connected to the second terminal of the inductor, and a plurality of switches for charging the flying capacitor with an input voltage during a first phase and applying a negative voltage to the second terminal of the inductor by connecting the flying capacitor in series with a ground node and the inductor during a second phase.

Description

{INVERTING SWITCHING REGULATOR USING CHARGE PUMP AND OPERATING METHOD THEREOF}

The technical idea of the present disclosure relates to generation of a negative supply voltage, and more particularly, to an inverting switching regulator using a charge pump and an operating method thereof.

The supply voltage can be generated to provide power to electronic components, i.e., loads, and a switching regulator that generates the supply voltage from an input voltage provided by a battery, etc., can be used. In addition, there may be a load that requires not only a positive supply voltage but also a negative supply voltage, and accordingly, an inverting switching regulator that generates a negative supply voltage from a positive input voltage can be used. When a large voltage swing occurs in the inverting switching regulator, components having a large breakdown voltage may be required. However, such components may have low efficiency due to high parasitic components, may occupy a relatively large area, and may not be easy to integrate with other components in the same integrated circuit.

The technical idea of the present disclosure provides an inverting switching regulator including components having high efficiency due to low voltage swing and a method of operating the same.

To achieve the above object, according to one aspect of the technical idea of the present disclosure, an inverting switching regulator for generating a negative output voltage from a positive input voltage may include an inductor through which an inductor current passes from a first terminal to a second terminal, a flying capacitor connected to the second terminal of the inductor, and a plurality of switches for charging the flying capacitor with an input voltage during a first phase and applying a negative voltage to the second terminal of the inductor by connecting the flying capacitor in series with a ground node and the inductor during a second phase.

According to one aspect of the technical idea of the present disclosure, an inverting switching regulator for generating a negative output voltage from a positive input voltage may include an inductor through which an inductor current passes from a first terminal to a second terminal, and a flying capacitor which is charged with an input voltage during a first phase and induces a negative voltage at the second terminal of the inductor according to the charged charge during a second phase, wherein the inductor current may flow to a ground node during the first phase and to the flying capacitor during the second phase.

According to one aspect of the technical idea of the present disclosure, a method of converting a positive input voltage into a negative output voltage may include: a step of charging a flying capacitor with an input voltage during a first phase; a step of regulating an inductor current to flow to a ground node sequentially through a first terminal and a second terminal of the inductor during the first phase; a step of applying a negative voltage to the second terminal of the inductor according to the charged charge of the flying capacitor during the second phase; and a step of regulating the inductor current to flow to the flying capacitor sequentially through the first terminal and the second terminal of the inductor during the second phase.

According to the inverting switching regulator and its operating method according to the exemplary embodiment of the present disclosure, devices having high efficiency can be used due to the reduced voltage swing.

In addition, according to the inverting switching regulator and its operating method according to the exemplary embodiment of the present disclosure, the inverting switching regulator can have a reduced area and can be easily integrated with other circuits.

In addition, according to the inverting switching regulator and its operating method according to the exemplary embodiment of the present disclosure, reduced output ripple and stable feedback stability can be achieved.

The effects obtainable from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be clearly derived and understood by a person having ordinary skill in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from practicing the exemplary embodiments of the present disclosure can also be derived by a person having ordinary skill in the art from the exemplary embodiments of the present disclosure.

FIG. 1 is a block diagram illustrating an inverting switching regulator according to an exemplary embodiment of the present disclosure.
FIG. 2 illustrates a circuit diagram of an inverting switching regulator according to an exemplary embodiment of the present disclosure.
FIGS. 3A and 3B are circuit diagrams showing equivalent circuits of the inverting switching regulator of FIG. 2 according to exemplary embodiments of the present disclosure.
FIG. 4 is a timing diagram illustrating an example of the operation of the inverting switching regulator of FIG. 2 according to an exemplary embodiment of the present disclosure.
FIG. 5 shows a circuit diagram of an inverting switching regulator according to an exemplary embodiment of the present disclosure.
FIG. 6 is a timing diagram illustrating an example of the operation of the inverting switching regulator of FIG. 5 according to an exemplary embodiment of the present disclosure.
FIGS. 7A and 7B are circuit diagrams showing equivalent circuits of the inverting switching regulator of FIG. 5 according to exemplary embodiments of the present disclosure.
FIG. 8 is a timing diagram illustrating an example of the operation of the inverting switching regulator of FIG. 5 according to an exemplary embodiment of the present disclosure.
FIG. 9 shows a circuit diagram of an inverting switching regulator according to an exemplary embodiment of the present disclosure.
FIG. 10 is a circuit diagram showing an equivalent circuit of the inverting switching regulator of FIG. 9 according to an exemplary embodiment of the present disclosure.
FIG. 11 is a timing diagram illustrating an example of the operation of the inverting switching regulator of FIG. 9 according to an exemplary embodiment of the present disclosure.
FIG. 12 is a flowchart illustrating a method for converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure.
FIG. 13 is a flowchart illustrating a method for converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure.
FIGS. 14A and 14B are flowcharts illustrating examples of a method for converting a positive input voltage to a negative output voltage according to exemplary embodiments of the present disclosure.
FIG. 15 is a flowchart illustrating a method for converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure.
FIGS. 16A, 16B, and 16C are flowcharts illustrating examples of methods for converting a positive input voltage to a negative output voltage according to exemplary embodiments of the present disclosure.
FIG. 17 is a block diagram illustrating a wireless communication device according to an exemplary embodiment of the present disclosure.

FIG. 1 is a block diagram illustrating an inverting switching regulator (10) according to an exemplary embodiment of the present disclosure. The inverting switching regulator (10) can receive a positive input voltage (V _IN ) through an input node (IN) and output a negative output voltage (V _OUT ) through an output node (OUT). The output voltage (V _OUT ) can be used as a supply voltage for other electronic components, i.e., loads. As illustrated in FIG. 1 , the inverting switching regulator (10) can include a switch circuit (12), a switch controller (14), a flying capacitor (C _F ), an inductor (L), and an output capacitor (C _O ). In some embodiments, two or more of the components included in the inverting switching regulator (10) can be included in one package. For example, the switch circuit (12) and the switch controller (14) may be integrated into a single die and included in the same semiconductor package. In some embodiments, the inverting switching regulator (10) may include a printed circuit board (PCB), and at least two of the components of the inverting switching regulator (10) may be mounted on the printed circuit board (PCB) as separate packages.

The inverting switching regulator (10) is a type of switching regulator, and may refer to any electronic circuit that generates a negative output voltage (V _OUT ) by switching the element on/off. For example, the switch circuit (12) of the inverting switching regulator (10) may include a plurality of switches, and at least one switch included in the switch circuit (12) may be turned on/off according to a switch control signal (C_SW) provided from a switch controller (14). Accordingly, the path of the inductor current (I _L ) passing through the inductor (L) may be steered so that a negative output voltage (V _OUT ) is generated. In the present specification, the on state of the switch may refer to a state in which both ends of the switch are electrically connected, and the off state of the switch may refer to a state in which both ends of the switch are electrically disconnected. Additionally, two or more components that are electrically connected via a switch in the on state may be referred to as simply connected, and two or more components that are always electrically connected via a wire or the like may be referred to as coupled.

V_OUT) 중 하나로 설정될 수 있다. 본 명세서에서, 반전형 벅 컨버터, 반전형 부스트 컨버터 및 반전형 벅-부스트 컨버터는, 벅 컨버터, 부스트 컨버터 및 벅-부스트 컨버터로서 단순하게 각각 지칭될 수 있고, 반전 벅 모드, 반전 부스트 모드 및 반전 벅-부스트 모드 역시 벅 모드, 부스트 모드 및 벅-부스트 모드로서 단순하게 각각 지칭될 수 있다. 이하에서, 반전형 스위칭 레귤레이터(10)는 DC-DC 컨버터를 주로 참조하여 설명될 것이나, 본 개시의 예시적 실시예들이 반전형 AC-DC 컨버터 등과 같이 다른 종류의 반전형 스위칭 레귤레이터에도 적용될 수 있는 점이 이해될 것이다.As an example of an inverting switching regulator (10), as described below with reference to FIG. 2, an inverting DC-DC converter can generate a negative output voltage (V _OUT ), which is a DC voltage, from a positive input voltage (V _IN ), which is a DC voltage. For example, an inverting buck converter can generate an output voltage (V _OUT ) having a level higher than the level of the inverted input voltage (V _IN ) (-V _IN ≤V _OUT ≤0). An inverting boost converter can generate an output voltage (V _OUT ) having a level lower than the level of the inverted input voltage (V _IN ) (V _OUT ≤-V _IN ≤0). An inverting buck-boost converter can generate an output voltage (V _OUT ) having a level lower or higher than the level of the inverted input voltage (V _IN ). In some embodiments, the inverting buck-boost converter has an inverting buck mode (-V _IN <V _OUT <0) that generates an output voltage (V _OUT ) having a level higher than that of an inverted input voltage (V _IN ), an inverting boost mode (V _OUT <-V _IN <0) that generates an output voltage (V _OUT ) having a level lower than that of the inverted input voltage (V _IN ), and an inverting buck-boost mode (-V _IN ) that generates an output voltage (V _OUT ) having a level similar to that of the inverted input voltage (V _IN ).

V _OUT ) may be set to one of the following. In this specification, the inverting buck converter, the inverting boost converter and the inverting buck-boost converter may be simply referred to as a buck converter, a boost converter and a buck-boost converter, respectively, and the inverting buck mode, the inverting boost mode and the inverting buck-boost mode may also be simply referred to as a buck mode, a boost mode and a buck-boost mode, respectively. Hereinafter, the inverting switching regulator (10) will be described mainly with reference to a DC-DC converter, but it will be appreciated that the exemplary embodiments of the present disclosure may be applied to other types of inverting switching regulators, such as an inverting AC-DC converter.

The switch circuit (12) may receive a switch control signal (C_SW) from the switch controller (14), and may include at least one switch that is turned on/off according to the switch control signal (C_SW). Each of the switches included in the switch circuit (12) may have any structure that electrically connects or electrically disconnects both ends according to the switch control signal (C_SW) provided from the switch controller (14). In some embodiments, the switch may include an NFET (N-channel Field Effect Transistor) or a PFET (P-channel Field Effect Transistor) having a gate to which the switch control signal (C_SW) is applied, and in some embodiments, may include at least one NFET and/or at least one PFET that are connected in series or in parallel with each other. In addition, in some embodiments, the switch may include at least one other type of transistor, such as a BJT (Bipolar Junction Transistor).

In some embodiments, the switch circuit (12) may form a first circuit including a flying capacitor (C _F ), an inductor (L) and an output capacitor (C _O ) in a first phase (P1), and may form a second circuit including a flying capacitor (C _F ), an inductor (L) and an output capacitor (C _O ) in a second phase (P2), according to a switch control signal (C_SW). For example, the first circuit may charge the flying capacitor (C _F ) with an input voltage (V _IN ) and cause the inductor current (I _L ) to flow to a ground node (GND). Additionally, in the second circuit, the flying capacitor (C _F ) may be connected in series with the ground node (GND) and the inductor (L), and a negative voltage may be induced in the first node ( _{N1) to which the flying capacitor (C F )} and the inductor (L) are connected according to the charge charged in the flying capacitor (C F ), and the inductor current (I _L ) may be caused to flow to the flying capacitor (C _F ). The voltage swing at the nodes of the first and second circuits may be limited, and thus the switch circuit (12) may include elements having a low breakdown voltage, high efficiency, and a reduced area, for example, transistors manufactured with a CMOS (Complementary Metal Oxide Semiconductor) process. As illustrated in Fig. 1, a positive output transfer current (I _D ) can flow from the output node to the switch circuit (12), thereby generating a negative output voltage (V _OUT ) at the output node (OUT). Examples of the switch circuit (12) will be described later with reference to Figs. 2, 5, and 9.

As illustrated in FIG. 1, a flying capacitor (C _F ) and an inductor (L) may be connected at a first node (N1). In the first circuit, the first node (N1) may be connected to the ground node (GND) so that the flying capacitor (C _F ) is charged with an input voltage (V _IN ) and the inductor current (I _L ) flows to the ground node (GND). On the other hand, in the second circuit, the first node (N1) may be disconnected from the ground node (GND) so that the first node (N1) has a negative voltage according to the charge charged in the flying capacitor (C _F ). The output capacitor (C _O ) may be connected to the output node (OUT) and the ground node (GND), and may be charged or discharged so that the output voltage (V _OUT ) may be maintained constant. In some embodiments, the capacitance of the flying capacitor (C _F ), the inductance of the inductor (L) and the capacitance of the output capacitor (C _O ) can be determined based on the input voltage (V _IN ), the output voltage (V _OUT ), the switching frequency and/or the load current (I _O ). Furthermore, in some embodiments, the flying capacitor (C _F ), the inductor (L) and/or the output capacitor (C _O ) can be discrete devices.

The switch controller (14) can generate the switch control signal (C_SW) based on the reference voltage (V _REF ) and the output voltage (V _OUT ). For example, the switch controller (14) can generate a feedback voltage from the output voltage (V _OUT ), and generate the switch control signal (C_SW) so that the feedback voltage matches the reference voltage (V _REF ) by comparing the feedback voltage and the reference voltage (V _REF ). Accordingly, the level of the output voltage (V _OUT ) can be determined by the level of the reference voltage (V _REF ), and the level of the output voltage (V _OUT ) can be changed by changing the level of the reference voltage (V _REF ). In some embodiments, the switch controller (14) can detect at least one of a current, for example, an inductor current (I _L ), an output delivery current (I _D ), and a load current (I _O ), and generate the switch control signal (C_SW) further based on the magnitude of the detected current. In some embodiments, the switch controller (14) may include at least one comparator and at least one logic gate.

In some embodiments, the inverting switching regulator (10) can be set to one of the buck mode, the buck-boost mode, and the boost mode depending on the target level of the output voltage (V _OUT ). For example, the switch controller (14) can set the mode of the inverting switching regulator (10) based on the input voltage (V _IN ) and the reference voltage (V _REF ), and can generate a switch control signal (C_SW) depending on the set mode. In some embodiments, the switch controller (14) can set the inverting switching regulator (10) to buck mode when the output voltage (V _OUT ) is greater than about 90% of the input voltage (V _IN ) inverted voltage (-V _IN ), can set the inverting switching regulator (10) to boost mode when the output voltage (V _OUT ) is less than about 110% of the input voltage (V _IN ) inverted voltage (-V _IN ), and can set the inverting switching regulator (10) to buck-boost mode when the output voltage (V _OUT ) is less than or equal to about 90% but greater than or equal to about 110% of the input voltage (V _IN ) inverted voltage (-V _IN ).

The switch controller (14) can generate a switch control signal (C_SW) so that the flying capacitor (C _F ) and the switch circuit (12) function as a charge pump generating a negative voltage, and can apply the negative voltage generated by the charge pump to the inductor (L) at the start of some phases included in the switching cycle. In some embodiments, the negative voltage applied to the inductor (L) can correspond to a voltage (-V _IN ) that is an inverted input voltage (V _IN ). Accordingly, the voltage applied to both ends of the elements included in the switch circuit (12), i.e., the switches, can be limited, and as a result, the inverting switching regulator (10) can include elements with high efficiency.

The output voltage (V _OUT ) generated by the inverting switching regulator (10) can function as a supply voltage that provides power to electronic components, and such electronic components can be referred to as a load of the inverting switching regulator (10). For example, the output voltage (V _OUT ) can be provided to a digital circuit that processes a digital signal, an analog circuit that processes an analog signal, and/or an RF circuit that processes an RF signal.

FIG. 2 illustrates a circuit diagram of an inverting switching regulator (20) according to an exemplary embodiment of the present disclosure. Specifically, the circuit diagram of FIG. 2 illustrates an inverting switching regulator (20) that functions as an inverting buck converter. As described above with reference to FIG. 1, the inverting switching regulator (20) may include a switch circuit (22), a flying capacitor (C _F ), an inductor (L), and an output capacitor (C _O ).

The switch circuit (22) may include first, second, and third switches (SW1, SW2, SW3). As illustrated in FIG. 2, the first switch (SW1) may be connected to an input node (IN) and a second node (N2), the second switch (SW2) may be connected to a ground node (GND) and the first node (N1), and the third switch (SW3) may be connected to the second node (N2) and the ground node (GND). As described above with reference to FIG. 1, the first, second, and third switches (SW1, SW2, SW3) may be turned on or off by a switch control signal (C_SW) provided by the switch controller (14).

The flying capacitor (C _F ) can be connected to the second switch (SW2) and the inductor (L) at the first node (N1), and can be connected to the first and third switches (SW1, SW3) at the second node (N2). As described below with reference to FIG. 3a , when the first and second switches (SW1, SW2) are turned on and the third switch (SW3) is turned off, the flying capacitor (C _F ) can be charged with the input voltage (V _IN ), while as described below with reference to FIG. 3b , when the first and second switches (SW1, SW2) are turned off and the third switch (SW3) is turned on, the flying capacitor (C _F ) can induce a negative voltage at the first node (N1).

The inductor (L) can have a first terminal (T1) connected to the output node (OUT) and a second terminal (T2) connected to the first node (N1), and the inductor current (I _L ) can flow from the first terminal (T1) to the second terminal (T2). Since the inductor (L) is connected to the output node (OUT), the output transmission current (I _D ) can match the inductor current (I _L ) as illustrated in FIG. 2 (I _L =I _D ). As described below with reference to FIG. 3a , when the second switch (SW2) is turned on, the inductor current (I _L ) can flow to the ground node (GND), while as described below with reference to FIG. 3b , when the second switch (SW2) is turned off, the inductor current (I _L ) can flow to the flying capacitor (C _F ).

The output capacitor (C _O ) can be connected to the inductor (L) at the output node (OUT) and can be connected to the ground node (GND). Accordingly, the output capacitor (C _O ) can receive a portion of the load current (I _O ) or provide a portion of the output delivery current (I _D ).

FIGS. 3A and 3B are circuit diagrams showing equivalent circuits of the inverting switching regulator (20) of FIG. 2 according to exemplary embodiments of the present disclosure, and FIG. 4 is a timing diagram showing an example of the operation of the inverting switching regulator (20) of FIG. 2 according to exemplary embodiments of the present disclosure. Specifically, the circuit diagram of FIG. 3A shows an equivalent circuit (30a) of the inverting switching regulator (20) and a path of an inductor current (I _L ) during a first phase (P1), and the circuit diagram of FIG. 3B shows an equivalent circuit (30b) of the inverting switching regulator (20) and a path of an inductor current (I _L ) during a second phase (P2). In the drawings included in the present specification, durations of phases included in a switching cycle are shown to be the same, but this is for convenience of illustration, and it is to be noted that the durations of the phases may be different. Hereinafter, FIGS. 3a, 3b and 4 will be described with reference to FIG. 2.

Referring to FIGS. 3a and 4, during the first phase (P1), the first and second switches (SW1, SW2) may be turned on, and the third switch (SW3) may be turned off, whereby an equivalent circuit (30a) of FIG. 3a may be formed. As illustrated in FIG. 4, during the first phase (P1), the voltage (V _N2 ) of the second node (N2) may match the input voltage (V _IN ), and the voltage (V _N1 ) of the first node (N1) may match the ground potential. Accordingly, the input voltage (V _IN ) may be applied to the flying capacitor (C _F ), and the flying capacitor (C _F ) may be charged with the input voltage (V _IN ). Additionally, as illustrated in FIG. 3a, the inductor current (I _L ) can flow from the output node (OUT) through the inductor (L) to the ground node (GND), and thus, can gradually decrease due to the ground potential, as illustrated in FIG. 4.

Referring to FIGS. 3b and 4, during the second phase (P2), the first and second switches (SW1, SW2) may be turned off, and the third switch (SW3) may be turned on, whereby the equivalent circuit (30b) of FIG. 3b may be formed. As illustrated in FIG. 4, during the second phase (P2), the voltage (V _N2 ) of the second node (N2) may coincide with the ground potential, and when the second phase (P2) begins, the voltage (V _N1 ) of the first node (N1) may coincide with the inverted voltage (-V _{IN ) of the input voltage (V IN )} . Accordingly, a negative voltage (-V _IN ) may be applied to the second terminal (T2) of the inductor (L) when the second phase (P2) begins. Additionally, as illustrated in FIG. 3b, the inductor current (I _L ) may flow from the output node (OUT) through the inductor (L) to the flying capacitor (C _F ), thereby gradually increasing due to the negative voltage (-V _IN ), as illustrated in FIG. 4 . Although not illustrated in FIG. 4 , in some embodiments, the voltage (V _N1 ) of the first node (N1) during the second phase (P2) may gradually increase due to the inductor current (I _L ).

Assuming a structure of an inverting switching regulator in which one terminal of the inductor is connected to the ground node and the other terminal of the inductor is alternately connected to the input node and the output node, the output transfer current may be discontinuous between the phase in which the inductor is connected to the input node and the phase in which the inductor is connected to the output node. The discontinuous output transfer current may cause a large ripple in the output voltage, which may consequently hinder the generation of a good output voltage. In addition, the node connected to the inductor may experience a large voltage swing due to the alternating application of positive input voltage and negative output voltage, and thus, the components connected to the corresponding node may have a large breakdown voltage, low efficiency, and large area. On the other hand, as described above with reference to FIGS. 3A, 3B and 4, by generating a negative voltage at the second terminal (T2) of the inductor (L) during the second phase (P2) in the inverting switching regulator (20) of FIG. 2, the inductor current (I _L ) can continuously drive the output transfer current (I _D ), and accordingly, as shown in FIG. 4, the output transfer current (I _D ) matching the inductor current (I _L ) can be continuous during the first phase (P1) and the second phase (P2), and as a result, the output voltage (V _OUT ) can have reduced ripple. The reduced ripple can enable the use of a small inductor (L) and a small output capacitor (C _O ). In addition, the voltage applied to the components included in the inverting switching regulator (20) can be limited. For example, no voltage exceeding |V _IN | or |V _OUT | may be applied to any element included in the inverting switching regulator (20) during the first phase (P1) and the second phase (P2).

FIG. 5 illustrates a circuit diagram of an inverting switching regulator (50) according to an exemplary embodiment of the present disclosure. Specifically, the circuit diagram of FIG. 5 illustrates an inverting switching regulator (50) that functions as an inverting buck-boost converter. The inverting switching regulator (50) may be set to a buck mode, as described below with reference to FIG. 6 , or may be set to a boost mode, as described below with reference to FIG. 8 . As described above with reference to FIG. 1 , the inverting switching regulator (50) may include a switch circuit (52), a flying capacitor (C _F ), an inductor (L), and an output capacitor (C _O ).

The switch circuit (52) may include first, second, third, fourth, and fifth switches (SW1, SW2, SW3, SW4, SW5). Similar to the inverting switching regulator (20) of FIG. 2, the first switch (SW1) may be connected to the input node (IN) and the second node (N2), the second switch (SW2) may be connected to the ground node (GND) and the first node (N1), and the third switch (SW3) may be connected to the second node (N2) and the ground node (GND). As illustrated in FIG. 5, the fourth switch (SW4) may be connected to the ground node (GND) and the third node (N3), and the fifth switch (SW5) may be connected to the third node (N3) and the output node (OUT). As described above with reference to FIG. 1, the first, second, third, fourth and fifth switches (SW1, SW2, SW3, SW4, SW5) can be turned on or off by a switch control signal (C_SW) provided by the switch controller (14).

The flying capacitor (C _F ) can be connected to the second switch (SW2) and the inductor (L) at the first node (N1), and can be connected to the first and third switches (SW1, SW3) at the second node (N2). Similar to what was described above with reference to FIGS. 3A and 4 , when the first and second switches (SW1, SW2) are turned on and the third switch (SW3) is turned off, the flying capacitor (C _F ) can be charged with the input voltage (V _IN ), while similar to what was described above with reference to FIGS. 3B and 4 , when the first and second switches (SW1, SW2) are turned off and the third switch (SW3) is turned on, the flying capacitor (C _F ) can induce a negative voltage at the first node (N1).

The inductor (L) may have a first terminal (T1) connected to a third node (N3) and a second terminal (T2) connected to the first node (N1), and the inductor current (I _L ) may flow from the first terminal (T1) to the second terminal (T2). Due to the fifth switch (SW5), the inductor current (I _L ) may be equal to or different from the output transfer current (I _D ). For example, as described below with reference to FIG. 7a, when the third switch (SW3) is turned off and the fifth switch (SW5) is turned on, the inductor current (I _L ) may match the output transfer current (I _D ) and flow to the ground node (GND), while as described below with reference to FIG. 7b, when the third switch (SW3) is turned on and the fifth switch (SW5) is turned off, the inductor current (I _L ) may differ from the output transfer current (I _D ) and flow to the flying capacitor (C _F ).

The output capacitor (C _O ) can be connected to the fifth switch (SW5) at the output node (OUT) and can be connected to the ground node (GND). Accordingly, the output capacitor (C _O ) can receive a portion of the load current (I _O ) or provide a portion of the output transfer current (I _D ) when the fifth switch (SW5) is turned on, while receiving the output transfer current (I _D ) when the fifth switch (SW5) is off. As described below with reference to FIGS. 6, 7a, 7b, and 8, no voltage exceeding |V _IN | or |V _OUT | may be applied to any element included in the inverting switching regulator (50) during the first phase (P1) and the second phase (P2).

FIG. 6 is a timing diagram showing an example of the operation of the inverting switching regulator (50) of FIG. 5 according to an exemplary embodiment of the present disclosure. Specifically, the timing diagram of FIG. 6 shows the operation of the inverting switching regulator (50) set to a buck mode. Hereinafter, FIG. 6 will be described with reference to FIG. 5.

In some embodiments, the inverting switching regulator (50) of FIG. 5 may be set to a buck mode. For example, as illustrated in FIG. 6, during the first phase (P1) and the second phase (P2), the fourth switch (SW4) may be turned off and the fifth switch (SW5) may be turned on. Accordingly, the inverting switching regulator (50) may have the same structure as the inverting switching regulator (20) of FIG. 2, which functions as a buck converter. That is, the inverting switching regulator (50) may correspond to the equivalent circuit (30a) of FIG. 3a in the first phase (P1), and may correspond to the equivalent circuit (30b) of FIG. 3b in the second phase.

Referring to FIGS. 5 and 6, during the first phase (P1), the first and second switches (SW1, SW2) may be turned on, and the third switch (SW3) may be turned off. As illustrated in FIG. 6, during the first phase (P1), the voltage (V _N2 ) of the second node (N2) may coincide with the input voltage (V _IN ), and the voltage (V _N1 ) of the first node (N1) may coincide with the ground potential. Accordingly, the input voltage (V _IN ) may be applied to the flying capacitor (C _F ), and the flying capacitor (C _F ) may be charged with the input voltage (V _IN ). In addition, the inductor current (I _L ) may flow from the output node (OUT) through the inductor (L) to the ground node (GND), and may gradually decrease due to the ground potential, as illustrated in FIG. 6.

Referring to FIGS. 5 and 6, during the second phase (P2), the first and second switches (SW1, SW2) may be turned off, and the third switch (SW3) may be turned on. As illustrated in FIG. 6, during the second phase (P2), the voltage (V _N2 ) of the second node (N2) may coincide with the ground potential, and at the start of the second phase (P2), the voltage (V _N1 ) of the first node (N1) may coincide with the inverted voltage (-V _IN ) of the input voltage (V _IN ). Accordingly, a negative voltage (-V _IN ) may be applied to the second terminal (T2) of the inductor (L) at the start of the second phase (P2). Additionally, the inductor current (I _L ) may flow from the output node (OUT) through the inductor (L) to the flying capacitor (C _F ) and may gradually increase due to the negative voltage (-V _IN ), as illustrated in FIG. 6 . Although not illustrated in FIG. 6 , in some embodiments, the voltage (V _N1 ) of the first node (N1) during the second phase (P2) may gradually increase due to the inductor current (I _L ).

FIGS. 7A and 7B are circuit diagrams showing equivalent circuits of the inverting switching regulator (50) of FIG. 5 according to exemplary embodiments of the present disclosure, and FIG. 8 is a timing diagram showing an example of the operation of the inverting switching regulator (50) of FIG. 5 according to exemplary embodiments of the present disclosure. Specifically, the circuit diagram of FIG. 7A shows an equivalent circuit (70a) of the inverting switching regulator (50) and a path of an inductor current (I L ) during a first phase (P1) in boost mode, the circuit diagram of FIG. 7B shows an equivalent circuit (70b) of the inverting switching regulator (50) and a path of an inductor current (I _L ) during a second phase ( _P2 ) in boost mode, and the timing diagram of FIG. 8 shows an example of the operation of the inverting switching regulator (50) in boost mode. In some embodiments, the inverting switching regulator (50) of FIG. 5 may be set to a boost mode, and as illustrated in FIG. 8, during the first phase (P1) and the second phase (P2), not only the first, second and third switches (SW1, SW2, SW3) but also the fourth and fifth switches (SW4, SW5) may be switched on and off. Hereinafter, FIGS. 7A, 7B and 8 will be described with reference to FIG. 5.

Referring to FIGS. 7a and 8, during the first phase (P1), the first, second, and fifth switches (SW1, SW2, SW5) may be turned on, and the third and fourth switches (SW3, SW4) may be turned off, whereby an equivalent circuit (70a) of FIG. 7a may be formed. As illustrated in FIG. 8, during the first phase (P1), the voltage (V _N2 ) of the second node (N2) may match the input voltage (V _IN ), and the voltage (V _N1 ) of the first node (N1) may match the ground potential. Accordingly, the input voltage (V _IN ) may be applied to the flying capacitor (C _F ), and the flying capacitor (C _F ) may be charged with the input voltage (V _IN ). Additionally, the voltage (V _N3 ) of the third node (N3) can match the output voltage (V _OUT ), and as shown in FIG. 7a, the inductor current (I _L ) can flow from the output node (OUT) through the inductor (L) to the ground node (GND), and thus, as shown in FIG. 8, can gradually decrease due to the ground potential.

Referring to FIGS. 7b and 8, during the second phase (P2), the first, second and fifth switches (SW1, SW2, SW5) may be turned off, and the third and fourth switches (SW3, SW4) may be turned on, whereby the equivalent circuit (70b) of FIG. 7b may be formed. As illustrated in FIG. 8, during the second phase (P2), the voltage (V _N2 ) of the second node (N2) may be equal to the ground potential, and at the start of the second phase, the voltage (V _N1 ) of the first node (N1) may be equal to the inverted voltage (-V _IN ) of the input voltage (V _IN ). Accordingly, a negative voltage (-V _IN ) may be applied to the second terminal (T2) of the inductor (L) at the start of the second phase (P2). Additionally, the voltage (V _N3 ) of the third node (N3) may coincide with the ground potential, and as illustrated in FIG. 7b, the inductor current (I _L ) may flow from the ground node (GND) through the inductor (L) to the flying capacitor (C _F ), thereby gradually increasing due to the negative voltage (-V _IN ), as illustrated in FIG. 8 . Although not illustrated in FIG. 8 , in some embodiments, the voltage (V _N1 ) of the first node (N1) may gradually increase due to the inductor current (I _L ) during the second phase (P2).

FIG. 9 illustrates a circuit diagram of an inverting switching regulator (90) according to an exemplary embodiment of the present disclosure. Specifically, the circuit diagram of FIG. 9 illustrates an inverting switching regulator (90) functioning as an inverting buck-boost converter. The inverting switching regulator (90) may be set to a buck mode, as described above with reference to FIG. 6, or may be set to a boost mode, as described below with reference to FIG. 10. In some embodiments, the inverting switching regulator (90) of FIG. 9 may generate an output voltage (V _OUT ) in the boost mode that is lower than the output voltage (V _OUT ) that the inverting switching regulator (50) of FIG. 5 generates in the boost mode, and thus, the boost mode of the inverting switching regulator (90) of FIG. 9 may also be referred to as a wide inverting boost mode or a wide boost mode. As described above with reference to FIG. 1, the inverting switching regulator (90) may include a switch circuit (92), a flying capacitor (C _F ), an inductor (L), and an output capacitor (CO).

The switch circuit (92) may include first, second, third, fourth, and fifth switches (SW1, SW2, SW3, SW4, SW5). Similar to the inverting switching regulator (50) of FIG. 5, the first switch (SW1) may be connected to the input node (IN) and the second node (N2), the second switch (SW2) may be connected to the ground node (GND) and the first node (N1), the third switch (SW3) may be connected to the second node (N2) and the ground node (GND), and the fifth switch (SW5) may be connected to the third node (N3) and the output node (OUT). As illustrated in FIG. 9, the fourth switch (SW4) may be connected to the input node (IN) and the third node (N3). As described above with reference to FIG. 1, the first, second, third, fourth and fifth switches (SW1, SW2, SW3, SW4, SW5) can be turned on or off by a switch control signal (C_SW) provided by the switch controller (14).

The flying capacitor (C _F ) can be connected to the second switch (SW2) and the inductor (L) at the first node (N1), and can be connected to the first and third switches (SW1, SW3) at the second node (N2). Similar to what was described above with reference to FIGS. 7a and 8 , when the first and second switches (SW1, SW2) are turned on and the third switch (SW3) is turned off, the flying capacitor (C _F ) can be charged with the input voltage (V _IN ), while similar to what was described above with reference to FIGS. 7b and 8 , when the first and second switches (SW1, SW2) are turned off and the third switch (SW3) is turned on, the flying capacitor (C _F ) can induce a negative voltage at the first node (N1).

The inductor (L) may have a first terminal (T1) connected to a third node (N3) and a second terminal (T2) connected to the first node (N1), and the inductor current (I _L ) may flow from the first terminal (T1) to the second terminal (T2). Due to the fifth switch (SW5), the inductor current (I _L ) may be equal to or different from the output transfer current (I _D ). The output capacitor (C _O ) may be connected to the fifth switch (SW5) at the output node (OUT) and to a ground node (GND). Accordingly, the output capacitor (C _O ) can accommodate a portion of the load current (I _O ) or provide a portion of the output transfer current (I _D ) when the fifth switch (SW5) is turned on, while it can accommodate the output transfer current (I _D ) when the fifth switch (SW5) is turned off.

In some embodiments, the inverting switching regulator (90) may be set to the buck mode. For example, in the buck mode, the fourth switch (SW4) may always be off, and the fifth switch (SW5) may always be on. Accordingly, the inverting switching regulator (90) may correspond to the equivalent circuit (30a) of FIG. 3A during the first phase (P1), and may correspond to the equivalent circuit (30b) of FIG. 3B during the second phase (P2). Accordingly, similar to how the inverting switching regulator (50) of FIG. 5 operates in the buck mode, the inverting switching regulator (90) of FIG. 9 may operate in the buck mode as described above with reference to FIG. 6.

FIG. 10 is a circuit diagram showing an equivalent circuit of the inverting switching regulator (90) of FIG. 9 according to an exemplary embodiment of the present disclosure, and FIG. 11 is a timing diagram showing an example of the operation of the inverting switching regulator (90) of FIG. 9 according to an exemplary embodiment of the present disclosure. Specifically, the circuit diagram of FIG. 10 shows an equivalent circuit (100) of the inverting switching regulator (90) and a path of an inductor current (I _L ) during a second phase (P2) in the boost mode (or wide boost mode), and the timing diagram of FIG. 11 shows an example of the operation of the inverting switching regulator (90) in the boost mode. Hereinafter, FIGS. 10 and 11 will be described with reference to FIG. 9.

The inverting switching regulator (90) of FIG. 9 may correspond to an equivalent circuit identical to the equivalent circuit (70a) of FIG. 7a during the first phase (P1) in the boost mode. Referring to FIG. 10, during the first phase (P1) in the boost mode, the first, second, and fifth switches (SW1, SW2, SW5) may be turned on, and the third and fourth switches (SW3, SW4) may be turned off. As illustrated in FIG. 10, during the first phase (P1), the voltage (V _N2 ) of the second node (N2) may match the input voltage (V _IN ), and the voltage (V _N1 ) of the first node (N1) may match the ground potential. Accordingly, the input voltage (V _IN ) may be applied to the flying capacitor (C _F ), and the flying capacitor (C _F ) may be charged with the input voltage (V _IN ). Additionally, the voltage (V _N3 ) of the third node (N3) can match the output voltage (V _OUT ), and as shown in FIG. 7a, the inductor current (I _L ) can flow from the output node (OUT) through the inductor (L) to the ground node (GND), and thus, can gradually decrease due to the ground potential, as shown in FIG. 10.

Referring to FIGS. 10 and 11, during the second phase (P2), the first, second, and fifth switches (SW1, SW2, SW5) may be turned off, and the third and fourth switches (SW3, SW4) may be turned on, whereby the equivalent circuit (100) of FIG. 10 may be formed. Compared to the equivalent circuit (70b) of FIG. 7b, in the equivalent circuit (100) of FIG. 10, the third node (N3) may be connected to the input node (IN) instead of the ground node (GND), whereby a higher voltage than the voltage applied to both terminals of the inductor (L) of the equivalent circuit (70b) of FIG. 7b may be applied to both terminals of the inductor (L) of FIG. 10. Accordingly, a high inductor current (I _L ) may occur in the second phase (P2), resulting in a lower output voltage (V _OUT ).

Referring to FIG. 11, during the second phase (P2), the voltage (V _N2 ) of the second node (N2) may coincide with the ground potential, and at the start of the second phase, the voltage (V _N1 ) of the first node (N1) may coincide with the voltage (-V _IN ) that is an inverted input voltage (V _IN ). Accordingly, a negative voltage (-V _IN ) may be applied to the second terminal (T2) of the inductor (L) at the start of the second phase (P2). In addition, the voltage (V _N3 ) of the third node (N3) may coincide with the ground potential, and as illustrated in FIG. 7b, the inductor current (I _L ) may flow from the ground node (GND) through the inductor (L) to the flying capacitor (C _F ), and thus may gradually increase due to the negative voltage (-V _IN ), as illustrated in FIG. 10. Although not shown in FIG. 8, in some embodiments, the voltage (V _N1 ) of the first node (N1) may gradually increase due to the inductor current (I _L ) during the second phase (P2).

FIG. 12 is a flowchart illustrating a method of converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure. As illustrated in FIG. 12, the method of converting a positive input voltage into a negative output voltage may include steps S100 and S200, and step S100 may be performed in a first phase (P1), while step S200 may be performed in a second phase (P2). In some embodiments, the method of FIG. 12 may be performed by the inverting switching regulator (10) of FIG. 1, and the method of FIG. 12 may be referred to as an operating method of the inverting switching regulator (10). Hereinafter, FIG. 12 will be described with reference to FIG. 1.

Referring to FIG. 12, step S100 may include steps S120 and S140, and steps S120 and S140 may be performed in parallel. In step S120, an operation of charging a flying capacitor (C _F ) with an input voltage (V _IN ) may be performed. For example, as described above with reference to the drawings, the flying capacitor (C _F ) may be connected to the input node (IN) during the first phase (P1) and may be charged with a charge proportional to the input voltage (V _IN ) and the capacitance of the flying capacitor (C _F ). An example of step S120 will be described below with reference to FIG. 13. In addition, in step S140, an operation of adjusting the inductor current (I _L ) to flow to the ground node (GND) may be performed. For example, as described above with reference to the drawings, the inductor (L) can be connected to the ground node (GND) during the first phase (P1), and the inductor current (I _L ) can flow to the ground node (GND). Examples of step S140 will be described below with reference to FIGS. 14a and 14b.

Step S200 may include steps S220 and S240, and steps S220 and S240 may be performed in parallel. In step S220, an operation of applying a negative voltage to the inductor (L) may be performed. For example, as described above with reference to the drawings, a negative voltage may be applied to the inductor (L) during the second phase (P2) due to the charge charged in the flying capacitor (C _F ) in step S120. An example of step S220 will be described below with reference to FIG. 15. In addition, in step S240, an operation of adjusting the inductor current (I _L ) to flow to the flying capacitor (C _F ) may be performed. For example, as described above with reference to the drawings, the inductor (L) can be connected to the flying capacitor (C _F ) during the second phase (P2), and the inductor current (I _L ) can flow to the flying capacitor (C _F ). Examples of step S240 will be described below with reference to FIGS. 16a, 16b, and 16c.

FIG. 13 is a flowchart illustrating a method of converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 13 illustrates an example of step S120 of FIG. 12. As described above with reference to FIG. 12, step S120' of FIG. 13 may be performed during the first phase (P1), and an operation of charging the flying capacitor (C _F ) with the input voltage (V _IN ) may be performed in step S120'. In some embodiments, step S120' may be performed by the inverting switching regulator (20) of FIG. 2, and hereinafter, FIG. 13 will be described with reference to FIGS. 2 and 12.

Referring to FIG. 13, step S120' may include steps S122 and S124, and in some embodiments, steps S122 and S124 may be performed in a different order from that illustrated in FIG. 13. In step S122, an operation of connecting a first terminal of the flying capacitor (C _F ) to a ground node (GND) may be performed. For example, the first terminal of the flying capacitor (C _F ) may refer to a terminal connected to the first node (N1), and by turning on the second switch (SW2), the first node (N1) may be connected to the ground node (GND). Additionally, in step S124, an operation of connecting a second terminal of the flying capacitor (C _F ) to an input node (IN) may be performed. For example, the second terminal of the flying capacitor (C _F ) may refer to a terminal connected to the second node (N2), and the second node (N2) may be connected to the input node (IN) by turning on the first switch (SW1) and turning off the third switch (SW3).

FIGS. 14A and 14B are flowcharts illustrating examples of methods for converting a positive input voltage into a negative output voltage according to exemplary embodiments of the present disclosure. Specifically, the flowchart of FIG. 14A illustrates an example of step S140 of FIG. 12 performed by the inverting switching regulator (20) of FIG. 2, and the flowchart of FIG. 14B illustrates an example of step S140 of FIG. 12 performed by the inverting switching regulator (50) of FIG. 5 or the inverting switching regulator (90) of FIG. 9. As described above with reference to FIG. 12, steps S140a and S140b of FIGS. 14A and 14B may be performed during the first phase (P1), and an operation of adjusting the inductor current (I _L ) to flow to the ground node (GND) may be performed in steps S140a and S140b. Hereinafter, FIGS. 14a and 14b will be described with reference to FIGS. 2, 5, and 9.

Referring to FIG. 14a, step S140a may include step S142a and step S144a, and in some embodiments, step S142a and step S144a may be performed in a different order from that illustrated in FIG. 14a. In step S142a, an operation of connecting a first terminal (T1) of the inductor (L) to the output node (OUT) may be performed. In some embodiments, differently from that illustrated in FIG. 2, when the inductor (L) is not connected to the output node (OUT) but is connected to the output node (OUT) through at least one switch, the first terminal (T1) of the inductor (L) may be connected to the output node (OUT) by turning on at least one switch between the inductor (L) and the output node (OUT). In some embodiments, when the inductor (L) is connected to the output node (OUT) as illustrated in FIG. 2, step S142a may be omitted. In addition, in step S144a, an operation of connecting the second terminal (T2) of the inductor (L) to the ground node (GND) may be performed. For example, the second terminal (T2) of the inductor (L) may be connected to the first node (N1), and the first node (N1) may be connected to the ground node (GND) by turning on the second switch (SW2). Accordingly, the inductor current (I _L ) may flow from the output node (OUT) through the inductor (L) to the ground node (GND).

Referring to FIG. 14b, step S140b may include steps S142b, S144b, and S146b, and in some embodiments, step S146b may be performed before step S142b or in parallel with steps S142b and S146b, differently from what is illustrated in FIG. 14b. In step S142b, an operation of disconnecting the first terminal (T1) of the inductor (L) from the ground node (GND) or the input node (IN) may be performed. In some embodiments, the first terminal (T1) of the inductor (L) may be disconnected from the ground node (GND) by turning off the fourth switch (SW4) in the inverting switching regulator (50) of FIG. 5. In some embodiments, the first terminal (T1) of the inductor (L) may be disconnected from the input node (IN) by turning off the fourth switch (SW4) in the inverting switching regulator (90) of FIG. 9. In addition, in step S144b, an operation of connecting the first terminal (T1) of the inductor (L) to the output node (OUT) may be performed. For example, the inductor (L) may be connected to the third node (N3), and the third node (N3) may be connected to the output node (OUT) by turning on the fifth switch (SW5) of FIG. 5 or FIG. 9. In addition, in step S146b, an operation of connecting the second terminal (T2) of the inductor (L) to the ground node (GND) may be performed. For example, the second terminal (T2) of the inductor (L) can be connected to the first node (N1), and the first node (N1) can be connected to the ground node (GND) by turning on the second switch (SW2) of FIG. 5 or FIG. 9. Accordingly, the inductor current (I _L ) can flow from the output node (OUT) through the inductor (L) to the ground node (GND).

FIG. 15 is a flowchart illustrating a method of converting a positive input voltage into a negative output voltage according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 15 illustrates an example of step S220 of FIG. 12. As described above with reference to FIG. 12, step S220' may be performed during the second phase (P2), and an operation of applying a negative voltage to the inductor (L) may be performed in step S220'. In some embodiments, step S220' may be performed by the inverting switching regulator (20) of FIG. 2, and hereinafter, FIG. 15 will be described with reference to FIG. 2 and FIG. 12.

Referring to FIG. 15, step S220' may include steps S222, S224, and S226, and in some embodiments, steps S222, S224, and S226 may be performed in a different order from that illustrated in FIG. 15. In step S222, an operation of disconnecting a first terminal of the flying capacitor (C _F ) from the ground node (GND) may be performed. For example, the first terminal of the flying capacitor (C _F ) may refer to a terminal connected to the first node (N1), and the first node (N1) may be disconnected from the ground node (GND) by turning off the second switch (SW2). Additionally, in step S224, an operation of connecting the first terminal of the flying capacitor (C _F ) to an inductor may be performed. In some embodiments, unlike as illustrated in FIG. 2, when the flying capacitor (C _F ) is not connected to the inductor (L) but is connected to the inductor (L) through at least one switch, the first terminal of the flying capacitor (C _F ), which is disconnected from the ground node (GND), can be connected to the inductor (L) in step S222 by turning on at least one switch between the flying capacitor (C _F ) and the inductor (L). In some embodiments, when the flying capacitor (C _F ) and the inductor (L) are connected as illustrated in FIG. 2 , step S224 may be omitted. In addition, in step S226, an operation of connecting the second terminal of the flying capacitor (C _F ) to the ground node can be performed. For example, the second terminal of the flying capacitor (C _F ) may refer to a terminal connected to the second node (N2), and the second node (N2) may be connected to the ground node (GND) by turning off the second switch (SW2) and turning on the third switch (SW3). Accordingly, a voltage drop corresponding to a voltage drop occurring at the second node (N2) may occur at the first node (N1) due to the charge charged in the flying capacitor (C _F ), and as a result, a negative voltage, for example, an inverted voltage (-V _IN ) of the input voltage (V _IN ), may be induced at the first node (N1).

FIGS. 16A, 16B, and 16C are flowcharts illustrating examples of a method of converting a positive input voltage into a negative output voltage according to exemplary embodiments of the present disclosure. Specifically, the flowchart of FIG. 16A illustrates an example of step S240 of FIG. 12 performed in a buck converter or a buck-boost converter in buck mode, and the flowcharts of FIGS. 16B and 16C illustrate examples of step S240 of FIG. 12 performed in a boost converter or a buck-boost converter in boost mode. As described above with reference to FIG. 12, steps S240a, S240b and S240c of FIGS. 16a, 16b and 16c can be performed during the second phase (P2), and an operation of adjusting the inductor current (I _L ) to flow to the flying capacitor (C _F ) in steps S240a, S240b and S240c can be performed. In some embodiments, step S240a of FIG. 16a can be performed by the inverting switching regulator (20) of FIG. 2, step S240b of FIG. 16b can be performed by the inverting switching regulator (50) of FIG. 5, and step S240c of FIG. 16c can be performed by the inverting switching regulator (90) of FIG. 9. Hereinafter, FIGS. 16a, 16b and 16c will be described with reference to FIGS. 2, 5 and 9, and any overlapping content in the descriptions of FIGS. 16a, 16b and 16c will be omitted.

Referring to FIG. 16a, step S240a may include steps S242a and S244a, and in some embodiments, steps S242a and S244a may be performed in a different order than illustrated in FIG. 16a. In step S242a, an operation of disconnecting a second terminal (T2) of an inductor (L) from a ground node (GND) may be performed. For example, as illustrated in FIG. 2, the second terminal (T2) of the inductor (L) may be connected to a first node (N1), and by turning off the second switch (SW2), the first node (N1) may be disconnected from the ground node (GND). Additionally, in step S244a, an operation of connecting the second terminal (T2) of the inductor (L) to a flying capacitor (C _F ) may be performed. In some embodiments, unlike as illustrated in FIG. 2, when the inductor (L) is not connected to the flying capacitor (C _F ) but is connected to the flying capacitor (C _F ) through at least one switch, the second terminal (T2) of the inductor (L), which is disconnected from the ground node (GND) in step S242a, can be connected to the flying capacitor (C _F ) by turning on at least one switch between the inductor ( _L ) and the flying capacitor (C F ). In some embodiments, when the inductor (L) and the flying capacitor (C _F ) are connected as illustrated in FIG. 2 , step S242a may be omitted.

Referring to FIG. 16b, step S240b may include steps S242b, S244b, S246b, and S248b, and in some embodiments, steps S242b, S244b, S246b, and S248b may be performed in a different order than that illustrated in FIG. 16b. Similar to steps S242a and S244a of FIG. 16a, in step S242b, an operation of disconnecting the second terminal (T2) of the inductor (L) from the ground node (GND) may be performed, and in step S244b, an operation of connecting the second terminal (T2) of the inductor (L) to the flying capacitor (C _F ) may be performed.

In step S246b, an operation of disconnecting the first terminal (T1) of the inductor (L) from the output node (OUT) can be performed. For example, as illustrated in FIG. 5, the first terminal (T1) of the inductor (L) can be connected to the third node (N3), and by turning off the fifth switch (SW5), the third node (N3) can be disconnected from the output node (OUT). In addition, in step S248b, an operation of connecting the first terminal (T1) of the inductor (L) to the ground node (GND) can be performed. For example, as illustrated in FIG. 5, the fourth switch (SW4) can be connected to the ground node (GND) and the third node (N3), and by turning on the fourth switch (SW4), the third node (N3) can be connected to the ground node (GND). Accordingly, the inductor current (I _L ) can flow from the ground node (GND) through the inductor (L) to the flying capacitor (C _F ).

Referring to FIG. 16c, step S240c may include steps S242c, S244c, S246c, and S248c, and in some embodiments, steps S242c, S244c, S246c, and S248c may be performed in a different order than shown in FIG. 16c. Similar to steps S242a and S244a of FIG. 16a, in step S242c, an operation of disconnecting the second terminal (T2) of the inductor (L) from the ground node (GND) may be performed, and in step S244c, an operation of connecting the second terminal (T2) of the inductor (L) to the flying capacitor (C _F ) may be performed.

In step S246c, an operation of disconnecting the first terminal (T1) of the inductor (L) from the output node (OUT) can be performed. For example, as illustrated in FIG. 9, the first terminal (T1) of the inductor (L) can be connected to the third node (N3), and by turning off the fifth switch (SW5), the third node (N3) can be disconnected from the output node (OUT). In addition, in step S248c, an operation of connecting the first terminal (T1) of the inductor (L) to the input node (IN) can be performed. For example, as illustrated in FIG. 9, the fourth switch (SW4) can be connected to the input node (IN) and the third node (N3), and by turning on the fourth switch (SW4), the third node (N3) can be connected to the input node (IN). Accordingly, the inductor current (I _L ) can flow from the ground node (GND) through the inductor (L) to the flying capacitor (C _F ). Accordingly, the inductor current (I _L ) can be greater than the inductor current (I _L ) by step S240b of Fig. 16b, and the output voltage (V _OUT ) can be lower than the output voltage (V _OUT ) by step S240b of Fig. 16b.

FIG. 17 is a block diagram illustrating a wireless communication device (100) according to an exemplary embodiment of the present disclosure. Specifically, FIG. 17 illustrates a user equipment (UE) (or terminal) that is powered by a battery (150). The wireless communication device (100), in some embodiments, may be included in a wireless communication system using a cellular network such as 5G (5th Generation), LTE (Long-Term Evolution), or the like, or may be included in a WPAN (Wireless Personal Area Network) system or any other wireless communication system. In the wireless communication device (100), an inverting switching regulator according to an exemplary embodiment of the present disclosure may be used to provide a second output voltage (V _OUT2 ) as a negative voltage to a transceiver (110). As illustrated in FIG. 17, the wireless communication device (100) may include a transceiver (110), a baseband processor (120), an antenna (130), a power circuit (140), and a battery (150).

The transceiver (110) may include an antenna interface circuit (111), a receiver including an input circuit (112), a low-noise amplifier (113), and a receive circuit (114), and a transmitter including a transmit circuit (115), a power amplifier (116), and an output circuit (117). The antenna interface circuit (111) may connect the transmitter or the receiver to the antenna (130) depending on a transmit mode or a receive mode. In some embodiments, the input circuit (112) may include a matching circuit or a filter, the low-noise amplifier (113) may amplify an output signal of the input circuit (112), and the receive circuit (114) may include a mixer for down-conversion. In some embodiments, the transmitter circuit (115) may include a mixer for up-conversion, the power amplifier (116) may amplify the output signal of the transmitter circuit (115), and the output circuit (117) may include a matching circuit or filter.

The baseband processor (120) can transmit and receive baseband signals with the transceiver (110), and perform modulation/demodulation, encoding/decoding, channel estimation, etc. In some embodiments, the baseband processor (120) may be referred to as a communication processor, a modem, etc.

The power circuit (140) can receive an input voltage (V _IN ) from the battery (150) and generate first and second output voltages (V _OUT1 , V _OUT2 ) that are provided to the transceiver (110). For example, the power circuit (140) can include a DC-DC converter to generate a first output voltage (V _OUT1 ) that is a positive voltage from the positive input voltage (V _IN ). In addition, the power circuit (140) can include an inverting switching regulator as described above with reference to the drawings to generate a first output voltage (V _OUT2 ) that is a negative voltage from the positive input voltage (V IN ). Accordingly, the power circuit (140) can have high efficiency, a small area, and can be integrated on the same die together with other components of the wireless communication device (100), such as the transceiver (110).

As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms have been used in the specification to describe the embodiments, these have been used only for the purpose of explaining the technical idea of the present disclosure and have not been used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be determined by the technical idea of the appended claims.

Claims (20)

An inverting switching regulator that generates a negative output voltage from a positive input voltage,
An inductor configured to allow inductor current to pass from a first terminal to a second terminal;
A flying capacitor connected to the second terminal of the above inductor;
A plurality of switches configured to charge the flying capacitor with the input voltage during a first phase and to apply a negative voltage to the second terminal of the inductor by connecting the flying capacitor in series with the ground node and the inductor during a second phase; and
Includes an output capacitor connected to an output node from which the above output voltage is output,
An inverting switching regulator, characterized in that the plurality of switches comprises at least one switch configured to, in an inverting boost mode, connect the first terminal of the inductor to the output node during the first phase and to connect the first terminal of the inductor to the ground node during the second phase. In claim 1,
An inverting switching regulator, characterized in that the inductor current flows to the ground node during the first phase and to the flying capacitor during the second phase. In claim 1,
An inverting switching regulator, wherein said plurality of switches comprises at least one switch configured to provide said input voltage to said flying capacitor during said first phase and to connect said flying capacitor to said ground node during said second phase. In claim 1,
An inverting switching regulator, characterized in that the plurality of switches include a switch configured to connect the second terminal of the inductor to the ground node during the first phase and to disconnect the second terminal of the inductor from the ground node during the second phase. delete delete In claim 1,
An inverting switching regulator, characterized in that the inductor current, in the inverting boost mode, flows from the output node through the inductor to the ground node during the first phase, and from the ground node through the inductor to the flying capacitor during the second phase. An inverting switching regulator that generates a negative output voltage from a positive input voltage,
An inductor configured to allow inductor current to pass from a first terminal to a second terminal;
a flying capacitor connected to the second terminal of the inductor; and
A plurality of switches configured to charge the flying capacitor with the input voltage during a first phase and to apply a negative voltage to the second terminal of the inductor by connecting the flying capacitor in series with a ground node and the inductor during a second phase,
Further comprising an output capacitor connected to an output node from which the above output voltage is output,
An inverting switching regulator, wherein said plurality of switches comprises at least one switch configured to connect said first terminal of said inductor to said output node during said first phase and to apply said input voltage to said first terminal of said inductor during said second phase, in an inverting boost mode. In claim 8,
An inverting switching regulator, characterized in that the inductor current, in the inverting boost mode, flows from the output node through the inductor to the ground node during the first phase, and from the input node to which the input voltage is applied through the inductor to the flying capacitor during the second phase. An inverting switching regulator that generates a negative output voltage from a positive input voltage,
An inductor configured to allow inductor current to pass from a first terminal to a second terminal;
A flying capacitor, which is charged with the input voltage during the first phase and configured to induce a negative voltage at the second terminal of the inductor according to the charged charge during the second phase; and
Includes an output capacitor connected to an output node from which the above output voltage is output,
The above inductor current flows to the ground node during the first phase and to the flying capacitor during the second phase,
An inverting switching regulator, characterized in that the inductor current flows from the output node to the first terminal of the inductor during the first phase, and from the ground node to the first terminal of the inductor during the second phase. In claim 10,
The above flying capacitor,
A first terminal configured to be connected to an input node to which the input voltage is applied during the first phase and to be connected to the ground node during the second phase; and
An inverting switching regulator characterized by comprising a second terminal connected to the ground node during the first phase, disconnected from the ground node during the second phase, and connected to the second terminal of the inductor. In claim 10,
An inverting switching regulator, characterized in that the second terminal of the inductor has a ground potential during the first phase and is configured such that the input voltage has an inverted negative voltage when the second phase starts. delete delete An inverting switching regulator that generates a negative output voltage from a positive input voltage,
An inductor configured to allow inductor current to pass from a first terminal to a second terminal;
A flying capacitor, which is charged with the input voltage during the first phase and configured to induce a negative voltage at the second terminal of the inductor according to the charged charge during the second phase; and
Includes an output capacitor connected to an output node from which the above output voltage is output,
The above inductor current flows to the ground node during the first phase and to the flying capacitor during the second phase,
An inverting switching regulator, characterized in that the inductor current flows from the output node to the first terminal of the inductor during the first phase, and from the input node to which the input voltage is applied to the first terminal of the inductor during the second phase. A method of converting a positive input voltage into a negative output voltage and outputting it to an output node,
During the first phase, a step of charging the flying capacitor with the input voltage;
During the first phase, a step of regulating the inductor current to flow from the output node to the ground node sequentially through the first terminal and the second terminal of the inductor by connecting the first terminal of the inductor to the output node;
During the second phase, a step of applying a negative voltage to the second terminal of the inductor according to the charged charge of the flying capacitor; and
A method comprising the step of: during the second phase, connecting the first terminal of the inductor to the ground node so that the inductor current flows sequentially from the ground node through the first terminal and the second terminal of the inductor to the flying capacitor. In claim 16,
The step of charging the above flying capacitor is:
A step of connecting the first terminal of the above flying capacitor to the ground node; and
A method characterized by comprising the step of connecting the second terminal of the flying capacitor to an input node to which the input voltage is applied. In claim 17,
The step of applying a negative voltage to the second terminal of the above inductor is:
A step of disconnecting the first terminal of the flying capacitor from the ground node;
A step of connecting the first terminal of the flying capacitor to the second terminal of the inductor; and
A method characterized by comprising a step of connecting the second terminal of the flying capacitor to the ground node. In claim 16,
The step of adjusting the above inductor current to flow to the ground node is,
A method characterized by comprising the step of connecting the second terminal of the inductor to the ground node. delete

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