KR102743456B1 - Ate for performing linear test for high-speed memory and method for operation thereof - Google Patents

Abstract

According to various embodiments, an automated test equipment (ATE) for performing a linear test on a high-speed memory includes a processor, wherein the processor is configured to obtain a test pattern program, and in response to a save pattern (SVP) command code, store a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in a pattern queue register, and convert a value of the data field from first data to second data based on a specific table corresponding to a characteristic of a device under test among pre-stored data conversion tables, and allocate the second data according to a preset data allocation order. Various other embodiments may also be possible.

Description

{ATE FOR PERFORMING LINEAR TEST FOR HIGH-SPEED MEMORY AND METHOD FOR OPERATION THEREOF}

Various embodiments of this document relate to an automated test apparatus and its operating method for performing linear tests on high-speed memories.

Recently, with the rapid development of memory semiconductor design technology, the operating speed of memory is rapidly increasing. In addition, semiconductor process technology is developing, and the integration of memory circuits is increasing. Such high-speed, high-density memory is leading to the rapid development of the memory semiconductor industry. However, high-speed, high-density memory not only operates at high speed but also greatly increases the complexity of the circuit, which also greatly increases the testing cost compared to the semiconductor production cost. Accordingly, efficient testing technology to reduce testing costs and enhance the competitiveness of memory semiconductor products has become a very important issue.

A representative method of testing memory semiconductors is the method using automatic test equipment (ATE). Unlike the BIST (built-in self test) method, the memory semiconductor test method using ATE has the advantage of being able to test a wider range of functions without inserting a test circuit inside the memory semiconductor.

(Patent Document 0001) Republic of Korea Registered Patent No. 10-0850204 (Announcement Date: 2008.08.04)

As semiconductor memory devices become increasingly faster, the data input/output speed of the semiconductor memory devices exceeds the speed limit of the test pattern that can be measured by ATE. Therefore, many problems may occur in testing for mass production of high-speed memory devices. For example, if the maximum frequency that can be measured by ATE is 200 MHz and the operating frequency of the semiconductor memory device to be tested is 800 MHz, a problem may occur in which it is difficult to accurately measure whether a defect occurs in the actual memory cell. In other words, since the low-speed ATE that was previously used has difficulty testing the speed of the latest high-speed memory, the latest ATE that is faster than the processing speed of the memory is required, and this can cause the problem of incurring too high replacement costs.

According to various embodiments, an automated test equipment (ATE) for performing a linear test on a high-speed memory includes a processor, wherein the processor is configured to obtain a test pattern program, and in response to a save pattern (SVP) command code, store a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in a pattern queue register, and convert a value of the data field from first data to second data based on a specific table corresponding to a characteristic of a device under test among pre-stored data conversion tables, and allocate the second data according to a preset data allocation order.

According to various embodiments, a method of operating an automated test equipment (ATE) for performing a linear test on a high-speed memory may include an operation of acquiring a test pattern program, an operation of storing, in a pattern queue register, a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in response to a save pattern (SVP) command code, an operation of converting a value of the data field from first data to second data based on a specific table corresponding to a characteristic of a device under test among pre-stored data conversion tables, and an operation of allocating the second data according to a preset data allocation order.

According to various embodiments, the present invention can provide an effect of improving the slow processing speed of existing ATE through a small number of setting cycles with a constant setting cycle regardless of the number of memory cells.

FIG. 1 illustrates a block diagram of an ATE according to various embodiments.
FIG. 2 is a diagram for explaining the operation of ATE according to various embodiments.
FIG. 3a illustrates an embodiment of a test pattern converted based on a pattern conversion table according to various embodiments.
FIG. 3b illustrates an example of an instruction structure according to various embodiments.
FIG. 4 is a diagram for explaining the operation of a data extraction module according to various embodiments.
FIG. 5 is a diagram for explaining the operation of a data conversion module according to various embodiments.
FIG. 6 is a diagram for explaining a pattern generator module and the operation of the generator module according to various embodiments.
In connection with the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings. It should be understood that the embodiments and the terms used herein are not intended to limit the technology described in this document to a specific embodiment, but rather to include various modifications, equivalents, and/or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar components. The singular expression may include plural expressions unless the context clearly indicates otherwise. In this document, expressions such as "A or B" or "at least one of A and/or B" may include all possible combinations of the items listed together. Expressions such as "first," "second," "first," or "second," may modify the corresponding components, regardless of order or importance, and are only used to distinguish one component from another, but do not limit the corresponding components. When it is said that a certain (e.g., a first) component is "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, said certain component may be directly connected to said other component, or may be connected through another component (e.g., a third component).

In this document, "configured to" can be used interchangeably with, for example, "suitable for," "capable of," "modified to," "made to," "capable of," or "designed to," either hardware-wise or software-wise. In some contexts, the phrase "a device configured to" can mean that the device is "capable of" doing something together with other devices or components. For example, the phrase "a processor configured to perform A, B, and C" can mean a dedicated processor (e.g., an embedded processor) for performing the operations, or a general-purpose processor (e.g., a CPU or application processor) that can perform the operations by executing one or more software programs stored in a memory device.

FIG. 1 illustrates a block diagram of an ATE (e.g., ATE (101) of FIG. 1) according to various embodiments.

According to various embodiments, the ATE (101) may include a bus (110), a processor (120), a memory (130), an input/output interface (140), and a communication interface (150). In some embodiments, the ATE (101) may omit at least one of the components or additionally include another component. The bus (110) may include a circuit that connects the components (110-150) to each other and transmits communication (e.g., control messages or data) between the components. The processor (120) may include one or more of a central processing unit, an application processor, or a communication processor (CP). The processor (120) may execute, for example, operations or data processing related to control and/or communication of at least one other component of the ATE (101).

The memory (130) may include volatile and/or nonvolatile memory. The memory (130) may store, for example, instructions or data related to at least one other component of the ATE (101). According to one embodiment, the memory (130) may store software and/or programs. The programs may include, for example, a kernel, middleware, an application programming interface (API), and/or an application program (or “application”). At least a portion of the kernel, the middleware, or the API may be referred to as an operating system. The kernel may control or manage, for example, system resources (e.g., a bus (110), a processor (120), or memory (130)) used to execute operations or functions implemented in other programs (e.g., middleware, APIs, or application programs). In addition, the kernel may provide an interface that allows the middleware, APIs, or application programs to control or manage system resources by accessing individual components of the ATE (101). The middleware may, for example, act as an intermediary so that an API or an application program can communicate with the kernel and exchange data. In addition, the middleware may process one or more work requests received from the application program according to priorities. For example, the middleware may give at least one of the application programs a priority to use the system resources (e.g., bus (110), processor (120), or memory (130)) of the ATE (101) and process the one or more work requests. The API is an interface for the application to control functions provided by the kernel or the middleware, and may include at least one interface or function (e.g., command) for, for example, file control, window control, image processing, or character control.

The input/output interface (140) can, for example, transmit commands or data input from a user or another external device to other component(s) of the ATE (101), or output commands or data received from other component(s) of the ATE (101) to the user or another external device.

The communication interface (150) can establish communication between, for example, the ATE (101) and an external electronic device. For example, the communication interface (150) can be connected to a network via wireless communication or wired communication to communicate with an external electronic device (e.g., a high-speed memory device to be tested). The wireless communication can include, for example, cellular communication using at least one of LTE, LTE-A (LTE Advance), CDMA (code division multiple access), WCDMA (wideband CDMA), UMTS (universal mobile telecommunications system), WiBro (Wireless Broadband), or GSM (Global System for Mobile Communications). According to one embodiment, the wireless communication can include, for example, at least one of WiFi (wireless fidelity), Bluetooth, Bluetooth low energy (BLE), Zigbee, near field communication (NFC), Magnetic Secure Transmission, Radio Frequency (RF), or Body Area Network (BAN). The wired communication may include at least one of, for example, a universal serial bus (USB), a high definition multimedia interface (HDMI), a recommended standard232 (RS-232), power line communication, or plain old telephone service (POTS). The network may include at least one of a telecommunications network, for example, a computer network (e.g., a LAN or WAN), the Internet, or a telephone network.

According to various embodiments, ATE (101) can perform tests on a device under test (DUT) (e.g., a high-speed memory device) using various memory test algorithms (particularly, the March SS algorithm). ATE (101) can perform read and write operations in a specific order using the memory test algorithm to check whether a memory cell operates normally. At this time, the number of times and order of the read and write operations may vary depending on the type of defect to be found. According to one embodiment, the DUT may be a word-oriented memory (WOM).

FIG. 2 is a diagram for explaining the operation of an ATE (e.g., ATE (101) of FIG. 1) according to various embodiments.

FIG. 3a illustrates an embodiment of a test pattern converted based on a pattern conversion table according to various embodiments.

FIG. 3b illustrates an example of an instruction structure according to various embodiments.

FIG. 4 is a diagram for explaining the operation of a data extraction module according to various embodiments.

FIG. 5 is a diagram for explaining the operation of a data conversion module according to various embodiments.

FIG. 6 is a diagram for explaining a pattern generator module and the operation of the generator module according to various embodiments.

According to various embodiments, the ATE (101) may include a data extraction module (201), a data transformation module (202), a pattern generator module (203), and a selector module (204). At least one of the modules (201, 202, 203, 204) may be a hardware element physically implemented in a processor (e.g., processor (120) of FIG. 1) or a software element executed by the processor (120).

According to one embodiment, the processor (120) (e.g., the data extraction module (201)) can obtain a test pattern program. For example, the data extraction module (201) can obtain a test pattern program from an external processor, or can obtain a test pattern program by an internal processor (120). According to one embodiment, the processor (120) (e.g., the data extraction module (201)) can obtain an instruction that generates a converted test pattern according to a specific format based on a pattern conversion table. For example, referring to FIG. 3A, <301> represents a first test pattern program in which a specific direction is specified in the March SS algorithm, <302> represents a second test pattern program that expresses the first test pattern program as instruction-based test patterns, and <303> represents a third test pattern program that expresses the second test pattern program as binary test patterns based on the pattern conversion table (310). The above-described conversion operation may be performed by one of the external processor, the internal processor (120), or the data extraction module (201), and, according to one embodiment, may be directly converted from the first test pattern program (301) to the third test pattern program (303) by the above-described component. For example, referring to 320 of FIG. 3A, the data extraction module (201) may convert the first test pattern (e.g., |(w0);) of the first test pattern program (301) into an instruction-based test pattern (e.g., up/w0/end), and may convert it into a binary test pattern (e.g., 0/10/1) based on a pattern conversion table (310). According to one embodiment, the pattern conversion table (310) may include information about a direction, information about an end, and information about a March element.

According to one embodiment, each instruction of a test pattern program (e.g., 301, 302, or 302) acquired by the processor (120) (e.g., data extraction module (301)) may include a 5-bit opcode field, a 3-bit set_sel field, and a 24-bit operand field. For example, referring to FIG. 3B, the opcode field may indicate an operation code (330), the set_sel field may indicate a value related to a location of a queue, and the operand field may indicate a value related to a test pattern. Meanwhile, the types of the operation codes may be classified into (i) commands for pattern generation, (ii) commands for controlling interrupts, (iii) commands for controlling PCs, and (iv) commands for controlling repetition of pattern programs. Additionally, the operand field may be generated according to a specific format among a plurality of formats (340), and the specific format may be determined according to a setting value of a word-oriented memory (WOM) (e.g., x4, x8, x16).

According to one embodiment, the processor (120) (e.g., the data extraction module (201)) may store, in response to an SVP (save pattern) instruction code, a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of a test pattern program in a pattern queue register. For example, referring to <401> of FIG. 4, when the SVP instruction code is identified, the data extraction module (201) may store a value of a direction field (e.g., 0), a value of a read/write field (e.g., 1), and a value of a data field (e.g., 0) identified from a test pattern (e.g., up=0, w0=10, end=1) in a pattern queue register. By pre-storing a test pattern in the pattern queue register, subsequent commands can be predicted.

According to one embodiment, the processor (120) (e.g., the data extraction module (201)) may extract the value of the data field stored in the pattern queue register. According to one embodiment, referring to <402> of FIG. 4, the data extraction module (201) may transfer the value of the extracted data field to the data conversion module (202). At this time, the transfer operation may be performed in response to a LOAD command code. According to one embodiment, referring to FIG. 4, data transferred from the data extraction module (201) to the data conversion module (202) may change according to a setting value of a word-oriented memory (e.g., x8).

According to one embodiment, the processor (120) (e.g., the data conversion module (202)) may convert the value of the data field from the first data to the second data based on a specific table corresponding to the characteristic of the device under test (205) among the pre-stored data conversion tables. For example, referring to FIG. 5, the data conversion module (202) may obtain the value (501) of the data field of the test pattern (e.g., 011 011 011 111 111 111), and may convert the value of the data field from the first data to the second data based on a specific table (512) corresponding to the characteristic (e.g., WOM x8) of the device under test (205) among the pre-stored data conversion tables (511, 512, 513). In the above example, referring to FIG. 5, when the value of the data field is '011', the data conversion module (202) can obtain the second data (e.g., 0000_1111) mapped to the first data (e.g., 011) by using the specific table (512). According to one embodiment, the characteristic of the device under test (205) can correspond to the setting value of the word-oriented memory.

According to one embodiment, the processor (120) (e.g., the data conversion module (202)) may allocate the second data to the pattern generator module (203) according to a preset data allocation order. For example, referring to FIG. 5, if the pattern generator module (203) is set to include six pattern generators (PGs), the data conversion module (202) may linearly allocate the second data (e.g., 0000_1111) to each pattern generator according to the preset data allocation order (e.g., PG1->PG2->PG3->PG4->PG5->PG6) for the pattern generators, as in <520> of FIG. 5, and as a result, data may be transmitted to each pattern generator, as in <530> of FIG. 5.

According to one embodiment, the processor (120) (e.g., the pattern generator module (203)) may transmit the assigned second data to the selector module (204). For example, referring to FIG. 6, each of the plurality of pattern generators (e.g., PG1 to PG6) in the pattern generator module (203) may be implemented in parallel to simultaneously transmit data and may transmit the data assigned to it to the selector module (204). According to one embodiment, the processor (120) (e.g., the selector module (204)) may transmit data to the device under test (205) according to a setting. For example, referring to FIG. 6, the selector module (204) may transmit data acquired from the pattern generator module (203) to the device under test (205) according to a preset order. In this case, by testing the device under test (205) using six parallel pattern generators capable of processing data at 600 MHz, rather than testing the device under test (205) using a single pattern generator capable of processing data at 100 MHz, it is possible to provide an effect of testing a high-speed memory device with a low-speed ATE (101). According to one embodiment, the selector module (204) can collect patterns generated in parallel from a plurality of pattern generators in the pattern generator (203) and reallocate them to the device under test (205). According to one embodiment, the operations of the pattern generator module (203) and the selector module (204) can be performed by a person skilled in the art using a technique known to those skilled in the art.

According to various embodiments, an automated test equipment (ATE) for performing a linear test on a high-speed memory includes a processor, wherein the processor is configured to obtain a test pattern program, and in response to a save pattern (SVP) command code, store a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in a pattern queue register, and convert a value of the data field from first data to second data based on a specific table corresponding to a characteristic of a device under test among pre-stored data conversion tables, and allocate the second data according to a preset data allocation order.

According to various embodiments, the processor may be configured to obtain an instruction, as the test pattern program, for generating a test pattern converted based on a pattern conversion table according to a specific format corresponding to a setting value of a word-oriented memory.

According to various embodiments, the test pattern program is a program generated according to the March SS algorithm, and each instruction of the test pattern program may include a 5-bit opcode field, a 3-bit set_sel field, and a 24-bit operand field.

According to various embodiments, the processor may be configured to linearly allocate the second data to each of the plurality of pattern generators according to a set order for the plurality of pattern generators as the preset data allocation order.

According to various embodiments, a method of operating an automated test equipment (ATE) for performing a linear test on a high-speed memory may include an operation of acquiring a test pattern program, an operation of storing, in a pattern queue register, a value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in response to a save pattern (SVP) command code, an operation of converting a value of the data field from first data to second data based on a specific table corresponding to a characteristic of a device under test among pre-stored data conversion tables, and an operation of allocating the second data according to a preset data allocation order.

The term "module" as used in this document includes a unit composed of hardware, software or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A "module" may be an integrally composed component or a minimum unit or a part thereof that performs one or more functions. A "module" may be implemented mechanically or electronically, and may include, for example, an ASIC (application-specific integrated circuit) chip, FPGAs (field-programmable gate arrays), or a programmable logic device, known or to be developed in the future, that performs certain operations. At least a portion of a device (e.g., modules or functions thereof) or a method (e.g., operations) according to various embodiments may be implemented as an instruction stored in a computer-readable storage medium (e.g., memory (130)) in the form of a program module. When the instruction is executed by a processor (e.g., processor (120)), the processor may perform a function corresponding to the instruction. The computer-readable recording medium may include a hard disk, a floppy disk, a magnetic medium (e.g., a magnetic tape), an optical recording medium (e.g., a CD-ROM, a DVD, a magneto-optical medium (e.g., a floptical disk), a built-in memory, etc. The instructions may include codes generated by a compiler or codes executable by an interpreter. A module or program module according to various embodiments may include at least one or more of the above-described components, some of them may be omitted, or other components may be further included. Operations performed by a module, a program module, or other components according to various embodiments may be executed sequentially, in parallel, iteratively, or heuristically, or at least some of the operations may be executed in a different order, omitted, or other operations may be added.

And the embodiments disclosed in this document are presented for the purpose of explanation and understanding of the disclosed technical contents, and do not limit the scope of the present disclosure. Therefore, the scope of the present disclosure should be interpreted to include all modifications or various other embodiments based on the technical idea of the present disclosure.

Claims (5)

In automated test equipment (ATE) for performing linear tests on high-speed memory,
Contains a processor,
The above processor,
Obtain the test pattern program,
In response to the SVP (save pattern) command code, the values of the direction field, the values of the read/write field, and the values of the data field identified from the test pattern of the test pattern program are stored in the pattern queue register,
Converting the value of the data field from first data to second data based on a specific table corresponding to the characteristics of the device under test among the stored data conversion tables, and
Set to allocate the above second data according to the preset data allocation order,
Automated test equipment.
In the first paragraph,
The above processor,
As the above test pattern program, it is set to obtain an instruction that generates a test pattern converted based on a pattern conversion table according to a specific format corresponding to a setting value of a word-oriented memory.
Automated test equipment.
In the second paragraph,
The above test pattern program is a program generated according to the March SS algorithm.
Each instruction in the above test pattern program includes a 5-bit opcode field, a 3-bit set_sel field, and a 24-bit operand field.
Automated test equipment.
In the third paragraph,
The above processor,
As the above preset data allocation order, the second data is set to be linearly allocated to each of the plurality of pattern generators according to the set order for the plurality of pattern generators.
Automated test equipment.
In the operating method of automated test equipment (ATE) for performing linear testing on high-speed memory,
The action of obtaining a test pattern program,
An operation of storing the value of a direction field, a value of a read/write field, and a value of a data field identified from a test pattern of the test pattern program in the pattern queue register in response to a SVP (save pattern) command code.
An operation of converting the value of the data field from first data to second data based on a specific table corresponding to the characteristics of the device under test among the stored data conversion tables, and
Including an operation of allocating the second data according to a preset data allocation order.
How automated test equipment works.

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