KR102743089B1 - Electronic device with vertically controlled carrier concentrations and manufacturing method thereof - Google Patents

Abstract

The present invention relates to an electronic device and a method for manufacturing the same. According to one embodiment, the electronic device includes a lower electrode formed on an upper portion of a substrate, an oxide semiconductor layer formed on an upper portion of the lower electrode and including a first oxide layer in which the occurrence of oxygen vacancies is suppressed, and an upper electrode formed on an upper portion of the oxide semiconductor layer.

Description

{ELECTRONIC DEVICE WITH VERTICALLY CONTROLLED CARRIER CONCENTRATIONS AND MANUFACTURING METHOD THEREOF}

The present invention relates to an electronic device and a method for manufacturing the same, and more specifically, to a technical idea for suppressing the occurrence of oxygen vacancies in an oxide layer.

Research is ongoing to apply metal oxides to the active layer (i.e., channel layer) of current electronic devices to replace the existing silicon (Si)-based active layer.

Metal oxide semiconductors have the advantages of a large optical band gap, low off-current, and high field-effect mobility, enabling high-resolution displays without significant signal delay, and are therefore being applied to the active layer of thin film transistors (TFTs) for displays, especially transparent or flexible displays.

In particular, interest in tin oxide (SnO ₂ ), which has high mobility characteristics and a wide optical band gap similar to indium (In) oxide semiconductors, is increasing; however, compared to conventional silicon (Si)-based transistors, metal oxide-based transistors have the problem of high instability due to continuous operation bias stress.

This is caused by trap regions existing at the interface between the semiconductor and the insulator or surface trap regions generated from water ( _H2O ) or oxygen ( _O2 ) molecules adsorbed in the air, and a technology for adding a dopant that suppresses the formation of oxygen vacancies has been proposed to address this.

However, although the above-described existing technology can improve the stability of the device by suppressing the formation of oxygen vacancies, there is a problem in that the device performance decreases due to a decrease in field-effect mobility.

Korean Patent Publication No. 10-2022-0158325, "V-NAND memory having dual oxide layers for improving ferroelectric performance and its manufacturing method" Korean Patent Publication No. 10-2019-0005665, “Resistance change memory device”

The present invention aims to provide an electronic device and a manufacturing method thereof capable of solving electrical stability problems by minimizing the occurrence of oxygen vacancies in an oxide semiconductor-based electronic device.

In addition, the present invention aims to provide an electronic device and a method for manufacturing the same, which can solve stability problems by minimizing the occurrence of oxygen vacancies only at the interface of an oxide layer that causes electrical stability problems of the device, while simultaneously securing unique mobility characteristics to the maximum extent possible.

An electronic device according to one embodiment of the present invention may include a lower electrode formed on an upper portion of a substrate, an oxide semiconductor layer formed on an upper portion of the lower electrode and including a first oxide layer in which the occurrence of oxygen vacancies is suppressed, and an upper electrode formed on an upper portion of the oxide semiconductor layer.

According to one aspect, the oxide semiconductor layer further includes a second oxide layer, and the first oxide layer can be formed on at least one of the upper and lower portions of the second oxide layer.

According to one aspect, the oxide semiconductor layer can be deposited using a target containing a preset metal material during deposition of the first oxide layer, and then a heat treatment process can be performed to suppress the occurrence of oxygen vacancies within the first oxide layer.

According to one aspect, the oxide semiconductor layer can suppress the occurrence of oxygen vacancies in the first oxide layer by performing a solution process and a heat treatment process on a mixture of a first precursor corresponding to the first oxide layer and a second precursor corresponding to a preset metal material during deposition of the first oxide layer.

According to one aspect, the oxide semiconductor layer can suppress the occurrence of oxygen vacancies within the first oxide layer by performing a heat treatment process in a state where a metal layer based on a preset metal material is formed on the first oxide layer.

According to one side, the first oxide layer can suppress the occurrence of oxygen vacancies within the first oxide layer by changing the metal material constituting the metal layer into an island structure based on metal oxide through a heat treatment process.

According to one side, the metal layer can be formed on at least one of the upper and lower portions of the first oxide layer with a thickness of 0.3 nm to 0.9 nm.

According to one aspect, the electronic device may further include an insulating layer formed between the first electrode and the semiconductor oxide layer.

According to one aspect, the upper electrode may include a first upper electrode and a second upper electrode.

A method for manufacturing an electronic device according to an embodiment of the present invention may include a step of forming a lower electrode formed on an upper portion of a substrate, a step of forming an oxide semiconductor layer including a first oxide layer in which the occurrence of oxygen vacancies is suppressed on the lower electrode, and a step of forming an upper electrode on the oxide semiconductor layer.

According to one aspect, the oxide semiconductor layer further includes a second oxide layer, and the first oxide layer can be formed on at least one of the upper and lower portions of the second oxide layer.

According to one aspect, the step of forming an oxide semiconductor layer may further include a step of forming a first oxide layer as a first semiconductor layer, a step of forming a second oxide layer as a second semiconductor layer on top of the first semiconductor layer, and a step of forming the first oxide layer as a third semiconductor layer on top of the second semiconductor layer.

According to one side, when a heat treatment process is performed on a metal layer based on a preset metal material on a first oxide layer, the metal material constituting the metal layer changes into an island structure based on a metal oxide, thereby suppressing the occurrence of oxygen vacancies within the first oxide layer.

According to one embodiment, the present invention can solve the electrical stability problem by minimizing the occurrence of oxygen vacancies in an oxide semiconductor-based electronic device.

According to one embodiment, the present invention can solve the stability problem by minimizing the occurrence of oxygen vacancies only at the interface of an oxide semiconductor layer that causes an electrical stability problem of a device, while simultaneously securing unique mobility characteristics to the maximum extent.

Figure 1 is a drawing for explaining an electronic device according to one embodiment.
FIG. 2 is a drawing for explaining the GIXRD analysis results of an electronic device according to one embodiment.
FIGS. 3A to 3C are drawings for explaining the XPS spectrum analysis results of an electronic device according to one embodiment.
FIGS. 4A and 4B are drawings for explaining the results of SEM image analysis of an electronic device according to one embodiment.
FIG. 5 is a drawing for explaining an implementation example of an electronic device according to one embodiment.
FIGS. 6 and 7 are drawings for explaining the NBS test results of an electronic device according to one embodiment.
FIGS. 8A and 8B are drawings for explaining the results of XPS depth profile analysis of an electronic device according to one embodiment.
Figure 9 is a drawing for explaining a method for manufacturing an electronic device according to one embodiment.

Specific structural or functional descriptions of embodiments according to the concept of the present invention disclosed in this specification are merely exemplified for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention can be implemented in various forms and are not limited to the embodiments described in this specification.

The embodiments according to the concept of the present invention can have various changes and can have various forms, so the embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, but includes changes, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Although the terms first or second may be used to describe various components, the components should not be limited by the terms. The terms are only intended to distinguish one component from another, for example, without departing from the scope of the invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

When it is said that an element is "connected" or "connected" to another element, it should be understood that it may be directly connected or connected to that other element, but that there may be other elements in between. On the other hand, when it is said that an element is "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between elements, such as "between" and "directly between" or "directly adjacent to", should be interpreted similarly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. As used herein, the terms "comprises" or "has" and the like are intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but should be understood to not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries, such as those defined in common usage, should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. However, the scope of the patent application is not limited or restricted by these embodiments. The same reference numerals presented in each drawing represent the same components.

Figure 1 is a drawing for explaining an electronic device according to one embodiment.

Referring to FIG. 1, an electronic device (100) according to one embodiment can solve an electrical stability problem by minimizing the occurrence of oxygen vacancies.

In addition, the electronic device (100) can solve the stability problem by minimizing the occurrence of oxygen vacancies only at the interface of the oxide layer that causes electrical stability problems, while simultaneously securing unique mobility characteristics to the maximum extent.

Hereinafter, for convenience of explanation, the electronic device (100) is exemplified as a thin film transistor, but the electronic device (100) according to one embodiment is not limited thereto and can be applied to all electronic devices based on oxide semiconductors.

To this end, the electronic device (100) may include a lower electrode (120) formed on an upper portion of a substrate (110), an oxide semiconductor layer (130) formed on an upper portion of the lower electrode (120), and an upper electrode (140-1, 140-2) formed on an upper portion of the oxide semiconductor layer (130), wherein the oxide semiconductor layer (130) may include a first oxide layer (130-1, 130-3) in which the occurrence of oxygen vacancies is suppressed.

According to one aspect, the electronic device (100) may further include an insulating layer (150) formed between the first electrode (120) and the semiconductor oxide layer (130).

Additionally, the upper electrode (140-1, 140-2) may include a first upper electrode (140-1) and a second upper electrode (140-2).

Specifically, when the electronic device (100) is a transistor, the lower electrode (120) may be a gate electrode, the insulating layer (150) may be a gate insulating layer, and the first upper electrode (140-1) and the second upper electrode (140-2) may be a source electrode and a drain electrode, respectively.

Additionally, each of the lower electrode (120), the first upper electrode (140-1), and the second upper electrode (140-2) can be formed using known electrode materials and process methods.

According to one side, the oxide semiconductor layer (130) can be deposited using a target containing a preset metal material during deposition of the first oxide layer (130-1, 130-3) and then a heat treatment process can be performed to suppress the occurrence of oxygen vacancies within the first oxide layer.

In addition, the oxide semiconductor layer (130) can suppress the occurrence of oxygen vacancies in the first oxide layer (130-1, 130-3) by performing a solution process and a heat treatment process on a mixture of a first precursor corresponding to the first oxide layer (130-1, 130-3) and a second precursor corresponding to a preset metal material during deposition of the first oxide layer (130-1, 130-3).

For example, the preset metal material may include at least one metal among aluminum (Al), zirconium (Zr), and hafnium (Hf).

Meanwhile, the oxide semiconductor layer (130) can suppress the occurrence of oxygen vacancies within the first oxide layer (130-1, 130-3) by performing a heat treatment process while depositing a metal layer based on a preset metal material on the first oxide layer (130-1, 130-3).

In other words, the first oxide layer (130-1, 130-3) forms a metal layer capable of suppressing the occurrence of oxygen vacancies within the oxide semiconductor, and then performs additional heat treatment to cause diffusion and doping processes during the heat treatment process, thereby suppressing the formation of oxygen vacancies within the semiconductor oxide.

Specifically, the first oxide layer (130-1, 130-3) can suppress the occurrence of oxygen vacancies within the first oxide layer (130-1, 130-3) by changing the metal material constituting the metal layer into an island structure based on metal oxide through a heat treatment process.

For example, the first oxide layer (130-1, 130-3) may be subjected to an additional heat treatment process for 5 to 40 minutes, preferably, an additional heat treatment process may be performed at a temperature of 400 °C to 600 °C for 20 minutes.

According to one aspect, the oxide semiconductor layer (130) further includes a second oxide layer (130-2), and a first oxide layer (130-1, 130-3) on which a metal layer is formed may be formed on at least one of the upper and lower portions of the second oxide layer (130-2). In other words, although FIG. 1 exemplifies an embodiment in which the first oxide layers (130-1, 130-3) are disposed both on the upper and lower portions of the second oxide layer (130-2), the first oxide layers (130-1, 130-3) according to one embodiment are not limited thereto, and only one of the first oxide layers of the drawing reference numerals 130-1 or 130-2 may be provided.

For example, the metal layer may be a metal ultra-thin film layer formed on at least one of the upper and lower portions of the first oxide layer (130-1, 130-3) with a thickness of 0.3 nm to 0.9 nm.

In addition, at least one of the first oxide layer (130-1, 130-3) and the second oxide layer (130-2) may be an oxide layer based on at least one metal among tin (Sn), aluminum (Al), zirconium (Zr), and hafnium (Hf), and the metal layer may be an aluminum (Al) layer, but is not limited thereto.

In other words, the first oxide layer (130-1, 130-3) may be an oxygen vacancy less layer in which the occurrence of oxygen vacancies is minimized through the formation of a metal layer and an additional heat treatment process, and the second oxide layer (130-2) may be a general semiconductor oxide layer.

Specifically, the oxide semiconductor layer (130) can be formed by at least one of sol-gel, slit-die, printing, spin-coating, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, thermal evaporation, and E-beam evaporation, and the concentration of oxygen vacancies can be controlled depending on process conditions (ambient heat treatment/deposition, temperature, deposition speed, and thickness of the thin film, etc.).

That is, the present invention controls the above-described process conditions to a preset first condition in which less oxygen vacancies are generated, thereby forming a first oxide layer (130-1, 130-3) (i.e., an oxygen vacancy reduction layer), and controls the above-described process conditions to a preset second condition in which many oxygen vacancies are generated, thereby forming a second oxide layer (130-2) (i.e., a general semiconductor oxide layer).

Meanwhile, in the process of forming the oxide semiconductor layer (130), the first oxide layer (130-1, 130-3) is formed using two sources (original oxides) and another oxide source for suppressing the formation of oxygen vacancies, and the second oxide layer (130-2) can be formed using only two sources (original oxides), through which the oxide semiconductor layer (130) can be formed with a different vertical profile.

FIG. 2 is a drawing for explaining the GIXRD analysis results of an electronic device according to one embodiment.

Referring to FIG. 2, the reference numeral 200 illustrates the results of the GIXRD _{(Grazing incidence x-ray diffraction) analysis of an oxide layer (Pristine) based on general tin oxide (SnO 2 )} and an oxide layer (Al+5 min, Al+20 min, Al+40 min) in which an aluminum (Al) island structure is formed by forming an ultra-thin aluminum (Al) film layer on tin oxide (SnO 2 ) and heat-treating for 5 minutes, 20 minutes, and 40 minutes, respectively (i.e., the first oxide layer on which a metal layer is formed).

Specifically, (a) of the drawing symbol 200 illustrates the analysis result of a GIXRD spectrum for the (110) lattice plane of the first oxide layer, i.e., tin oxide (SnO ₂ ), and (b) of the drawing symbol 200 illustrates the analysis result of a GIXRD pattern for the (110) lattice plane of tin oxide (SnO ₂ ).

According to (a) and (b) of the drawing symbol 200, the first oxide layer according to one embodiment was an aluminum (Al) ultra-thin film layer deposited on tin oxide (SnO ₂ ), but XRD peaks according to aluminum (Al) or aluminum oxide (Al ₂ O ₃ ) were not observed, and the diffraction peaks at 2θ = 26.61°, 33.89°, 37.95°, 51.78°, and 54.75°, respectively, were found to correspond to the (110), (101), (200), (211), and (220) planes of tin oxide (SnO ₂ ).

Additionally, the (110) peak of tin oxide (SnO ₂ ) was analyzed to have the lowest full width at half maximum (FWHM) among all the plane peaks, which means that the tin oxide (SnO ₂ ) crystals were initially grown on the (110) plane.

Meanwhile, the crystallite size of tin oxide (SnO ₂ ) can be derived from the Scherrer equation together with the (110) peak. Specifically, the crystallite sizes of tin oxide (SnO 2 ) were derived as 7.16 nm, 7.85 nm, 7.23 nm, and 7.10 nm when there was no aluminum (Al) ultra-thin film layer (Pristine) and when the aluminum ( _Al ) ultra-thin film was formed and then heat-treated for 5 min, 20 min, and 40 min (Al + 5 min, Al + 20 min, Al + 40 min).

Additionally, the full width at half maximum (FWHM) of the (110) peak of tin oxide (SnO ₂ ) was found to increase as the heat treatment time after deposition of the aluminum (Al) ultra-thin film layer increased.

FIGS. 3A to 3C are drawings for explaining the XPS spectrum analysis results of an electronic device according to one embodiment.

Referring to FIGS. 3a to 3c, FIGS. 3a to 3c illustrate the XPS spectrum analysis results of each of an oxide layer based on tin oxide (SnO ₂ ) on which an aluminum (Al) ultra-thin film layer is not formed and an oxide layer on which an aluminum (Al) ultra-thin film layer is formed (i.e., a first oxide layer on which a metal layer is formed) on which an aluminum (Al) island structure is formed by heat-treating for 5 minutes, 20 minutes, and 40 minutes, respectively.

Specifically, (a) to (d) of the drawing code 310 illustrate the XPS spectrum analysis results of Al 2p, (a) to (d) of the drawing code 320 illustrate the XPS spectrum analysis results of Sn 3d _{5 /2} , and (a) to (d) of the drawing code 330 illustrate the XPS spectrum analysis results of O 1s.

According to (a) to (d) of the drawing symbol 310, the metallic aluminum (Al) peak of 72.7 eV was not observed because the first oxide layer according to one embodiment was an aluminum (Al) ultra-thin film layer deposited, and only after an additional heat treatment process was the aluminum oxide (Al ₂ O ₃ ) peak of 73.4 eV was observed, confirming that aluminum oxide (Al ₂ O ₃ ) was successfully formed and that the remaining aluminum (Al) element was sufficiently doped into the aluminum oxide (Al ₂ O ₃ ) thin film through the additional heat treatment process.

In other words, a part of the deposited aluminum (Al) ultra-thin film is oxidized and converted to aluminum oxide (Al ₂ O ₃ ) during the additional heat treatment process, and the rest can simultaneously function as an Al ^{3 +} dopant source inside tin oxide (SnO ₂ ). However, no aluminum (Al) or aluminum (Al) related peaks were observed in the GIXRD data, which means that the formed aluminum oxide (Al ₂ O ₃ ) is in an amorphous state or is too thin to be detected.

According to (a) to (d) of the drawing symbol 320, the relative peak area of Sn ⁴⁺ ions was found to decrease from 83.5% to 57.0% as the time of the additional heat treatment process increased after deposition of the aluminum (Al ⁾ ultra-thin film layer, which caused a decrease in the number of carriers and a weakening of the characteristics of the n-type semiconductor, which means that the formation of oxygen vacancies is further suppressed as the heat treatment time increases.

According to (a) to (d) of the drawing reference numeral 330, the O 1s spectrum shows three configurations corresponding to oxygen contained in the metaloxide lattice (LO), VO and -OH at 529.9 eV, 531 eV and 532.4 eV, respectively.

Compared with tin oxide (SnO ₂ ) without an aluminum (Al) ultra-thin film layer, the relative peak area of VO of tin oxide (SnO ₂ ) that was additionally heat treated after depositing an aluminum (Al) ultra-thin film layer decreased from 28.73% to 17.41% with increasing heat treatment time, whereas the relative peak area of LO increased from 32.63% to 41.22%.

That is, the deposited aluminum (Al) ultra-thin film layer was completely converted to aluminum oxide (Al ₂ O ₃ ), and the partially diffused Al ^{3 +} ions were found to effectively suppress the formation of V2O.

The electronegativity difference between Al(1.5) and O(3.5) is larger than that between aluminum (Al) and Sn(1.8), which controls the ^{Al3 +} ion to have a stronger bond with ^O2- ion than ^{Sn4 +} ion, and the added aluminum (Al) was found to successfully reduce the number of oxygen vacancies.

FIGS. 4A and 4B are drawings for explaining the results of SEM image analysis of an electronic device according to one embodiment.

Referring to FIGS. 4a and 4b, (a) to (d) of the drawing reference numeral 410 illustrate SEM images of an oxide layer based on tin oxide (SnO ₂ ) on which an aluminum (Al) ultra-thin film layer is not formed ((a) of the drawing reference numeral 410) and an oxide layer on which an aluminum (Al) island structure is formed by heat-treating for 5 minutes, 20 minutes, and 40 minutes, respectively, while forming an aluminum (Al) ultra-thin film layer (i.e., a first oxide layer on which a metal layer is formed) ((b) to (d) of the drawing reference numeral 410).

In addition, (a) to (d) of the drawing reference numeral 420 illustrate the analysis results of drain current-drain voltage (I _D -V _D ) for each oxide layer of (a) to (d) of the drawing reference numeral 410.

According to (a) to (d) of the drawing symbol 410, on the surface of tin oxide (SnO ₂ ) on which an additional heat treatment process was performed after the aluminum (Al) ultra-thin film layer was formed, an island structure based on aluminum oxide (Al ₂ O ₃ ) was observed, and the size of the island structure was found to increase from 10 nm to 30 nm as the heat treatment time increased.

Additionally, as the heat treatment time increased, fragmentation of the island structure was observed due to dissolution of particles on the surface.

According to (a) to (d) of the drawing symbol 420, when the electronic device according to one embodiment is implemented as a transistor, the drain current (I _D ) is measured at a gate voltage of -30.0 V to +30.0 V, the drain voltage (V _D ) is fixed to +30.0 V, and the transistor functions as an n-type semiconductor.

Specifically, the drain current-drain voltage (I _D -V _D ) of the electronic device according to one embodiment did not exhibit a perfect linear curve in the region of low drain voltage (V _D ), which means that a Schottky barrier, rather than an ohmic contact, was formed between the active layer based on the main oxide (SnO ₂ ) and the gold (Au) electrode (i.e., the drain electrode), and here, the formation of the Schottky barrier is due to the difference in work functions of the gold (Au) electrode and the oxide semiconductor.

FIG. 5 is a drawing for explaining an implementation example of an electronic device according to one embodiment.

Referring to FIG. 5, (a) of the drawing symbol 500 illustrates a thin film transistor (TFT) based on tin oxide (SnO ₂ ) formed by a sol-gel method, that is, an electronic device according to one embodiment, wherein the inset illustrates an SEM image of tin oxide (SnO ₂ ).

In addition, (b) of the drawing symbol 500 illustrates the results of analyzing the drain current-gate voltage (I _D -V _G ) of the tin oxide (SnO ₂ ) on which the aluminum (Al) ultra-thin film layer of the electronic device of (a) of the drawing symbol 500 has been deposited according to the additional heat treatment time.

According to (a) and (b) of the drawing symbol 500, the field-effect mobility of the tin oxide (SnO ₂ )-based thin film transistors was derived as 8.77 cm 2 /Vs, 8.07 cm 2 /Vs, 8.49 cm 2 /Vs, and 8.49 cm ² /Vs, respectively, when there was no aluminum (Al) ultra-thin film layer (Pristine) and when the aluminum (Al) ultra-thin film layer was formed and then heat-treated for 5 min, 20 min, and 40 min (Al ⁺ 5 min, Al + 20 min, Al + ⁴⁰ min), and the Subthreshold Swing (SS) values were derived as 1.3 V/decade, 3.1 V/decade, 1.63 V ^/ decade, and 1.27 V/decade.

FIGS. 6 and 7 are drawings for explaining the NBS test results of an electronic device according to one embodiment.

Referring to FIGS. 6 and 7, (a) to (d) of the drawing reference numeral 600 illustrate analysis results of drain current-gate voltage (I D -V G ) derived from a negative bias stress (NBS) test process for a thin film transistor (Pristine) based on tin oxide (SnO ₂ ) on which an aluminum (Al) ultra-thin film layer is not formed, and a thin film transistor (Al + 5 min, Al + 20 min, Al + 40 min) based on tin oxide ( _{SnO 2 )} on which an aluminum (Al) island structure is formed by heat-treating for 5 minutes, 20 minutes, and 40 minutes, respectively (i.e., an electronic device according to an embodiment).

In addition, (a) and (b) of the drawing symbol 700 illustrate the results of analysis of field-effect mobility and threshold voltage (V th ) derived from the NBS test process for a thin film transistor (Pristine) based on tin oxide (SnO ₂ ) on which an ultra-thin film layer is not formed, and a thin film transistor (Al + 5 min, Al + 20 min, Al + 40 min) based on tin oxide (SnO ₂ ) on which an aluminum (Al) island structure is formed by heat-treating for 5 minutes, 20 minutes, and 40 minutes, respectively, while forming an aluminum ( _Al ) ultra-thin film layer (i.e., an electronic device according to an embodiment).

Specifically, the shift values of the threshold voltage (V th ) of tin oxide (SnO 2 )-based thin film transistors were -21.99 V, -5.08 V, -3.84 V, and -4.50 V when there was no aluminum (Al) ultra-thin film layer ( _Pristine ) and when an aluminum ( _Al ) ultra-thin film was formed and then heat-treated for 5, 20, and 40 minutes (Al + 5 min, Al + 20 min, Al + 40 min).

That is, the thin film transistor that underwent an additional heat treatment process for 20 minutes showed the best results in terms of high field-effect mobility and threshold voltage (V _th ) shift characteristics.

As described above, the NBS instability of metal oxide-based electronic devices is mainly caused by water ( _H2O ) molecules absorbed from defect sites inside the semiconductor or the back-channel surface at the semiconductor-insulator interface, and XPS data show that the electronic devices according to one embodiment exhibit a decrease in the number of surface oxygen vacancies in the thin film as the aluminum (Al) ultra-thin film layer functioning as an aluminum (Al) dopant source is deposited, thereby minimizing unwanted trap and detrap reactions, thereby deriving improved bias stress stability characteristics.

FIGS. 8A and 8B are drawings for explaining the results of XPS depth profile analysis of an electronic device according to one embodiment.

Referring to FIGS. 8a and 8b, the XPS depth profile analysis results of a thin film transistor (Pristine) based on tin oxide (SnO ₂ ) on which an aluminum (Al) ultra-thin film layer is not formed and a thin film transistor (Al+20 min) based on tin oxide (SnO ₂ ) on which an aluminum (Al) island structure is formed by heat treatment for 20 minutes in a state where an aluminum (Al) ultra-thin film layer is formed are exemplified.

Specifically, (a) and (b) of the drawing symbol 810 illustrate analysis results for Al 2p, (c) and (d) of the drawing symbol 810 illustrate analysis results for Sn _{3d 5/2 ,} and (e) and (f ₎ of the drawing symbol 810 illustrate analysis results for O 1s. In addition, (a) and (b) of the drawing symbol 820 illustrate summarized analysis results for O 1s and Sn _{3d 5/2 .}

Specifically, unlike the thin film transistor (Pristine) in which no Al 2p peak was observed, the thin film transistor (Al+20 min) on which an aluminum (Al) ultra-thin film layer was formed was analyzed to exhibit a single aluminum oxide (Al ₂ O ₃ ) peak at 73.4 eV, and the peak intensity was found to decrease with distance from the surface.

Additionally, in the thin film transistors (Al+20 min) on which an aluminum (Al) ultrathin film layer was formed, the relative peak area of the carrier concentration associated with ^{Sn4 +} ions was found to increase in the region farther from the surface and closer to the semiconductor-insulator interface.

Meanwhile, oxygen vacancies were found to decrease only in the surface region and not in the entire tin oxide (SnO ₂ ) semiconductor.

That is, the electronic device according to one embodiment can effectively suppress the formation of oxygen vacancies and reduce the concentration of oxygen vacancies on the surface by depositing an ultra-thin aluminum (Al) film layer and performing an additional heat treatment process, but it was found that the oxygen vacancies were not reduced in the entire area of the metal oxide.

In addition, the electronic device according to one embodiment forms an oxygen-vacancy (VO)-less region similar to a depletion region, and carrier transport occurs under this VO-less region, and this process can contribute to minimizing the occurrence of trap and detrap events at the back channel surface of the thin film transistor that cause bias stress instability arising from water (H ₂ O) or oxygen (O ₂ ) molecules.

Figure 9 is a drawing for explaining a method for manufacturing an electronic device according to one embodiment.

In other words, FIG. 9 is a drawing explaining a method for manufacturing an electronic device according to an embodiment explained through FIGS. 1 to 8b. In the following, any explanation that overlaps with the explanation through FIG. 1 to 8b among the contents explained through FIG. 9 will be omitted.

Referring to FIG. 9, at step 910, the manufacturing method can form a lower electrode formed on the upper portion of the substrate.

According to one side, the manufacturing method in step 910 can also utilize a highly doped p-type silicon (Si) substrate as the substrate on which the lower electrode is formed.

According to one side, in step 910, the manufacturing method can form an insulating layer on a substrate on which a lower electrode is formed.

For example, in step 910, the manufacturing method can form an insulating layer by growing a 100 nm thick silicon oxide (SiO ₂ ) layer on a silicon (Si) substrate.

Next, in step 920, the manufacturing method can form an oxide semiconductor layer including a first oxide layer in which the occurrence of oxygen vacancies is suppressed on the upper portion of the lower electrode.

Next, in step 930, the manufacturing method can form an upper electrode on top of the oxide semiconductor layer.

According to one side, in step 920, the manufacturing method can suppress the occurrence of oxygen vacancies within the first oxide layer by performing a heat treatment process after depositing using a target containing a preset metal material during deposition of the first oxide layer.

In addition, in step 920, the manufacturing method may suppress the occurrence of oxygen vacancies in the first oxide layer by performing a solution process and a heat treatment process for a mixture of a first precursor corresponding to the first oxide layer and a second precursor corresponding to a preset metal material during deposition of the first oxide layer.

Preferably, in step 920, the manufacturing method can suppress the occurrence of oxygen vacancies within the first oxide layer by performing a heat treatment process in a state where a metal layer based on a preset metal material is deposited on the first oxide layer.

Specifically, the first oxide layer on which the metal layer is formed can suppress the occurrence of oxygen vacancies within the first oxide layer by changing the metal material constituting the metal layer into an island structure based on metal oxide through a heat treatment process.

According to one aspect, the oxide semiconductor layer further includes a second oxide layer, and a first oxide layer on which a metal layer is formed can be formed on at least one of the upper and lower portions of the second oxide layer.

For example, at step 930, the manufacturing method can be to dissolve tin(II) chloride dihydrate ( _SnCl2 · _2H2O ; Sigma-Aldrich, 99.9%) in 10 mL of ethanol to form a precursor solution (0.025 M) of tin oxide ( _SnO2 ).

In addition, in step 930, the manufacturing method can spin coat the formed precursor solution on the UV/O ₃ treated substrate at 3000 rpm for 50 seconds, and at this time, the substrate can be baked on a hot plate at 150° C. for 10 minutes to evaporate the residual solvent, and thereafter, a heat treatment process can be performed to form at least one of the first oxide layer and the second oxide layer including tin oxide (SnO ₂ ).

For a more specific example, in step 930, the manufacturing method can form a 30 nm thick tin oxide (SnO ₂ ) layer as the first oxide layer by heat treatment at a temperature of 500 °C for 2 hours.

In addition, in step 930, the manufacturing method can form an aluminum (Al) ultra-thin film layer with a thickness of 0.6 nm on at least one of the lower surface and the upper surface of the first oxide layer through ^high vacuum thermal deposition at 5 x 10 -6 Torr, wherein the deposition process is performed for 60 seconds at 0.1 can be performed under the conditions of

In addition, in step 930, the manufacturing method can perform an additional heat treatment process for the first oxide layer on which an aluminum (Al) ultra-thin film layer is formed under a temperature condition of 300 °C for 5 to 40 minutes, thereby forming the first oxide layer on which an island structure based on aluminum oxide (Al ₂ O ₃ ) is formed.

According to one side, in step 930, the manufacturing method may form a first oxide layer having a metal layer formed thereon as a first semiconductor layer, a second oxide layer on top of the first semiconductor layer may be formed as a second semiconductor layer, and the first oxide layer having a metal layer formed thereon as a third semiconductor layer may be formed on top of the second semiconductor layer.

Meanwhile, in step 930, the manufacturing method may form an oxide semiconductor layer through at least one of sol-gel, slit-die, printing, spin-coating, atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, thermal evaporation, and E-beam evaporation, wherein the oxide semiconductor layer may have a concentration of oxygen vacancies controlled depending on process conditions (ambient heat treatment/deposition, temperature, deposition speed, and thickness of the thin film, etc.).

In addition, in the manufacturing method at step 930, in the process of forming an oxide semiconductor layer, the first oxide layer can be formed using two sources (original oxides) and another oxide source for suppressing the formation of oxygen vacancies, and the second oxide layer can be formed using only two sources (original oxides), and through this, the oxide semiconductor layer can be formed with a different vertical profile.

Next, in step 940, the manufacturing method can form an upper electrode on top of the oxide semiconductor layer.

According to one side, in step 940, the manufacturing method can form a first upper electrode and a second upper electrode in a preset region on the upper side of the oxide semiconductor layer.

For example, at step 940, the manufacturing method can form a 50 nm thick gold (Au) layer as the first upper electrode and the second upper electrode based on an e-beam evaporation and lift-off process.

Ultimately, by utilizing the present invention, the electrical stability problem can be solved by minimizing the occurrence of oxygen vacancies.

In addition, by utilizing the present invention, the occurrence of oxygen vacancies only at the interface of the oxide semiconductor layer, which causes electrical stability problems, can be minimized, thereby solving the stability problem while simultaneously maximizing the inherent mobility characteristics.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. The processing device may execute an operating system (OS) and one or more software applications that run on top of the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone, but those skilled in the art will appreciate that the processing device may include multiple processing elements and/or multiple types of processing elements. For example, the processing device may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

Although the embodiments have been described with limited drawings as described above, those skilled in the art will appreciate that various modifications and variations can be made from the above teachings. For example, even if the described techniques are performed in a different order than the described method, and/or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or are replaced or substituted by other components or equivalents, appropriate results can still be achieved.

Therefore, other implementations, other embodiments, and equivalents to the claims are also included in the scope of the claims described below.

100: electronic components 110: substrate
120: Lower electrode 130: Oxide semiconductor layer
130-1, 130-3: First oxide layer 130-2: Second oxide layer
140-1, 140-2: Upper electrode

Claims (13)

A lower electrode formed on the upper part of the substrate;
An oxide semiconductor layer formed on the upper portion of the lower electrode and including a first oxide layer in which the occurrence of oxygen vacancies is suppressed, wherein a metal layer based on a preset metal material is deposited on the first oxide layer and a heat treatment process is performed to suppress the occurrence of oxygen vacancies in the first oxide layer, and the first oxide layer is changed into an island structure based on a metal oxide through the heat treatment process in which the metal material constituting the metal layer is changed into a metal oxide-based island structure to suppress the occurrence of oxygen vacancies in the first oxide layer.
An upper electrode formed on top of the oxide semiconductor layer
An electronic device comprising: In the first paragraph,
The above oxide semiconductor layer is,
A second oxide layer is further included, characterized in that the first oxide layer is formed on at least one of the upper and lower portions of the second oxide layer.
Electronic components. In the first paragraph,
The above oxide semiconductor layer is,
It is characterized in that, when depositing the first oxide layer, a target containing a preset metal material is used for deposition, and then a heat treatment process is performed to suppress the occurrence of oxygen vacancies within the first oxide layer.
Electronic components. In the first paragraph,
The above oxide semiconductor layer is,
It is characterized in that, when depositing the first oxide layer, a solution process and a heat treatment process are performed on a mixture of a first precursor corresponding to the first oxide layer and a second precursor corresponding to a preset metal material, thereby suppressing the occurrence of oxygen vacancies within the first oxide layer.
Electronic components. delete delete In the first paragraph,
The above metal layer,
Characterized in that it is formed on at least one of the upper and lower portions of the first oxide layer with a thickness of 0.3 nm to 0.9 nm.
Electronic components. In the first paragraph,
It is characterized by further including an insulating layer formed between the lower electrode and the oxide semiconductor layer.
Electronic components. In the first paragraph,
The upper electrode is,
characterized by comprising a first upper electrode and a second upper electrode;
Electronic components. A step of forming a lower electrode formed on the upper part of a substrate;
A step of forming an oxide semiconductor layer including a first oxide layer in which the occurrence of oxygen vacancies is suppressed on the upper portion of the lower electrode; and
A step of forming an upper electrode on top of the above oxide semiconductor layer
Including,
The above oxide semiconductor layer is,
A method for manufacturing an electronic device, characterized in that when a heat treatment process is performed while a metal layer based on a preset metal material is deposited on the first oxide layer, the metal material constituting the metal layer changes into an island structure based on a metal oxide, thereby suppressing the occurrence of oxygen vacancies within the first oxide layer. In Article 10,
The above oxide semiconductor layer is,
A second oxide layer is further included, characterized in that the first oxide layer is formed on at least one of the upper and lower portions of the second oxide layer.
Method for manufacturing electronic components. In Article 11,
The step of forming the above oxide semiconductor layer is:
A step of forming the first oxide layer as a first semiconductor layer;
A step of forming the second oxide layer as a second semiconductor layer on top of the first semiconductor layer; and
A step of forming the first oxide layer as a third semiconductor layer on top of the second semiconductor layer.
A method for manufacturing an electronic device, characterized by including a . delete

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