KR102739435B1 - Gate driving circuit and display device including the same - Google Patents

Abstract

A gate driving circuit and a display device including the same are disclosed. A signal transmission unit of the gate driving circuit includes a first control unit which receives an activation clock for a first unit of time and controls a first control node as a pull-up control node to turn on a first transistor, and receives a deactivation clock for a second unit of time and deactivates the first transistor; and a second control unit which receives the activation clock for the second unit of time and controls a second control node as the pull-up control node to turn on a second transistor, and receives the deactivation clock for the first unit of time and deactivates the first transistor.

Description

GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

The present invention relates to a gate driving circuit and a display device including the same.

Electroluminescence displays can be divided into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. An organic light emitting display of the active matrix type includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has the advantages of a fast response speed, large luminous efficiency, brightness, and viewing angle. An organic light emitting display has an OLED (Organic Light Emitting Diode, "OLED") formed in each pixel. An organic light emitting display not only has a fast response speed and excellent luminous efficiency, brightness, and viewing angle, but also has excellent contrast ratio and color reproducibility because it can express black gradation as complete black.

The pixel circuit of the field emission display device includes a light-emitting element, a driving element for driving the light-emitting element, and one or more switching elements. The switching elements are turned on/off according to a gate voltage to connect or disconnect main nodes of the pixel circuit. The driving elements and the switching elements can be implemented as transistors.

The gate driving circuit controls the switch elements by generating a pulse of a gate signal applied to the gate electrode of the switch elements. This gate driving circuit includes a plurality of transistors. The transistor deteriorates rapidly as the driving time elapses due to gate bias stress. In the gate driving circuit, the buffer transistor is subjected to more stress because a relatively high voltage is applied and the driving time is longer than that of other transistors. This is a major cause of lowering the reliability of the gate driving circuit.

The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a gate driving circuit capable of reducing stress on a buffer transistor and a display device including the same.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A gate driving circuit according to one embodiment of the present invention includes a plurality of signal transmission units that receive a start signal and a shift clock and charge and discharge a first control node and a second control node; and first buffers respectively connected to the signal transmission units.

Each of the first buffers includes a first transistor driven in accordance with the voltage of the first control node; and a second transistor driven in accordance with the voltage of the second control node and connected to the first transistor across a first output node from which a gate pulse is output.

The signal transmission unit includes a first control unit that receives an activation clock for a first unit of time and controls the first control node as a pull-up control node to turn on the first transistor, and receives a deactivation clock for a second unit of time and deactivates it; and a second control unit that receives the activation clock for the second unit of time and controls the second control node as the pull-up control node to turn on the second transistor, and receives the deactivation clock for the first unit of time and deactivates it.

Each of the first buffers of the gate driving circuit according to another embodiment of the present invention includes a first-first pull-up transistor driven according to the voltage of the first pull-up control node; a first-second pull-up transistor driven according to the voltage of the second pull-up control node; and a first pull-down transistor driven according to the voltage of the pull-down control node.

The signal transmission unit includes a first Q generation logic unit which receives an activation clock during a first pull-up time, charges the first pull-up control node, and turns on the 1-1st pull-up transistor, and receives a deactivation clock during a second pull-up time and deactivates it; a second Q generation logic unit which receives the activation clock during the second pull-up time, charges the second pull-up control node, and turns on the 1-2nd pull-up transistor, and receives the deactivation clock during the first pull-up time and deactivates it; and a QB generation logic unit which charges the first pull-down control node during a pull-down time in which the first and second pull-up control nodes are discharged, and turns on the pull-down transistor.

The display device of the present invention includes the gate driving circuit.

The present invention enables the implementation of a narrow bezel of a display device by alternately controlling the first and second control nodes as a pull-up control node and a pull-down control node or by alternately activating two pull-up control nodes, and can also reduce the stress on buffer transistors of a gate driving circuit.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

FIG. 1 is a diagram schematically showing a shift register of a gate driving circuit according to one embodiment of the present invention.
FIG. 2 is a waveform diagram showing a shift clock, gate pulse, and carry signal input to the shift register illustrated in FIG. 1.
Figure 3 is a drawing showing an example of a gate driving circuit arranged on both sides of a display panel.
FIGS. 4A and 4B are drawings showing a driving method of a gate driving circuit according to a first embodiment of the present invention.
Figure 5 is a circuit diagram showing in detail the signal transmission unit and buffer illustrated in Figures 4a and 4b.
Figures 6a and 6b are waveform diagrams showing input/output signals and voltages of major nodes of the circuit illustrated in Figure 5.
FIGS. 7A and 7B are circuit diagrams showing the operation of the first unit time and the second unit time in the circuit illustrated in FIG. 5.
Fig. 8 is a simulation waveform in which the signals shown in Figs. 6a and 6b are input to the circuit shown in Fig. 5.
FIGS. 9A and 9B are drawings showing a driving method of a gate driving circuit according to a second embodiment of the present invention.
FIGS. 10A and 10B are circuit diagrams showing the operation of the first pull-up time and the second pull-up time in the circuits illustrated in FIGS. 9A and 9B.
FIG. 11 is a block diagram showing a display device according to one embodiment of the present invention.
Fig. 12 is a cross-sectional view showing the cross-sectional structure of the display panel illustrated in Fig. 11.
FIG. 13 is a circuit diagram showing a pixel circuit according to one embodiment of the present invention.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated in the drawings. The same reference numerals throughout the specification refer to substantially the same components. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the specification, when “comprises,” “includes,” “has,” and “consists of,” other parts may be added unless “only” is used. When a component is expressed in the singular, it may be interpreted as plural unless otherwise explicitly stated.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when a positional relationship is described between two components as 'on', 'above', 'below', 'next to', etc., one or more other components may intervene between those components for which 'directly' or 'directly' is not used.

Although the terms 1st, 2nd, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and may be technically capable of various interconnections and operations. Each embodiment may be implemented independently of each other, or may be implemented together in a related relationship.

Each pixel is divided into multiple sub-pixels with different colors for color implementation, and each sub-pixel includes a transistor used as a switching element or a driving element. This transistor can be implemented as a TFT (Thin Film Transistor).

The driving circuit of the display device writes pixel data of an input image into pixels. The driving circuit of the flat panel display device includes a data driving circuit that supplies data signals to data lines, a gate driving circuit that supplies gate signals to gate lines, and the like.

In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistor may be implemented as a TFT having a MOSFET (Metal-Oxide-Semiconductor FET) structure, and may be an Oxide TFT including an oxide semiconductor or an LTPS TFT including low temperature poly silicon (LTPS). Hereinafter, the transistors constituting the pixel circuit and the gate driving circuit will be described based on an example implemented as an n-channel Oxide TFT implemented as an Oxide TFT, but the present invention is not limited thereto.

A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode from which carriers exit the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the invention is not limited by the source and drain of a transistor. In the following description, the source and drain of the transistor are referred to as the first and second electrodes.

The gate signal can swing between the Gate On Voltage and the Gate Off Voltage. The Gate On Voltage is set to a voltage higher than the threshold voltage of the transistor. The Gate Off Voltage is set to a voltage lower than the threshold voltage of the transistor.

A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. For an n-channel transistor, the gate-on voltage can be a gate high voltage (VGH and VEH), and the gate-off voltage can be a gate low voltage (VGL and VEH).

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the embodiments below, the display device is described with a focus on an organic light-emitting display device, but the present invention is not limited thereto.

Referring to FIGS. 1 and 2, the gate driving circuit includes a shift register that sequentially outputs pulses of gate signals (hereinafter, “gate pulses”) [Gout(n-1) to Gout(n+2)] in synchronization with a shift clock (CLK).

The shift register includes dependently connected signal transmission units [ST(n-1) to ST(n+2)]. Each of the signal transmission units [ST(n-1) to ST(n+2)] includes a VST node to which a start signal (VST) is input, a CLK node to which shift clocks (CLK1 to 4) are input, first and second control nodes for alternately driving buffer transistors (TR1, TR2), etc.

The start signal (VST) is generally input to the first signal transmission unit. In Fig. 1, the n-1th signal transmission unit [ST(n-1)] may be the first signal transmission unit that receives the start signal (VST). The shift clocks (CLK1 to 4) may be k (k is a natural number) phase clocks, but are not limited thereto.

The signal transmission units [ST(n) to ST(n+2)] dependently connected to the n-1 signal transmission unit [ST(n-1)] are started to be driven by receiving a carry signal (CAR) from the previous signal transmission unit as a start signal. Each of the signal transmission units [ST(n-1) to ST(n+2)] can output a gate pulse [Gout(n-1) to Gout(n+2)] through the first output node and simultaneously output a carry signal (CAR) through the second output node.

The buffer (BUF) illustrated in Fig. 1 is a buffer connected to a first output node from which a gate pulse is output. The buffer (BUF) includes a first transistor (TR1) and a second transistor (TR2) connected to the first output node and outputs a gate pulse [Gout(n-1) to Gout(n+2)] through the first output node. The first output node is connected to gate lines of a display panel on which an input image is reproduced.

In at least one of the buffers (BUF), the first and second transistors (TR1, TR2) alternately operate as pull-up transistors at predetermined time intervals to supply a gate driving voltage (GVDD) to a first output node to rise a voltage of the first output node. The first and second transistors (TR1, TR2) alternately operate as pull-down transistors at predetermined time intervals to discharge the first output node to cause a gate pulse [Gout(n-1) to Gout(n+2)] to fall. The gate driving voltage (GVDD) may be a voltage higher than the gate reference voltage (GVSS). The gate driving voltage (GVDD) may be set as a gate-on voltage, and the gate reference voltage (GVSS) may be set as a gate-off voltage.

The given time can be a frame period of j (where j is a natural number), or a unit time set in seconds [sec].

In at least one of the buffers (BUF), the first and second transistors (TR1, TR2) alternately operate as pull-up transistors at a predetermined time cycle. When one of the first and second transistors (TR1, TR2) operates as a pull-up transistor, the other operates as a pull-down transistor to output a gate pulse through the first output node.

Each of the signal transmission units [ST(n-1) to ST(n+2)] alternately charges and discharges the first control node controlling the first transistor (TR1) and the second control node controlling the second transistor (TR2) at a predetermined time cycle.

The first transistor (TR1) may be driven as a pull-up transistor during an odd-numbered unit time, and as a pull-down transistor during an even-numbered unit time. The second transistor (TR2) may be driven as a pull-up transistor during an even-numbered unit time, and as a pull-down transistor during an odd-numbered unit time. Hereinafter, the first unit time may be interpreted as an odd-numbered unit time, and the second unit time may be interpreted as an even-numbered unit time.

FIG. 3 is a drawing showing an example in which a shift register of a gate driving circuit is mounted on a display panel on which an input image is reproduced. The gate driving circuit may include a first gate driving unit formed in a left bezel area of the display panel and a second gate driving unit formed in a right bezel area. The first gate driving unit and the second gate driving unit may be separated to both sides with a pixel array (AA) of a screen on which an input image is displayed interposed therebetween. Each of the first and second gate driving units includes a shift register as in FIG. 1. In order to reduce the bezel area of the display panel, at least some of the circuit components of the first and second gate driving units may be arranged on the pixel array (AA).

The gate pulses [Gout(n-1) to Gout(n+2)] sequentially output through the shift register of the gate driving circuit may be scan pulses (or scan pulses) and emission control pulses (hereinafter, “EM pulses”).

The present invention can reduce the stress of transistors (TR1, TR2) connected to one signal transmission unit by alternately driving the transistors (TR1, TR2) at a predetermined time cycle. In another embodiment, the present invention can reduce the stress of a plurality of transistors connected to one signal transmission unit by alternately driving the transistors.

A buffer (BUF) connected to at least one of the signal transmission units [ST(n-1) to ST(n+2)] can be driven as shown in FIG. 4a and FIG. 4b.

FIGS. 4A and 4B are drawings showing a method of driving buffer transistors (TR1, TR2) according to the first embodiment of the present invention.

The first transistor (TR1) is driven as a pull-up transistor for a first unit time and then as a pull-down transistor for a second unit time. As illustrated in FIG. 4a, the transistor (TR1) operates as a first pull-up transistor in response to the voltage of the first control node (Q/QB) controlled by the pull-up control node [Q(n)] for the first unit time. At this time, the gate drive voltage (GVDD) is applied to the first power node and the gate reference voltage (GVSS) is applied to the second power node. The second control node (QB/Q) is controlled by the pull-down control node [QB(n)] for the first unit time to operate the second transistor (TR2) as a pull-down transistor.

The second transistor (TR2) is driven alternately with the first transistor (TR1). For example, the second transistor (TR2) operates as a pull-down transistor according to the second control node (QB/Q) controlled by the pull-down control node [QB(n)] for a first unit of time, and then operates as a pull-up transistor in response to the voltage of the second control node (QB/Q) controlled by the pull-up control node [Q(n)] for a second unit of time. Accordingly, the first and second transistors (TR1, TR2) are driven alternately as pull-up transistors at a predetermined interval, so that stress is distributed.

As illustrated in FIG. 4B, during the second unit time when the second control node (QB/Q) is controlled by the pull-up control node [Q(n)], the second transistor (TR2) operates as a pull-up transistor. At this time, the gate driving voltage (GVDD) is applied to the second power node, and the gate reference voltage (GVSS) is applied to the first power node. During the second unit time when the second control node (QB/Q) is the pull-up control node [Q(n)], the first control node (Q/QB) is controlled by the pull-down control node [QB(n)] to operate the first transistor (TR1) as a pull-down transistor.

The signal transmission unit [ST(n)] includes a first control unit (CTR1) that controls the voltage of the first control node (Q/QB) and a second control unit (CTR2) that controls the voltage of the second control node (Q/QB). The first control unit (CTR1) controls the first transistor (TR1) as a pull-up transistor by charging the first control node (Q/QB) during a first unit time when an activation clock is input, and is deactivated during a second unit time when a deactivation clock is input. The second control unit (CTR2) controls the second transistor (TR2) as a pull-up transistor by charging the second control node (QB/Q) during a second unit time when an activation clock is input, and is deactivated during the first unit time when a deactivation clock is input. In Fig. 1, one of the two shift clocks input to the signal transmission unit may be an activation clock and the other may be a deactivation clock.

The activation clock includes a plurality of pulses that swing between a high voltage and a low voltage during a unit time. The deactivation clock can maintain a low voltage during a unit time. The pulse voltage of the activation clock, i.e., the high voltage, can be set as a gate-on voltage. The low voltage can be set as a gate-off voltage.

The first transistor (TR1) operates as a pull-up transistor during a first unit time when the first control node (Q/QB) is a pull-up control node [Q(n)]. During the first unit time, the second control node (QB/Q) can be controlled as a pull-down control node [QB(n)] by the first control section (CTR1). During the first unit time, the second control node (QB/Q) is maintained at the gate reference voltage (GVSS). At this time, the second transistor (TR2) operates as a pull-down transistor.

The second transistor (TR2) operates as a pull-up transistor during a second unit time when the second control node (Q/QB) is a pull-up control node [Q(n)]. During the second unit time, the first control node (Q/QB) can be controlled as a pull-down control node [QB(n)] by the second control unit (CTR2). During the second unit time, the first control node (Q/QB) is maintained at the gate reference voltage (GVSS). At this time, the second transistor (TR2) operates as a pull-down transistor.

FIG. 5 is a circuit diagram showing in detail the signal transmission unit [ST(n)] and the buffer (BUF) illustrated in FIGS. 4a and 4b. The embodiment illustrated in FIG. 5 exemplifies the circuit of the nth signal transmission unit [ST(n)] that outputs an EM pulse and the buffer (BUF) connected thereto, but the present invention is not limited thereto. For example, if a circuit substantially identical to the circuit illustrated in FIG. 5 is used and a clock matching the scan pulse is used as the shift clock, the scan pulse can be generated. Signal transmission units other than the nth signal transmission unit [ST(n)] can also be implemented with a circuit substantially identical to the nth stage (ST(n)). All of the transistors constituting the shift register can be implemented with n-channel oxide TFTs.

FIGS. 6A and 6B are waveform diagrams showing input/output signals and voltages of major nodes of the circuit illustrated in FIG. 5. FIG. 6A shows first and second control node voltages charged and discharged by a first control unit (CTR1) activated for a first unit time. FIG. 6B shows first and second control node voltages charged and discharged by a second control unit (CTR2) activated for a second unit time. In FIGS. 6A and 6B, 'VDD' is a high voltage, and 'VSS' is a low voltage. FIGS. 7A and 7B are circuit diagrams showing operations of the first unit time and the second unit time in the circuit illustrated in FIG. 5. Fig. 7a shows a current flow in which a first control node (Q/QB) is controlled as a pull-up control node [Q(n)] by a first control unit (CTR1) that is activated for a first unit of time, and a second control node (QB/Q) is controlled as a pull-down control node [QB(n)]. Fig. 7b shows a current flow in which a second control node (QB/Q) is controlled as a pull-up control node [Q(n)] by a second control unit (CTR2) that is activated for a second unit of time, and a first control node (Q/QB) is controlled as a pull-down control node [QB(n)].

Referring to FIGS. 5 to 7b, the nth signal transmission unit [ST(n)] includes a first control unit (CTR1) and a second control unit (CTR2) and is connected to first and second buffers (BUF1, BUF2).

In Fig. 5, the gate driving voltages (GVDD1, GVDD2) can be set to different voltages, but are not limited thereto. The gate reference voltages (GVSS, GVSS0, GVSS2) can be set to different voltages, but are not limited thereto.

The first buffer (BUF1) charges and discharges the first output node according to the voltages of the first and second control nodes (Q/QB, QB/Q) to output an EM pulse [EMOUT(n)]. The first buffer (BUF1) includes first and second transistors (TR1, TR2). The first transistor (TR1) includes a gate electrode connected to the first control node (Q/QB), a first electrode connected to the first power node, and a second electrode connected to the first output node. The second transistor (TR2) is connected to the first transistor (TR1) across the first output node. The second transistor (TR2) includes a gate electrode connected to the second control node (QB/Q), a first electrode connected to the first output node, and a second electrode connected to the second power node. A voltage applied to each of the first power node and the second power node is switched between a gate driving voltage (GVDD2) and a gate reference voltage (GVSS0). For example, after the gate driving voltage (GVDD2) is applied to the first power node for a first unit time, the gate reference voltage (GVSS0) may be applied for a second unit time. Conversely, after the gate reference voltage (GVSS0) is applied to the second power node for the first unit time, the gate driving voltage (GVDD2) may be applied for a second unit time.

A third capacitor (C3) may be connected between the gate electrode and the second electrode of the first transistor (TR1). A fourth capacitor (C4) may be connected between the gate electrode and the first electrode of the second transistor (TR2).

The second buffer (BUF2) charges and discharges the second output node according to the voltages of the first and second control nodes (Q/QB, QB/Q) to output a carry pulse [CAR(n)]. The second buffer (BUF2) includes third and fourth transistors (TR3, TR4). The third transistor (TR3) includes a gate electrode connected to the first control node (Q/QB), a first electrode connected to a third power node, and a second electrode connected to the second output node. The fourth transistor (TR4) is connected to the third transistor (TR3) across the second output node. The fourth transistor (TR4) includes a gate electrode connected to the second control node (QB/Q), a first electrode connected to the second output node, and a second electrode connected to the fourth power node. A voltage applied to each of the third power node and the fourth power node is switched between a gate driving voltage (GVDD1) and a gate reference voltage (GVSS2). For example, after the gate driving voltage (GVDD1) is applied to the third power node for a first unit time, the gate reference voltage (GVSS2) may be applied for a second unit time. Conversely, after the gate reference voltage (GVSS2) is applied to the fourth power node for a first unit time, the gate driving voltage (GVDD1) may be applied for a second unit time.

A power voltage applied to the first and second transistors in at least one of the first buffers (BUF1) may be periodically switched. A power voltage applied to the third and fourth transistors in at least one of the second buffers (BUF2) may be periodically switched.

The first control unit (CTR1) includes a first Q generation logic unit (QG1) and a first QB generation logic unit (QBG1).

The first Q generation logic unit (QG1) controls the first control node (Q/QB) as a pull-up control node [Q(n)] by charging the first control node (Q/QB) by inputting an activation clock (ECLK) to the first CLK node for a first unit time as illustrated in FIGS. 6A and 7A, and controls the second control node (QB/Q) as a pull-down control node [QB(n)]. The first Q generation logic unit (QG1) is deactivated during the second unit time when an deactivation clock (ECLKB) is input to the first CLK node.

The first Q generation logic unit (QG1) may include fifth to eighth transistors (T5 to T8).

The fifth transistor (T5) is turned on during a first unit time when an activation clock (ECLK) is input to the first CLK node to connect the carry signal node to the first buffer node (Qh). A carry pulse [CAR(n-1)] is applied to the carry signal node. The carry pulse [CAR(n-1)] is output from a second output node of a previous signal transmission unit, for example, an n-1th signal transmission unit [ST(n-1)]. The fifth transistor (T5) includes a gate electrode connected to the first CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the first buffer node (Qh). An inactivation clock (ECLKB) is input to the first CLK node during a second pull-up time.

The sixth transistor (T6) is turned on during the first unit time when an activation clock (ECLK) is input to the first CLK node to connect the first buffer node (Qh) to the first control node (Q/QB). The sixth transistor (T6) includes a gate electrode connected to the first CLK node, a first electrode connected to the first buffer node (Qh), and a second electrode connected to the first control node (Q/QB).

The fifth and sixth transistors (T5, T6) are turned on according to the high voltage (VDD) of the activation clock (ECLK) during the first unit time when the activation clock (ECLK) is applied to the first CLK node, thereby charging the first buffer node (Qh) and the first control node (Q/QB). At this time, the first control node (Q/QB) is a pull-up control node [Q(n)]. The fifth and sixth transistors (T5, T6) maintain an off state during the second unit time when the deactivation clock (ECLKB) is input to the first CLK node.

The seventh transistor (T7) is turned on when the first control node (Q/QB) is charged to a high voltage (VDD) to connect the fifth power node to the first buffer node (Qh) to charge and discharge the first buffer node (Qh). As illustrated in FIG. 7a, a gate driving voltage (GVDD1) is applied to the fifth power node for a first unit time, and as illustrated in FIG. 7b, a gate reference voltage (GVSS0) is applied to the fifth power node for a second unit time. The seventh transistor (T7) includes a gate electrode connected to the first control node (Q/QB), a first electrode connected to the fifth power node, and a second electrode connected to the first buffer node (Qh).

The eighth transistor (T8) is turned on when the voltage of the second buffer node (QhB) is a high voltage (VDD) to connect the sixth power node to the first control node (Q/QB) to discharge the first control node (Q/QB). A gate reference voltage (GVSS2) is applied to the sixth power node. The eighth transistor (T8) includes a gate electrode connected to the second buffer node (QhB), a first electrode connected to the sixth power node, and a second electrode connected to the first control node (Q/QB).

The first QB generation logic unit (QBG1) controls the second control node (QB/Q) to a pull-down control node [QB(n)] by charging the second control node (QB/Q) when the first control node (Q/QB) is discharged to a low voltage for the first unit time as illustrated in FIGS. 6A and 7A.

The first QB generation logic unit (QBG1) may include ninth to eleventh transistors (T9, T10, T11).

The ninth transistor (T9) is turned on when the voltage of the second control node (QB/Q) of the previous stage signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)], is a high voltage (VDD), and connects the seventh power node to the gate electrode of the eleventh transistor (T11). As illustrated in FIG. 7A, a gate driving voltage (GVDD1) is applied to the seventh power node for a first unit time, and as illustrated in FIG. 7B, a gate reference voltage (GVSS) is applied to the seventh power node for a second unit time. The ninth transistor (T9) includes a gate electrode connected to the second control node (QB/Q) of the previous stage signal transmission unit, a first electrode connected to the seventh power node, and a second electrode connected to the gate electrode of the eleventh transistor (T11).

The tenth transistor (T10) is turned on when the voltage of the first buffer node (Qh) is a high voltage (VDD) to connect the gate electrode of the eleventh transistor (T11) to the tenth power node. A gate reference voltage (GVSS1) is applied to the tenth power node. The tenth transistor (T10) includes a gate electrode connected to the first buffer node (Qh), a first electrode connected to the gate electrode of the eleventh transistor (T11), and a second electrode connected to the tenth power node.

The eleventh transistor (T11) is turned on when the gate voltage is a high voltage (VDD) to connect the eleventh power node to the second control node (QB/Q). A gate driving voltage (GVDD1) is applied to the eleventh power node. The eleventh transistor (T11) includes a gate electrode connected to the second electrode of the ninth transistor (T9) and the first electrode of the tenth transistor (T10), a first electrode connected to the eleventh power node, and a second electrode connected to the second control node (QB/Q). A first capacitor (C1) may be connected between the gate electrode and the second electrode of the eleventh transistor (T11).

The second control unit (CTR2) includes a second Q generation logic unit (QG2) and a second QB generation logic unit (QBG2).

The second Q generation logic unit (QG2) controls the second control node (QB/Q) as a pull-up control node [Q(n)] and controls the first control node (Q/QB) as a pull-down control node [QB(n)] by charging the second control node (QB/Q) during the second unit time when the activation clock (ECLK) is input to the second CLK node, as illustrated in FIGS. 6b and 7b. The second Q generation logic unit (QG2) is deactivated during the second unit time when the deactivation clock (ECLKB) is input to the second CLK node.

The second Q generation logic unit (QG2) may include twelfth to fifteenth transistors (T12 to T15).

The twelfth transistor (T12) is turned on during the second unit time when the activation clock (ECLK) is input to the second CLK node to connect the carry signal node to the second buffer node (QhB). A carry pulse [CAR(n-1)] is applied to the carry signal node. The carry pulse [CAR(n-1)] is output from the second output node of a previous signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)]. The twelfth transistor (T12) includes a gate electrode connected to the second CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node (QhB).

The thirteenth transistor (T13) is turned on for a second unit time during which an activation clock (ECLK) is input to the second CLK node to connect the second buffer node (QhB) to the second control node (QB/Q). The thirteenth transistor (T13) includes a gate electrode connected to the second CLK node, a first electrode connected to the second buffer node (QhB), and a second electrode connected to the second control node (QB/Q).

The twelfth and thirteenth transistors (T12, T13) are turned on according to the high voltage (VDD) of the activation clock (ECLK) during the second unit time when the activation clock (ECLK) is applied to the second CLK node, thereby charging the second buffer node (QhB) and the second control node (QB/Q). At this time, the second control node (QB/Q) is a pull-up control node [Q(n)]. The twelfth and thirteenth transistors (T12, T13) maintain an off state during the first unit time when the deactivation clock (ECLKB) is input to the second CLK node.

The fourteenth transistor (T14) is turned on when the second control node (QB/Q) is charged to the high voltage (VDD) to connect the twelfth power node to the second buffer node (QhB) to charge and discharge the second buffer node (QhB). The twelfth power node is applied with a gate driving voltage (GVDD1) for a second unit time as illustrated in FIG. 7B, and is applied with a gate reference voltage (GVSS0) for a first unit time as illustrated in FIG. 7A. The fourteenth transistor (T14) includes a gate electrode connected to the second control node (QB/Q), a first electrode connected to the twelfth power node, and a second electrode connected to the second buffer node (QhB).

The fifteenth transistor (T15) is turned on when the voltage of the first buffer node (Qh) is a high voltage (VDD) to connect the sixth power node to the second control node (QB/Q) to discharge the second control node (QB/Q). A gate reference voltage (GVSS2) is applied to the sixth power node. The fifteenth transistor (T15) includes a gate electrode connected to the first buffer node (Qh), a first electrode connected to the sixth power node, and a second electrode connected to the second control node (QB/Q).

The second QB generation logic unit (QBG2) controls the first control node (Q/QB) to the pull-down control node [QB(n)] by charging the first control node (Q/QB) when the second control node (QB/Q) is discharged to the low voltage (VSS) for the second unit time as illustrated in FIGS. 6b and 7b.

The second QB generation logic unit (QBG2) may include sixteenth to eighteenth transistors (T16, T17, T18).

The 16th transistor (T16) is turned on when the voltage of the first control node (Q/QB) of the previous stage signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)], is a high voltage (VDD) to connect the 13th power node to the gate electrode of the 18th transistor (T18). The 13th power node is applied with a gate reference voltage (GVSS) for a first unit time as illustrated in FIG. 7A, and with a gate driving voltage (GVDD1) for a second unit time as illustrated in FIG. 7B. The 13th transistor (T13) includes a gate electrode connected to the first control node (Q/QB) of the previous stage signal transmission unit, a first electrode connected to the 13th power node, and a second electrode connected to the gate electrode of the 18th transistor (T18).

The 17th transistor (T17) is turned on when the voltage of the second buffer node (QhB) is a high voltage (VDD) to connect the gate electrode of the 18th transistor (T18) to the 10th power node. A gate reference voltage (GVSS1) is applied to the 10th power node. The 17th transistor (T17) includes a gate electrode connected to the second buffer node (QhB), a first electrode connected to the gate electrode of the 18th transistor (T11), and a second electrode connected to the 10th power node.

The eighteenth transistor (T18) is turned on when the gate voltage is a high voltage (VDD) to connect the eleventh power node to the first control node (Q/QB). A gate driving voltage (GVDD1) is applied to the eleventh power node. The eighteenth transistor (T18) includes a gate electrode connected to the second electrode of the sixteenth transistor (T16) and the first electrode of the seventeenth transistor (T17), a first electrode connected to the eleventh power node, and a second electrode connected to the first control node (Q/QB). A second capacitor (C2) may be connected between the gate electrode and the second electrode of the eighteenth transistor (T18).

Fig. 8 is a simulation waveform in which the signals shown in Figs. 6a and 6b are input to the circuit shown in Fig. 5. In Fig. 8, 'Q' is a waveform of a pull-up control node, which is the voltage of the first control node (Q/QB) for the first unit time and the voltage of the second control node (QB/Q) for the second unit time. In Fig. 8, 'QB' is a waveform of a pull-down control node, which is the voltage of the second control node (QB/Q) for the first unit time and the voltage of the first control node (Q/QB) for the second unit time.

Another embodiment of the gate driving circuit can distribute the stress of the pull-up transistors by alternately driving two pull-up transistors as illustrated in FIGS. 9A and 10B. This embodiment can be applied to at least one of the first and second Q generation units described above and a buffer connected to the Q generation unit, or can be applied alone. For example, the present invention can configure the Q generation logic unit of at least one of the first and second control units (CTR1, CTR2) in the gate driving circuit illustrated in FIGS. 4A to 5 as the first and second Q generation logic units illustrated in FIGS. 10A and 10B. In this case, each of the buffer transistors can include two transistors that are alternately driven. One unit time is divided into first and second pull-up times, and the first Q generation logic unit can drive one of the two pull-up transistors during the first pull-up time, and the second Q generation logic unit can drive the other pull-up transistor during the second pull-up time.

FIGS. 9A and 9B are diagrams showing a driving method of buffer transistors according to a second embodiment of the present invention. In FIG. 9, gate driving voltages (GVDD, GVDD1, GVDD2) may be set to different voltages, but are not limited thereto. Gate reference voltages (GVSS0, GVSS1, GVSS2) may be set to different voltages, but are not limited thereto. FIGS. 10A and 10B are circuit diagrams showing the operation of the first pull-up time and the second pull-up time in the circuits shown in FIGS. 9A and 9B.

Referring to FIGS. 9a to 10b, the nth signal transmission unit [ST(n)] includes a first Q generation logic unit (QG11), a second Q generation logic unit (QG12), and a QB generation logic unit (QGB).

The first Q generation logic unit (QG11) charges the first pull-up control node [Q1(n)] during the first pull-up time when the activation clock (ECLK) is input to drive the 1-1st pull-up transistor (TR11) of the first buffer (BUF1). The first Q generation logic unit (QG11) can further drive the 3-1st pull-up transistor (TR31) of the second buffer (BUF2) during the first pull-up time as illustrated in FIG. 10a. The first Q generation logic unit (QG11) can be deactivated by inputting the deactivation clock (ECLK) during the second pull-up time as illustrated in FIG. 10b.

The second Q generation logic unit (QG12) is activated alternately with the first Q generation logic unit (QG11) to charge the second pull-up control node [Q2(n)] and drive the first-second pull-up transistor (TR11). The second Q generation logic unit (QG12) drives the first-second pull-up transistor (TR12) of the first buffer (BUF1) during the second pull-up time to which the activation clock (ECLK) is input, as illustrated in FIG. 10a. The second Q generation logic unit (QG12) can further drive the third-second pull-up transistor (TR32) of the second buffer (BUF2) during the second pull-up time. The second Q generation logic unit (QG12) can be deactivated by inputting the deactivation clock (ECLK) during the first pull-up time, as illustrated in FIG. 10a.

The enable clock (ECLK) contains multiple pulses that swing between high and low voltages during a unit of time. The disable clock (ECLKB) remains low during a unit of time.

The QB generation logic unit (QGB) charges the pull-down control node [QB(n)] during the pull-down time when the first and second pull-up control nodes [Q1(n), Q2(n)] are discharged, thereby driving the pull-down transistors (TR20, TR40). The QB generation logic unit (QGB) can drive the pull-down transistors (TR20, TR40) of the first buffer (BUF) in response to the pull-up control node voltage of a previous signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)].

The first buffer (BUF1) charges and discharges the first output node to output an EM pulse [EMOUT(n)]. The first buffer (BUF1) includes first-first and first-second pull-up transistors (TR11, TR12) alternately driven by first and second Q generation logic units (QG11, QG12), and a first pull-down transistor (TR20) driven by a QB generation logic unit (QGB).

The first-first pull-up transistor (TR11) includes a gate electrode connected to a first pull-up control node [Q1(n)], a first electrode connected to a first power node, and a second electrode connected to a first output node. The first-second pull-up transistor (TR12) includes a gate electrode connected to a second pull-up control node [Q2(n)], a first electrode connected to the first power node, and a second electrode connected to the first output node. A gate driving voltage (GVDD2) is applied to the first power node. The second capacitor (C6) may be connected between the gate electrode and the second electrode of the first-first pull-up transistor (TR11). The third capacitor (C7) may be connected between the gate electrode and the second electrode of the first-second pull-up transistor (TR12).

The first pull-down transistor (TR20) is connected to the first-first and first-second pull-up transistors (TR11, TR12) with the first output node interposed therebetween. The first pull-down transistor (TR20) includes a gate electrode connected to the pull-down control node (QB), a first electrode connected to the first output node, and a second electrode connected to a second power node. A gate reference voltage (GVSS0) is applied to the second power node.

The second buffer (BUF2) charges and discharges the second output node to output a carry pulse [CAR(n)]. The second buffer (BUF2) includes 3-1 and 3-2 pull-up transistors (TR31, TR32) alternately driven by the first and second Q generation logic units (QG11, QG12), and a second pull-down transistor (TR40) driven by the QB generation logic unit (QGB).

The third-first pull-up transistor (TR31) includes a gate electrode connected to the first pull-up control node [Q1(n)], a first electrode connected to the first power node, and a second electrode connected to the second output node. The third-second pull-up transistor (TR32) includes a gate electrode connected to the second pull-up control node [Q2(n)], a first electrode connected to the first power node, and a second electrode connected to the second output node.

The second pull-down transistor (TR40) is connected to the 3-1 and 3-2 pull-up transistors (TR31, TR32) with the second output node interposed therebetween. The second pull-down transistor (TR40) includes a gate electrode connected to the pull-down control node (QB), a first electrode connected to the second output node, and a second electrode connected to the second power node.

The first Q generation logic unit (QG11) may include fourth to sixth transistors (T25 to T27) as illustrated in FIGS. 10A and 10B. The first Q generation logic unit (QG11) further includes a seventh transistor (Q28) shared with the second Q generation logic unit (QG12).

The fourth transistor (T25) is turned on during a first pull-up time when an activation clock (ECLK) is input to the first CLK node to connect the carry signal node to the first buffer node (Qh1). A carry pulse [CAR(n-1)] from a previous signal transmission unit is applied to the carry signal node. The carry pulse [CAR(n-1)] can be output from a second output node of the previous signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)]. The fourth transistor (T25) includes a gate electrode connected to the first CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the first buffer node (Qh1). An inactivation clock (ECLKB) is input to the first CLK node during the second pull-up time.

The fifth transistor (T26) is turned on during the first pull-up time when the activation clock (ECLK) is input to the first CLK node to connect the first buffer node (Qh1) to the first pull-up control node [Q1(n)]. The fifth transistor (T26) includes a gate electrode connected to the first CLK node, a first electrode connected to the first buffer node (Qh1), and a second electrode connected to the first pull-up control node [Q1(n)].

The fourth and fifth transistors (T25, T26) are turned on according to the high voltage of the activation clock (ECLK) during the first pull-up time when the activation clock (ECLK) is applied to the first CLK node, thereby charging the first buffer node (Qh1) and the first pull-up control node [Q1(n)]. The fourth and fifth transistors (T25, T26T) are maintained in an off state during the second pull-up time when the deactivation clock (ECLKB) is input to the first CLK node, and during the pull-down time.

The sixth transistor (T27) is turned on when the first pull-up control node [Q1(n)] is charged to a high voltage to connect the third power node to the first buffer node (Qh1) to charge the first buffer node (Qh1). A gate driving voltage (GVDD) is applied to the third power node. The sixth transistor (T27) includes a gate electrode connected to the first pull-up control node [Q1(n)], a first electrode connected to the third power node, and a second electrode connected to the first buffer node (Qh1).

The seventh transistor (T28) is turned on when the voltage of the first buffer node (Qh1) or the second buffer node (Qh2) is a high voltage to connect the pull-down control node [QB(n)] to the fourth power node to discharge the pull-down control node [QB(n)]. A gate reference voltage (GVSS2) is applied to the fourth power node. The seventh transistor (T28) includes a gate electrode connected to the first and second buffer nodes (Qh1, Qh2), a first electrode connected to the pull-down control node [QB(n)], and a second electrode connected to the fourth power node.

The second Q generation logic unit (QG12) may include eighth to tenth transistors (T29 to T31) as illustrated in FIGS. 10a and 10b.

The eighth transistor (T29) is turned on during a second pull-up time when an activation clock (ECLK) is input to the second CLK node to connect the carry signal node to the first buffer node (Qh1). A carry pulse [CAR(n-1)] from a previous stage signal transmission section is applied to the carry signal node. The eighth transistor (T29) includes a gate electrode connected to the third CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node (Qh2). An inactivation clock (ECLKB) is input to the second CLK node during the first pull-up time.

The ninth transistor (T30) is turned on during the second pull-up time when the activation clock (ECLK) is input to the second CLK node to connect the second buffer node (Qh2) to the second pull-up control node [Q2(n)]. The ninth transistor (T30) includes a gate electrode connected to the second CLK node, a first electrode connected to the second buffer node (Qh2), and a second electrode connected to the second pull-up control node [Q2(n)].

The eighth and ninth transistors (T29, T30) are turned on according to the high voltage of the activation clock (ECLK) during the second pull-up time when the activation clock (ECLK) is applied to the second CLK node, thereby charging the second buffer node (Qh2) and the second pull-up control node [Q2(n)]. The eighth and ninth transistors (T29, T30) are maintained in an off state during the first pull-up time when the deactivation clock (ECLKB) is input to the second CLK node, and during the pull-down time.

The tenth transistor (T31) is turned on when the second pull-up control node [Q2(n)] is charged to a high voltage to connect the third power node to the second buffer node (Qh2) to charge the second buffer node (Qh2). A gate driving voltage (GVDD) is applied to the third power node. The tenth transistor (T31) includes a gate electrode connected to the second pull-up control node [Q2(n)], a first electrode connected to the third power node, and a second electrode connected to the second buffer node (Qh2).

Pull-up transistors (TR11, TR12, TR31, TR32) are turned on in response to the voltages of the first and second pull-up control nodes [Q1(n), Q2(n)], which are alternately charged during the first and second pull-up times, to charge the output nodes.

The QB generation logic section (QBG) charges the pull-down control node [QB(n)] when the pull-down time is reached. The pull-down transistors (TR20, TR40) are turned on when the pull-down control node [QB(n)] is charged to a high voltage, thereby discharging the output nodes to the gate reference voltage (GVSS0, GVSS2).

The QB generation logic unit (QBG) may include eleventh to fourteenth transistors (T32 to T35).

The eleventh transistor (T32) is turned on when the voltage of the pull-down control node [QB(n-1)] of the previous stage signal transmission unit, for example, the n-1th signal transmission unit [ST(n-1)], is a high voltage, that is, at the pull-down time, to connect the fifth power node to the gate electrode of the fourteenth transistor (T35). A gate driving voltage (GVDD1) is applied to the fifth power node. The eleventh transistor (T32) includes a gate electrode connected to the pull-down control node [QB(n-1)] of the previous stage signal transmission unit, a first electrode connected to the fifth power node, and a second electrode connected to the gate electrode of the fourteenth transistor (T35).

The 12th transistor (T33) is turned on when the voltage of the first buffer node (Qh1) is a high voltage, that is, at the first pull-up time, to connect the gate electrode of the 14th transistor (T35) to the sixth power node. A gate reference voltage (GVSS1) is applied to the sixth power node. The 12th transistor (T33) includes a gate electrode connected to the first buffer node (Qh1), a first electrode connected to the gate electrode of the 14th transistor (T35), and a second electrode connected to the sixth power node.

The 13th transistor (T34) is turned on when the voltage of the second buffer node (Qh2) is a high voltage, that is, at the second pull-up time, to connect the gate electrode of the 14th transistor (T35) to the sixth power node. The 13th transistor (T34) includes a gate electrode connected to the second buffer node (Qh2), a first electrode connected to the gate electrode of the 14th transistor (T35), and a second electrode connected to the sixth power node.

The fourteenth transistor (T35) is turned on during the pull-down time when the gate voltage is a high voltage to connect the fifth power node to the pull-down control node [QB(n)] to charge the pull-down control node [QB(n)]. The fourteenth transistor (T35) includes a gate electrode connected to the second electrode of the eleventh transistor (T32) and the first electrodes of the twelfth and thirteenth transistors (T33, T34), a first electrode connected to the fifth power node, and a second electrode connected to the pull-down control node [QB(n)]. A first capacitor (C5) may be connected between the gate electrode and the second electrode of the fourteenth transistor (T35).

Fig. 11 is a block diagram showing a display device according to one embodiment of the present invention. Fig. 12 is a cross-sectional view showing a cross-sectional structure of the display panel shown in Fig. 11.

Referring to FIGS. 11 and 12, a display device according to an embodiment of the present invention includes a display panel (100), a display panel driver for writing pixel data to pixels of the display panel (100), and a power supply unit (140) for generating power required to drive the pixels and the display panel driver.

The display panel (100) may be a display panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel (100) includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines (102), a plurality of gate lines (103) intersecting the data lines (102), and pixels arranged in a matrix form. The display panel (100) may further include power lines commonly connected to the pixels. The power lines may include a power line to which a pixel driving voltage (ELVDD) is applied, a power line to which an initialization voltage (Vinit1) is applied, a power line to which a low-potential power voltage (ELVSS) is applied, etc.

The cross-sectional structure of the display panel (100) may include a circuit layer (12), a light-emitting element layer (14), and an encapsulation layer (16) laminated on a substrate (10), as illustrated in FIG. 2.

The circuit layer (12) may include a TFT array including pixel circuits connected to wiring such as data lines, gate lines, and power lines, a demultiplexer array (112), a gate driver (120), etc. The wiring and circuit elements of the circuit layer (12) may include a plurality of insulating layers, two or more metal layers separated by an insulating layer, and an active layer including a semiconductor material. All of the transistors formed in the circuit layer (12) may be implemented as n-channel oxide TFTs.

The light-emitting element layer (14) may include light-emitting elements (EL) driven by pixel circuits. The light-emitting elements (EL) may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer (14) may include a white light-emitting element and a color filter. The light-emitting elements (EL) of the light-emitting element layer (14) may be covered by a protective layer including an organic film and a protective film.

The sealing layer (16) covers the light-emitting element layer (14) to seal the circuit layer (12) and the light-emitting element layer (14). The sealing layer (16) may be a multi-insulating film structure in which organic films and inorganic films are alternately laminated. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are laminated in multiple layers, the migration path of moisture or oxygen becomes longer compared to a single layer, so that the penetration of moisture and oxygen affecting the light-emitting element layer (14) can be effectively blocked.

A touch sensor layer, which is omitted in the drawing, may be formed on the sealing layer (16), and a polarizing plate or a color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense a touch input based on a change in capacitance before and after a touch input. The touch sensor layer may include metal wiring patterns and insulating films that form the capacitance of the touch sensors. The insulating films may insulate an intersecting portion of the metal wiring patterns and flatten the surface of the touch sensor layer. The polarizing plate may convert the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer to improve visibility and contrast ratio. The polarizing plate may be implemented as a polarizing plate or a circular polarizing plate in which a linear polarizing plate and a phase delay film are bonded. A cover glass may be adhered to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer can replace the role of a polarizing plate by absorbing some of the wavelengths of light reflected from the circuit layer and the touch sensor layer, thereby increasing the color purity of the image reproduced in the pixel array.

The pixel array includes a plurality of pixel lines (L1 to Ln). Each of the pixel lines (L1 to Ln) includes one line of pixels arranged along a line direction (X-axis direction) in the pixel array of the display panel (100). The pixels arranged in one pixel line share gate lines (103). The sub-pixels arranged in the column direction (Y) along the data line direction share the same data line (102). One horizontal period is a time obtained by dividing one frame period by the total number of pixel lines (L1 to Ln).

The display panel (100) can be implemented as a non-transparent display panel or a transparent display panel. The transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual object in the background is visible. The display panel (100) can be manufactured as a flexible display panel.

Each of the pixels (101) may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. Hereinafter, a pixel may be interpreted as having the same meaning as a sub-pixel. Each of the pixel circuits is connected to data lines, gate lines, and power lines.

Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can implement higher resolution than real color pixels by driving two sub-pixels with different colors into one pixel (101) using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color expression in each pixel with the color of light emitted from an adjacent pixel.

The power supply unit (140) generates a DC power required to drive the pixel array of the display panel (100) and the display panel driver using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit (140) may adjust the level of a DC input voltage applied from a host system (not shown) to generate a DC voltage (or constant voltage) such as a gamma reference voltage (VGMA), a gate-on voltage (VGH), a gate-off voltage (VGL), a pixel driving voltage (ELVDD), a low-potential power supply voltage (ELVSS), and an initialization voltage (Vinit1). The gamma reference voltage (VGMA) is supplied to the data driving unit (110). The gate-on voltage (VGH) and the gate-off voltage (VGL) are supplied to the gate driving unit (120). The pixel driving voltage (ELVDD), the low-potential power supply voltage (ELVSS), and the initialization voltage (Vinit) are commonly supplied to the pixels (101).

The display panel driving unit writes pixel data of an input image to the pixels of the display panel (100) under the control of a timing controller (130).

The display panel driver includes a data driver (110) and a gate driver (120). The display panel driver may further include a demultiplexer array (112) arranged between the data driver (110) and data lines (102).

The demultiplexer array (112) sequentially supplies data voltages output from the channels of the data driving unit (110) to the data lines (102) using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements arranged on the display panel (100). When the demultiplexer is arranged between the output terminals of the data driving unit (110) and the data lines (102), the number of channels of the data driving unit (110) may be reduced. The demultiplexer array (112) may be omitted.

The display panel driving unit may further include a touch sensor driving unit for driving touch sensors. The touch sensor driving unit is omitted in Fig. 1. The data driving unit (110) and the touch sensor driving unit may be integrated into one drive IC (Integrated Circuit). In a mobile device or wearable device, a timing controller (130), a power supply unit (140), a data driving unit (110), etc. may be integrated into one drive IC.

The display panel driving unit can operate in a low speed driving mode under the control of the timing controller (130). The low speed driving mode can be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. The low speed driving mode can reduce power consumption of the display panel driving unit and the display panel (100) by lowering the refresh rate of pixels when a still image is input for a certain period of time or longer. The low speed driving mode is not limited to when a still image is input. For example, the display panel driving circuit can operate in the low speed driving mode when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a certain period of time or longer.

The data driving unit (110) receives pixel data of an input image as a digital signal from a timing controller (130) and outputs a data voltage. The data driving unit (110) converts pixel data of an input image into a gamma compensation voltage for each frame period using a DAC (Digital to Analog Converter) to generate a data voltage. A gamma reference voltage (VGMA) is divided into a gamma compensation voltage for each grayscale through a voltage divider circuit. The gamma compensation voltage for each grayscale is provided to the DAC of the data driving unit (110). The data voltage is output through an output buffer from each channel of the data driving unit (110).

The gate driver (120) may be implemented as a GIP (Gate in panel) circuit formed on a circuit layer (12) on a display panel (100) together with a TFT array and wires of a pixel array. The gate driver (120) may be disposed on a bezel area (BZ), which is a non-display area of the display panel (100), or may be distributed within the pixel array on which an input image is reproduced. The gate driver (120) sequentially outputs gate signals to the gate lines (103) under the control of a timing controller (130). The gate driver (120) may sequentially supply the signals to the gate lines (103) by shifting the gate signals using a shift register. The gate signal may include a scan pulse, an EM pulse, an initialization pulse, etc. in an organic light emitting display device.

The gate driving unit (120) may include a first shift register (121) that outputs a scan pulse, a second shift register (122) that outputs an EM pulse, and a third shift register (123) that outputs an initialization pulse. At least one of the shift registers (121, 122, 123) may be implemented with the gate driving circuit described in the above-described embodiments.

The timing controller (130) receives digital video data (DATA) of an input image from the host system and a timing signal synchronized therewith. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may be omitted. The data enable signal (DE) has a cycle of 1 horizontal period (1H).

The host system may be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale a video signal from a video source to a resolution of a display panel (100) and transmit the same to a timing controller (130) together with a timing signal.

The timing controller (130) lowers the frame rate at which pixel data is written to pixels in the low-speed driving mode compared to the normal driving mode. For example, the data refresh frame frequency at which pixel data is written to pixels in the normal driving mode may occur at a frequency higher than 60 Hz, for example, a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and the data refresh frame (DRF) of the low-speed driving mode may occur at a refresh rate of a lower frequency than that of the low-speed driving mode. The timing controller (130) may lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of the pixels in the low-speed driving mode, thereby lowering the driving frequency of the display panel driving unit.

The timing controller (130) generates a data timing control signal for controlling the operation timing of the data driving unit (110), a control signal for controlling the operation timing of the demultiplexer array (112), and a gate timing control signal for controlling the operation timing of the gate driving unit (120) based on timing signals (Vsync, Hsync, DE) received from the host system. The timing controller (130) controls the operation timing of the display panel driving unit to synchronize the data driving unit (110), the demultiplexer array (112), the touch sensor driving unit, and the gate driving unit (120).

A gate timing control signal generated from a timing controller (130) can be input to shift registers (121, 122, 123) of a gate driver (120) through a level shifter (not shown). The level shifter can receive the gate timing control signal and generate a start pulse and a shift clock to provide them to the shift registers (121, 122, 123).

Due to process deviation and element characteristic deviation caused in the manufacturing process of the display panel (100), there may be a difference in the electrical characteristics of the driving elements between pixels, and such difference may become larger as the driving time of the pixels elapses. In order to compensate for the electrical characteristic deviation of the driving elements between pixels, an internal compensation technology or an external compensation technology may be applied to the organic light emitting display device. The internal compensation technology samples the threshold voltage of the driving element for each subpixel using an internal compensation circuit implemented in each pixel circuit and compensates the gate-source voltage (Vgs) of the driving element by the threshold voltage. The external compensation technology senses in real time the current or voltage of the driving element that changes according to the electrical characteristics of the driving elements using an external compensation circuit. The external compensation technology compensates for the electrical characteristic deviation (or change) of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image by the electrical characteristic deviation (or change) of the driving element sensed for each pixel. The display panel driver may drive the pixels using the external compensation technology and/or the internal compensation technology.

Fig. 13 is a circuit diagram showing a pixel circuit according to one embodiment of the present invention. The pixel circuit of the present invention may be implemented as a pixel circuit including an internal compensation circuit as in Fig. 13, but is not limited thereto.

Referring to FIG. 13, the pixel circuit includes a light-emitting element (EL) driving element (DT), first to fourth switching elements (M1 to M4), and a capacitor (Cst). The driving element (DT) and the switching elements (M1 to M4) can be implemented as n-channel oxide TFTs.

The light emitting element (EL) may include an anode electrode, a cathode electrode, and an organic compound layer connected between the electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML), whereby excitons are formed and visible light is emitted from the emission layer (EML).

A driving element (DT) generates a current for driving a light-emitting element (EL) according to a gate-source voltage (Vgs). The driving element (DT) includes a gate electrode connected to a first node (DRG), a first electrode connected to a second node (DRD), and a third electrode connected to a third node (DRD). A capacitor (Cst) may be connected between the first node (DRG) and an anode electrode of the light-emitting element (EL).

The first switching element (M1) includes a gate electrode to which an n-th scan pulse [SCAN(n)] is applied, a first electrode connected to a first node (DRG), and a second electrode connected to a second node (DRD). The first switching element (M1) is turned on according to a gate-on voltage of the n-th scan pulse [SCAN(n)] to connect the first node (DRG) and the second node (DRD) to connect the electrodes of the driving element (DT) in a diode connection structure.

The second switching element (M2) includes a gate electrode to which the nth scan pulse [SCAN(n)] is applied, a second electrode connected to a third node (DRS), and a second electrode connected to a data line to which a data voltage (Vdata) is applied. The second switching element (M2) is turned on according to the gate-on voltage of the nth scan pulse [SCAN(n)] and supplies the data voltage (Vdata) to the third node (DRS).

The third switching element (M3) includes a gate electrode to which a first EM pulse (EM1) is applied, a first electrode to which a pixel driving voltage (ELVDD) is applied, and a second electrode connected to the first node (DRD). The third switching element (M3) is turned on according to the gate-on voltage of the first EM pulse (EM1) and supplies the pixel driving voltage (ELVDD) to the first node (DRD).

The fourth switching element (M4) includes a gate electrode to which a second EM pulse (EM2) is applied, a first electrode connected to a third node (DRS), and a second electrode connected to the anode electrode of the light-emitting element (EL). The fourth switching element (M4) is turned on according to the gate-on voltage of the second EM pulse (EM2) to connect the third node (DRS) to the anode electrode of the light-emitting element (EL).

The fifth switching element (M5) includes a gate electrode to which the n-1th scan pulse [SCAN(n-1)] is applied, a first electrode connected to a power node to which an initialization voltage (Vinit1) is applied, and a second electrode connected to the anode electrode of the light-emitting element (EL). The fifth switching element (M5) is turned on according to the gate-on voltage of the n-1th scan pulse [SCAN(n-1)] and supplies the initialization voltage (Vinit1) to the anode electrode of the light-emitting element (EL).

Since the contents of the specification described above in terms of the problem to be solved, the means for solving the problem, and the effect do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the contents of the specification.

Although the embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical idea of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain it, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive. The protection scope of the present invention should be interpreted by the claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

ST(n-1) ~ ST(n+2): Signal transmission section of shift register
VST: Start signal CLK1~CLK4: Shift clock
ECLK: Enable Clock ECLKB: Disable Clock
CTR1, CTR2: Control unit BUF, BUF1, BUF2: Buffer
QG1, QG2, QG11, QG12: Q generation logic section
QBG1, QBG2, QBG: QB generation logic section
Q/QB: 1st control node QB/Q: 2nd control node
Q: Pull-up control node QB: Pull-down control node
TR1, TR2, TR3, TR4, TR11, TR12, TR20, TR31, TR32, TR40: Buffer transistors
GVDD, GVDD1, GVDD2: Gate drive voltage
GVSS, GVSS0, GVSS2: Gate Reference Voltage

Claims (14)

A plurality of signal transmission units that input a start signal and a shift clock and charge and discharge a first control node and a second control node; and
Including first buffers respectively connected to the signal transmission units,
Each of the above first buffers,
A first transistor driven according to the voltage of the first control node; and
A second transistor is connected to the first transistor with a first output node interposed therebetween, the first transistor being driven by the voltage of the second control node and outputting a gate pulse;
The above signal transmission unit,
A first control unit that receives an activation clock for a first unit of time and controls the first control node as a pull-up control node, and receives a deactivation clock for a second unit of time and deactivates the first control node; and
A second control unit is included that receives the activation clock during the second unit time and controls the second control node as the pull-up control node, and receives the deactivation clock during the first unit time and deactivates it.
The first transistor includes a gate electrode connected to the first control node, a first electrode connected to the first power node, and a second electrode connected to the first output node,
The second transistor includes a gate electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode connected to a second power node,
During the first unit time, the first transistor operates as a pull-up transistor and a gate driving voltage is applied to the first power node connected to the first electrode of the first transistor.
A gate driving circuit in which, during the second unit time, the second transistor operates as the pull-up transistor and the gate driving voltage is applied to the second power node connected to the second electrode of the second transistor. In paragraph 1,
Including second buffers respectively connected to the above signal transmission units,
Each of the above second buffers,
a third transistor driven according to the voltage of the first control node; and
A fourth transistor is connected to the third transistor with a second output node interposed therebetween, the second transistor being driven by the voltage of the second control node and outputting a carry pulse;
A gate driving circuit in which the power voltage applied to the third and fourth transistors in at least one of the second buffers is periodically switched. delete delete In paragraph 1,
The above activation clock comprises a plurality of pulses that swing between a high voltage and a low voltage during a unit time,
The above-described inactive clock is a gate driving circuit that maintains the low voltage for the above-described unit time. In paragraph 5,
The above first control unit,
A first Q generation logic unit that charges the first control node during the first unit time and controls it with the pull-up control node; and
Including a first QB generation logic unit that controls the second control node as a pull-down control node by charging the second control node when the first control node is discharged during the first unit time,
The second control unit,
A second Q generation logic unit that charges the second control node during the second unit time and controls it with the pull-up control node; and
A gate drive circuit including a second QB generation logic section for controlling the first control node as the pull-down control node by charging the first control node when the second control node is discharged during the second unit time. In paragraph 6,
The above first Q generation logic unit,
including a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
The fifth transistor includes a gate electrode connected to a first CLK node to which the activation clock is input during the first unit time and the deactivation clock is input during the second unit time, a first electrode connected to a carry signal node to which a carry pulse is input from a signal transmission section of a previous stage, and a second electrode connected to a first buffer node.
The sixth transistor includes a gate electrode connected to the first CLK node, a first electrode connected to the first buffer node, and a second electrode connected to the first control node,
The seventh transistor includes a gate electrode connected to the first control node, a first electrode connected to a fifth power node to which the gate driving voltage is applied for the first unit time and a gate reference voltage that is lower than the gate driving voltage is applied for the second unit time, and a second electrode connected to the first buffer node,
The eighth transistor includes a gate electrode connected to a second buffer node, a first electrode connected to a sixth power node to which the gate reference voltage is applied, and a second electrode connected to the first control node.
The above first QB generation logic unit,
including a ninth transistor, a tenth transistor, and an eleventh transistor;
The ninth transistor includes a gate electrode connected to the second control node of the signal transmission section of the previous stage, a first electrode connected to the seventh power node to which the gate driving voltage is applied for the first unit time and the gate reference voltage is applied for the second unit time, and a second electrode connected to the gate electrode of the eleventh transistor,
The 10th transistor includes a gate electrode connected to the first buffer node, a first electrode connected to the gate electrode of the 11th transistor, and a second electrode connected to the 10th power node to which the gate reference voltage is applied.
A gate driving circuit in which the 11th transistor includes a gate electrode connected to the second electrode of the 9th transistor and the first electrode of the 10th transistor, a first electrode connected to an 11th power node to which the gate driving voltage is applied, and a second electrode connected to the second control node. In paragraph 7,
The above second Q generation logic unit,
including a 12th transistor, a 13th transistor, a 14th transistor, and a 15th transistor,
The 12th transistor includes a gate electrode to which the deactivation clock is input for a first unit time and the activation clock is input for a second unit time, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node,
The 13th transistor has a gate electrode connected to a second CLK node to which the activation clock is input during the second unit time and the deactivation clock is input during the first unit time, a first electrode connected to the second buffer node, and connected to the second control node,
The 14th transistor includes a gate electrode connected to the second control node, a first electrode connected to a 12th power node to which the gate reference voltage is applied for the first unit time and the gate driving voltage is applied for the second unit time, and a second electrode connected to the second buffer node,
The 15th transistor includes a gate electrode connected to the first buffer node, a first electrode connected to the sixth power node, and a second electrode connected to the second control node,
The above second QB generation logic unit,
including a 16th transistor, a 17th transistor, and an 18th transistor;
The 16th transistor includes a gate electrode connected to a first control node of the signal transmission section of the previous stage, a first electrode connected to a 13th power node to which the gate reference voltage is applied for the first unit time and the gate driving voltage is applied for the second unit time, and a second electrode connected to the gate electrode of the 18th transistor,
The 17th transistor includes a gate electrode connected to the second buffer node, a first electrode connected to the gate electrode of the 18th transistor, and a second electrode connected to the 10th power node,
The 18th transistor is a gate driving circuit including a gate electrode connected to the second electrode of the 16th transistor and the first electrode of the 17th transistor, a first electrode connected to the 11th power node, and a second electrode connected to the first control node. A plurality of signal transmission units that input a start signal and a shift clock and charge and discharge a first pull-up control node, a second pull-up control node, and a pull-down control node; and
Including first buffers respectively connected to the above signal transmission units,
Each of the above first buffers,
A first-first pull-up transistor driven according to the voltage of the first pull-up control node;
A first-second pull-up transistor driven by the voltage of the second pull-up control node; and
A first pull-down transistor is included, which is driven according to the voltage of the pull-down control node,
The above signal transmission unit,
A first Q generation logic section that receives an activation clock during a first pull-up time to charge the first pull-up control node and turns on the first-first pull-up transistor, and receives a deactivation clock during a second pull-up time to deactivate the first Q generation logic section;
A second Q generation logic unit that receives the activation clock during the second pull-up time to charge the second pull-up control node and turns on the first-second pull-up transistor, and receives the deactivation clock during the first pull-up time to deactivate it; and
A gate drive circuit including a QB generation logic section for turning on the first pull-down transistor by charging the pull-down control node during a pull-down time when the first and second pull-up control nodes are discharged. In Article 9,
Further comprising second buffers respectively connected to the above signal transmission units,
Each of the above second buffers,
A third-first pull-up transistor driven according to the voltage of the first pull-up control node;
A third-second pull-up transistor driven by the voltage of the second pull-up control node; and
A gate driving circuit including a second pull-down transistor driven according to the voltage of the pull-down control node. In Article 10,
The above first Q generation logic unit,
including a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
The fourth transistor includes a gate electrode connected to a first CLK node to which the activation clock is input during the first pull-up time and the deactivation clock is input during the second pull-up time, a first electrode connected to a carry signal node to which a carry pulse from a previous stage signal transmission unit is input, and a second electrode connected to a first buffer node.
The fifth transistor includes a gate electrode connected to the first CLK node, a first electrode connected to the first buffer node, and a second electrode connected to the first pull-up control node,
The sixth transistor includes a gate electrode connected to the first pull-up control node, a first electrode connected to a third power node to which a gate driving voltage is applied, and a second electrode connected to the first buffer node.
The seventh transistor includes a gate electrode connected to the first buffer node and the second buffer node, a first electrode connected to the pull-down control node, and a second electrode connected to a fourth power node to which a gate reference voltage is applied.
The above second Q generation logic unit,
Including an 8th transistor, a 9th transistor, and a 10th transistor,
The eighth transistor includes a gate electrode connected to a second CLK node to which the activation clock is input during the second pull-up time and the deactivation clock is input during the first pull-up time, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node,
The ninth transistor includes a gate electrode connected to the second CLK node, a first electrode connected to the second buffer node, and a second electrode connected to the second pull-up control node,
The gate driving circuit of the 10th transistor includes a gate electrode connected to the second pull-up control node, a first electrode connected to the third power node, and a second electrode connected to the second buffer node. In Article 11,
The above QB generation logic section is,
Including an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor,
The above 11th transistor includes a gate electrode connected to the pull-down control node of the previous stage signal transmission section, a first electrode connected to the fifth power supply node to which the gate driving voltage is applied, and a second electrode connected to the gate electrode of the 14th transistor,
The 12th transistor includes a gate electrode connected to the first buffer node, a first electrode connected to the gate electrode of the 14th transistor, and a second electrode connected to the 6th power node to which the gate reference voltage is applied.
The 13th transistor includes a gate electrode connected to the second buffer node, a first electrode connected to the gate electrode of the 14th transistor, and a second electrode connected to the 6th power node.
The 14th transistor is a gate driving circuit including a gate electrode connected to the second electrode of the 11th transistor and the first electrodes of the 12th and 13th transistors, a first electrode connected to the fifth power node, and a second electrode connected to the pull-down control node. A display panel having pixels connected to a plurality of data lines to which a data voltage is applied, a plurality of gate lines intersecting the data lines and to which a gate signal is applied, and a plurality of power lines;
A data driving circuit that inputs pixel data and outputs the data voltage; and
A gate driving circuit is included that outputs the gate signal using a shift register,
The shift register of the above gate driving circuit is,
A plurality of signal transmission units that input a start signal and a shift clock and charge and discharge a first control node and a second control node; and
Contains buffers each connected to a signal transmission unit,
Each of the above buffers,
A first transistor driven according to the voltage of the first control node; and
A second transistor is connected to the first transistor with a first output node interposed therebetween, the first transistor being driven by the voltage of the second control node and outputting a gate pulse;
The above signal transmission unit,
A first control unit that receives an activation clock for a first unit of time and controls the first control node as a pull-up control node, and receives a deactivation clock for a second unit of time and deactivates the first control node; and
A second control unit is included that receives the activation clock during the second unit time and controls the second control node as the pull-up control node, and receives the deactivation clock during the first unit time and deactivates it.
The first transistor includes a gate electrode connected to the first control node, a first electrode connected to the first power node, and a second electrode connected to the first output node,
The second transistor includes a gate electrode connected to the second control node, a first electrode connected to the first output node, and a second electrode connected to a second power node,
During the first unit time, the first transistor operates as a pull-up transistor and a gate driving voltage is applied to the first power node connected to the first electrode of the first transistor.
A display device in which, during the second unit time, the second transistor operates as the pull-up transistor and the gate driving voltage is applied to the second power node connected to the second electrode of the second transistor. A display panel having pixels connected to a plurality of data lines to which a data voltage is applied, a plurality of gate lines intersecting the data lines and to which a gate signal is applied, and a plurality of power lines;
A data driving circuit that inputs pixel data and outputs the data voltage; and
A gate driving circuit is included that outputs the gate signal using a shift register,
The shift register of the above gate driving circuit is,
A plurality of signal transmission units that input a start signal and a shift clock and charge and discharge a first pull-up control node, a second pull-up control node, and a pull-down control node; and
Including first buffers respectively connected to the above signal transmission units,
Each of the above first buffers,
A first-first pull-up transistor driven according to the voltage of the first pull-up control node;
A first-second pull-up transistor driven by the voltage of the second pull-up control node; and
A first pull-down transistor is included, which is driven according to the voltage of the pull-down control node,
The above signal transmission unit,
A first Q generation logic section that receives an activation clock during a first pull-up time to charge the first pull-up control node and turns on the first-first pull-up transistor, and receives a deactivation clock during a second pull-up time to deactivate the first Q generation logic section;
A second Q generation logic unit that receives the activation clock during the second pull-up time to charge the second pull-up control node and turns on the first-second pull-up transistor, and receives the deactivation clock during the first pull-up time to deactivate it; and
A display device including a QB generation logic section for turning on the first pull-down transistor by charging the pull-down control node during a pull-down time when the first and second pull-up control nodes are discharged.