KR102731015B1 - Method for Manufacturing SiC Trench Gate MOSFET Device Based on NO Post-Deposition Annealing (PDA) - Google Patents

Abstract

The present invention relates to a method for manufacturing a trench gate type SiC MOSFET device, and the method for manufacturing a trench gate type SiC MOSFET device comprises the steps of: forming a gate trench by etching deeper than a doping layer in a source region of a SiC substrate; forming a gate oxide film using TEOS and O ₂ ; performing a heat treatment after deposition of the gate oxide film in an NO atmosphere; forming a gate electrode in the gate trench; forming an interlayer insulating film on a substrate on which the gate electrode is formed; patterning the gate oxide film and the interlayer insulating film; forming a source electrode covering an upper surface of a doping layer for a source region formed on an entire surface of an epitaxial layer of the substrate and an upper surface of the interlayer insulating film; and forming a drain electrode on a back surface of the substrate.

Description

Method for Manufacturing SiC Trench Gate MOSFET Device Based on NO Post-Deposition Annealing (PDA)

The present invention relates to a method for manufacturing a trench gate type SiC MOSFET device, and more particularly, to a method for manufacturing a trench gate type SiC MOSFET device having a high-quality and stable gate oxide film by applying NO heat treatment after deposition.

Metal-oxide semiconductor field-effect transistor (MOSFET) devices based on 4H-SiC are being widely considered for high-voltage device applications due to their excellent physical and electronic properties.

However, the use of SiC-MOSFETs is still limited by their low field-effect mobility (μ _fe ), which is particularly due to the high oxide-semiconductor interface defect density (D _it ) near the conduction band edge of the semiconductor.

The main factor causing high D _it is the presence of intrinsic carbon from two sources: residual carbon from the substrate surface before oxidation and carbon generated at the interface during oxidation.

To reduce the interfacial defects as described above, the annealing of the gate oxide in a nitric oxide (NO) or nitrous oxide (N ₂ O) environment has been proven to be the best technique for growing device-grade gate oxides. That is, nitrogen atoms can remove the bonding of silicon-oxycarbon complexes inherent to carbon and SiC oxide. On the other hand, the deposited oxide can minimize carbon incorporation at the oxide/SiC interface. Among the deposition methods, low pressure chemical vapor deposition (LPCVD) has unique advantages such as excellent electrical insulation properties, high growth rate, low growth temperature, and excellent thickness controllability. In addition, TetraEthylOrthoSilicate (TEOS, Si(OC ₂ H ₅ ) ₄ ) as a source material in the oxide deposition process has the advantages of being less sensitive to the morphology of the wafer surface and obtaining a deposited oxide with low surface roughness. It has been reported that the μ _fe of 4H-SiC MOSFETs using plasma enhanced CVD deposited oxide films with TEOS source is significantly improved (~40 cm ² /Vs) compared to thermal oxide films, but the leakage current density is higher and the breakdown field is lower (≤6.5 MV/cm).

Therefore, in order for the deposited TEOS oxide film to be used as the gate oxide film of a SiC MOSFET, the establishment of a process technology that can minimize leakage current and increase the critical oxide breakdown field (E _B ) is required.

Accordingly, the present invention has been made to solve the above-described problems, and the present invention provides a method for manufacturing a trench gate type SiC MOSFET device having a high-quality and stable gate oxide film by performing post-heat treatment (NO post-deposition annealing (PDA)) of a low-pressure CVD TEOS deposited gate oxide film on a 4H-SiC substrate in an NO atmosphere.

First, to summarize the features of the present invention, a method for manufacturing a trench gate type SiC MOSFET device according to one aspect of the present invention for achieving the above object includes the steps of: forming a gate trench by etching deeper than a doping layer of a source region of a SiC substrate (e.g., a 4H-SiC substrate); depositing a gate oxide film using TEOS and O ₂ ; performing a heat treatment after deposition of the gate oxide film in an NO atmosphere; forming a gate electrode in the gate trench; forming an interlayer insulating film on the substrate on which the gate electrode is formed; patterning the gate oxide film and the interlayer insulating film; forming a source electrode covering an upper surface of a doping layer for a source region formed on an entire surface of an epitaxial layer of the substrate and an upper surface of the interlayer insulating film; and forming a drain electrode on a back surface of the substrate.

The method for manufacturing the trench gate type SiC MOSFET device further includes, prior to the step of depositing the gate oxide film, a step of ion implantation to form a doped well under the gate oxide film in the gate trench region.

In the step of forming the gate oxide film, an oxide film SiO ₂ is formed with a thickness of 50 to 110 nm at 600 to 800° C. using TEOS and O ₂ on the trench region including the gate trench sidewall and bottom surface using LPCVD equipment.

In the step of performing heat treatment after deposition of the above gate oxide film, heat treatment is performed at 800 to 1200°C for 60 to 180 minutes in an atmosphere containing NO gas.

The method for manufacturing the trench gate type SiC MOSFET device is characterized by inducing the effective oxide charge density (Q _eff ) of the gate oxide film to a positive value by generating positive charges at the interface of the gate oxide film by heat treatment after deposition of the gate oxide film in the NO atmosphere, and increasing the dielectric breakdown field (E _B ) and field-effect mobility (μ _fe ).

The effective oxide charge density (Q _eff ) can be in the range of 2.81Х10 ¹¹ cm ^-2 < Q _eff ≤ 4.27Х10 ¹¹ cm ^-2 depending on the design.

According to the method for manufacturing a trench gate type SiC MOSFET device according to the present invention, a low-pressure CVD TEOS deposited gate oxide film on a 4H-SiC substrate is subjected to NO post-deposition annealing (PDA) treatment, thereby improving the interface characteristics of the TEOS gate oxide film/4H-SiC MOS capacitor and the side MOSFET, thereby providing a high-quality and stable gate oxide film.

In the present invention, the electrical properties of low pressure CVD TEOS deposited oxide films followed by post-NO deposition annealing (PDA) treatment on 4H-SiC are disclosed. In addition, for comparison, a wet thermal oxide film was also fabricated followed by a post-NO oxidation annealing (POA) treatment. Improved electrical properties of the wet thermal oxide and the TEOS oxide film with 90 min POA/PDA were observed. In particular, the NO PDA treated TEOS oxide film showed lower leakage current and higher E _B compared to the NO POA treated wet oxide film. In addition, the μ _fe of the MOSFET with the TEOS oxide film with 90 min NO PDA showed higher properties than that with the wet thermal oxide film.

That is, the NO PDA treatment significantly improved the oxide quality as well as the SiO ₂ /SiC interface, especially for the TEOS oxide films deposited by LPCVD. The low D _it and high positive effective oxide charge density (Q _eff ) of the TEOS oxide films with 90 min NO PDA can hinder the injection of electrons tunneling from SiC through the oxide. As a result, the leakage current is reduced, followed by the increase of E _B . The correlations among the Q _eff , D _it parameters and E _B and the barrier height (Φ _B ) in the oxide films were established. The barrier height was calculated by the Fowler–Nodhiem (FN) plot. It was found that the positive Q _eff is the dominant factor affecting E _B , and the Φ _B value depends only on Q _eff but not on D _it . The maximum μ _fe = 17.8 cm ² /V s observed for the TEOS oxide with 90 min NO PDA was higher than that of the thermally grown wet oxide with 90 min NO POA = 11 cm ² /V s. The rapidly grown TEOS oxide with 90 min NO PDA can be applied as the gate oxide of 4H-SiC MOSFETs to effectively form a high-quality nitrided SiO ₂ /SiC interface, which can enhance the μ _fe .

The accompanying drawings, which are included as a part of the detailed description to aid understanding of the present invention, provide examples of the present invention and, together with the detailed description, explain the technical idea of the present invention.
Figure 1 shows typical normalized high frequency CV curves for the MOS capacitors with wet oxide, wet oxide with 90 min NO POA, and TEOS oxide with 90 min NO PDA, respectively.
Figure 2 is an example of current density (J)-electric field (E) graphs of wet oxide, wet oxide with 90 min NO POA, and TEOS oxide with 90 min NO PDA, respectively.
Figure 3 is a graph showing the interface defect density (D _it ) measured at room temperature above the 4H-SiC band gap.
Figure 4 shows the barrier heights of the wet oxide film, the 90-minute NO POA-treated wet oxide film, and the 90-minute NO PDA-treated TEOS oxide film, respectively.
Figure 5 shows (a) a correlation graph of the effective oxide charge (Qeff) and the interface defect density ( _Dit ) at 0.3 eV below the conduction band of 4H-SiC with respect to the oxide breakdown field (E _B ), and (b) a correlation graph of the effective oxide charge (Qeff) and the interface defect density ( _Dit ) at 0.3 eV below the conduction band of 4H-SiC with respect to the barrier height (Φ _B ).
Figure 6 is an example of a secondary electron microscopy (SEM) image of a poly-Si gate and TEOS oxide film on 4H-SiC.
Figure 7 is a graph of the extracted field-effect mobility (μ fe ) from a horizontal SiC MOSFET with 50 μm channel length and 50 _μm width using a 90-minute NO POA-treated wet oxide and a 90-minute NO PDA-treated TEOS gate oxide.
FIG. 8 is a drawing for explaining the structure of a trench gate type SiC MOSFET device as a side MOSFET of the present invention.
FIG. 9 is a drawing for explaining a method for manufacturing a trench gate type SiC MOSFET device of the present invention.

Hereinafter, the present invention will be described in detail with reference to the attached drawings. At this time, in each drawing, the same components are represented by the same reference numerals as much as possible. In addition, detailed descriptions of functions and/or configurations that are already known will be omitted. The contents disclosed below will focus on parts necessary for understanding operations according to various embodiments, and descriptions of elements that may obscure the gist of the description will be omitted. In addition, some components of the drawings may be exaggerated, omitted, or schematically illustrated. The size of each component does not entirely reflect the actual size, and therefore, the contents described herein are not limited by the relative sizes or spacings of the components drawn in each drawing.

In describing embodiments of the present invention, if it is judged that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. In addition, the terms described below are terms defined in consideration of their functions in the present invention, and may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification. The terms used in the detailed description are only for describing embodiments of the present invention, and should never be limited. Unless clearly used otherwise, the singular form includes the plural form. In this description, expressions such as "comprises" or "comprising" are intended to indicate certain features, numbers, steps, operations, elements, parts or combinations thereof, and should not be construed to exclude the presence or possibility of one or more other features, numbers, steps, operations, elements, parts or combinations thereof other than those described.

Additionally, although the terms first, second, etc. may be used to describe various components, the components are not limited by the terms, and the terms are used only for the purpose of distinguishing one component from another.

First, the experimental results of a structure according to one embodiment of a MOS capacitor that can be applied to a lateral MOSFET, i.e., a trench gate type SiC MOSFET device, having a high-quality and stable gate oxide film of the present invention are described.

MOS capacitor test structures were fabricated using N-type, 4°off (0001)-oriented 4H-SiC wafers with a 10 µm thick epilayer doped with 5Х10 ¹⁵ cm ^-3 nitrogen. The wafers underwent a standard RCA wafer cleaning process followed by a final 1-minute HF dip treatment.

Subsequently, the deposition process of SiO ₂ is performed at 700 °C for 10 min using TetraEthylOrthoSilicate (TEOS, Si(OC ₂ H ₅ ) ₄ ) and O ₂ as gaseous precursors. After deposition of the SiO ₂ layer, the sample is subjected to a standard post-deposition annealing (PDA) at 1175 °C for 90 min in NO atmosphere. The thickness of the sample treated with NO PDA for 90 min was about 100 nm, calculated from the high-frequency (100 kHz) capacitance-voltage (CV) curve. For comparison, a 100 nm-thick wet oxide film (e.g., thermal oxide film grown in water vapor or oxygen atmosphere) grown at 1150 °C for 7 h was also prepared, and post-oxidation annealing (POA) was performed under the same conditions of NO atmosphere.

After these oxidation and nitridation steps, aluminum (work function 4.3 eV) was used as the gate electrode of the MOS capacitor. The area of the capacitor (4.5Х10 ^-4 cm ² ) was defined by the photolithography process. Finally, after the oxide film on the back surface of the substrate was removed, a large-area Al back contact (drain electrode) was deposited on the N+ substrate. A summary of the fabrication process conditions for all oxide films is presented in [Table 1].

[Table 1]

An n-channel lateral SiC MOSFET was fabricated using a p-type epitaxial layer having an Al doping concentration of about 2Х10 ¹⁷ cm ^-3 and a thickness of 1 μm. The gate oxides of the MOSFET were formed by LPCVD TEOS deposited oxide and thermally grown wet oxide, respectively, similar to the MOS capacitors. The thicknesses of the TEOS oxide and wet oxide were about 100 nm. In addition, the MOS structure of the present invention can be applied to a p-channel lateral MOSFET as well as an n-channel lateral MOSFET.

High-frequency and low-frequency capacitance-voltage (CV) characteristics of capacitors are measured simultaneously using a computer-controlled Keithley 590 CV analyzer and a 595 quasistatic CV meter. For high-frequency measurements (e.g., 100 kHz), a small-signal amplitude AC voltage (e.g., 15 mV) is superimposed on the DC bias at a sweep rate of 0.1 V s ^-1 . The interface defect density (D _it ) can be calculated as [Mathematical Formula 1].

[Mathematical Formula 1]

Here, C _QS , C _HF , C _ox , and q are the quasi-static (low frequency) capacitance, high frequency capacitance, oxide capacitance, and electron charge, respectively. C _ox is measured in the accumulation region. Here, all capacitances represent unit area capacitance. The current-voltage (IV) characteristics were measured using an HP4156B analyzer. The samples were tested three times consecutively to obtain reliable results. All electrical measurements are performed at room temperature.

Figure 1 shows typical normalized high-frequency CV curves for the MOS capacitors with wet oxide, wet oxide with 90 min NO POA, and TEOS oxide with 90 min NO PDA, respectively. An ideal curve is included for comparison. The gate voltage sweep direction was performed from accumulation to depletion mode, and all measurements were performed at room temperature. The measured capacitances were normalized to the oxide capacitance (C _ox ) value of each measurement, which is used to calculate the oxide thickness (t _ox ) using Equation (2).

[Mathematical formula 2]

Here, k is the dielectric constant of SiO ₂ (3.9), ε _o is the free space permittivity (8.854Х10 ^-14 Fcm ^-1 ), A is the capacitor gate area (cm ^-2 ), and C _ox is the oxide cofactor value. As can be seen in Fig. 1, the CV curve shifts from the ideal CV curve to the positive direction of the gate voltage for the wet oxide, implying an increase in the positive flat band voltage (V _FB ). The positive value indicates that interface defects and electron traps such as donors are created in the oxide.

However, wet oxide films and TEOS oxide films with NO treatment showed a shift in the negative direction. This opposite shift can be attributed to the reduction of interfacial defects by incorporating nitrogen into the oxide network and suppressing accumulated carbon. The value of V _FB for each oxide film was extracted from the CV curve using the flat band capacitance (C _FB ) value obtained from [Mathematical Formula 3].

[Mathematical Formula 3]

Here, T is room temperature (K), N _D is the substrate doping concentration (cm ^-3 ) and T _ox is the thickness (cm). By comparing the measured ideal high-frequency CV curves of the samples, the flat band voltage change (△V _FB ) can be calculated based on [Mathematical Formula 4].

[Mathematical Formula 4]

△V _FB = ideal V _FB - measured V _FB

The measured V _FB values of the wet oxide, the 90-min NO POA-treated wet oxide, and the 90-min NO PDA-treated TEOS oxide, respectively, were 1.95, -1.04, and -1.69. The effective oxide charge (number) density (Q _eff ), which is composed of mobile ions (Q _m ), fixed oxide charges (Q _f ), oxide trap charges (Q _t ), and interface trap charges (Q _it ), can be calculated based on the flat band voltage shift (△V _FB ) as shown in [Mathematical Formula 5].

[Mathematical Formula 5]

The Q _eff of the wet oxide film had a negative value of -3.04Х10 ¹¹ cm ^-2 , while that of the wet oxide film with 90 min NO POA showed a high positive value of about 2.81Х10 ¹¹ cm ^-2 . The Q _eff of the TEOS oxide film with 90 min NO PDA had the largest positive value of 4.27Х10 ¹¹ cm ^-2 compared to the others. The positive Q _eff of the wet oxide and TEOS oxide films _indicate that the negative charge at the oxide film and/or the interface was significantly reduced by 90 min NO PDA. This can be attributed to the decrease in the negative charge trap density at the interface and/or the positive charge at the interface resulting from nitridation. The summary of Q _eff , V _FB and other parameters is listed in [Table 2]. This is exemplary, and in particular, the Q _eff of the TEOS oxide film having the NO PDA of the present invention can have a value in the range of 2.81Х10 ¹¹ cm ^-2 < Q _eff ≤ 4.27Х10 ¹¹ cm ^-2 depending on the design.

[Table 2]

Figure 2 is an example of current density (J)-electric field (E) graphs of wet oxide, wet oxide with 90 min NO POA, and TEOS oxide with 90 min NO PDA, respectively.

For E<6.5 MV/cm, the leakage current density through the TEOS oxide film with 90 min NO PDA is about one order of magnitude lower than that of the wet oxide film. Beyond 6.5 MV/cm, the lowest leakage current and the highest E _B are also observed for the TEOS oxide film with 90 min NO PDA, where E _B is defined as the electric field value at which the leakage current is ~ 10 ^-6 A/cm ² .

In addition, it has been reported that the μ _fe of 4H-SiC MOSFETs using plasma-enhanced CVD-deposited oxide films using TEOS source is somewhat improved (~ 40 cm ² /Vs) compared to wet oxide (or thermal oxide), but the leakage current density is higher and the breakdown field (E _B ) is lower (≤ 6.5 MV/cm).

In the present invention, in order to minimize the leakage current as described above and increase the breakdown field (E _B ), a low-pressure CVD TEOS deposited gate oxide is post-annealed (PDA) in an NO atmosphere, thereby inducing the effective oxide charge (number) density (Q _eff ) to be a positive value in the range of 2.81Х10 ¹¹ cm ^-2 < Q _eff ≤ 4.27Х10 ¹¹ cm ^-2 , unlike the wet oxide film or its POA-treated counterpart.

Figure 3 is a graph showing the interface defect density (D _it ) measured at room temperature above the 4H-SiC band gap.

Figure 3 is a graph comparing the interface defect density (D _it ) measured at room temperature for all oxides at 0.2-0.6 eV below the conduction band edge of 4H-SiC. The D _it of the wet oxide was much higher than that of the other oxides. For the TEOS oxide with 90 min NO PDA, a significant decrease in _{the D it value} was observed, and the measured D _it value was similar to that reported for the nitrided oxide with NO POA treatment at 1175 °C. However, this decrease was to the extent that it showed a higher defect density than that of the wet oxide with 90 min NO POA. This was presumed to be due to the interfacial defects created by the breaking of Si-N, Si-O bonds at the TEOS oxide-SiC interface during the NO PDA heat treatment. Therefore, the interfacial defects may not be the only parameter determining the level of leakage current and E _B through the 100 nm-thick oxide. To further explain these results, the current conduction mechanism was investigated.

Figure 4 shows the barrier heights of the wet oxide film, the 90-minute NO POA-treated wet oxide film, and the 90-minute NO PDA-treated TEOS oxide film, respectively.

As shown in the current density (J)-electric field (E) graphs in Fig. 2, it can be concluded that the current conduction mechanisms of the investigated oxide films are similar. In general, FN (Fowler-Nordheim) and direct tunneling are the main conduction paths for electrons injected through the oxide film in the SiC substrate. From the FN graph, the barrier height (Φ _B ) between the conduction band edge of SiC and the oxide film was extracted, as shown in Fig. 4. The barrier height (Φ _B ) values of the wet oxide film, the wet oxide film with 90 min NO POA, and the TEOS oxide film with 90 min NO PDA were 2.15, 2.55, and 2.61 (eV), respectively. The small value of Φ _B (2.15 eV) obtained from the wet oxide film is a good indicator that the current conduction mechanism in the oxide film is not dominated by FN tunneling. The effects of NO treatment on wet oxide films and TEOS oxide films on E _B and Φ _B can be correlated with Q _eff and D _it .

Figure 5 is a graph showing (a) the relationship between the effective oxide charge (Q _eff ) and the interface defect density (D _it ) at 0.3 eV below the conduction band of 4H-SiC versus the oxide breakdown field (E _B ), and (b) the relationship between the effective oxide charge (Q _eff ) and the interface defect density (D _it ) at 0.3 eV below the conduction band of 4H-SiC versus the barrier height (Φ _B ). The coefficient of determination r ² is indicated on the graphs to indicate the goodness of the fitted data.

Referring to the correlation graph of E _B and Q _eff and D _it in Fig. 5(a), it can be seen that Q _eff is the main factor affecting the E _B value in 7 ≤ E _B ≤ 7.8 MV/cm. When the Q _eff value becomes more positive, more injected electrons from SiC can be captured at the positive trap centers and neutralized after dipole formation instead of being used to destroy the oxide network. Also, for 7 ≤ E _B ≤ 7.4 MV/cm, the decrease of D _it leads to an improved value of E _B . However, D _it did not become the main factor for the improvement in 7.4 ≤ E _B ≤ 7.8 MV/cm compared to Q _eff .

Meanwhile, referring to the correlation graph between Φ _B and Q _eff in Fig. 5(b), a more positive Q _eff value leads to an increase in Φ _B . Conversely, a negative Q _eff is obtained in the wet oxide film, which leads to a decrease in Φ _B . These are consistent with the theory revealed in the Si-SiO ₂ system, where the effective positive charge of the bulk oxide film can be converted into neutral electron traps, and the effective negative charge of the bulk can be increased when electrons are injected through FN tunneling. Therefore, it can be seen that the Φ _B value mainly depends on Q _eff rather than D _it .

Therefore, it was confirmed that by performing post-annealing (PDA) of the low-pressure CVD TEOS deposited gate oxide in an NO atmosphere as in the present invention, the effective oxide charge (number) density (Q _eff ) can be induced to a positive value in the range of 2.81Х10 ¹¹ cm ^-2 < Q _eff ≤ 4.27Х10 ¹¹ cm ^-2 and Φ _B can be increased, thereby increasing the breakdown field (E _B ) to 7.8 MV/cm or more. This result is significantly higher than the breakdown field (E _B ) (≤6.5 MV/cm) in 4H-SiC MOSFETs using conventional Plasma Enhanced CVD deposited oxide films using a TEOS source. Fig. 6 is an example of a secondary electron microscopy (SEM) image of a poly-Si gate and a TEOS oxide film in 4H-SiC.

The electrical characteristics were characterized for 4H-SiC lateral MOSFETs (see Fig. 7) using TEOS gate oxide with 90 min NO PDA as shown in Fig. 6. A MOSFET with 50 μm gate length and width is used to extract the field-effect mobility (μ _fe ). As shown in Fig. 6, the SEM cross-section shows that the physical thickness of the TEOS gate oxide is about 100 nm. μ _fe is obtained from the I _ds -V _gs transfer curves, where I _ds is the drain-source current and V _gs is the gate-source voltage.

Figure 7 is a graph of the extracted field-effect mobility (μ fe ) from a 4H-SiC horizontal MOSFET fabricated using a TEOS gate oxide treated for 90 minutes NO PDA, compared to the results for a horizontal MOSFET using a wet oxide treated for 90 minutes NO _POA .

The maximum μ _fe values of the wet oxide with 90 min NO POA and TEOS oxide with 90 min NO PDA were 11 and 17.8 cm ² /V s, respectively. The MOSFETs using the TEOS gate oxide with 90 min NO PDA exhibited much higher μ _fe than those using the wet oxide with 90 min NO POA. For the TEOS gate oxide, this improvement was expected because a high-quality nitrided SiO ₂ /SiC interface was formed by the 90 min NO PDA. Unfortunately, this extracted μ _fe value (~ 17.8 cm ² /V s) is much lower than the reported μ _fe value (~ 40 cm ² /V s) for PECVD TEOS gate oxide on 4H-SiC.

The difference in μ _fe for TEOS oxide films may be due to the difference in doping concentration in the p-well region. In contrast, the μ _fe of the wet oxide film with 90 min NO POA showed a gradual increase with increasing V _gs , indicating that Coulomb scattering was prominent. It is presumed that the combination of wet oxidation at high temperature and 90 min NO POA during (420 min) could not sufficiently form a stable nitrided oxide film at the SiC-SiO ₂ interface, resulting in a very rough MOS interface. In addition, it is expected that the μ _fe value will be improved by optimizing the NO POA time at the SiC-SiO ₂ interface.

Also, based on rough estimates, the growth rate of LPCVD TEOS oxide films is about 40 times faster than that of wet thermal oxide films. Therefore, deposition of LPCVD TEOS oxide films is an alternative technique to grow/deposit high-quality gate oxide films with shorter growth/deposition times.

FIG. 8 is a drawing for explaining the structure of a trench gate type SiC MOSFET device (1000) as a side MOSFET of the present invention.

Referring to FIG. 8, the trench gate type SiC MOSFET device (1000) of the present invention comprises: a gate oxide film (240) covering a gate trench (230) formed in a substrate (e.g., an n-type 4H-SiC substrate) (200) having an epitaxial layer (222); a doped well (e.g., BPW, bottom p-well) (225) formed under the gate oxide film (240) in the region of the gate trench (230); a gate electrode (250) formed inside the gate trench (230) covered with the gate oxide film (240); an interlayer insulating film (260) formed on the gate electrode (250); a source electrode (270) covering the upper surface of the doped layer (224, 226, 228) for the source region formed on the entire surface of the epitaxial layer of the SiC substrate (200) and the upper surface of the interlayer insulating film (260); and a SiC It includes a drain electrode (280) formed on the back surface of the substrate (200). The formation of a doped well (e.g., BPW) (225) is an optional feature that can be omitted.

The source region formed on the entire surface of the epitaxial layer (222) of the SiC substrate (200) includes doping layers (224, 226, 228) to the left and right of the gate electrode (250).

When the SiC substrate (200) is a substrate having an n-type epitaxial layer (222) as shown in the drawing, the doping layer (224, 226, 228) of the source region includes a layer in which an n + layer (228), which is a high-concentration n-type doping layer, and a p + layer (226), which is a high-concentration p-type doping layer, are side by side and adjacent to each other on a p-base layer (224), which is a low-concentration p-type doping layer.

Referring to FIG. 9 below, a method for manufacturing a trench gate type SiC MOSFET device (1000) of the present invention will be described in more detail.

FIG. 9 is a drawing for explaining a method for manufacturing a trench gate type SiC MOSFET device (1000) of the present invention.

First, referring to FIG. 3, for example, an n-type (e.g., doped with a concentration of 7 x 10 ¹⁵ cm ^-3 ) epitaxial layer (222) is formed on a substrate (210) (e.g., a 6-inch n-type 4 ^o off-axis <0001> oriented 4H-SiC substrate), and a substrate (200) is prepared by forming a doped layer (224, 226, 228) for a source region on the entire surface of the epitaxial layer (222) (S110). When the substrate (200) is a substrate having an n-type epitaxial layer as shown in the drawing, the doping layers (224, 226, 228) of the source region include layers in which an n + layer (228), which is a high-concentration n-type doping layer, and a p + layer (226), which is a high-concentration p-type doping layer, are adjacent side by side on a p-base layer (224), which is a low-concentration p-type doping layer. For example, the p-base layer (224) and the p + layer (226) can be formed by implanting Al ions, and the n + layer (228) can be formed by implanting N (nitrogen) ions.

Next, a gate trench (230) is formed by etching deeper than the doping layer (224, 226, 228) of the source region (S120). For example, SiO ₂ deposited by a plasma-enhanced chemical vapor deposition (PECVD) device may be used as an etching mask by patterning an area corresponding to an area where a gate electrode (250) is to be formed, and a trench (e.g., a trench depth of about 2 μm) may be formed through a dry etcher using an inductively coupled plasma (ICP). As an example, the trench may be formed with a cell pitch of 6.5 μm in an active area of 5 x 5 mm ² .

Next, a doped well (e.g., BPW) (225) is formed in the gate trench (230) region by, for example, injecting Al ions (S130). The formation of the doped well (e.g., BPW) (225) is an optional step that may be omitted.

Next, a gate oxide film (240) is deposited using TEOS and O ₂ (S140). For example, in a low pressure chemical vapor deposition (LPCVD) equipment, a SiO _{2 oxide film with a thickness of 50 to 110 nm can be formed in a short time (about 10 minutes) at 600 to 800° C. (preferably 700° C.) using TEOS and O 2 over} the entire trench area including the gate trench sidewall and bottom surface.

After forming the gate oxide film (240) (or after forming the doped well (e.g., BPW) (225)), the sample is subjected to a standard post-deposition heat treatment (PDA) (S150) as described above. For example, nitriding heat treatment can be performed at 800 to 1200° C. (e.g., 1175° C.) for 60 to 180 minutes (e.g., 90 minutes) in an atmosphere containing NO gas.

Next, a gate electrode (250) is formed using a conductive material such as metal or polycrystalline Si within the gate trench (230) (S160). For example, a highly doped n-type polycrystalline Si may be stacked and then patterned using CVD equipment, etc. to form the gate electrode (250). It is preferable that the upper surface of the gate electrode (250) be formed so as to be flush with the surface of the doped layer (224, 226, 228) of the epitaxial layer (222).

Next, an interlayer dielectric (260) is formed on the substrate on which the gate electrode (250) is formed (S170). The interlayer dielectric (260) may be formed of an insulating film such as SiO ₂ .

Next, the gate oxide film (240) and the interlayer insulating film (260) can be patterned simultaneously through exposure work using one mask (S180).

Next, a source electrode (270) is formed using a conductive material such as metal (e.g., Ti) (S190). For example, a source electrode (270) is formed covering the upper surface of the doping layer (224, 226, 228) for the source region formed on the entire surface of the epitaxial layer (222) of the substrate (200) and the upper surface of the interlayer insulating film (260).

Next, a drain electrode (280) is formed on the back surface of the substrate (200) using a conductive material such as a metal (e.g., a Ni/Ti alloy) (S200). Here, it goes without saying that an ohmic layer may be formed before the formation of the source electrode (270) and the drain electrode (280). Finally, the input/output pad metal connected to each of the gate electrode (250), the source electrode (270), and the drain electrode (280) may be made of Al.

As described above, according to the method for manufacturing a trench gate type SiC MOSFET device (100) according to the present invention, NO post-deposition annealing (PDA) is performed on a low-pressure CVD TEOS deposited gate oxide on a 4H-SiC substrate to improve the interface characteristics of the TEOS gate oxide/4H-SiC MOS capacitor and the lateral MOSFET, thereby providing a high-quality and stable gate oxide. In the present invention, the electrical characteristics of the low-pressure CVD TEOS deposited oxide were followed by the NO PDA method on 4H-SiC. In addition, for comparison, a wet thermal oxide was also manufactured followed by the NO POA treatment method. Improved electrical characteristics of the wet oxide and the TEOS oxide with 90 min POA/PDA were observed. In particular, the NO PDA-treated TEOS oxide had a lower leakage current and a higher breakdown field compared to the NO POA-treated wet oxide. Additionally, MOSFETs with TEOS oxide films with 90 min NO PDA showed high field-effect mobility.

Although the present invention has been described with reference to specific details such as specific components and limited examples and drawings, these have been provided only to help a more general understanding of the present invention, and the present invention is not limited to the above-described examples, and those with ordinary skill in the art to which the present invention pertains may make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the spirit of the present invention should not be limited to the described examples, and all technical ideas that are equivalent or equivalent to the scope of the following claims, as well as the claims, should be interpreted as being included in the scope of the rights of the present invention.

Substrate (210)
Gate Trench (230)
Gate oxide film (240)
Well (eg BPW) (225)
Gate electrode (250)
Interlayer insulation film (260)
Source electrode (270)
Drain electrode (280)

Claims (7)

A step of forming a gate trench by etching deeper than the doping layer in the source region of the SiC substrate;
A step of depositing a gate oxide film using TEOS and O ₂ ;
A step of performing heat treatment (PDA) after deposition of the gate oxide film in a NO atmosphere;
A step of forming a gate electrode within the gate trench;
A step of forming an interlayer insulating film on a substrate on which the gate electrode is formed;
A step of patterning the gate oxide film and the interlayer insulating film;
A step of forming a source electrode covering the upper surface of the doping layer for the source region formed on the epitaxial layer of the substrate and the upper surface of the interlayer insulating film; and
Comprising a step of forming a drain electrode on the back surface of the substrate,
For the heat treatment (PDA) after deposition of the above gate oxide film, heat treatment is performed at 800 to 1200°C for 60 to 180 minutes in an atmosphere containing NO gas.
By generating positive charges at the interface, the effective oxide charge density (Q _eff ) of the gate oxide is induced to a positive value.
A method for manufacturing a trench gate type SiC MOSFET device to increase the breakdown field (E _B ) and increase the field effect mobility (μ _fe ) to reduce leakage current. In the first paragraph,
Before the step of depositing the above gate oxide film,
A step of ion implantation to form a doped well under the gate oxide film in the gate trench region.
A method for manufacturing a trench gate type SiC MOSFET device further comprising: In the first paragraph,
A method for manufacturing a trench gate type SiC MOSFET device, wherein the substrate is a 4H-SiC substrate. In the first paragraph,
In the step of forming the gate oxide film,
A method for manufacturing a trench gate type SiC MOSFET device, comprising forming an oxide film SiO ₂ with a thickness of 50 to 110 nm on a trench region including the gate trench sidewalls and bottom surface at 600 to 800° C. using LPCVD equipment and using TEOS and O ₂ . delete delete In the first paragraph,
A method for manufacturing a trench gate type SiC MOSFET device, wherein the effective oxide charge density (Q _eff ) is in the range of 2.81Х10 ¹¹ cm ^-2 < Q _eff ≤ 4.27Х10 ¹¹ cm ^-2 .