KR102728030B1 - 3d memory with dual juction structure - Google Patents

Abstract

A three-dimensional memory having a dual junction structure is disclosed. According to one embodiment, the three-dimensional memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; and vertical channel structures that penetrate the gate electrodes and extend in the vertical direction, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having a double structure doped with different types of impurities is formed on an upper end of each of the vertical channel structures.

Description

3D MEMORY WITH DUAL JUCTION STRUCTURE

The following examples describe technologies relating to a three-dimensional structured memory, its operating method, and its manufacturing method.

Conventional DRAM supports random access in byte units, enabling high-speed memory operations, but has the disadvantage of low storage capacity.

On the other hand, existing 3D NAND flash memory can implement large storage space, but has the problem of not supporting byte-level random access because memory operations are performed in page or block units.

More specifically, referring to FIG. 1 to explain the problem of the existing three-dimensional NAND flash memory, when the existing three-dimensional NAND flash memory performs a write operation (erase operation) to record "0" data by forming a P-type channel in the channel pattern (110), a negative voltage (-V _write0 ) is applied to the selected gate electrode (120) corresponding to the target memory cell, and a positive pass voltage (+V _pass ) is applied to the remaining gate electrodes (130), so that an NPN junction is formed in the channel pattern (110). Accordingly, the erase operation for the target memory cell (111) is not performed. Therefore, the existing three-dimensional NAND flash memory performs an erase operation in units of pages or blocks using the GIDL method, and has a problem in that it cannot support random access in units of bytes.

Meanwhile, with the popularization of digital devices and sensors, big data is being generated at a scale that is difficult to estimate in real life. With the development of such big data, the memory technology field is demanding memory that supports random access to enable high-speed memory operation and implements large-capacity storage space.

Accordingly, in the embodiments below, we propose a three-dimensional memory that supports random access to enable high-speed memory operation while implementing a large storage space.

One embodiment proposes a three-dimensional memory that enables high-speed memory operation by supporting random access while implementing a large storage space, and an operating method and a manufacturing method thereof.

However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical idea and scope of the present invention.

According to one embodiment, a three-dimensional memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; and vertical channel structures that penetrate the gate electrodes and extend in the vertical direction, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having a double structure doped with different types of impurities is formed on an upper end of each of the vertical channel structures.

According to one aspect, the dual junction may be characterized by including an N+ doped N+ junction and a P+ doped P+ junction.

According to another aspect, the N+ junction and the P+ junction may be characterized by having a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern.

According to another aspect, one of the N+ junction and the P+ junction may be characterized in that, in response to a voltage applied to a selected gate electrode corresponding to a target memory cell to be a target of a memory operation among the gate electrodes during a memory operation, the selected gate electrode is selectively activated to form a channel in the vertical channel pattern.

According to another aspect, the N+ junction may be characterized by forming an N-type channel in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode.

According to another aspect, the N-type channel may be characterized in that it is formed to extend in the vertical direction so as to be connected to the N+ junction.

According to another aspect, the P+ junction may be characterized by forming a P-type channel in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode.

According to another aspect, the P-type channel,

It can be characterized by being formed to extend in the vertical direction so as to be connected to the above P+ junction.

According to another aspect, the dual junction may be characterized in that it is connected to the bit line plug through a contact plug disposed at the top.

According to another aspect, the dual junction may be characterized in that it is also formed at the bottom of each of the vertical channel structures.

According to another aspect, each of the vertical channel structures may be characterized in that a source region is formed at the bottom.

According to another aspect, the three-dimensional memory may be characterized by having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures.

According to one embodiment, a memory operation method of a three-dimensional memory including gate electrodes which are formed to extend horizontally on a substrate and are spaced apart vertically and stacked; and vertical channel structures which penetrate the gate electrodes and extend vertically, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having a dual structure doped with different types of impurities is formed on an upper end of each of the vertical channel structures, may include the steps of: applying a voltage to a selected gate electrode corresponding to a target memory cell to be a target of a memory operation among the gate electrodes; and performing a memory operation by forming a channel in the vertical channel pattern when one of an N+ junction and a P+ junction included in the dual junction is selectively activated in response to the voltage applied to the selected gate electrode.

According to one aspect, the step of applying may include a step of applying a positive voltage to the selected gate electrode, and the step of performing the memory operation may include a step of performing a write operation by forming an N-type channel in the vertical channel pattern through the N+ junction in response to the positive voltage applied to the selected gate electrode.

According to another aspect, the step of applying may include a step of adjusting a value of a positive voltage applied to the selected gate electrode, and the step of performing the memory operation may include a step of performing a write operation of a multi-valued value according to a value of the adjusted positive voltage.

According to another aspect, the step of applying may include a step of applying a negative voltage to the selected gate electrode, and the step of performing the memory operation may include a step of performing a write operation by forming a P-type channel in the vertical channel pattern through the P+ junction in response to the negative voltage applied to the selected gate electrode.

According to another aspect, a memory operation method of a three-dimensional memory, characterized in that the step of applying includes a step of adjusting a value of a negative voltage applied to the selected gate electrode, and the step of performing a memory operation includes a step of performing a write operation of a multi-valued value according to the value of the adjusted negative voltage.

According to another aspect, the step of performing the memory operation may further include the step of performing the memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction included in the dual junction formed at the bottom of each of the vertical channel structures.

According to one embodiment, a method for manufacturing a three-dimensional memory including a dual junction having a double structure, each doped with a different type of impurity, may include the steps of preparing a semiconductor structure including gate electrodes which are formed to extend horizontally on a substrate and are vertically spaced apart and stacked; and vertical channel structures which penetrate the gate electrodes and extend vertically, each of the vertical channel structures including a vertical channel pattern and a data storage pattern; disposing a first mask pattern on the semiconductor structure to cover a portion of a top surface of each of the vertical channel structures; forming an N+-doped N+ junction on a remaining top surface area of each of the vertical channel structures that is not covered by the first mask pattern using the first mask pattern; disposing a second mask pattern on the semiconductor structure to cover the remaining top surface area of each of the vertical channel structures; and forming a P+-doped P+ junction on a portion of the top surface area of each of the vertical channel structures that is not covered by the second mask pattern using the second mask pattern.

According to one aspect, the first mask pattern and the second mask pattern may be characterized in that they each cover a symmetrical region of the same area so that the N+ junction and the P+ junction in each of the vertical channel structures have a structure that is symmetrical to each other.

According to another aspect, the step of preparing the semiconductor structure may be characterized as a step of preparing the semiconductor structure in which the dual junction is formed at the bottom of each of the vertical channel structures.

According to another aspect, the step of preparing the semiconductor structure may be characterized as a step of preparing the semiconductor structure in which a source region is formed at the bottom of each of the vertical channel structures.

According to another aspect, the step of preparing the semiconductor structure may be characterized by a step of preparing the semiconductor structure having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures.

One embodiment can propose a three-dimensional memory, an operating method thereof, and a manufacturing method thereof that enables high-speed memory operation by supporting random access while implementing a large storage space.

However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

Figure 1 is a drawing to explain the problems of existing 3D NAND flash memory.
FIG. 2 is a simplified circuit diagram illustrating an array of three-dimensional memories according to one embodiment.
FIG. 3 is a plan view illustrating the structure of a three-dimensional memory according to one embodiment.
FIGS. 4A to 4C are cross-sectional views illustrating the structure of a three-dimensional memory according to one embodiment, corresponding to cross-sections taken along line A-A' of FIG. 3.
FIG. 5 is a flow chart illustrating a memory operation method of a three-dimensional memory according to one embodiment.
FIGS. 6A and 6B are cross-sectional views illustrating the structure of a three-dimensional memory to explain the memory operation method of the three-dimensional memory illustrated in FIG. 5.
FIGS. 7A and 7B are diagrams illustrating an improved memory window of a three-dimensional memory according to one embodiment.
FIG. 8 is a diagram illustrating a memory window to explain a reading operation of a three-dimensional memory according to one embodiment.
FIGS. 9A and 9B are diagrams illustrating memory windows to explain an erase operation of a three-dimensional memory according to one embodiment.
FIG. 10 is a flow chart illustrating a method for manufacturing a three-dimensional memory according to one embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by the embodiments. In addition, the same reference numerals presented in each drawing represent the same members.

In addition, the terms used in this specification are terms used to appropriately express the preferred embodiments of the present invention, and may vary depending on the intention of the viewer, operator, or the customs of the field to which the present invention belongs. Therefore, the definitions of these terms should be made based on the contents throughout this specification. For example, in this specification, the singular includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and/or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, operations, and/or elements mentioned. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part mentioned as a first part in one embodiment may be mentioned as a second part in another embodiment.

It should also be understood that the various embodiments of the present invention, while different from one another, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. It should also be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiment categories may be changed without departing from the spirit and scope of the present invention.

Hereinafter, with reference to the drawings, a three-dimensional memory that implements a large storage space while supporting random access to enable high-speed memory operation, its operating method, and its manufacturing method are described in detail.

FIG. 2 is a simplified circuit diagram illustrating an array of three-dimensional memories according to one embodiment.

Referring to FIG. 2, an array of three-dimensional memory according to one embodiment may include a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a plurality of cell strings (CSTR) arranged between the common source line (CSL) and the bit lines (BL0, BL1, BL2).

The bit lines (BL0, BL1, BL2) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, BL2). The cell strings (CSTR) may be commonly connected to the common source line (CSL) provided between the bit lines (BL0, BL1, BL2) and one common source line (CSL). At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may be arranged two-dimensionally while extending in the first direction (D1) and being spaced apart from each other along the second direction (D2). The plurality of common source lines (CSL) may be electrically the same voltage applied, but is not limited thereto, and each of the plurality of common source lines (CSL) may be electrically independently controlled so that different voltages may be applied.

The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) per bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may be composed of a ground select transistor (GST) connected to a common source line (CSL), first and second string select transistors (SST1, SST2) connected to bit lines (BL0, BL1, BL2) and connected in series, memory cell transistors (MCT) and an erase control transistor (ECT) arranged between the ground select transistor (GST) and the first and second string select transistors (SST1, SST2) and connected in series. In addition, each of the memory cell transistors (MCT) may include a data storage element.

For example, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, and the second string select transistor (SST2) may be connected to one of the bit lines (BL0, BL1, BL2). However, without being limited thereto, each of the cell strings (CSTR) may include one string select transistor. As another example, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of MOS transistors connected in series, similar to the first and second string select transistors (SST1, SST2).

A cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from common source lines (CSL). That is, the memory cell transistors (MCT) may be connected in series along a third direction (D3) between a first string select transistor (SST1) and a ground select transistor (GST). An erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) may further include dummy cell transistors (DMC) each connected between the first string select transistor (SST1) and an uppermost one of the memory cell transistors (MCT) and between the ground select transistor (GST) and a lowermost one of the memory cell transistors (MCT).

According to an embodiment, a first string select transistor (SST1) may be controlled by first string select lines (SSL1-1, SSL1-2, SSL1-3), and a second string select transistor (SST2) may be controlled by second string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may be controlled by a dummy word line (DWL), respectively. The ground select transistor (GST) may be controlled by the ground select lines (GSL0, GSL1, GSL2), and the erase control transistor (ECT) may be controlled by the erase control line (ECL). A plurality of erase control transistors (ECTs) may be provided. Common source lines (CSL) can be commonly connected to the sources of the erase control transistors (ECT).

The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and may be in an equipotential state. However, the present invention is not limited thereto, and even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be independently controlled.

The ground selection lines (GSL0, GSL1, GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) extend along the first direction (D1), are spaced apart from each other in the second direction (D2) and can be arranged two-dimensionally. The ground selection lines (GSL0, GSL1, GSL2), the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3), which are provided at substantially the same level from the common source lines (CSL), can be electrically isolated from each other. In addition, the erase control transistors (ECT) of different cell strings (CSTR) can be controlled by a common erase control line (ECL). The erase control transistors (ECT) may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and/or the common source lines (CSL) during an erase operation of the memory cell array, and gate induced leakage current may be generated in the string select transistor (SST) and/or the erase control transistors (ECT).

The string selection line (SSL) described above may be represented as an upper selection line (USL), and the ground selection line (GSL) may be represented as a lower selection line.

FIG. 3 is a plan view illustrating the structure of a three-dimensional memory according to one embodiment, and FIGS. 4a to 4c are cross-sectional views illustrating the structure of a three-dimensional memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 3.

Referring to FIGS. 3 and 4a to 4c, the substrate (SUB) may be a semiconductor substrate, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductive type impurity (e.g., P- impurity).

Laminated structures (ST) may be arranged on the substrate (SUB). The laminated structures (ST) may be arranged two-dimensionally along the second direction (D2) while being formed to extend in the first direction (D1). In addition, the laminated structures (ST) may be spaced apart from each other in the second direction (D2).

Each of the stacked structures (ST) may include gate electrodes (EL1, EL2, EL3) and interlayer insulating films (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to a top surface of a substrate (SUB). The stacked structures (ST) may have a substantially flat top surface. That is, the top surfaces of the stacked structures (ST) may be parallel to the top surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

Referring again to FIG. 2, each of the gate electrodes (EL1, EL2, EL3) may be one of the erase control line (ECL), ground select lines (GSL0, GSL1, GSL2), word lines (WL0-WLn, DWL), first string select lines (SSL1-1, SSL1-2, SSL1-3), and second string select lines (SSL2-1, SSL2-2, SSL2-3) sequentially stacked on the substrate (SUB).

Each of the gate electrodes (EL1, EL2, EL3) may be formed to extend in the first direction (D1) and have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL1, EL2, EL3) may be formed of a conductive material. For example, each of the gate electrodes (EL1, EL2, EL3) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL1, EL2, EL3) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

More specifically, the gate electrodes (EL1, EL2, EL3) may include a first gate electrode (EL1) at the lowermost position, a third gate electrode (EL3) at the uppermost position, and a plurality of second gate electrodes (EL2) between the first gate electrode (EL1) and the third gate electrode (EL3). Although the first gate electrode (EL1) and the third gate electrode (EL3) are each illustrated and described as a single number, this is exemplary and is not limited thereto, and the first gate electrode (EL1) and the third gate electrode (EL3) may be provided in plural numbers as needed. The first gate electrode (EL1) may correspond to any one of the ground selection lines (GSL0, GSL1, GLS2) illustrated in FIG. 2. The second gate electrode (EL2) may correspond to any one of the word lines (WL0-WLn, DWL) illustrated in FIG. 2. The third gate electrode (EL3) may correspond to any one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) or any one of the second string selection lines (SSL2-1, SSL2-2, SSL2-3) illustrated in FIG. 2.

Although not shown, each end of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL1, EL2, EL3) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). The third gate electrode (EL3) may have the smallest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). The first gate electrode (EL1) may have the largest length in the first direction (D1) and the smallest distance from the substrate (SUB) in the third direction (D3). By means of the step structure, each of the stacked structures (ST) can have a thickness that decreases as it gets further away from the outermost one of the vertical channel structures (VS) described below, and the side walls of the gate electrodes (EL1, EL2, EL3) can be spaced apart at a constant interval along the first direction (D1) in a planar view.

Each of the interlayer insulating films (ILDs) may have a different thickness. For example, the lowermost and uppermost of the interlayer insulating films (ILDs) may have a smaller thickness than the other interlayer insulating films (ILDs). However, this is merely an example and is not limited thereto, and the thickness of each of the interlayer insulating films (ILDs) may have a different thickness or may be set to be the same depending on the characteristics of the semiconductor device. The interlayer insulating films (ILDs) may be formed of an insulating material for insulation between the gate electrodes (EL1, EL2, EL3). For example, the interlayer insulating films (ILDs) may be formed of silicon oxide.

A plurality of channel holes (CH) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures (VS) may be formed as a plurality of cell strings (CSTR) as shown in FIG. 2 and may be extended in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical channel structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical channel structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical channel structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

The rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. For example, as illustrated in FIG. 3, rows of three vertical channel structures (VS) may penetrating one of the stacked structures (ST). However, the invention is not limited thereto, and rows of four or more vertical channel structures (VS) may penetrating one of the stacked structures (ST), or rows of one or more but not more than two vertical channel structures (VS) may penetrating one of the stacked structures (ST). In a pair of adjacent rows, the vertical channel structures (VS) corresponding to one row may be shifted in a first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent row. In a planar view, the vertical channel structures (VS) may be arranged in a zigzag shape along the first direction (D1). However, without being limited or restricted thereto, the vertical channel structures (VS) may also form an array arranged side by side in rows and columns.

Each of the vertical channel structures (VS) may be formed to extend in a third direction (D3) from the substrate (SUB). In the drawing, each of the vertical channel structures (VS) is illustrated as having a pillar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) can include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical semiconductor pattern (VSP), and a dual junction (DJ). In each of the vertical channel structures (VS), the data storage pattern (DSP) can have a pipe shape or a macaroni shape with an open bottom, and the vertical channel pattern (VCP) can have a pipe shape or a macaroni shape with a closed bottom. The vertical semiconductor pattern (VSP) can fill a space surrounded by the vertical channel pattern (VCP) and the dual junction (DJ).

The data storage pattern (DSP) may cover the inner sidewall of each of the channel holes (CH), surround the outer sidewall of the vertical channel pattern (VCP) toward the inner side, and contact the sidewalls of the gate electrodes (EL1, EL2, EL3) toward the outer side. Accordingly, the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) may, together with the regions corresponding to the second gate electrodes (EL2) of the vertical channel pattern (VCP), form memory cells in which a memory operation (a program operation, a read operation, or an erase operation) is performed by a voltage applied through the second gate electrodes (EL2). The memory cells correspond to the memory cell transistors (MCT) illustrated in FIG. 2. To this end, the data storage pattern (DSP) may be a data storage element that represents a data value by trapping charges by the voltage applied through the second gate electrodes (EL2) or maintaining the state of the charges (e.g., the polarization state of the charges).

For example, the data storage pattern (DSP) can represent binary data values or multi-valued data values by the polarization state of charge by being formed of a ferroelectric material. The ferroelectric material can include at least one of HfO _x having an orthorhombic crystal structure, HfO _x doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O ₃ ), PTO (PbTiO ₃ ), SBT (SrBi ₂ Ti ₂ O ₃ ), BLT (Bi(La, Ti)O ₃ ), PLZT (Pb(La, Zr)TiO ₃ ), BST (Bi(Sr, Ti)O ₃ ), barium titanate (BaTiO ₃ ), P(VDF-TrFE), PVDF, AlO _x , ZnO _x , TiO _x , TaO _x or InO _x .

As another example, the data storage pattern (DSP) is formed of ONO (Tunneling Oxide-Charge trap Nitride-Blocking Oxide), and can represent binary data values or multi-valued data values by trapping charges in a charge trap nitride layer.

Although the drawing illustrates that the data storage pattern (DSP) is formed to extend in a vertical direction (e.g., in the third direction (D3)), it is not limited thereto and may have a structure in which it is segmented into multiple pieces and is spaced apart only in areas corresponding to the second gate electrodes (EL2) on the outer wall of the vertical channel pattern (VCP) and the inner wall of each of the channel holes (CH).

A vertical channel pattern (VCP) can cover an inner wall of a data storage pattern (DSP) and can extend in a vertical direction (e.g., a third direction (D3)). The vertical channel pattern (VCP) can include a first portion (VCP1) and a second portion (VCP2) on the first portion (VCP1).

A first portion (VCP1) of the vertical channel pattern (VCP) can be provided at a lower portion of each of the channel holes (CH) and can be in contact with the substrate (SUB). The first portion (VCP1) of the vertical channel pattern (VCP) can be used for the purpose of blocking, suppressing, or minimizing leakage current in each of the vertical channel structures (VS) and/or for the purpose of an epitaxial pattern. A thickness of the first portion (VCP1) of the vertical channel pattern (VCP) can be, for example, greater than a thickness of the first gate electrode (EL1). A sidewall of the first portion (VCP1) of the vertical channel pattern (VCP) can be surrounded by a data storage pattern (DSP). An upper surface of the first portion (VCP1) of the vertical channel pattern (VCP) can be located at a higher level than an upper surface of the first gate electrode (EL1). More specifically, the upper surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located between the upper surface of the first gate electrode (EL1) and the lower surface of the lowermost one of the second gate electrodes (EL2). The lower surface of the first part (VCP1) of the vertical channel pattern (VCP) may be located at a level lower than the uppermost surface of the substrate (SUB) (i.e., the lower surface of the lowermost one of the interlayer insulating films (ILD)). A part of the first part (VCP1) of the vertical channel pattern (VCP) may overlap with the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction (D1) and the second direction (D2).

A second portion (VCP2) of the vertical channel pattern (VCP) may extend in a third direction (D3) from an upper surface of the first portion (VCP1). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical semiconductor pattern (VSP) and may correspond to the second gate electrodes (EL2). Accordingly, the second portion (VCP2) of the vertical channel pattern (VCP) may form memory cells together with regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP) as described above.

The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) can be substantially coplanar with the upper surface of the vertical semiconductor pattern (VSP). The upper surface of the second part (VCP2) of the vertical channel pattern (VCP) can be located at a level higher than the upper surface of the uppermost one of the second gate electrodes (EL2). More specifically, the upper surface of the second part (VCP2) of the vertical channel pattern (VCP) can be located between the upper surface and the lower surface of the third gate electrode (EL3).

A vertical channel pattern (VCP) is a component that transfers charges or holes to a data storage pattern (DSP), and may be formed of single-crystalline silicon or polysilicon to form or boost a channel by an applied voltage. However, the vertical channel pattern (VCP) is not limited thereto and may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing a leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material including at least one of In, Zn, or Ga having excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of a ZnOx series material including, for example, AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and improve transistor characteristics (e.g., threshold voltage distribution and speed of program/read operations) of at least one of the gate electrodes (EL1, EL2, EL3), thereby improving electrical characteristics of the three-dimensional memory.

In particular, the vertical channel pattern (VCP) can be formed of not only single-crystalline silicon or polysilicon, but also low-concentration p-doped material or low-concentration n-doped material for the channel forming operation of the dual junction (DJ) described below.

Although the vertical channel pattern (VCP) has been described as having a structure including a first portion (VCP1) and a second portion (VCP2), it is not limited or restricted thereto and may have a structure in which the first portion (VCP1) is excluded. For example, the vertical channel pattern (VCP) may be provided between a vertical semiconductor pattern (VSP) and a data storage pattern (DSP) that extend to a substrate (SUB) and may be formed to extend to the substrate (SUB) so as to be in contact with the substrate (SUB). In this case, a lower surface of the vertical channel pattern (VCP) may be positioned at a level lower than an uppermost surface of the substrate (SUB) (a lower surface of the lowest one of the interlayer insulating films (ILD)), and an upper surface of the vertical channel pattern (VCP) may be substantially coplanar with an upper surface of the vertical semiconductor pattern (VSP).

The vertical semiconductor pattern (VSP) can be surrounded by a second portion (VCP2) of the vertical channel pattern (VCP). An upper surface of the vertical semiconductor pattern (VSP) can be in contact with the dual junction (DJ), and a lower surface of the vertical semiconductor pattern (VSP) can be in contact with a first portion (VCP1) of the vertical channel pattern (VCP). The vertical semiconductor pattern (VSP) can be spaced apart from the substrate (SUB) in a third direction (D3). In other words, the vertical semiconductor pattern (VSP) can be electrically floated from the substrate (SUB).

The vertical semiconductor pattern (VSP) can be formed of a material that helps diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical semiconductor pattern (VSP) can be formed of a material having excellent charge and hole mobility. For example, the vertical semiconductor pattern (VSP) can be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern (VSP) can be formed of polysilicon doped with a first conductivity type impurity (e.g., P- impurity) that is the same as that of the substrate (SUB). That is, the vertical semiconductor pattern (VSP) can improve the electrical characteristics of the 3D flash memory, thereby enhancing the speed of the memory operation.

Although the vertical channel structures (VS) are described as including a vertical semiconductor pattern (VSP), the vertical semiconductor pattern (VSP) may be omitted without limitation or restriction thereto.

In addition, each of the vertical channel structures (VS) may not only have a structure in which the vertical semiconductor pattern (VSP) is omitted, but may also have a structure including a back gate (BG; not shown). In this case, the back gate (BG) may be in contact with the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP), and may be a component that applies voltage to the vertical channel pattern (VCP) for memory operation.

Referring again to FIG. 2, the vertical channel structures (VS) may correspond to channels of the erase control transistor (ECT), the first and second string select transistors (SST1, SST2), the ground select transistor (GST), and the memory cell transistors (MCT).

As illustrated in FIG. 4a, a dual junction (DJ) may be provided on the upper surface of the vertical channel pattern (VCP). That is, the dual junction (DJ) may be positioned at the upper end of each of the vertical channel structures (VS) and connected to the upper portion of the vertical channel pattern (VCP), thereby functioning as a drain junction.

A dual junction (DJ) can have a dual structure doped with different types of impurities. More specifically, the dual junction (DJ) can have a dual structure composed of an N+ doped N+ junction and a P+ doped P+ junction.

The N+ junction and the P+ junction of the dual junction (DJ) can be selectively activated to form a channel in the vertical channel pattern (VCP) in response to a voltage applied to a selected gate electrode (Sel EL) corresponding to a target memory cell to be a target of the memory operation among the gate electrodes (EL1, EL2, EL3) (more specifically, the second gate electrodes (EL2)) during a memory operation. For example, the N+ junction can perform a write operation (program operation) for writing data of "1" by forming an N-type channel in the vertical channel pattern (VCP) in response to a positive voltage applied to the selected gate electrode (Sel EL). As another example, the P+ junction can perform a write operation (erase operation) for writing data of "0" by forming a P-type channel in the vertical channel pattern (VCP) in response to a negative voltage applied to the selected gate electrode (Sel EL). That is, the N-type channel can be formed to extend vertically to connect to the N+ junction, and the P-type channel can also be formed to extend vertically to connect to the P+ junction.

At this time, the N+ junction and the P+ junction of the dual junction (DJ) may have a structure that is symmetrical to each other so as to have the same contact area with respect to the vertical channel pattern (VCP). For example, the N+ junction and the P+ junction may be formed to symmetrically divide the space located above the vertical channel pattern (VCP) as illustrated in the drawing. However, the dual junction (DJ) is not limited or restricted thereto, and may include the N+ junction and the P+ junction configured to have different contact areas with respect to the vertical channel pattern (VCP).

In this way, the contact area of each of the N+ junction and the P+ junction to the vertical channel pattern (VCP) in the dual junction (DJ) can be controlled and determined based on the operation of forming an N-type channel and the operation of forming a P-type channel in the vertical channel pattern (VCP) according to the voltage applied through the gate electrodes (EL1, EL2, EL3). For example, the contact area of each of the N+ junction and the P+ junction to the vertical channel pattern (VCP) can be controlled and determined so that a condition is satisfied that the speed of the operation of forming an N-type channel in the vertical channel pattern (VCP) in response to the positive voltage applied to the selected gate electrode (Sel EL) and the speed of the operation of forming a P-type channel in the vertical channel pattern (VCP) in response to the negative voltage applied to the selected gate electrode (Sel EL) are faster than a preset memory operation speed.

The upper surface of the dual junction (DJ) can be substantially coplanar with the upper surfaces of each of the stacked structures (ST) (i.e., the upper surface of the uppermost one of the interlayer insulating films (ILDs). The lower surface of the dual junction (DJ) can be located at a level lower than the upper surface of the third gate electrode (EL3). More specifically, the lower surface of the dual junction (DJ) can be located between the upper and lower surfaces of the third gate electrode (EL3). That is, at least a portion of the dual junction (DJ) can horizontally overlap with the third gate electrode (EL3).

A contact plug (CPG) connected to a bit line plug (BLPG) may be placed on the upper side of the dual junction (DJ). That is, the dual junction (DJ) may be connected to the bit line plug (BLPG) through the contact plug (CPG).

The reason why the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG) is because the cross-sectional area of the bit line plug (BLPG) is not large enough to apply voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (not large enough to provide current to each of the N+ junction and the P+ junction of the dual junction (DJ)). Therefore, the contact plug (CPG) may be configured with a sufficient area to apply voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (a sufficient area to provide current to each of the N+ junction and the P+ junction of the dual junction (DJ)).

In addition, the dual junction (DJ) is connected to the bit line plug (BLPG) through the contact plug (CPG) to reduce contact resistance between the dual junction (DJ) and the bit line plug (BLPG). Accordingly, the contact plug (CPG) may be formed of a material that may reduce the contact resistance between the dual junction (DJ) and the bit line plug (BLPG). For example, the contact plug (CPG) may be formed of a semiconductor or conductive material doped with impurities. For example, the contact plug (CPG) may be formed of a semiconductor material doped with impurities different from those of the substrate (SUB) or the vertical semiconductor pattern (VSP) (more precisely, impurities of a second conductive type (e.g., N-) that are different from those of the first conductive type (e.g., P-).

Above, the dual junction (DJ) has been described as being connected to the bit line plug (BLPG) through the contact plug (CPG), but it is not limited thereto and the contact plug (CPG) may be omitted. In this case, the bit line plug (BLPG) is configured with a sufficient area capable of applying voltage to each of the N+ junction and the P+ junction of the dual junction (DJ) (a sufficient area capable of providing current to each of the N+ junction and the P+ junction of the dual junction (DJ)), so that voltage can be directly applied to or current can be provided to the dual junction (DJ).

The dual junction (DJ) may also be provided below the bottom of the vertical channel pattern (VCP) as illustrated in FIG. 4b. That is, the dual junction (DJ) may be positioned at the bottom of each of the vertical channel structures (VS) and connected to the bottom of the vertical channel pattern (VCP), thereby operating as a source junction. Since the dual junction (DJ) operating as a source junction also has the same structure as the dual junction (DJ) operating as the drain junction described above, a detailed description thereof will be omitted. A source region (SR) may be formed below the dual junction (DJ) operating as a source junction in each of the vertical channel structures (VS). The source regions (SR) of each of the vertical channel structures (VS) may be connected to each other through separate wiring (not illustrated) in the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 2. However, without being limited or restricted thereto, the source region (SR) of each of the vertical channel structures (VS) may have a structure that is not connected to each other so that each of the vertical channel structures (VS) operates independently.

In addition, if a dual junction (DJ) is positioned at the bottom of each of the vertical channel structures (VS), the source region (SR) may be omitted. In this case, the dual junctions (DJ) operating as source junctions in each of the vertical channel structures (VS) may be connected to each other through separate wiring (not shown) in the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 2. However, without being limited thereto, the dual junctions (DJ) operating as source junctions in each of the vertical channel structures (VS) may have a structure in which they are not connected to each other so as to operate independently for each of the vertical channel structures (VS).

In the case where the dual junction (DJ) is positioned only at the upper end of each of the vertical channel structures (VS), a source region (SR) may be formed under the lower surface of the vertical channel pattern (VCP) as illustrated in FIG. 4a. The source regions (SR) of each of the vertical channel structures (VS) may be connected to each other through separate wiring (not illustrated) in the substrate (SUB), thereby corresponding to the common source line (CSL) of FIG. 2. However, without being limited thereto, the source regions (SR) of each of the vertical channel structures (VS) may have a structure in which they are not connected to each other so that each of the vertical channel structures (VS) operates independently.

Additionally, when the dual junction (DJ) is positioned only at the top of each of the vertical channel structures, each of the vertical channel structures (VS) may have a source free structure in which the source region (SR) is omitted below the bottom of the vertical channel pattern (VCP), as illustrated in FIG. 4c.

In addition, although not shown in the drawing, a separation trench (TR) extending in the first direction (D1) may be provided between adjacent stacked structures (ST). A common source region (CSR) may be provided inside the substrate (SUB) exposed by the separation trench (TR). The common source region (CSR) may extend in the first direction (D1) within the substrate (SUB). The common source region (CSR) may be formed of a semiconductor material doped with an impurity of the second conductivity type (e.g., an impurity of N+). The common source region (CSR) may correspond to the common source line (CSL) of FIG. 2.

A common source plug (CSP) may be provided within a separation trench (TR). The common source plug (CSP) may be connected to a common source region (CSR). An upper surface of the common source plug (CSP) may be substantially coplanar with an upper surface of each of the stacked structures (ST) (i.e., an upper surface of an uppermost one of the interlayer insulating films (ILDs). The common source plug (CSP) may have a plate shape extending in a first direction (D1) and a third direction (D3). In this case, the common source plug (CSP) may have a shape in which a width in the second direction (D2) increases as it goes in the third direction (D3).

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). The insulating spacers (SP) may be provided so as to face each other between adjacent stacked structures (ST). For example, the insulating spacers (SP) may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating film (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS) and the common source plug (CSP). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating films (ILD), an upper surface of the dual junction (DJ) and an upper surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A contact plug (CPG) and a bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

A bit line (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line (BL) corresponds to any one of a plurality of bit lines (BL0, BL1, BL2) illustrated in FIG. 2 and may be formed by extending along a second direction (D2) with a conductive material. The conductive material forming the bit line (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL1, EL2, EL3).

The bit line (BL) may be electrically connected to the vertical channel structures (VS) through a bit line contact plug (BLPG). Here, the connection of the bit line (BL) to the vertical channel structures (VS) may mean that the bit line (BL) is connected to the vertical channel pattern (VCP) through a dual junction (DJ) included in the vertical channel structures (VS).

As described above, since the rows of three vertical channel structures (VS) penetrate within the stacked structures (ST), the three vertical channel structures (VS) positioned in the same row may have their respective bit line contact plugs (BLPG) misaligned with each other so as to be connected to each of the bit lines (BL0, BL1, BL2) positioned on the same plane. For example, as illustrated in FIG. 3, the first vertical channel structure (VS1) may include a bit line contact plug (BLPG) biased in a first direction (D1) on the plane so as to be connected to the bit line (BL0), the second vertical channel structure (VS2) may include a bit line contact plug (BLPG) positioned at the center on the plane so as to be connected to the bit line (BL1), and the third vertical channel structure (VS3) may include a bit line contact plug (BLPG) biased in an opposite direction to the first direction (D1) on the plane so as to be connected to the bit line (BL2).

The three-dimensional memory according to one embodiment is not limited or restricted to the described structure, and may be implemented in various structures, assuming that it includes a vertical channel pattern (VCP), a dual junction (DJ), a data storage pattern (DSP), gate electrodes (EL1, EL2, EL3), and a bit line (BL), according to an implementation example.

The operating method and manufacturing method for a three-dimensional memory having a structure including a dual junction (DJ) as described above are described below.

FIG. 5 is a flow chart illustrating a memory operation method of a three-dimensional memory according to one embodiment, FIGS. 6a and 6b are cross-sectional views illustrating the structure of a three-dimensional memory to explain the memory operation method of the three-dimensional memory illustrated in FIG. 5, FIGS. 7a and 7b are drawings illustrating an improved memory window of a three-dimensional memory according to one embodiment, FIG. 8 is a drawing illustrating a memory window to explain a read operation of a three-dimensional memory according to one embodiment, and FIGS. 9a and 9b are drawings illustrating a memory window to explain an erase operation of a three-dimensional memory according to one embodiment.

The following memory operation method is described with reference to FIGS. 2 to 4, assuming that it is performed by a three-dimensional memory having the structure described above.

Referring to FIG. 5, in step (S510), the three-dimensional memory can apply a voltage to a selected gate electrode (Sel EL) corresponding to a target memory cell that is a target of a memory operation among the gate electrodes (EL1, EL2, EL3) (more precisely, the second gate electrode (EL2)).

Accordingly, in step (S520), the three-dimensional memory can perform a memory operation by forming a channel in the vertical channel pattern (VCP) by selectively activating one of the N+ junction and the P+ junction included in the dual junction (DJ) formed at the top of each of the vertical channel structures (VS) in response to the voltage applied to the selected gate electrode (Sel EL).

For example, the three-dimensional memory can perform a write operation by forming an N-type channel in the vertical channel pattern (VCP) through the N+ junction of the dual junction (DJ) in step (S520) by applying a positive voltage to the gate electrode (Sel EL) selected in step (S510) as illustrated in FIG. 6a. For a more specific example, the three-dimensional memory can perform a write operation (program operation) of recording data of "1" by forming an N-type channel in the vertical channel pattern (VCP) through the N+ junction of the dual junction (DJ) in step (S520) by applying a positive voltage to the gate electrode (Sel EL) selected in step (S510). Accordingly, the N-type channel can be formed to extend in the vertical direction so as to be connected to the N+ junction.

As another example, the three-dimensional memory can perform a write operation by forming a P-type channel in the vertical channel pattern (VCP) through the P+ junction of the dual junction (DJ) in step (S520) by applying a negative voltage to the gate electrode (Sel EL) selected in step (S520) as illustrated in FIG. 6b. As a more specific example, the three-dimensional memory can perform a write operation (erase operation) of writing data "0" by forming a P-type channel in step (S520) by applying a negative voltage to the gate electrode (Sel EL) selected in step (S520). Accordingly, the P-type channel can be formed to extend in the vertical direction so as to be connected to the P+ junction.

At this time, in step (S520), the three-dimensional memory can perform a memory operation by forming a channel in the vertical channel pattern (VCP) by using the dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS). Since using the dual junction (DJ) formed at the bottom of each of the vertical channel structures (VS) is accomplished through the same process as using the dual junction (DJ) formed at the top of each of the vertical channel structures (VS), a detailed description thereof will be omitted.

In this way, a three-dimensional memory according to one embodiment can support random access and enable high-speed memory operation by implementing a write operation (erase operation) that forms a P-type channel by applying a negative voltage to a selected gate electrode (Sel EL) based on a dual junction (DJ).

In addition, the three-dimensional memory can implement multi-valued operation by controlling the value of the voltage applied to the selected gate electrode (Sel EL) to various multiple values. In particular, since the three-dimensional memory can select the value of the voltage applied to the selected gate electrode (Sel EL) not only within the positive range but also within the negative range, it can implement multi-valued operation of 5 bits or more as illustrated in FIG. 7b, which is more improved than the 4-bit multi-valued operation of the existing three-dimensional NAND flash memory as illustrated in FIG. 7a. That is, the three-dimensional memory can perform a write operation (program operation) of a multi-valued value according to the controlled positive voltage value and the controlled negative voltage value by controlling the values of the positive voltage and the negative voltage applied to the selected gate electrode (Sel EL).

When the value of the voltage applied to the selected gate electrode (Sel EL) is selected within the positive and negative ranges, the read voltage (V _read ) and pass voltage (V _pass ) applied during the read operation are as shown in Fig. 8.

In addition, in this case, the erase operation can be performed in a page unit or a block unit. Specifically, the three-dimensional memory can perform the erase operation in two steps, as illustrated in FIGS. 9a and 9b. For example, the three-dimensional memory can perform the erase operation in a first step of moving memory cells programmed with a negative voltage to around a threshold voltage (V _th ) of 0 V, and a second step of moving memory cells programmed with a positive voltage to around a threshold voltage (V _th ) of 0 V. Accordingly, the program operation can be performed by applying a positive voltage or a negative voltage as described above.

The erase operation performed in two steps like this has the advantage of taking less than several ms, because, unlike the erase operation in which an erase voltage (V _erase ) of 25 V or more is applied to move the threshold voltage (V _th ) of +6 V to -4 V in a conventional 3D NAND flash memory, as illustrated in FIG. 9c, it takes less than several ms because a voltage of +/- 20 V or less is applied to move the threshold voltage (V _th ) of +6 V to 0 V and to move the threshold voltage (V _th ) of -6 V to 0 V.

FIG. 10 is a flow chart illustrating a method for manufacturing a three-dimensional memory according to one embodiment.

The manufacturing method described below is for manufacturing a three-dimensional memory having the structure described above with reference to FIGS. 2 to 4, and is assumed to be performed by an automated and mechanized manufacturing system.

Referring to FIG. 10, in step S1010, the manufacturing system can prepare a semiconductor structure (SEMI-STR). Here, the semiconductor structure (SEM-STR) can include gate electrodes (EL1, EL2, EL3) that are formed to extend horizontally on a substrate (SUB) and are spaced apart in the vertical direction and are stacked; and vertical channel structures (VS) that penetrate the gate electrodes (EL1, EL2, EL3) and extend in the vertical direction. That is, the semiconductor structure (SEMI-STR) can include the stacked structures (ST) and the vertical channel structures (VS) of the structure described above with reference to FIGS. 2 to 4. However, a dual junction (DJ) is not formed in the vertical channel structures (VS).

Here, the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a source region is formed at the bottom of each of the vertical channel structures (VS). Alternatively, the manufacturing system can prepare a semiconductor structure having a source-free structure in which the source region is omitted at the bottom of each of the vertical channel structures (VS).

As described above, when a dual junction is formed at the bottom of each of the vertical channel structures (VS), in step (S1010), the manufacturing system can prepare a semiconductor structure (SEMI-STR) in which a dual junction is formed at the bottom of each of the vertical channel structures (VS).

In step (S1020), the manufacturing system can place a first mask pattern (MASK 1) that covers a portion of an upper surface of each of the vertical channel structures (VS) on a semiconductor structure (SEMI-STR).

In step (S1030), the manufacturing system can form an N+-doped N+ junction in the remaining upper surface area of each of the vertical channel structures (VS) that is not covered by the first mask pattern (MASK 1) using the first mask pattern (MASK 1).

In step (S1040), the manufacturing system can place a second mask pattern (MASK 2) that covers the remaining area of the upper surface of each of the vertical channel structures (VS) on the semiconductor structure (SEMI-STR).

In step (S1050), the manufacturing system can form a P+-doped P+ junction in a portion of the upper surface of each of the vertical channel structures (VS) that is not covered by the second mask pattern (MASK 2) using the second mask pattern (MASK 2).

Here, the first mask pattern (MASK 1) and the second mask pattern (MASK 2) can be configured and arranged to cover symmetrical regions of the same area, respectively, so that the N+ junction and the P+ junction in each of the vertical channel structures (VS) have symmetrical structures.

In this way, a dual junction (DJ) including an N+ junction and a P+ junction can be formed in each of the vertical channel structures (VS) through steps (S1010 to S1050).

Although the manufacturing method in which a P+ junction is formed after an N+ junction is formed has been described, the method is not limited thereto and the N+ junction may be formed after the P+ junction is formed. In this case, the P+ junction may be formed before the N+ junction by performing steps (S1020 to S1030) after steps (S1040 to S1050).

Although the embodiments have been described above by way of limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, appropriate results can be achieved even if the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or are replaced or substituted by other components or equivalents.

Therefore, other implementations, other embodiments, and equivalents to the claims are also included in the scope of the claims described below.

Claims (23)

Gate electrodes are formed extending horizontally on the substrate and are vertically spaced and stacked; and
Vertical channel structures formed to extend in the vertical direction while penetrating the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having a dual structure including an N+ doped N+ junction and a P+ doped P+ junction is formed at the top of each of the vertical channel structures.
Including,
The contact area for each of the above N+ junction and the above P+ junction to the vertical channel pattern is,
The speed at which the N+ junction forms an N-type channel in the vertical channel pattern and the speed at which the P+ junction forms a P-type channel in the vertical channel pattern are controlled and determined based on this speed,
A contact plug positioned on the upper side of the dual junction to connect the dual junction with the bit line plug,
A three-dimensional memory characterized in that each of the N+ junction and the P+ junction is configured with an area capable of providing current. delete delete In the first paragraph,
Either one of the above N+ junction and the above P+ junction,
A three-dimensional memory characterized in that, in response to a voltage applied to a selected gate electrode corresponding to a target memory cell to be the target of a memory operation among the gate electrodes during a memory operation, the gate electrodes are selectively activated to form a channel in the vertical channel pattern. In paragraph 4,
The above N+ junction is,
A three-dimensional memory characterized in that an N-type channel is formed in the vertical channel pattern in response to a positive voltage applied to the selected gate electrode. In paragraph 5,
The above N-type channel is,
A three-dimensional memory characterized in that it is formed to extend in the vertical direction so as to be connected to the above N+ junction. In paragraph 4,
The above P+ junction is,
A three-dimensional memory characterized in that a P-type channel is formed in the vertical channel pattern in response to a negative voltage applied to the selected gate electrode. In Article 7,
The above P-type channel is,
A three-dimensional memory characterized in that it is formed to extend in the vertical direction so as to be connected to the above P+ junction. delete In the first paragraph,
The above dual junction is,
A three-dimensional memory characterized in that each of the above vertical channel structures is formed at the bottom. In the first paragraph,
At the bottom of each of the above vertical channel structures,
A three-dimensional memory characterized by the formation of a source region. In the first paragraph,
The above three-dimensional memory is,
A three-dimensional memory characterized by having a source free structure in which a source region is omitted at the bottom of each of the above vertical channel structures. A memory operating method comprising: a three-dimensional memory including gate electrodes formed to extend horizontally on a substrate and spaced apart vertically and stacked; and vertical channel structures formed to extend vertically and penetrate the gate electrodes, each of the vertical channel structures including a vertical channel pattern and a data storage pattern, and a dual junction having a dual structure including an N+-doped N+ junction and a P+-doped P+ junction is formed on an upper end of each of the vertical channel structures; wherein a contact area of each of the N+ junction and the P+ junction with respect to the vertical channel pattern is controlled and determined based on a speed at which the N+ junction forms an N-type channel in the vertical channel pattern and a speed at which the P+ junction forms a P-type channel in the vertical channel pattern, and a contact plug disposed on an upper end of the dual junction to connect the dual junction to a bit line plug is configured with an area capable of providing current to each of the N+ junction and the P+ junction;
A step of applying a voltage to a selected gate electrode corresponding to a target memory cell to be the target of a memory operation among the above gate electrodes; and
A step of performing a memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction in response to a voltage applied to the selected gate electrode.
A memory operation method of a three-dimensional memory including: In Article 13,
The above-mentioned steps are:
A step of applying a positive voltage to the selected gate electrode
Including,
The steps for performing the above memory operation are:
A step of performing a write operation by forming an N-type channel in the vertical channel pattern through the N+ junction in response to a positive voltage applied to the selected gate electrode.
A memory operation method of a three-dimensional memory, characterized by including a . In Article 14,
The above-mentioned steps are:
A step of controlling the value of the positive voltage applied to the selected gate electrode
Including,
The steps for performing the above memory operation are:
A step of performing a recording operation of a multi-value according to the value of the above-mentioned regulated positive voltage.
A memory operation method of a three-dimensional memory, characterized by including a . In Article 13,
The above-mentioned steps are:
A step of applying a negative voltage to the selected gate electrode
Including,
The steps for performing the above memory operation are:
A step of performing a write operation by forming a P-type channel in the vertical channel pattern through the P+ junction in response to a negative voltage applied to the selected gate electrode.
A memory operation method of a three-dimensional memory, characterized by including a . In Article 16,
The above-mentioned steps are:
A step of controlling the value of the negative voltage applied to the selected gate electrode
Including,
The steps for performing the above memory operation are:
A step of performing a recording operation of a multi-value according to the value of the above-mentioned adjusted negative voltage.
A memory operation method of a three-dimensional memory, characterized by including a . In Article 13,
The steps for performing the above memory operation are:
A step of performing a memory operation by forming a channel in the vertical channel pattern by selectively activating one of the N+ junction and the P+ junction included in the dual junction formed at the bottom of each of the vertical channel structures.
A memory operation method of a three-dimensional memory, characterized by further including: A method for manufacturing a three-dimensional memory including a dual junction having a double structure, each doped with different types of impurities,
A step of preparing a semiconductor structure including gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart and stacked; and vertical channel structures that penetrate the gate electrodes and extend vertically, each of the vertical channel structures including a vertical channel pattern and a data storage pattern;
A step of placing a first mask pattern covering a portion of an upper surface of each of the vertical channel structures on the semiconductor structure;
A step of forming an N+-doped N+ junction in the remaining upper surface area not covered by the first mask pattern of each of the vertical channel structures using the first mask pattern;
A step of arranging a second mask pattern covering the remaining area of the upper surface of each of the vertical channel structures on the semiconductor structure; and
A step of forming a P+-doped P+ junction in a portion of the upper surface that is not covered by the second mask pattern in each of the vertical channel structures using the second mask pattern.
Including,
The contact area for each of the above N+ junction and the above P+ junction to the vertical channel pattern is,
The speed at which the N+ junction forms an N-type channel in the vertical channel pattern and the speed at which the P+ junction forms a P-type channel in the vertical channel pattern are controlled and determined based on this speed,
A contact plug positioned on the upper side of the dual junction to connect the dual junction with the bit line plug,
A method for manufacturing a three-dimensional memory, characterized in that each of the N+ junction and the P+ junction is configured with an area capable of providing current. delete In Article 19,
The step of preparing the above semiconductor structure is:
A method for manufacturing a three-dimensional memory, characterized by comprising the step of preparing a semiconductor structure in which the dual junction is formed at the bottom of each of the vertical channel structures. In Article 19,
The step of preparing the above semiconductor structure is:
A method for manufacturing a three-dimensional memory, characterized by comprising the step of preparing a semiconductor structure in which a source region is formed at the bottom of each of the vertical channel structures. In Article 19,
The step of preparing the above semiconductor structure is:
A method for manufacturing a three-dimensional memory, characterized by comprising the step of preparing a semiconductor structure having a source free structure in which a source region is omitted at the bottom of each of the vertical channel structures.