KR102723603B1 - Timing generating apparatus using fpga and test apparatus using the same - Google Patents

Abstract

The purpose of the present invention is to provide a timing generation device using an FPGA (Field Programmable Gate Array), in which a delay unit formed of an FPGA can delay signals at various intervals, and a timing signal generated using signals generated in the delay unit can be transmitted to a pattern generation device, and a test device using the same. To this end, the timing generation device using an FGPA according to the present invention includes a delay unit formed of an FPGA (Field Programmable Gate Array) and which generates a first rising signal, a second rising signal, a first falling signal, and a second falling signal using a reference pulse, a generation unit which generates a first pulse signal using the first rising signal and the first falling signal, and a second pulse signal using the second rising signal and the second falling signal, and a combining unit which generates a timing signal by combining the first pulse signal and the second pulse signal.

Description

Timing generation apparatus using FPGA and test apparatus using the same {TIMING GENERATING APPARATUS USING FPGA AND TEST APPARATUS USING THE SAME}

The present invention relates to a timing generation device and a test device using the same.

A test device is used to test the performance of a memory device or semiconductor device. The memory device or semiconductor device tested by the test device is called a device under test (hereinafter, simply referred to as DUT).

The test device can generate various types of test patterns and transmit them to the DUT, analyze the patterns and various signals received from the DUT to analyze the performance of the DUT, and provide analysis results.

To this end, the test device is equipped with a pattern generation device for generating test patterns of various forms and a timing generation device for transmitting timing signals required for generating the test patterns to the pattern generation device.

The timing generator includes coarse delays and fine delays formed of integrated circuits to generate a rising signal and a falling signal constituting one timing signal.

That is, fine delays are connected to a single coarse delay composed of an FPGA (Field Programmable Gate Array), and thus, rising signals and falling signals can be generated.

In this case, at least four fine delays are required to generate one rising signal and one falling signal, and each of the fine delays must be connected to at least eight of the pins provided in the coarse delay.

Therefore, as the number of test patterns required in a test device increases, the number of timing signals must increase, and accordingly, the number of rising signals and the number of falling signals must increase, and accordingly, the number of fine delays must also increase.

However, as described above, one fine delay must be connected to at least eight pins among the pins provided in the coarse delay, and since the number of pins provided in one coarse delay is limited, it is difficult for a conventional timing generation device to generate the number of timing signals required by the test device.

In addition, the rising signal and falling signal generated in the conventional timing generator are finally combined in the pattern generator, so that one timing signal can be supplied to the pattern generator.

Therefore, in order for one timing signal to be used in the pattern generator, at least two pins must be provided in the pattern generator, and a coupling unit for coupling the rising signal and the falling signal must also be provided in the pattern generator. Accordingly, the pattern generator must also be configured with a complex structure.

The purpose of the present invention to solve the above-described problem is to provide a timing generation device using an FPGA, in which a delay unit formed of an FPGA can delay signals at various intervals, and a timing signal generated using signals generated in the delay unit can be transmitted to a pattern generation device, and a test device using the same.

According to the present invention for achieving the above-described purpose, a timing generation device using an FGPA is configured with an FPGA (Field Programmable Gate Array), and includes a delay unit which generates a first rising signal, a second rising signal, a first falling signal, and a second falling signal using a reference pulse, a generation unit which generates a first pulse signal using the first rising signal and the first falling signal, and a second pulse signal using the second rising signal and the second falling signal, and a combining unit which generates a timing signal by combining the first pulse signal and the second pulse signal.

The above timing signal can be transmitted to a pattern generating device that generates pulses.

The first pulses constituting the first pulse signal and the second pulses constituting the second pulse signal can be generated alternately from the timing signal.

The above delay unit includes a coarse delay that delays the reference pulse by a multiple of the first reference unit and a fine delay that delays signals generated from the coarse delay by a multiple of a second reference unit smaller than the first reference unit.

The above course delay can generate a first auxiliary rising signal and a second auxiliary rising signal by delaying the reference pulse by a multiple of the first reference unit, generate a first auxiliary falling signal by delaying the first auxiliary rising signal by a multiple of the first reference unit, and generate a second auxiliary falling signal by delaying the second auxiliary rising signal by a multiple of the first reference unit.

The above fine delay may generate the first rising signal by delaying the first auxiliary rising signal by a multiple of the second reference unit smaller than the first reference unit, generate the second rising signal by delaying the second auxiliary rising signal by a multiple of the second reference unit, generate the first falling signal by delaying the first auxiliary falling signal by a multiple of the second reference unit, and generate the second falling signal by delaying the second auxiliary falling signal by a multiple of the second reference unit.

The above first reference unit may be 5 nanoseconds (ns), and the above second reference unit may be 50 picoseconds (ps).

According to the present invention for achieving the above-described object, a test device includes a high-fix to which a device under test (DUT) is connected, and a test board which supplies test patterns to the device under test through the high-fix and analyzes signals transmitted from the device under test to analyze the quality of the device under test, wherein the test board includes a pattern generation device which generates the test patterns; and a timing generation device which supplies timing signals to the pattern generation device, wherein the timing generation device is configured as an FPGA (Field Programmable Gate Array) and includes a delay unit which generates a first rising signal, a second rising signal, a first falling signal, and a second falling signal using a reference pulse, a generation unit which generates a first pulse signal using the first rising signal and the first falling signal and generates a second pulse signal using the second rising signal and the second falling signal, and a combining unit which combines the first pulse signal and the second pulse signal to generate a timing signal.

The timing signal generated in the above-mentioned coupling unit can be transmitted to the pattern generating device and used to generate the test pattern.

According to the present invention, signals can be delayed at various intervals in a delay unit formed of an FPGA. Therefore, according to the present invention, there is no need to provide different types of integrated circuits to generate delay times at different intervals. Accordingly, the structure of the timing generation device can be simplified.

Additionally, since the number of components connected to the delay section composed of the FPGA can be reduced compared to the conventional one, a greater number of timing signals can be generated than the conventional one.

In addition, according to the present invention, since the finally generated timing signal can be transmitted to and utilized by the pattern generating device, the connection structure of the pattern generating device and the timing generating device can be simplified, and the internal structure of the pattern generating device can also be simplified.

Figure 1 is an exemplary diagram showing a test device according to the present invention.
Figure 2 is an exemplary diagram showing the structure of a timing generation device using an FPGA according to the present invention.
Figure 3 is an example diagram showing various signals generated in a timing generation device using the FPGA illustrated in Figure 2.

Throughout the specification, the same reference numerals refer to substantially identical components. In the following description, if it is not related to the core configuration of the present invention, detailed descriptions of the configurations and functions known in the technical field of the present invention may be omitted. The meanings of terms described in this specification should be understood as follows.

The advantages and features of the present invention, and the method for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated. The same reference numerals refer to the same components throughout the specification. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

In the present specification, when the words "includes," "has," and "consists of," are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes the plural unless there is a special explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on ~', 'upper ~', 'lower ~', 'next to ~', etc., one or more other parts may be located between the two parts, unless 'right' or 'directly' is used.

When describing a temporal relationship, for example, when describing a temporal relationship using phrases such as 'after', 'following', 'next to', or 'before', it can also include cases where there is no continuity, as long as 'right away' or 'directly' is not used.

Although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component referred to below may also be a second component within the technical concept of the present invention.

“X-axis direction”, “Y-axis direction” and “Z-axis direction” should not be interpreted as merely geometric relationships in which the relationship between them is perpendicular to each other, but may mean a wider directionality within the range in which the configuration of the present invention can function functionally.

The term "at least one" should be understood to include all combinations that can be represented from one or more of the associated items. For example, the meaning of "at least one of the first, second, and third items" can mean not only each of the first, second, or third items, but also all combinations of items that can be represented from two or more of the first, second, and third items.

The individual features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

Figure 1 is an exemplary diagram showing a test device according to the present invention.

A test device (200) according to the present invention, as illustrated in FIG. 1, includes a hypix (210) to which a device under test (UDT) (100) is connected, and a test board (230) that supplies test patterns to the device under test through the hypix and analyzes signals transmitted from the device under test to analyze the quality of the device under test. The test device (200) can be connected to an administrator terminal (300) through a network.

The administrator can control various functions of the test device (200) through the administrator terminal (300), and can monitor various test information collected from the test device (200) through the administrator terminal (300).

The above-mentioned hyfix (210) can be changed into various forms depending on the type of the test target device (100). The above-mentioned hyfix (210) performs the function of electrically connecting the test target device (100) and the test board (230).

For example, the above-described high-fix (210) is provided with a connection part (211) that is electrically connected to a test target device (100). The connection part (211) may be in the form of a slot that is connected one-to-one with a test target device (100), may be in the form of a socket board on which a plurality of test target devices (100) are mounted, or may be a pogo plate composed of a plurality of pogo pins.

The above test board (230) may be connected one-to-one with a test target device (100), or a plurality of test boards (230) may be connected to a single test target device (100), or a plurality of test target devices (100) may be connected to a single test board (230).

The test board (230) transmits test signals to a corresponding test target device (100), and, using signals received from the test target device (100) according to the test signals, can test various characteristics of the test target device (100) and whether it is operating normally.

To this end, the test board (230) includes a pattern generation device (400) that generates various types of test patterns, a timing generation device (hereinafter, simply referred to as a timing generation device) (500) using an FPGA that supplies timing signals to the pattern generation device (400), and a test board control device that controls the operation of the pattern generation device and the timing generation device.

That is, test patterns generated by the pattern generating device (400) are transmitted to the test target device (100) through the hypix (210), and signals generated in the test target device (100) by the test patterns can be transmitted to the test board control device through the hypix (210). The test board control device can analyze the signals received through the hypix (210) to test the characteristics of the test target device (100) and whether it is operating normally.

In order for the test patterns to be generated in the pattern generating device (400), timing signals must be transmitted to the pattern generating device (400).

That is, the timing generation device (500) generates timing signals used to generate test patterns and transmits them to the pattern generation device (400), and the pattern generation device (400) can generate various types of test patterns using the timing signals.

The structure and function of the above timing generator (500) are described in detail below with reference to FIGS. 2 and 3.

FIG. 2 is an exemplary diagram showing the structure of a timing generation device using an FPGA according to the present invention, and FIG. 3 is an exemplary diagram showing various signals generated in the timing generation device using the FPGA illustrated in FIG. 2.

A timing generation device (500) using an FPGA according to the present invention (hereinafter, simply referred to as a timing generation device) includes a delay unit (510), a generation unit (520), and a combination unit (530), as illustrated in FIG. 2.

The above delay unit (510) is composed of a Field Programmable Gate Array (FPGA) and generates a first rising signal (RS_B1_CLK), a second rising signal (RS_B2_CLK), a first falling signal (RS_C1_CLK), and a second falling signal (RS_C2_CLK) using a reference pulse (RP). FPGA refers to a programmable non-memory semiconductor.

That is, the delay unit (510) can generate a first rising signal (RS_B1_CLK), a second rising signal (RS_B2_CLK), a first falling signal (RS_C1_CLK), and a second falling signal (RS_C2_CLK) using a reference signal (RATE) composed of reference pulses (RP).

The above-described generating unit (520) can generate a first pulse signal (CLKa) using the first rising signal (RS_B1_CLK) and the first falling signal (RS_C1_CLK), and can generate a second pulse signal (CLKb) using the second rising signal (RS_B2_CLK) and the second falling signal (RS_C2_CLK).

The coupling unit (530) can generate a timing signal (BCCLK1) by combining the first pulse signal (CLKa) and the second pulse signal (CLKb).

The timing signal (BCCLK1) generated by the timing generation device (500) is transmitted to the pattern generation device (400) that generates a test pattern.

In this case, one test pattern can be generated by one timing signal (BCCLK1).

The structure of the above delay unit (510) is specifically described as follows.

The above delay unit (510) includes a coarse delay (511) that delays the reference pulse (RP) by a multiple of a first reference unit, and a fine delay (512) that delays signals generated from the coarse delay (511) by a multiple of a second reference unit smaller than the first reference unit.

For example, the first reference unit may be 5 nanoseconds (ns), and the second reference unit may be 50 picoseconds (ps).

The above course delay (511) can generate a first auxiliary rising signal (RS_B1_CLKa) and a second auxiliary rising signal (RS_B2_CLKa) by delaying the reference pulse (RP) by a multiple of the first reference unit, generate a first auxiliary falling signal by delaying the first auxiliary rising signal (RS_B1_CLKa) by a multiple of the first reference unit, and generate a second auxiliary falling signal by delaying the second auxiliary rising signal (RS_B2_CLKa) by a multiple of the first reference unit.

The above fine delay (512) can generate the first rising signal (RS_B1_CLK) by delaying the first auxiliary rising signal (RS_B1_CLKa) by a multiple of the second reference unit smaller than the first reference unit, generate the second rising signal (RS_B2_CLK) by delaying the second auxiliary rising signal (RS_B2_CLKa) by a multiple of the second reference unit, generate the first falling signal (RS_C1_CLK) by delaying the first auxiliary falling signal by a multiple of the second reference unit, and generate the second falling signal (RS_C2_CLK) by delaying the second auxiliary falling signal by a multiple of the second reference unit.

In this case, the first pulse signal (CLKa) can be generated using the first rising signal (RS_B1_CLK) and the first falling signal (RS_C1_CLK), and the second pulse signal (CLKb) can be generated using the second rising signal (RS_B2_CLK) and the second falling signal (RS_C2_CLK).

Hereinafter, a specific method for generating a timing signal (BCCLK1) using the configurations described above and FIG. 3 is described. In FIG. 3, the reference pulses (RP) can be delayed by a multiple of a first reference unit, for example, 5 nanoseconds (ns), and the second reference unit can be 50 picosecs (ps). That is, the width of each of the reference pulses (RP) in FIG. 3 can be 5 nanoseconds (ns) corresponding to the first reference unit, and therefore, the reference pulses (RP) output adjacent to each other can have an interval of at least 5 nanoseconds (ns).

First, the course delay (511) generates a first reference pulse (RP1) by delaying a reference pulse generated from the course delay (511) or generated from outside the course delay (511) by a multiple of the first reference unit, and generates a first auxiliary rising signal (RS_B1_CLKa) using the first reference pulse (RP1). As illustrated in FIG. 3, the first auxiliary rising signal (RS_B1_CLKa) rises at the same timing as the first reference pulse (RP1).

Next, the course delay (511) delays the first reference pulse (RP1) by a multiple of the first reference unit, for example, 5 nanoseconds (ns), to generate a second reference pulse (RP2), and generates a second auxiliary rising signal (RS_B2_CLKa) using the second reference pulse (RP2). As illustrated in FIG. 3, the second auxiliary rising signal (RS_B2_CLKa) rises at the same timing as the second reference pulse (RP2).

Next, the course delay (511) generates a third reference pulse (RP3) by delaying the second reference pulse (RP2) by a multiple of the first reference unit, generates a fourth reference pulse (RP4) by delaying the third reference pulse (RP3) by a multiple of the first reference unit, and generates a fifth reference pulse (RP4) by delaying the fourth reference pulse (RP4) by a multiple of the first reference unit.

For example, the drawing symbol C illustrated in FIG. 5 represents an area where the reference pulses are delayed by a multiple of the first reference unit by the course delay (511).

That is, the second reference pulse (RP2) is generated by delaying the first reference pulse (RP1) by 1 multiple of the first reference unit, the third reference pulse (RP3) is generated by delaying the second reference pulse (RP2) by 3 multiples of the first reference unit, the fourth reference pulse (RP4) is generated by delaying the third reference pulse (RP3) by 6 multiples of the first reference unit, and the fifth reference pulse (RP5) is generated by delaying the fourth reference pulse (RP4) by 5 multiples of the first reference unit.

In this case, the first auxiliary rising signal (RS_B1_CLKa) rises at the same timing as the first reference pulse (RP1), the third reference pulse (RP3), and the fifth reference pulse (RP5), and the second auxiliary rising signal (RS_B2_CLKa) rises at the same timing as the second reference pulse (RP2) and the fourth reference pulse (RP4).

That is, the course delay (511) delays the reference pulse (RP) by a multiple of the first reference unit to generate the first auxiliary rising signal (RS_B1_CLKa) and the second auxiliary rising signal (RS_B2_CLKa).

Next, the fine delay (512) delays the first auxiliary rising signal (RS_B1_CLKa) by a multiple of the second reference unit smaller than the first reference unit, for example, 50 picosecs (ps), to generate the first rising signal (RS_B1_CLK), and delays the second auxiliary rising signal (RS_B2_CLKa) by a multiple of the second reference unit to generate the second rising signal (RS_B2_CLK).

For example, the drawing symbol F illustrated in FIG. 3 represents a region in which the first auxiliary rising signal (RS_B1_CLKa) or the second auxiliary rising signal (RS_B2_CLKa) is delayed by a multiple of the second reference unit by the fine delay (512).

As described above, since the second reference unit can be set to a smaller value than the first reference unit, the first rising signal (RS_B1_CLK) and the second rising signal (RS_B2_CLK) having intervals of various sizes can be generated by the first reference unit and the second reference unit. Accordingly, various types of timing signals desired by a user can be formed.

Next, as described above, the first rising signal (RS_B1_CLK) and the second rising signal (RS_B2_CLK) can be generated by the coarse delay (511) and the fine delay (512), and by a similar method, the first falling signal (RS_C1_CLK) and the second falling signal (RS_C2_CLK) can be generated.

For example, the course delay (511) can generate the first auxiliary falling signal by delaying the first auxiliary rising signal (RS_B1_CLKa) by a multiple of the first reference unit, and the fine delay (512) can generate the first falling signal (RS_C1_CLK) by delaying the first auxiliary falling signal by a multiple of the second reference unit.

In addition, the course delay (511) can generate a second auxiliary falling signal by delaying the second auxiliary rising signal (RS_B2_CLKa) by a multiple of the first reference unit, and the fine delay (512) can generate the second falling signal (RS_C2_CLK) by delaying the second auxiliary falling signal by a multiple of the second reference unit.

Next, the first generator (521) of the generating unit (520) generates a first pulse signal (CLKa) using the first rising signal (RS_B1_CLK) and the first falling signal (RS_C1_CLK) transmitted from the delay unit (510).

Additionally, the second generator (522) of the generating unit (520) generates a second pulse signal (CLKb) using the second rising signal (RS_B2_CLK) and the second falling signal (RS_C2_CLK) transmitted from the delay unit (510).

That is, each of the first pulses constituting the first pulse signal (CLKa) rises when the first rising signal (RS_B1_CLK) rises, and falls when the first falling signal (RS_C1_CLK) rises. Therefore, the width of each of the first pulses constituting the first pulse signal (CLKa) is equal to the interval from when the first rising signal (RS_B1_CLK) rises until when the first falling signal (RS_C1_CLK) rises.

Additionally, each of the second pulses constituting the second pulse signal (CLKb) rises when the second rising signal (RS_B2_CLK) rises and falls when the second falling signal (RS_C2_CLK) rises. Therefore, the width of each of the second pulses constituting the second pulse signal (CLKb) is equal to the interval from when the second rising signal (RS_B2_CLK) rises to when the second falling signal (RS_C2_CLK) rises.

Next, the first pulse signal (CLKa) and the second pulse signal (CLKb) are combined at the coupling unit (530) to finally generate a timing signal (BCCLK1).

In this case, as illustrated in FIG. 3, the first pulses constituting the first pulse signal (CLKa) and the second pulses constituting the second pulse signal (CLKb) are alternately generated from the timing signal (BCCLK1).

Finally, the timing signal (BCCLK1) generated in the above-mentioned coupling unit (530) is transmitted to the pattern generating device (400) and used to generate a test pattern.

In this case, since the pattern generating device (400) directly receives the timing signal (BCCLK1), there is no need to perform additional operations related to the timing signal (BCCLK1), and a test pattern can be generated directly using the received timing signal (BCCLK1).

Therefore, compared to the structure of a conventional pattern generating device that requires additional configuration to ultimately generate a timing signal, the structure of the pattern generating device (400) applied to the present invention can be simplified.

It should be understood that the embodiments described above are exemplary in all respects and are not restrictive. The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

100: Device under test (DUT) 200: Test device
300: Admin Terminal 230: Test Board
400: Pattern generator 500: Timing generator

Claims (9)

A delay unit composed of an FPGA (Field Programmable Gate Array) that generates a first rising signal, a second rising signal, a first falling signal, and a second falling signal using a reference pulse;
A generation unit that generates a first pulse signal using the first rising signal and the first falling signal, and generates a second pulse signal using the second rising signal and the second falling signal; and
A coupling unit is included that combines the first pulse signal and the second pulse signal to generate a timing signal,
The above delay part,
A course delay that delays the above reference pulse by a multiple of the first reference unit; and
A timing generation device using an FPGA including a fine delay that delays signals generated from the above course delay by a multiple of a second reference unit smaller than the first reference unit. In paragraph 1,
A timing generation device using an FPGA in which the above timing signal is transmitted to a pattern generation device that generates pulses. In paragraph 1,
A timing generation device using an FPGA, wherein the first pulses constituting the first pulse signal and the second pulses constituting the second pulse signal are alternately generated from the timing signal. delete In paragraph 1,
The above course delay is,
A timing generation device using an FPGA that delays the reference pulse by a multiple of the first reference unit to generate a first auxiliary rising signal and a second auxiliary rising signal, delays the first auxiliary rising signal by a multiple of the first reference unit to generate a first auxiliary falling signal, and delays the second auxiliary rising signal by a multiple of the first reference unit to generate a second auxiliary falling signal. In paragraph 5,
The above fine delay is,
A timing generation device using an FPGA, which generates the first rising signal by delaying the first auxiliary rising signal by a multiple of the second reference unit smaller than the first reference unit, generates the second rising signal by delaying the second auxiliary rising signal by a multiple of the second reference unit, generates the first falling signal by delaying the first auxiliary falling signal by a multiple of the second reference unit, and generates the second falling signal by delaying the second auxiliary falling signal by a multiple of the second reference unit. In paragraph 1,
A timing generation device using an FPGA, wherein the first reference unit is 5 nanoseconds (ns) and the second reference unit is 50 picoseconds (ps). Hypix to which the Device Under Test (DUT) is connected: and
A test board is included that supplies test patterns to the test target device through the above-mentioned hyperfix and analyzes signals transmitted from the test target device to analyze the quality of the test target device.
The above test board includes a pattern generating device for generating the test patterns; and a timing generating device for supplying timing signals to the pattern generating device.
The above timing generator,
A delay unit composed of an FPGA (Field Programmable Gate Array) that generates a first rising signal, a second rising signal, a first falling signal, and a second falling signal using a reference pulse;
A generation unit that generates a first pulse signal using the first rising signal and the first falling signal, and generates a second pulse signal using the second rising signal and the second falling signal; and
A coupling unit is included that combines the first pulse signal and the second pulse signal to generate a timing signal,
The above delay part,
A course delay that delays the above reference pulse by a multiple of the first reference unit; and
A test device including a fine delay for delaying signals generated from the above course delay by a multiple of a second reference unit smaller than the first reference unit. In Article 8,
A test device in which the timing signal generated in the above-mentioned joint is transmitted to the above-mentioned pattern generating device and used to generate the above-mentioned test pattern.

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