KR102720980B1 - Thin film transistor array substrate for digital x-ray detector and the digital x-ray detector including the same - Google Patents

Abstract

The present invention provides a thin film transistor array substrate for a digital X-ray detector capable of improving a fill factor by increasing a light-receiving area of a PIN diode, and a digital X-ray detector including the same.
To this end, by forming the data line to overlap the lower portion of the PIN diode, the area where the data line is placed can be secured as the area of the PIN diode, thereby minimizing the light-receiving area of the PIN diode lost due to the data line.
In addition, since the bias line is arranged to overlap along the gate line but not to overlap with the PIN diode, the light-receiving area of the PIN diode covered by the bias line can be minimized.

Description

Thin film transistor array substrate for digital X-ray detector and X-ray detector including the same {THIN FILM TRANSISTOR ARRAY SUBSTRATE FOR DIGITAL X-RAY DETECTOR AND THE DIGITAL X-RAY DETECTOR INCLUDING THE SAME}

The present invention relates to a thin film transistor array substrate for a digital X-ray detector capable of improving fill factor and a digital X-ray detector including the same.

Since X-rays have a short wavelength, they can easily penetrate objects. The amount of penetration of X-rays is determined by the density inside the object. Therefore, by detecting the amount of penetration of X-rays through the object, the internal structure of the object can be observed.

One of the X-ray examination methods used for medical purposes is the film development method. However, in the case of the film development method, since the film must be photographed and then developed before the results can be confirmed, it takes a lot of time to confirm the results. In particular, in the case of the film development method, there are many difficulties in storing and preserving the developed film.

Accordingly, digital X-ray detectors (DXD) using thin film transistors have been developed recently and are widely used for medical purposes.

A digital X-ray detector is a device that detects the amount of X-rays passing through a subject and displays the internal state of the object to the outside.

Therefore, digital X-ray detectors have the advantage of being able to display the internal structure of a subject without using separate film and photographic paper, and of being able to check the results in real time immediately after X-ray shooting.

A digital X-ray detector detects the current inside a digital X-ray detection panel and converts it into an image, and includes various components such as a scintillator layer that converts X-rays into light, a PIN diode that reacts to light, and a driving thin film transistor that drives the diode.

In this case, the digital X-ray detector has a plurality of pixel areas including various elements as described above, and the ratio of the area occupied by the part that detects X-rays or light to one pixel area can be defined as a fill factor.

Fill factor is a key characteristic affecting the brightness and sensitivity characteristics of digital X-ray detectors. As higher resolution products become available, the pixel area size becomes smaller, requiring an even higher fill factor.

Meanwhile, X-rays irradiated by the digital X-ray detector are converted into light in the visible light range in the scintillator layer. The light in the visible light range is converted into an electronic signal in the PIN layer of the PIN diode.

Therefore, as the light-receiving area of the PIN diode increases, the fill factor can also be improved.

However, in the case of a digital X-ray detector, in addition to the various elements mentioned above, a number of wires such as gate lines, data lines, and bias lines are included, and the light-receiving area of the PIN diode may be reduced depending on the arrangement of the wires.

Accordingly, the inventors of the present invention invented a thin film transistor array substrate for a digital X-ray detector capable of improving the fill factor by increasing the light-receiving area of a PIN diode, and a digital X-ray detector including the same.

An object of the present invention is to provide a thin film transistor array substrate for an X-ray detector and a digital X-ray detector capable of minimizing a reduction in the light-receiving area of a PIN diode due to a data line.

It is also an object of the present invention to provide a thin film transistor array substrate for an X-ray detector and a digital X-ray detector capable of minimizing a reduction in the light-receiving area of a PIN diode due to a bias line.

It is also an object of the present invention to provide a thin film transistor array substrate for an X-ray detector and a digital X-ray detector capable of improving a fill factor by increasing the light-receiving area of a PIN diode.

It is also an object of the present invention to provide a thin film transistor array substrate for an X-ray detector and a digital X-ray detector capable of minimizing the occurrence of asymmetric capacitance that may occur between data lines and adjacent PIN diodes.

The purposes of the present invention are not limited to the purposes mentioned above, and other purposes and advantages of the present invention which are not mentioned can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. In addition, it will be easily understood that the purposes and advantages of the present invention can be realized by the means and combinations thereof indicated in the claims.

According to one embodiment of the present invention, a thin film transistor array substrate for a digital X-ray detector capable of improving a fill factor by increasing a light-receiving area of a PIN diode and a digital X-ray detector including the same are provided.

According to one embodiment of the present invention, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector include a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a PIN diode on the gate lines and the data lines and including a lower electrode, a PIN layer and an upper electrode, and a bias line on the PIN diode.

In this case, the data line is arranged to overlap with the PIN diode, and the bias line is arranged to overlap with the gate line.

Specifically, the bias line may be arranged parallel to the gate line, the bias line and the gate line may be arranged orthogonal to the data line, and the bias line and the gate line may not overlap with the PIN diode.

In addition, the PIN diodes are provided in multiple numbers and arranged to be spaced apart from each other, and a data line may not be arranged between the PIN diodes adjacent to each other in the first direction, and a gate line and a bias line may be arranged between the PIN diodes adjacent to each other in the second direction.

According to the present invention, by forming the data line to overlap the lower portion of the PIN diode, the area where the data line is arranged can be secured as the area of the PIN diode, thereby minimizing the light-receiving area of the PIN diode lost due to the data line.

In addition, according to the present invention, since the bias line is arranged to overlap along the gate line but not to overlap with the PIN diode, the light-receiving area of the PIN diode covered by the bias line can be minimized.

In addition, according to the present invention, the light-receiving area of the PIN diode can be maximized by minimizing the loss of the light-receiving area of the PIN diode due to the arrangement of the data line and the bias line, thereby improving the fill factor of the PIN diode.

In addition, according to the present invention, by forming the data line so as to overlap the lower portion of the PIN diode, it is possible to minimize the occurrence of asymmetric capacitance that may occur between the data line and adjacent PIN diodes due to process errors, etc. when the data line is placed between adjacent PIN diodes.

In addition to the effects described above, specific effects of the present invention are described below together with specific matters for carrying out the invention.

Figure 1 is a block diagram schematically illustrating a digital X-ray detector.
FIG. 2 is a plan view of a portion of a digital X-ray detector according to one embodiment of the present invention.
FIG. 3 is a cross-sectional view of region II' of a digital X-ray detector according to one embodiment of the present invention.
FIG. 4 is a cross-sectional view of area II-II' of a digital X-ray detector according to one embodiment of the present invention.

The above-mentioned objects, features and advantages will be described in detail below with reference to the attached drawings, so that those with ordinary skill in the art to which the present invention pertains can easily practice the technical idea of the present invention. In describing the present invention, if it is judged that a detailed description of a known technology related to the present invention may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted. Hereinafter, a preferred embodiment according to the present invention will be described in detail with reference to the attached drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

Hereinafter, the phrase “any configuration is disposed on (or below)” a component or “on (or below)” a component may mean not only that any configuration is disposed in contact with the upper surface (or lower surface) of said component, but also that another configuration may be interposed between said component and any configuration disposed on (or below) said component.

Additionally, when a component is described as being "connected," "coupled," or "connected" to another component, it should be understood that the components may be directly connected or connected to one another, but that other components may also be "interposed" between the components, or that each component may be "connected," "coupled," or "connected" through other components.

Hereinafter, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector including the same according to some embodiments of the present invention will be described.

Figure 1 is a block diagram for schematically explaining a digital X-ray detector. The digital X-ray detector may include a thin film transistor array (110), a gate driver (120), a bias supply unit (130), a readout circuit unit (140), and a timing control unit (150).

A thin film transistor array (110) may include a plurality of cell areas defined by a plurality of gate lines (Gate Lines, GL) arranged in one direction and a plurality of data lines (Data Lines, DL) arranged in one direction orthogonal to the gate lines (GL).

The cell regions are arranged in a matrix form, and each cell region can include a pixel region in which light-sensitive pixels (Pixels, P) are formed.

However, in one embodiment of the present invention, the cell area and the pixel area do not coincide, and at least a portion of a plurality of pixel areas may correspond to one cell area.

In this case, one pixel (P), or one pixel area, may mean an area where a PIN diode, which is a light-sensitive element, is placed.

A thin film transistor array (110) can detect X-rays emitted from an X-ray source, convert the detected X-rays into photoelectric signals, and output them as electrical detection signals.

Each light-detecting pixel may include a PIN diode that converts light in the visible light range converted from an X-ray by a scintillator into an electronic signal and outputs it, and a thin film transistor (TFT) that transmits a detection signal output from the PIN diode to a readout circuit unit (140). One side of the PIN diode may be connected to the thin film transistor and the other side may be connected to a bias line (BL).

The gate electrode of the thin film transistor can be connected to a gate line (GL) that transmits a scan signal, and the source/drain electrodes can be connected to a PIN diode and a data line (DL) that transmits a detection signal output from the PIN diode, respectively.

The gate driver (120) can sequentially apply gate signals to the thin film transistors of the light-sensing pixels through the gate lines (GL). The thin film transistors of the light-sensing pixels can be turned on in response to a gate signal having a gate-on voltage level.

The bias supply unit (130) can apply a driving voltage to the light-sensing pixels through the bias lines (BL). The bias supply unit (130) can selectively apply a reverse bias or a forward bias to the PIN diode.

The readout circuit unit (140) can read out a detection signal transmitted from a thin film transistor that is turned on in response to a gate signal of a gate driver. That is, a detection signal output from a PIN diode can be input to the readout circuit unit (140) through the thin film transistor and a data line (DL).

The readout circuit unit (140) can read out detection signals output from light detection pixels in an offset readout section that reads out an offset image and an X-ray readout section that reads out a detection signal after X-ray exposure.

The readout circuit unit (140) may include a signal detection unit and a multiplexer, etc. The signal detection unit may include a plurality of amplifier circuit units corresponding one-to-one with the data lines (DL), and each amplifier circuit unit may include an amplifier, a capacitor, a reset element, etc.

The timing control unit (150) can control the operation of the gate driving unit (120) by generating a start signal and a clock signal, etc. and supplying them to the gate driving unit (120). In addition, the timing control unit (150) can control the operation of the readout circuit unit (140) by generating a readout control signal and a readout clock signal, etc. and supplying them to the readout circuit unit (140).

Hereinafter, a thin film transistor substrate for a digital X-ray detector and a digital X-ray detector including the same according to one embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

First, a digital X-ray detector (200) according to one embodiment of the present invention includes a base substrate (210).

The base substrate (210) may be a glass substrate, but is not limited thereto, and when applied to a flexible digital X-ray detector, a polyimide substrate having flexible properties may be used.

On the base substrate (210), a plurality of cell areas are defined by a plurality of gate lines (223) and a plurality of data lines (225) that intersect each other orthogonally.

A PIN diode (230) including a lower electrode (231), a PIN layer (232), and an upper electrode (233) is arranged on the gate line (223) and the data line (225), and a bias line (243) is arranged on the PIN diode (230).

In this case, the data line (225) is arranged to overlap with the PIN diode (230).

Since the data line (225) is arranged to overlap the PIN diode (230) at the bottom of the PIN diode (230) as shown in FIGS. 2 and 4, the fill factor may not be reduced even if the data line (225) is arranged to overlap the PIN diode (230).

In addition, in the case where a plurality of PIN diodes (230) are provided and arranged to be spaced apart from each other, a data line (225) is not arranged between PIN diodes (230) that are adjacent to each other in the first direction (x-axis direction).

Since the data lines (225) are arranged so as to overlap the PIN diodes (230) rather than being arranged between adjacent PIN diodes (230), the space between adjacent PIN diodes (230) can be avoided as a data line (225) arrangement area, thereby increasing the area of the PIN diodes (230).

In this way, when the area of the PIN diode (230) is increased, the light-receiving area of each PIN diode (230) can be increased accordingly, thereby improving the fill factor.

In addition, since the data line (225) is not arranged between adjacent PIN diodes (230) but is arranged to overlap the PIN diodes (230), the occurrence of asymmetric capacitance that may occur between the data line (225) and adjacent PIN diodes (230) due to process errors, etc. can be minimized.

For example, if a data line is placed between adjacent PIN diodes, capacitance may occur between each PIN diode and the data line.

In this case, in order to ensure the stability of the device, it is common to form the gap between each PIN diode and the data line to be constant so that the occurrence of capacitance deviation is minimized. However, the gap between the data line and each PIN diode may not be constant due to external factors such as process errors in forming the data line and the PIN diode.

In this case, when the spacing between each PIN diode and data line is not constant, an asymmetric capacitance may occur between each PIN diode and data line, which may deteriorate the stability of the device.

However, in the case of one embodiment of the present invention, even if some process errors occur in forming the data line and the PIN diode, since the distance between the adjacent PIN diodes and the data line is considerable, excluding the PIN diode overlapping one data line, the influence is hardly felt, so that the occurrence of asymmetric capacitance due to process errors, etc. can be minimized.

Accordingly, in one embodiment of the present invention, a plurality of pixel areas, that is, at least some areas of a plurality of PIN diodes (230), are arranged to correspond to one cell area.

For example, as illustrated in FIG. 2, PIN diodes (230) corresponding to P ₁ to P ₆ are arranged to be spaced apart from each other. In this case, it can be confirmed that at least a portion of the PIN diodes (230) corresponding to P ₅ and P ₆ are arranged to be included in one cell area defined by crossing the gate line (223) and the data line (225).

Likewise, the gate line (223) and the data line (225) may be arranged so that at least a portion of the PIN diodes (230) corresponding to P ₂ and P ₃ are included in one cell area defined by crossing each other.

In this way, in one embodiment of the present invention, at least some areas of PIN diodes (230) adjacent to each other are included in one cell area defined by crossing gate lines (223) and data lines (225), and at least some areas of a plurality of PIN diodes (230) may be included in one cell area.

Meanwhile, the bias line (243) is arranged to overlap with the gate line (223).

Specifically, as shown in FIGS. 2 and 3, the bias line (243) is arranged parallel to the gate line (223), and accordingly, the bias line (243) is arranged orthogonal to the data line (225) like the gate line (223).

In this case, the bias line (243) and the gate line (223) are arranged so as not to overlap with the PIN diode (230).

Specifically, in a case where a plurality of PIN diodes (230) are provided and arranged to be spaced apart from each other, a gate line (223) and a bias line (243) can be arranged between PIN diodes (230) adjacent to each other in the second direction (y-axis direction).

For example, as illustrated in FIG. 2, PIN diodes (230) corresponding to P ₁ to P ₆ are arranged to be spaced apart from each other, and in this case, a gate line (223) and a bias line (243) may be arranged between the PIN diodes (230) corresponding to P ₂ and P ₅ .

Similarly, a gate line (223) and a bias line (243) can be placed between the PIN diodes (230) corresponding to P ₃ and P ₆ .

Since the bias line (243) is placed above the PIN diode (230), when the bias line (243) is placed so as to overlap with the PIN diode (230), the light-receiving area of the PIN diode (230) is reduced by the amount of the overlapping area.

However, in the case of one embodiment of the present invention, the bias line (243) is not arranged to overlap the PIN diode (230), but is arranged to overlap the gate line (223) in a parallel manner along the gate line (223), so that the light-receiving area of the PIN diode (230) may not be reduced.

In this way, in one embodiment of the present invention, the bias line (243) is not arranged to overlap the PIN diode (230), but rather to overlap the gate line (223), so that the light-receiving area of the PIN diode (230) is not reduced, thereby ultimately improving the fill factor.

That is, according to one embodiment of the present invention, by minimizing the light-receiving area loss of the PIN diode due to the arrangement of the data line and the bias line, the light-receiving area of the PIN diode can be maximized, thereby ultimately improving the fill factor of the PIN diode.

In one embodiment of the present invention, each thin film transistor (220) and PIN diode (230) are arranged to correspond to each other for each pixel, so that a plurality of thin film transistors (220) and a plurality of PIN diodes (230) can be formed on an array substrate having a plurality of pixel areas. Hereinafter, a description will be given based on a thin film transistor (220) and a PIN diode (230) corresponding to one pixel, and unless otherwise specified, the same can be applied to adjacent pixels.

A thin film transistor (220) including a first electrode (225a), a second electrode (225b), a gate electrode (223a), and an active layer (221) is formed on a base substrate (210).

A buffer layer (not shown) may be formed between the base substrate (210) and the thin film transistor (220). In this case, the buffer layer (not shown) may be formed of an inorganic material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx), and may be formed as a multi-buffer layer of multiple layers.

An active layer (221) is formed on the base substrate (210). The active layer (221) may be formed of an oxide semiconductor material such as IGZO (Indium Gallium Zinc Oxide), but is not limited thereto, and may be formed of low temperature polycrystalline silicon (LTPS) or amorphous silicon (a-Si).

The active layer (221) may include, for example, a channel region and conductive regions interposed between the channel regions. Specifically, the conductive regions may be divided into a first conductive region that is in direct contact with and connected to the first electrode (225a) and a second conductive region that is in direct contact with and connected to the second electrode (225b).

The conductive regions of the active layer (221) can be formed by conductiveizing both end regions of the active layer (221), and various methods such as dry etching, hydrogen plasma treatment, and helium plasma treatment can be used as the conductive treatment method.

A gate electrode (223a) is formed on the active layer (221), and a gate insulating layer (222) is formed between the active layer (221) and the gate electrode (223a), thereby insulating the active layer (221) and the gate electrode (223a) from each other.

That is, a gate electrode (223a) may be formed on the gate insulating layer (222) to correspond to the channel region of the active layer (221). The gate electrode (223a) may be one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof, and may be formed as a single layer or multiple layers.

The gate electrode (223a) may be formed by extending from the gate line (223), and the gate line (223) and the gate electrode (223a) may be aligned so that the gate electrode (223a) may be formed within the gate line (223). Accordingly, the gate line (223) and the gate electrode (223a) may be formed on the same layer.

The gate insulating layer (222) made of an inorganic material is formed to correspond to the gate electrode (223a), and may be formed to have an area equal to or larger than that of the gate electrode (223a) for effective insulation.

The gate electrode (223a) and the gate insulating layer (222) can be formed to correspond to the center of the active layer (221). Accordingly, the region of the active layer (221) that is not covered by the gate electrode (223a) and is exposed, i.e., both ends of the active layer (221) other than the channel region, can become the first conductive region and the second conductive region.

In this case, the first conductive region and the second conductive region can be the drain region and the source region, respectively.

The source region of the active layer (221) may be positioned closer to the PIN diode (230) than the drain region, but is not limited thereto, and the positions of the source region and the drain region may be swapped.

An interlayer insulating layer (224) made of an inorganic material may be formed on the gate electrode (223a) to cover the base substrate (210), and a first electrode (225a) and a second electrode (225b) may be formed on the interlayer insulating layer (224).

The first electrode (225a) and the second electrode (225b) may be formed to correspond to each side of the active layer (221) with the gate electrode (223a) therebetween. A first contact hole (224a) and a second contact hole (224b) may be formed in the interlayer insulating layer (224) to correspond to the area where the active layer (221) and the first electrode (225a) and the second electrode (225b) overlap each other.

Specifically, a first contact hole (224a) may be formed to correspond to the drain region of the active layer (221), and a second contact hole (224b) may be formed to correspond to the source region. Accordingly, the first electrode (225a) may be connected to the drain region of the active layer (221) through the first contact hole (224a), and the second electrode (225b) may be connected to the source region of the active layer (221) through the second contact hole (224b).

Accordingly, the first electrode (225a) connected to the drain region can become a drain electrode, and the second electrode (225b) connected to the source region can become a source electrode.

The first electrode (225a) and the second electrode (225b) may be formed to extend from the data line (225) and may be formed in the same layer as the data line (225).

The data line (225) may be made of one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu), or an alloy thereof, but is not limited thereto.

A first planarization layer (226) may be formed on the thin film transistor (220) to cover the entire surface of the base substrate (210) including the PIN diode (230).

The first flattening layer (226) may be made of an organic material such as PAC (Photo Acryl), but is not limited thereto.

A first passivation layer (227) may be formed on the first planarization layer (226) to cover the entire surface of the base substrate. The first passivation layer (227) may include an inorganic material such as a silicon oxide film (SiOx). The first passivation layer (227) may serve to protect the thin film transistor (220) underneath, particularly the active layer (221).

A PIN diode (230) is formed on the first passivation layer (227) and connected to the thin film transistor (220) underneath. The PIN diode (230) can be placed in the pixel area.

A PIN diode (230) may include a lower electrode (231) connected to a thin film transistor (220), a PIN layer (232) on the lower electrode (231), and an upper electrode (233) on the PIN layer (232).

The lower electrode (231) can serve as a pixel electrode in the PIN diode (230). Depending on the characteristics of the PIN diode (230), the lower electrode (231) can be made of one or more materials among an opaque metal such as molybdenum (Mo) or a transparent oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide).

The lower electrode (231) is connected to be in contact with the second electrode (225b) of the thin film transistor (220) through the third contact hole (226a), which is a contact hole of the first planarization layer (226) and the first passivation layer (227), so that the thin film transistor (220) can be connected to the PIN diode (230).

In one embodiment of the present invention, the first planarization layer (226) and the first passivation layer (227) are illustrated as sharing one contact hole, but this is not limited to the first planarization layer (226) and the first passivation layer (227) may have separate contact holes through different patterning processes.

A PIN layer (232) that converts visible light converted from X-rays into an electrical signal through a scintillator can be formed on the lower electrode (231).

The PIN layer (232) can be formed by sequentially stacking an n-type semiconductor layer containing an n-type impurity, an intrinsic semiconductor layer, and a p-type semiconductor layer containing a p-type impurity from the lower electrode (231).

The intrinsic semiconductor layer may be formed relatively thicker than the n-type semiconductor layer and the p-type semiconductor layer. The PIN layer (232) is formed to include a material capable of converting X-rays emitted from an X-ray source into electrical signals, and may include materials such as a-Se, HgI2, CdTe, PbO, PbI2, BiI3, GaAs, and Ge, for example.

An upper electrode (233) may be formed on the PIN layer (232). The upper electrode (233) may be made of one or more transparent oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide), and may improve the fill factor of the PIN diode (230).

A second passivation layer (235) may be formed on the PIN diode (230) to cover the PIN diode (230). The second passivation layer (235) may include an inorganic material such as a silicon nitride film (SiNx).

Since the silicon nitride film (SiNx) is excellent as a moisture barrier film, when the entire surface of the base substrate including the PIN diode (230) is covered with the silicon nitride film (SiNx), the influence of external moisture on the elements under the silicon nitride film (SiNx) can be minimized.

However, in order to maximize the effect as a moisture barrier, if a silicon nitride film (SiNx) is covered over the entire surface of the base substrate (210), the external moisture blocking effect may be excellent, but the path through which hydrogen in the active layer can escape to the outside may be blocked, making it difficult for hydrogen to escape to the outside.

Therefore, it is desirable to form the second passivation layer so as to effectively protect the PIN diode from external moisture while effectively discharging hydrogen from the active layer of the thin film transistor.

Accordingly, the second passivation layer (235) according to one embodiment of the present invention is preferably positioned so as to cover the PIN diode (230) but not cover at least a portion of the active layer (221) of the thin film transistor (220), more specifically, the channel region of the active layer (221).

In this way, since the second passivation layer (235) is formed to cover the entire side of the PIN diode (230), the side of the PIN diode (230) can be effectively protected from moisture or other foreign substances, and since at least a portion of the active layer (221) of the thin film transistor (220) is not covered, hydrogen in the active layer can be effectively discharged.

A second planarization layer (237) may be formed on the second passivation layer (235) to cover the entire surface of the base substrate (210) including the PIN diode (230).

The second flattening layer (237) may be made of an organic material such as PAC (Photo Acryl), but is not limited thereto.

A bias connection electrode (241) may be formed on the second planarization layer (237) on the PIN diode (230). The bias connection electrode (241) may be electrically connected to the upper electrode (233) of the PIN diode (230) through the fourth contact hole (235a), which is a contact hole of the second passivation layer (235), and the fifth contact hole (237a), which is a contact hole of the second planarization layer (237).

Additionally, a bias line (243) is arranged on the second flattening layer (237).

In this case, the bias connection electrode (241) is arranged to cover the bias line (243), so that the bias connection electrode (241) and the bias line (243) can be electrically connected to make surface contact.

In this way, the bias connection electrode (241) is electrically connected by making surface contact with the bias line (243), thereby increasing the contact area and lowering the overall resistance.

That is, one side of the bias connection electrode (241) is electrically connected to the upper electrode (233) of the PIN diode (230) through a contact hole in the second passivation layer (235), and the other side of the bias connection electrode (241) is electrically connected to the bias line (243), so that the bias voltage applied through the bias line (243) can be applied to the PIN diode (230) through the bias connection electrode (241).

In this way, in one embodiment of the present invention, since the bias line (243) is arranged so as not to overlap in order not to reduce the light-receiving area of the PIN diode (230), a bias connection electrode (241) that can electrically connect the bias line (243) and the PIN diode (230) is additionally included.

In this case, since the bias connection electrode (241) is arranged to overlap with the PIN diode (230), in order to minimize the reduction in the light-receiving area of the PIN diode (230), the bias connection electrode (241) includes at least one material among transparent oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide), so that even if the bias connection electrode (241) is arranged to overlap with the PIN diode (230), the reduction in the light-receiving area can be minimized.

A third passivation layer (244) including an inorganic material such as a silicon oxide film (SiOx) or a silicon nitride film (SiNx) may be formed on the bias connection electrode (241).

A third planarization layer (245) can be formed on the third passivation layer (244) to cover the entire surface of the base substrate (210).

The third flattening layer (245) may be made of an organic material such as PAC (Photo Acryl), but is not limited thereto.

A scintillator layer (250) may be formed on the base substrate to cover the PIN diode (230) on the third flattening layer (245).

Specifically, the scintillator layer (250) is positioned on the thin film transistor (220) and the PIN diode (230) so as to cover the thin film transistor (220) and the PIN diode (230).

Since the scintillator layer (250) can be formed by direct deposition on the array substrate (201), flattening of the lower surface of the scintillator layer (250) may be required. Accordingly, by forming a third flattening layer (245) to flatten the lower surface of the scintillator layer (250), the formation of the scintillator layer (250) by deposition of the scintillator can be facilitated.

The scintillator layer (250) may be formed in a form in which a plurality of scintillator columnar crystals are arranged in a parallel manner by being grown in a vertical direction so as to have a plurality of columnar crystal phases, but is not limited thereto. The scintillator may be formed of a material such as cesium iodide (CsI), but is not limited thereto.

The digital X-ray detector (200) according to the present invention operates as follows.

X-rays irradiated to the digital X-ray detector (200) are converted into light in the visible light range in the scintillator layer (250). The light in the visible light range is converted into an electronic signal in the PIN layer (232) of the PIN diode (230).

Specifically, when light in the visible light range is irradiated on the PIN layer (232), the intrinsic semiconductor layer is depleted by the n-type semiconductor layer and the p-type semiconductor layer, and an electric field is generated inside. Then, holes and electrons generated by the light drift by the electric field and are collected in the p-type semiconductor layer and the n-type semiconductor layer, respectively.

The PIN diode (230) converts light in the visible light range into an electronic signal and transmits it to the thin film transistor (220). The electronic signal transmitted in this manner is displayed as an image signal through the data line (225) connected to the thin film transistor (220).

According to one embodiment of the present invention as described above, a thin film transistor array substrate for a digital X-ray detector and a digital X-ray detector include a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a PIN diode on the gate lines and the data lines and including a lower electrode, a PIN layer and an upper electrode, and a bias line on the PIN diode.

In this case, the data line is arranged to overlap with the PIN diode, and the bias line is arranged to overlap with the gate line.

The bias line may be arranged parallel to the gate line, the bias line and the gate line may be arranged orthogonal to the data line, and the bias line and the gate line may not overlap the PIN diode.

In addition, the PIN diodes are provided in multiple numbers and arranged to be spaced apart from each other, and a data line may not be arranged between the PIN diodes adjacent to each other in the first direction, and a gate line and a bias line may be arranged between the PIN diodes adjacent to each other in the second direction.

In this case, each cell region among the plurality of cell regions defined by the intersection of the plurality of gate lines and the plurality of data lines may include at least a portion of regions of PIN diodes adjacent to each other in the first direction.

In addition, according to one embodiment of the present invention, a thin film transistor array substrate for a digital X-ray detector and the digital X-ray detector may include a driving thin film transistor disposed below a PIN diode, the driving thin film transistor including an active layer, a first electrode, a second electrode, and a gate electrode, a first passivation layer disposed between the PIN diode and the driving thin film transistor, and a second passivation layer disposed on the PIN diode to cover the PIN diode.

In this case, the second electrode is electrically connected to the lower electrode through a contact hole in the first passivation layer, and the second passivation layer may not cover at least a portion of the active layer.

The second passivation layer may comprise silicon nitride.

A bias connection electrode is provided on the second passivation layer, one side of the bias connection electrode is electrically connected to the upper electrode through a contact hole in the second passivation layer, and the other side of the bias connection electrode can be electrically connected to a bias line.

The bias connection electrode is arranged to cover the bias line and makes surface contact with it, and the bias connection electrode may include one or more materials among ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide).

Although the present invention has been described with reference to the drawings as examples, it is obvious that the present invention is not limited to the embodiments and drawings disclosed in this specification, and that various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. In addition, even if the effects according to the configuration of the present invention were not explicitly described while describing the embodiments of the present invention, it is natural that the effects that can be predicted by the corresponding configuration should also be recognized.

110: Thin film transistor array 120: Gate driver
130: Bias supply section 140: Power voltage supply section
150: Lead-out circuit 160: Timing control section
200 : Digital X-ray detector 210 : Base board
220: Thin film transistor 221: Active layer
222: Gate insulation layer 223: Gate line
223a: Gate electrode 224: Interlayer insulating layer
224a: 1st contact hole 224b: 2nd contact hole
225: Data line 225a: First electrode
225b: Second electrode 226: First flattening layer
227: 1st passivation layer 226a: 3rd contact hole
230: PIN diode 231: Bottom electrode
232: PIN layer 233: Top electrode
235: 2nd passivation layer 235a: 4th contact hole
237: 2nd flattening layer 237a: 5th contact hole
241: Bias connection electrode 243: Bias line
244: Third passivation layer 245: Third planarization layer
250 : Scintillator layer

Claims (12)

base board;
A plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate;
A plurality of PIN diodes, each of which is disposed on the gate line and the data line and includes a lower electrode, a PIN layer, and an upper electrode, and is arranged so as to be spaced apart from each other; and
A bias line on the PIN diode;
The above data line is arranged to overlap with the PIN diode,
The above bias line is arranged to overlap the above gate line,
A thin film transistor array substrate for a digital X-ray detector, wherein no data line is arranged between adjacent PIN diodes in the first direction. In the first paragraph,
A thin film transistor array substrate for a digital X-ray detector, wherein the above bias lines are arranged parallel to the above gate lines. In the first paragraph,
A thin film transistor array substrate for a digital X-ray detector, wherein the above bias line and the above gate line are orthogonal to the above data line. In the first paragraph,
A thin film transistor array substrate for a digital X-ray detector, wherein the above bias line and the above gate line do not overlap with the PIN diode. base board;
A plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate;
A PIN diode on the gate line and the data line, and including a lower electrode, a PIN layer, and an upper electrode; and
A bias line on the PIN diode;
The above data line is arranged to overlap with the PIN diode,
The above bias line is arranged to overlap with the above gate line,
The above PIN diodes are provided in multiples and arranged so as to be spaced apart from each other.
The data line is not arranged between the PIN diodes adjacent to each other in the first direction.
A thin film transistor array substrate for a digital X-ray detector, wherein the gate line and the bias line are arranged between the PIN diodes adjacent to each other in the second direction. In paragraph 5,
In each cell area among the plurality of cell areas defined by the intersection of the plurality of gate lines and the plurality of data lines,
A thin film transistor array substrate for a digital X-ray detector, comprising at least a portion of areas of PIN diodes adjacent to each other in the first direction. base board;
A plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate;
A PIN diode located on the gate line and the data line and including a lower electrode, a PIN layer, and an upper electrode;
Bias line on the above PIN diode;
A driving thin film transistor disposed below the PIN diode, the driving thin film transistor including an active layer, a first electrode, a second electrode, and a gate electrode;
A first passivation layer disposed between the PIN diode and the driving thin film transistor; and
A second passivation layer disposed on the PIN diode to cover the PIN diode;
The above data line is arranged to overlap with the PIN diode,
The above bias line is arranged to overlap the above gate line,
The second electrode is electrically connected to the lower electrode through a contact hole in the first passivation layer,
A thin film transistor array substrate for a digital X-ray detector, wherein the second passivation layer does not cover at least a portion of the active layer in an area that does not overlap with a contact hole in the first passivation layer. In Article 7,
A thin film transistor array substrate for a digital X-ray detector, wherein the second passivation layer comprises silicon nitride. base board;
A plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate;
A PIN diode located on the gate line and the data line and including a lower electrode, a PIN layer, and an upper electrode;
Bias line on the above PIN diode;
A driving thin film transistor disposed below the PIN diode, the driving thin film transistor including an active layer, a first electrode, a second electrode, and a gate electrode;
A first passivation layer disposed between the PIN diode and the driving thin film transistor; and
A second passivation layer disposed on the PIN diode to cover the PIN diode;
The above data line is arranged to overlap with the PIN diode,
The above bias line is arranged to overlap the above gate line,
There is a bias connection electrode on the second passivation layer,
One side of the above bias connection electrode is electrically connected to the upper electrode through a contact hole in the second passivation layer,
A thin film transistor array substrate for a digital X-ray detector, wherein the other side of the above bias connection electrode is electrically connected to the above bias line. In Article 9,
A thin film transistor array substrate for a digital X-ray detector, wherein the above bias connection electrodes are arranged to cover the above bias lines and make surface contact with each other. In Article 9,
The above bias connection electrode is a thin film transistor array substrate for a digital X-ray detector including one or more materials among ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and ZnO (Zinc Oxide). A thin film transistor array substrate for a digital X-ray detector according to any one of claims 1 to 11; and
A digital X-ray detector comprising a scintillator layer on a thin film transistor array substrate for the digital X-ray detector.