KR102720942B1 - Non-stochastic resistive switching memory device and fabrication methods - Google Patents

Abstract

A resistive switching memory device is described herein. For example, the resistive switching memory device includes a bottom electrode, a conductive layer, a resistive switching layer, and a top electrode. Additionally, two or more layers may be selected to relieve mechanical stress on the device. In various embodiments, the resistive switching layer and the conductive layer may be formed of compatible metal nitride or metal oxide materials having different nitride/oxide concentrations and different electrical resistivities. Additionally, similar materials may relieve mechanical stress on the conductive filaments and the resistive switching layer of the resistive switching memory device.

Description

{NON-STOCHASTIC RESISTIVE SWITCHING MEMORY DEVICE AND FABRICATION METHODS}

The present disclosure relates generally to electronic memories, and for example, the present disclosure describes a selector device configured to provide a non-linear current-voltage response for a memory device.

A recent innovation in the field of integrated circuit technology is resistive memory. While many of the resistive memory technologies are in the development stage, various technical concepts for resistive memory have been demonstrated by the applicant of the present invention and are in one or more stages of verification to prove or disprove the associated theory(s). Nevertheless, resistive memory technology promises to maintain substantial advantages over competing technologies in the semiconductor electronics industry.

Resistive random access memory (RRAM) is an example of resistive memory. The inventors of the present disclosure believe that RRAM has the potential to be a high-density non-volatile information storage technology. In general, RRAM stores information by controllable switching between distinct resistive states. A single resistive memory may store a single bit of information, or multiple bits, and may be configured as a one-time programmable cell, or a programmable and erasable device, such as various memory models demonstrated by the applicant.

Various theories have been proposed by the inventors to explain the resistive switching phenomenon. In one such theory, resistive switching is the result of the formation of conducting structures within an otherwise electrically insulating medium. The conducting structures may be formed from ions, atoms that can be ionized under an appropriate environment (e.g., an appropriate electric field), or other charge-carrying mechanisms. In other such theories, field-assisted diffusion of atoms may occur in response to an appropriate electrical potential applied to the resistive memory cell. In still other theories proposed by the inventors, the formation of conducting filaments may occur in response to Joule heating and electrochemical processes of binary oxides (e.g., NiO, TiO ₂ , or the like), or by redox reactions of ionic conductors including oxides, chalcogenides, polymers, and the like.

The inventors anticipate that resistive devices based on the electrode, insulator, electrode model will exhibit good durability and lifetime. Additionally, the inventors anticipate that such devices will have high on-chip density. Thus, resistive elements may be viable alternatives to metal-oxide semiconductor (MOS) transistors used for digital information storage. For example, the inventors of the present patent application believe that models for resistive-switching memory devices offer certain potential technical advantages over non-volatile flash MOS devices.

In view of the above, the inventors of the present invention endeavor to make further improvements in memory technology and resistive memory.

The following presents a simplified summary of the disclosure in order to provide a basic understanding of aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure, nor to delineate the scope of any particular embodiments of the disclosure or any of the claims. The purpose of the summary is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is provided within the disclosure.

Various embodiments of the present disclosure provide a resistive switching memory device. In some embodiments, the resistive switching memory device includes a bottom electrode, a conductive layer, a resistive switching layer, and a top electrode. Additionally, two or more layers may be selected to relieve mechanical stress on the device. In various embodiments, the resistive switching layer and the conductive layer may be formed of compatible metal nitride or metal oxide materials having different electrical resistances, which relieve mechanical stress on the resistive switching layer and the conductive filament of the resistive switching memory device.

In a further embodiment, the present disclosure provides a resistive switching device. The resistive switching device may include a bottom electrode disposed on a semiconductor substrate, and a resistive switching material comprising aluminum and nitrogen material: AlNy disposed over the bottom electrode. Additionally, the resistive switching device may include a conductive material disposed over the resistive switching material comprising aluminum and nitrogen material: AlNx, wherein y>x, and an upper electrode disposed over the conductive material.

In further embodiments, the present disclosure provides a method for forming a semiconductor device. The method may include forming a bottom electrode on a semiconductor substrate, and forming a layer of a resistive switching material including aluminum and nitrogen material: AlNy over the bottom electrode. Additionally, the method may include forming a conductive material over the resistive switching material including aluminum and nitrogen material: AlNx, wherein y>x, and forming a top electrode over the conductive material.

The following description and drawings set forth certain exemplary aspects of the disclosure. These aspects, however, are indicative of only a few of the many ways in which the principles of the disclosure may be employed. Other advantages and novel features of the disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the drawings.

Various aspects or features of the present disclosure are described with reference to the drawings, in which like reference numerals are used to represent like elements throughout. In the present specification, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the present disclosure may be practiced without these specific details or with other methods, components, materials, etc. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the present disclosure.
FIG. 1 illustrates a block diagram of an exemplary monolithic structure providing a non-stochastic resistive memory device in various disclosed embodiments.
FIG. 2 illustrates a block diagram of a sample non-stochastic resistive switching memory device according to alternative disclosed embodiments.
FIG. 3 illustrates a block diagram of a sample monolithic structure providing a non-stochastic resistive memory device in other alternative disclosed embodiments.
FIG. 4 illustrates a flowchart of a sample method for manufacturing a resistive memory device in additional embodiments.
FIG. 5 illustrates a flowchart of an exemplary method for fabricating a non-probabilistic memory device in additional embodiments.
FIG. 6 illustrates a block diagram of a sample operation and control environment for a memory device according to various disclosed embodiments.
FIG. 7 illustrates a block diagram of an exemplary computing environment that may be implemented with various embodiments.

The present disclosure relates to a selector device for a two-terminal memory cell used for storing digital information. In some embodiments, the two-terminal memory cells may comprise a resistive technology, such as a resistive-switching two-terminal memory cell. As used herein, resistive-switching two-terminal memory cells (also referred to as resistive-switching memory cells or resistive-switching memory) include circuit components having conductive contacts with an active region between two conductive contacts. In the context of a resistive-switching memory, the active region of the two-terminal memory device exhibits a plurality of stable or quasi-stable resistive states, each resistive state having a distinct electrical resistance. Furthermore, each of the plurality of states may be formed or activated in response to a suitable electrical signal applied to the two conductive contacts. The suitable electrical signal may be a voltage value, a current value, a voltage or current polarity, or the like, or a suitable combination thereof. Although not exhaustive, examples of resistive switching two-terminal memory devices may include resistive random access memory (RRAM), phase change RAM (PCRAM), and magnetic RAM (MRAM).

For a non-volatile filament-based resistive switching memory cell, the resistive switching layer (RSL) can be selected to have sufficient physical defect sites therein to trap particles in place in the absence of appropriate external stimuli, thereby mitigating particle mobility and dispersion. This forms a conductive path or filament through the RSL in response to an appropriate program voltage applied across the memory cell. Specifically, upon application of a programming bias voltage, metal ions are generated from the active metal layer and migrate into the RSL layer. More specifically, the metal ions migrate into pores or defect sites within the RSL layer. In some embodiments, upon removal of the bias voltage, the metal ions become neutral metal ions and remain trapped within the pores or defects of the RSL layer. When sufficient particles are trapped, a filament is formed, causing the memory cell to switch from a relatively high resistive state to a relatively low resistive state. More specifically, the trapped metal particles provide a conductive path or filament through the RSL layer, the resistance of which is typically determined by the tunneling resistance through the RSL layer. In some resistive-switching devices, the erase process may be implemented to deform the conductive filament, which at least partially causes the memory cell to revert from a low-resistance state to a high-resistance state. More specifically, upon application of the erase bias voltage, the trapped metal particles within the voids or defects of the RSL become mobile and migrate back toward the active metal layer. In the context of memory, this change of state may be associated with individual states of a binary bit. For an array of a plurality of memory cells, words, bytes, pages, blocks, etc., of the memory cells may be programmed or erased to represent 0s or 1s of binary information, and these states may be maintained over time to effectively store binary information. In various embodiments, multi-level information (e.g., multiple bits) can be stored within these memory cells.

It should be appreciated that various embodiments of the present disclosure may utilize various memory cell technologies having different physical properties. For example, different resistive-switching memory cell technologies may have different discrete programmable resistors, different associated program/erase voltages, as well as other distinguishing characteristics. For example, various embodiments of the present disclosure may utilize a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erase state) to an electrical signal of a second polarity. A bipolar switching device is in contrast to a unipolar device, which exhibits both a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals of the same polarity and different magnitudes.

No particular memory cell technology or program/erase voltage is specified for the various aspects and embodiments of the present disclosure, which aspects and embodiments may incorporate any suitable memory cell technology and be operated with program/erase voltages appropriate to that technology as known to those of skill in the art or as would be appreciated by those of skill in the art using the context provided herein. It should be further understood that substituting a different memory cell technology may require circuit modifications or changes to operating signal levels that would be known to those of skill in the art, and that embodiments incorporating the substituted memory cell technology(s) or signal level changes are contemplated within the scope of the present disclosure.

The inventors of the present application are familiar with additional non-volatile two-terminal memory structures in addition to resistive memory. For example, ferroelectric random access memory (RAM) is one example. Some others include magneto-resistive RAM, organic RAM, phase change RAM, and conductive bridging RAM, etc. Two-terminal memory technologies have different advantages and disadvantages, and trade-offs between the advantages and disadvantages are common. While resistive-switching memory technology is mentioned in connection with many of the embodiments disclosed herein, other two-terminal memory cells may be used with some of the disclosed embodiments as would be appropriate to one skilled in the art.

Based on extensive experimentation by the inventors, it has been believed that compressive/tensile stresses between layers of the resistive switching devices may have an undesirable effect on the long-term storage performance of the resistive switching devices they have invented. Accordingly, in various embodiments, the inventors desire that the materials for the resistive switching devices, such as the top electrode, the resistive switching material, the conductive material, and the bottom electrode, be somewhat compatible with respect to composition and/or compressive or tensile stresses. By way of example only, in some embodiments, each of the conductive layers may be a relatively conductive metal nitride, or the like, and the switching layer may be a relatively resistive metal nitride (e.g., a ceramic), or the like.

The inventors have performed controlled fabrication of resistive switching devices using various metal nitrides and have discovered a combination of materials that enables effective resistive switching devices. The use and success of aluminum nitride as a resistive switching material was surprising to the inventors, since most metal nitrides are highly conductive and therefore unsuitable as switching materials.

Referring now to the drawings, FIG. 1 illustrates a block diagram of an exemplary resistive switching memory device (100) according to one or more embodiments. The resistive switching memory device includes a top electrode (102), a resistive switching layer (104), a conductive layer (106), and a bottom electrode (108). In various embodiments, one or more other layers may be provided for interlayer adhesion, conductivity, mitigation of particle diffusion, or the like (see, e.g., FIG. 3 below).

In one or more embodiments, the resistive switching memory device (100) can include a conductive layer (106) having a composition of AlNx and an adjacent switching layer (104) having a composition of AlNy. The conductive layer can have a ratio of metal (e.g., aluminum) to nitride (MNx) in the range of about 55:45 to about 60:40. Accordingly, in some embodiments, x can be in the range of about 0.80 to about 0.60. Additionally, in various embodiments, the switching layer (104) can have a ratio of metal (e.g., aluminum) to nitride (MNy) in the range of about 50:50 to about 40:60. Accordingly, in some embodiments, y can be in the range of about 1.00 to about 1.50. As shown, in some embodiments, the relationship of y to x is: y>x. In various embodiments, based on measurements, it is believed that the conductive layer (106) can have an electrical resistance of approximately 1 Kohm to approximately 100 Kohm, and the resistive switching layer (104) can have an initial resistance of approximately 1 Mohm or greater.

In some embodiments, the conductive layer (106) and the resistive switching layer (108) may be formed of the same elements (but as compounds having different proportions). As a result, the compressive or tensile properties of these layers are expected to be similar. In view of this, the conductive filaments formed within the switching material layer are expected to experience less mechanical stress (e.g., compressive stress, tensile stress, etc.) in response to repeated heating and cooling. Accordingly, the reliability of such resistive switching devices over multiple program and erase operations is expected to increase.

In additional embodiments, the use of a metal nitride for the conductive layer (106) may provide conductive material (e.g., particles, atoms, ions, etc.) for filament formation within the resistive switching layer (104). Additionally, the metal nitride may also provide the benefit of built-in current compliance for the resistive switching device (e.g., based on the electrical resistance of the metal nitride). In some embodiments, as discussed above, the switching material for the resistive switching layer (104) may be AlNy and the conductive material for the conductive layer (106) may be AlNx, where y>x. In view of the above, it should be appreciated that other combinations of switching materials and conductive materials are within the scope of the present invention. For example, metal oxides, such as conductive AlOx and switching AlOy (wherein x<y), may also be used. Other suitable materials known to those skilled in the art or made known through the context provided herein are considered to be within the scope of the present disclosure.

FIG. 2 illustrates a block diagram of a resistive switching memory device (200) according to an alternative embodiment of the present disclosure. The resistive switching memory device (200) may include a top electrode (202), a conductive layer (204), a resistive switching layer (206), and a bottom electrode (208). The top electrode (202) and the bottom electrode (208) may be made of suitable conductive materials. Examples of materials for the top electrode (202) or the bottom electrode (208) may include metals, metal alloys, metal nitrides or metal oxides, Cu, Al, Ti, and other suitable conductors. In some embodiments, the top electrode (202) or the bottom electrode (208) may include a conductive semiconductor material (e.g., doped Si, doped polysilicon, and the like). The conductive layer (204) may include a metal nitride or metal oxide having a first concentration x of the nitride or oxide. Additionally, the resistive switching layer can include a metal nitride or metal oxide having a second concentration y of the nitride or oxide. In various embodiments, y > x.

FIG. 3 illustrates a block diagram of a sample resistive switching memory device (300) according to additional disclosed embodiments. The resistive switching memory device (300) includes a top electrode (302), a resistive switching layer (306), a conductive layer (308), and a bottom electrode (312), as described. Additionally, the resistive switching memory device (300) may include one or more additional layers or sets of layers. For example, the first set of layers (304) may include one or more of the following: a conductive layer to enhance electrical conductivity between the resistive switching layer (306) and the top electrode (302), an adhesion layer to facilitate good interlayer adhesion, a barrier layer to mitigate diffusion of particles (such as metals such as Cu, Al, O, or similar) between the layers, or an ionic layer to provide ions to another layer. In additional embodiments, the resistive switching memory device can include a second set of layers (310) including one or more of the following: a conductive layer, an adhesion layer, a barrier layer, or an ionic layer between the conductive layer (308) and the bottom electrode layer (312).

The drawings referred to above have described the interaction between some components (e.g., layers) of a memory cell, or its resistive switching layer, or a memory architecture comprised of such a memory cell. It should be understood that in some suitable alternative aspects of the present disclosure, these drawings may include the components and layers thereof, some of the components/layers indicated, or additional components/layers. Sub-components may also be implemented as electrically connected to other sub-components instead of being contained within a parent component/layer. For example, an intermediate layer(s) may be provided adjacent to one or more of the disclosed layers. As an example, a suitable barrier layer that mitigates or controls unintended oxidation may be positioned between one or more of the disclosed layers. In still other embodiments, the disclosed memory stack or set of film layers may have fewer layers than shown. For example, the switching layer may be in direct electrical contact with the conductive wire instead of having an electrode layer therebetween. Additionally, one or more of the disclosed processes may be combined into a single process that provides integrated functionality. Components of the disclosed architectures may also interact with one or more other components known to those skilled in the art, although not specifically described herein.

Considering the exemplary drawings described above, the process methods that can be implemented in accordance with the disclosed subject matter will be better understood with reference to the flowcharts of FIGS. 6-7. For clarity of explanation, the methods of FIGS. 6-7 are illustrated and described as a series of blocks, and it is intended and should be understood that the claimed subject matter is not limited by the order of the blocks, and that some blocks may occur in different orders or concurrently with other blocks from the order illustrated and described herein. Furthermore, not all blocks required to implement the methods described herein are necessarily illustrated. Additionally, it should be further understood that some or all of the methods disclosed throughout this specification can be stored on an article of manufacture to enable such methodologies to be transmitted and communicated to an electronic device. As used, the term article of manufacture is intended to encompass a computer program accessible from any computer-readable device, a device having a carrier, or a storage medium.

FIG. 4 illustrates a flowchart of an exemplary method (400) for forming a resistive switching memory device according to one or more of the disclosed other embodiments. At 402, the method (400) may include forming a bottom electrode. The bottom electrode may be formed of a suitable conductive material, such as a metal, a doped semiconductor, or the like. At 404, the method (400) may include depositing (e.g., sputtering) a resistive switching layer of a first stress-compatible material having a first concentration. The first stress-compatible material may include a metal nitride in some embodiments, or a metal oxide in other embodiments. In one embodiment, the first stress-compatible material may be a part nitride or oxide in the range of about 1.00 to about 1.50 part metal to one part metal. In additional embodiments, the resistive switching layer can be formed with a thickness in the range of about 2 nanometers (nm) to about 20 nm. At 406, the method (400) can include depositing (e.g., sputtering) a conductive layer of a second stress-compatible material having a second concentration less than the first concentration. In one embodiment, the second stress-compatible material can be the same material as the first stress-compatible material. In various embodiments, the second stress-compatible material can be a partial nitride or oxide in the range of about 0.6 to about 0.8 part metal to one part metal. In at least one embodiment, the conductive layer can be formed with a thickness in the range of about 4 nm to about 100 nm.

In various embodiments, for example, when both the conductive layer and the resistive switching layer are formed of the same materials in different proportions, both layers may be fabricated in situ. In some embodiments, to form such a device, aluminum may be initially deposited (e.g., sputtered) in an argon and nitrogen-richer environment to form the resistive switching layer (having a thickness in the range of about 2 nm to about 20 nm), and then aluminum may be deposited (e.g., sputtered) in an argon and nitrogen-poorer environment to form the conductive layer (having a thickness in the range of about 4 nm to about 100 nm) without breaking the vacuum. In other embodiments, two separate deposition processes may be used to form the two layers, with or without an air break. Materials for the top electrode and bottom electrode may also be conductive nitrides, such as titanium nitride, tantalum nitride, aluminum nitride, or the like.

FIG. 5 illustrates a flowchart of a sample method (500) according to additional embodiments of the present disclosure. At 502, the method (500) may include forming a bottom electrode over a substrate. At 504, the method (500) may include depositing a metal in a nitrogen or oxygen rich environment to form a resistive switching layer having a high electrical resistance. At 506, the method (500) may include depositing a metal or a second metal in a nitrogen or oxygen less-rich environment (e.g., as compared to reference numeral 504) to form a conductive layer having a lower electrical resistance over the resistive switching layer. At 508, the method (508) may include forming a top electrode over the conductive layer.

In various embodiments of the present disclosure, the disclosed memory or memory architectures can be utilized as standalone or embedded memory devices integrated with a CPU or microcomputer. Some embodiments can be implemented, for example, as a portion of computer memory (e.g., a random access memory, a cache memory, a read-only memory, a storage memory, or the like). Other embodiments can be implemented, for example, as a portable memory device. Examples of suitable portable memory devices can include removable memory, such as a secure digital (SD) card, a universal serial bus (USB) memory stick, a compact flash (CF) card, or the like, or suitable combinations of the foregoing. (See, e.g., FIGS. 6 and 7 below.)

NAND flash is used for compact flash devices, USB devices, SD cards, solid state drives (SSDs), and storage class memory, as well as other form factors. While NAND has proven to be a successful technology in fueling the drive to scale down to smaller devices and higher chip densities over the past decade, as the technology scales down beyond 25 nanometer (nm) memory cell technology, several structural, performance, and reliability issues have become apparent. A subset of these or similar considerations are addressed by the disclosed aspects.

FIG. 6 illustrates a block diagram of an exemplary operational and control environment (600) for a memory array (602) of a memory cell array according to aspects of the present disclosure. In at least one aspect of the present disclosure, the memory array (602) may include memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array (602) may include a two-terminal memory technology arranged in a two-dimensional or three-dimensional architecture. Exemplary architectures may include a 1T1R memory array, and a 1TnR memory array (or a 1TNR memory array), as disclosed herein. Suitable two-terminal memory technologies may include resistive-switching memory, conductive-bridging memory, phase-change memory, organic memory, magneto-resistive memory, or the like, or any suitable combination of the foregoing.

A column controller (606) and sensing amplifiers (608) may be formed adjacent the memory array (602). Additionally, the column controller (606) may be configured to activate (or identify for activation) a subset of the bit lines of the memory array (602). The column controller (606) may use control signals provided by the reference and control signal generator(s) (618) to operate on individual ones of the subset of bit lines, as well as to apply appropriate program, erase, or read voltages to these bit lines to activate them. The non-activated bit lines may be maintained at an inhibit voltage (also applied by the reference and control signal generator(s) (618)) to mitigate or avoid bit-disturbing effects on these non-activated bit lines.

In addition, the operating and control environment (600) may include a row controller (604). The row controller (604) may be formed adjacent to and electrically connected to the word lines of the memory array (602). Additionally, using control signals from the reference and control signal generator(s) (618), the row controller (604) may select specific rows of memory cells with appropriate selection voltages. Additionally, the row controller (604) may enable program, erase, or read operations by applying appropriate voltages to the selected word lines.

The sensing amplifiers (608) can read data from or write data to activated memory cells of the memory array (602) selected by the column control unit (606) and the row control unit (604). Data read from the memory array (602) can be provided to the input/output buffer (612). Similarly, data to be written to the memory array (602) can be received from the input/output buffer (612) and written to the activated memory cells of the memory array (602).

The clock source(s) (608) can provide individual clock pulses to enable timing of read, write, and program operations of the row controller (604) and the column controller (606). The clock source(s) (608) can additionally enable selection of word lines or bit lines in response to external or internal commands received by the operating and control environment (600). The input/output buffer (612) can include bidirectional data input and output as well as command and address input. Commands are provided via the command and address input, and data read from the memory array (602) as well as data to be written to the memory array (602) are transferred over the bidirectional data input and output, which enables connection to an external host device, such as a computer or other processing device (not shown, but see, for example, computer (702) of FIG. 7 below).

The input/output buffer (612) can be configured to receive write data, receive an erase command, receive a status or hold command, output read data, output status information, and receive address data for individual commands as well as address data and command data. The address data can be transmitted to the row controller (604) and the column controller (606) by the address register (610). In addition, the input data is transmitted to the memory array (602) via signal input lines between the sensing amplifiers (608) and the input/output buffer (612), and the output data is received from the memory array (602) via signal output lines from the sensing amplifiers (608) to the input/output buffer (612). The input data can be received from a host device, and the output data can be transmitted to the host device via an I/O bus.

Commands received from the host device may be provided to the command interface (616). The command interface (616) may be configured to receive external control signals from the host device and to determine whether data input to the input/output buffer (612) is write data, a command, or an address. The input commands may be transmitted to a state machine (620).

The state machine (620) may be configured to manage programming and reprogramming of the memory array (602) (as well as other memory banks of the multi-bank memory array). Commands provided to the state machine (620) are implemented in accordance with control logic configurations that enable the state machine to manage reads, writes, data inputs, data outputs, and other functions associated with the memory cell array (602). In some aspects, the state machine (620) may send and receive acknowledgements and negative acknowledgments in connection with successful receipt or execution of various commands. In additional embodiments, the state machine (620) may decode and implement state-related commands, decode and implement configuration commands, etc.

To implement functions such as read, write, input, and output, the state machine (620) can control clock source(s) (608) or reference and control signal generator(s) (618). Control of the clock source(s) (608) can cause output pulses to be configured to enable the row controller (604) and the column controller (606) to implement specific functions. The output pulses can be transmitted to bit lines selected by, for example, the column controller (606), or to word lines selected by, for example, the row controller (604).

With respect to FIG. 7, the systems and processes described below may be implemented in hardware, such as a single integrated circuit (IC) chip, multiple ICs, an application specific integrated circuit (ASIC), or the like. Additionally, the order of some or all of the process blocks appearing in each process should not be considered limiting. Rather, it should be understood that some of the process blocks may be executed in various orders, not all of which may be explicitly illustrated herein.

Referring to FIG. 7, a suitable operating environment (700) for implementing various aspects of the claimed subject matter includes a computer (702). The computer (702) includes a processing unit (704), a system memory (706), a codec (735), and a system bus (708). The system bus (708) couples system components, including but not limited to the system memory (706), to the processing unit (704). The processing unit (704) may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be utilized as the processing unit (704).

The system bus (708) may be any of several types of bus architectures including a memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any of a variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

The system memory (706) includes volatile memory (710) and non-volatile memory (714), which may utilize one or more of the memory architectures disclosed in various embodiments. For example, a basic input/output system (BIOS), which includes basic routines for transferring information between elements within the computer (702) during startup, is stored in the non-volatile memory (712). In addition, according to the present innovations, the codec (735) may include at least one of an encoder or a decoder, wherein at least one of the encoder or decoder may be comprised of hardware, software, or a combination of hardware and software. Although the codec (735) is depicted as a separate component, the codec (735) may be included within the non-volatile memory (712). By way of non-limiting example, non-volatile memory (712) may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Non-volatile memory (712) may utilize one or more of the memory architectures disclosed in at least some disclosed embodiments. Additionally, non-volatile memory (712) may be computer memory or removable memory (e.g., physically integrated with the computer (702) or a motherboard thereof). Examples of suitable removable memory that may be implemented with the disclosed embodiments may include a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) memory stick, or the like. Volatile memory (710) includes random access memory (RAM) that acts as external cache memory, and may also utilize one or more of the memory architectures disclosed in various embodiments. By way of non-limiting example, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM), etc.

The computer (702) may also include removable/non-removable, volatile/non-volatile computer storage media. FIG. 7 illustrates, for example, disk storage (714). The disk storage (714) includes, but is not limited to, devices such as a magnetic disk drive, a solid state disk (SSD) floppy disk drive, a tape drive, a Jazz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. In addition, the disk storage (714) may include storage media separate or in combination with other storage media, including, but not limited to, an optical disk drive, such as a compact disk ROM drive (CD-ROM), a CD recordable drive (CD-R drive), a CD rewritable drive (CD-RW drive), or a digital versatile disk ROM drive (DVD-ROM). To enable connection of the disk storage (714) to the system bus (708), a removable or non-removable interface, such as the interface (716), is typically used. It should be appreciated that the disk storage (714) may store information about the user. Such information may be stored on or provided to a server or to an application running on the user device. In one embodiment, the user may be notified (e.g., using the output device(s) (736)) of the type of information transmitted to the server or application and/or stored in the disk storage (714). The user may be provided with an opportunity to consent (opt-in) or opt-out (e.g., using the input device(s) (728)) of such information being shared with or collected by the server or application.

It will be appreciated that FIG. 7 illustrates software that acts as an intermediary between the basic computer resources and users described within a suitable operating environment (700). This software includes an operating system (718). The operating system (718), which may be stored on disk storage (714), operates to control and allocate the resources of the computer (702). Applications (720) utilize the management of resources by the operating system (718) via program data (726) and program modules (724), such as a boot/shutdown transaction table and the like, stored within system memory (706) or on disk storage (714). It will be appreciated that the claimed subject matter may be implemented with various operating systems or combinations of operating systems.

A user enters commands or information into the computer (702) via input device(s) (728). The input devices (728) include, but are not limited to, pointing devices such as a mouse, a trackball, a stylus, a touch pad, a keyboard, a microphone, a joystick, a game pad, a satellite dish, a scanner, a TV tuner card, a digital camera, a digital video camera, a web camera, and the like. These and other input devices are connected to the processing unit (704) via the system bus (708) via interface port(s) (730). The interface port(s) (730) include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). The output device(s) (736) use some of the same types of ports as the input device(s) (728). Thus, for example, a USB port may be used to provide input to the computer (702) and to output information from the computer (702) to the output device (736). The output adapter (734) is provided to illustrate that there are some output devices, such as monitors, speakers, and printers, that require special adapters, among other output devices. The output adapters (734) may include, by way of non-limiting example, video and sound cards that provide a means of connection between the output device (736) and the system bus (708). It should be noted that other devices or systems of devices, such as remote computer(s) (738), may provide both input and output capabilities.

The computer (702) may operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) (738). The remote computer(s) (738) may be a personal computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device, a smart phone, a tablet, or other network node, and typically include many of the elements described with respect to the computer (702). For simplicity, only a memory storage device (740) is illustrated with the remote computer(s) (738). The remote computer(s) (738) is logically connected to the computer (702) via a network interface (742) and subsequently via connected communication connection(s) (744). The network interface (742) encompasses wired and/or wireless communication networks, such as local-area networks (LANs) and wide-area networks (WANs), and cellular networks. LAN technologies include, but are not limited to, Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and its variants, packet-switched networks, and Digital Subscriber Lines (DSL).

The communication connection(s) (744) refers to the hardware/software used to connect the network interface (742) to the system bus (708). For purposes of illustration and clarity, the communication connection (744) is shown as being internal to the computer (702), although it may also be external to the computer (702). The hardware/software required to connect to the network interface (742) includes, for illustration purposes only, internal and external technologies such as modems, including standard telephone grade modems, cable modems and DSL modems, ISDN adapters, and wired and wireless Ethernet cards, hubs, and routers.

The illustrative aspects of the present disclosure may also be implemented in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or stored information, instructions, or the like may be located in local or remote memory storage devices.

It will also be appreciated that the various components described herein may include electrical circuit(s) that may include circuit elements and components of suitable values to implement embodiments of the present disclosure. It will also be appreciated that many of the various components may be implemented on one or more IC chips. For example, in one embodiment, a set of components may be implemented within a single IC chip. In other embodiments, one or more of the individual components are fabricated or implemented on separate IC chips.

The terms "component," "system," "architecture," and the like, as used herein, are intended to refer to a computer or electronic-related entity, as well as hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component may be one or more transistors, a memory cell, an array of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on a processor, a semiconductor memory, an object executable program or application accessing or interfacing with a computer, or the like, or any suitable combination thereof. A component may include erasable programming (e.g., process instructions stored at least partially in erasable memory) or hard programming (e.g., process instructions burned into non-erasable memory during manufacture).

By way of example, both a processor and a processor executing from memory can be components. As another example, an architecture can include an arrangement of electronic hardware (e.g., parallel or series transistors), processing instructions, and a processor that implements the processing instructions in a manner suitable for the arrangement of electronic hardware. In addition, an architecture can include a single component (e.g., a transistor, a gate array, ...) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array coupled to a program circuit, power leads, electrical grounds, input signal lines and output signal lines, etc.). A system can include one or more components as well as one or more architectures. An exemplary system can include a switching block architecture including power supply(s), signal generator(s), communication bus(es), controllers, I/O interfaces, address registers, etc., as well as crossed input/output lines and pass gate transistors. Some overlapping definitions are expected, and it will be appreciated that a system or architecture can be a standalone component, or a component of another architecture, system, etc.

In addition to the foregoing, the disclosed subject matter can be implemented as a method, apparatus, or article of manufacture using typical manufacturing, programming, or engineering techniques to produce hardware, firmware, software, or any suitable combination thereof, for controlling an electronic device to implement the disclosed subject matter. The terms "apparatus" and "article of manufacture" as used herein are intended to encompass an electronic device, a semiconductor device, a computer, or a computer program accessible from any computer-readable device, carrier, or medium. The computer-readable medium can include a hardware medium, or a software medium. In addition, the medium can include a non-transitory medium, or a carrier medium. In one example, the non-transitory medium can include a computer-readable hardware medium. Specific examples of computer-readable media can include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, ...), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), ...), smart cards, and flash memory devices (e.g., cards, sticks, key drives, ...). A computer-readable carrier medium can include a carrier wave, or the like. Of course, those skilled in the art will recognize that many modifications can be made to these configurations without departing from the scope and spirit of the disclosed subject matter.

What has been described above includes examples of the present innovation. Of course, it may not be possible to describe every conceivable combination of components or methodologies for the purpose of describing the present innovation, but those skilled in the art will recognize that many additional combinations and permutations of the present innovation are possible. Accordingly, the disclosed subject matter is intended to cover all such modifications, variations, and variations that fall within the spirit and scope of the present invention. Furthermore, to the extent that the terms "comprises," "comprising," "has," or "having" and variations thereof are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "consisting of" as "consisting of" is interpreted when used as a transitional word in a claim.

Also, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" should not necessarily be construed as preferred or preferable over other aspects or designs. Rather, the use of the word exemplary is intended to present the concept in a clear manner. The term "or" as used herein is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the aforementioned instances. In addition, the articles “a” and “an,” as used in this application and the appended claims, should be construed to mean “one or more,” unless otherwise indicated or clear from the context to refer to the singular.

Additionally, some portions of the detailed description have been provided in relation to algorithms or process operations on data bits within an electronic memory. These process descriptions or representations are mechanisms used by those skilled in the art to effectively convey the substance of their work to others skilled in the art. A process is generally considered herein to be a self-consistent sequence of acts leading to a desired result. The acts are those requiring physical manipulations of physical quantities. Typically, although not necessarily, these quantities take the form of electrical and/or magnetic signals capable of being stored, transmitted, combined, compared, and/or otherwise manipulated.

In principle, for purposes of general usage, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities, and that they are merely convenient labels to be applied to these quantities. Unless specifically stated otherwise or apparent from the discussion above, discussions throughout the disclosure using terms such as processing, computing, replicating, imitating, determining, or transmitting, and the like, will be understood to refer to actions and processes of processing systems, and/or similar consumer or industrial electronic devices or machines, that manipulate data or signals represented as physical (electrical or electronic) quantities within circuits, registers or memories of electronic devices(s), or that transform them into other data or signals similarly represented as physical quantities within machine or computer system memories or registers or such other information storage, transmission and/or display devices.

In connection with the various functions performed by the components, architectures, circuits, processes, and the like described above, the terms (including references to "means") used to describe these components are intended to correspond to any component that performs the particular function (e.g., the functional equivalent) of the described component, unless otherwise stated, even if it is not structurally equivalent to the disclosed structure that performs the function of the exemplary aspects of the embodiments illustrated herein. In addition, although a particular feature is disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations as may be desirable and advantageous for any given or particular application. It will also be appreciated that embodiments include systems as well as computer-readable media having computer-executable instructions for performing the acts and/or events of various processes.

Claims (12)

As a resistive switching device,
A bottom electrode placed on a semiconductor substrate;
A resistive switching material disposed on the lower electrode, comprising a non-stoichiometric aluminum and nitrogen material AlNy, wherein y is in a first range from greater than 1.00 to 1.50;
A conductive material disposed on the resistive switching material, comprising a non-stoichiometric aluminum and nitrogen material AlNx, wherein x is in a second range of 0.60 to 0.80 and y>x; and
A resistive switching device comprising a top electrode disposed on the conductive material.
In claim 1,
A resistive switching device wherein the lower electrode comprises a metal nitride.
delete delete delete In claim 1,
A resistive switching device, wherein the resistive switching material has a thickness of 2 nm to 20 nm.
In claim 1,
A resistive switching device, wherein the conductor material has a thickness of 4 nm to 100 nm.
In claim 1,
A resistive switching device, wherein the resistive switching material is associated with an initial resistance in the range of 1 mega-ohm ((MOhm)) to 100 MOhm.
In claim 1,
A resistive switching device wherein the conductor material is associated with an initial resistance in the range of 1 kilo-ohm ((KOhm) to 100 KOhm.
In claim 1,
A resistive switching device wherein the lower electrode comprises materials selected from the group consisting of copper, titanium nitride and tantalum nitride.
A method for forming a semiconductor device,
A step of forming a bottom electrode on a semiconductor substrate;
A step of forming a resistive switching material layer including a non-stoichiometric aluminum and nitrogen material AlNy on the lower electrode, wherein y is in a first range from greater than 1.00 to 1.50;
A step of forming a conductive material comprising a non-stoichiometric aluminum and nitrogen material AlNx on the resistive switching material, wherein x is in a second range of 0.60 to 0.80 and y>x; and
A method comprising the step of forming a top electrode on the conductive material.
In claim 11,
The step of forming the resistive switching material layer and the step of forming the conductive material are,
A step of placing the semiconductor substrate within a processing chamber;
A step of sealing the above processing chamber from the surrounding atmosphere;
While the above processing chamber is sealed from the surrounding atmosphere,
The step of forming the resistive switching material includes the step of forming the AlNy material in nitrogen gas and argon gas associated with a first flow rate for nitrogen;
The step of forming the conductive material comprises a step of forming the AlNx material in nitrogen gas and argon gas associated with a second flow rate for nitrogen, wherein the first flow rate exceeds the second flow rate; and
A method comprising the step of unseal the processing chamber from the surrounding atmosphere.

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