KR102720582B1 - Pixel driving circuit having 8t1c structure capable of low refresh rate driving - Google Patents

Abstract

The present invention relates to a pixel driving circuit, comprising: a first transistor connected between a first node and a third node and having a gate electrode connected to a second node; a second transistor connected between a first driving power source and the first node and having a gate electrode connected to an emission control line; a third transistor connected between a data line and the first node and having a gate electrode connected to a first scan line, and transmitting or blocking a data voltage; a fourth transistor connected between the second node and the third node and having a gate electrode connected to a reverse emission control line, and having a dual gate structure; a fifth transistor connected between the third node and the fourth node and having a gate electrode connected to the second scan line and having a gate electrode connected to the reverse emission control line; a sixth transistor connected between the third node and the fifth node and having a gate electrode connected to the emission control line; a seventh transistor connected between a center node of the fourth transistor having a dual gate structure and a reference line and having a gate electrode connected to the first driving power source; an eighth transistor connected between the fourth node and the fifth node and having a gate electrode connected to a second scan line; a storage capacitor connected between the first driving power source and the second node; and a fifth node and It is characterized by including a light emitting diode connected between the second driving power sources.

Description

{PIXEL DRIVING CIRCUIT HAVING 8T1C STRUCTURE CAPABLE OF LOW REFRESH RATE DRIVING}

The present invention relates to a pixel driving circuit having an 8T1C structure capable of low refresh rate driving that can reduce or compensate for leakage current of an LTPS (Low Temperature Poly-Silicon) TFT.

Display technology has undergone various changes and developments over time. Among them, displays featuring low refresh rate (LRR) operation are attracting attention. Since the LRR operation method has the characteristic of images being updated extremely infrequently, it has different characteristics from existing high refresh rate displays.

The ability to maintain the screen state continuously without consuming energy during the display refresh interval is especially important in mobile devices or wearable devices that use batteries. One of the key characteristics of low refresh rate operation is to minimize the leakage current. However, LTPS TFTs have limitations in operation at low refresh rates due to their relatively high leakage current characteristics.

Meanwhile, the oxide TFT exhibits a tendency for the threshold voltage to change in a negative direction over time during use, i.e., a negative shift. This change can affect the stability and performance of the device.

As an example, as illustrated in FIG. 1, in the oxide TFT (120), the V _GD margin is set to be 1 V or more larger than that of the LTPS TFT (110). Here, V _GD represents the "gate-drain voltage", and the V _GD margin represents a safety area that is considered so that the transistor can operate stably. That is, since the oxide TFT (120) must have a large V _GD margin, there is a problem that the power consumption of the entire system increases and the display response time may be slowed down. Therefore, if this problem is overcome through a circuit technology that can reduce the leakage current of the LTPS TFT (110) or compensate for the current, both the driving and emission power consumption of the OLED product can be reduced.

In addition, considering the modern semiconductor manufacturing process, if low-cost LTPS technology is successfully introduced in the 8th generation large-area technology, it can lead to various product performance improvements, such as reduced power consumption and reduced bezel size.

To solve the above-mentioned problems, the purpose of the present invention is to provide a pixel driving circuit having a structure for reducing the leakage current of an LPTS TFT.

However, the technical tasks that this embodiment seeks to accomplish are not limited to the technical tasks described above, and other technical tasks may exist.

According to one embodiment of the present invention for achieving the above-described purpose, a pixel driving circuit comprises: a first transistor connected between a first node and a third node and having a gate electrode connected to a second node; a second transistor connected between a first driving power source and the first node and having a gate electrode connected to an emission control line; a third transistor connected between a data line and the first node and having a gate electrode connected to a first scan line, and transmitting or blocking a data voltage; a fourth transistor connected between the second node and the third node and having a gate electrode connected to a reverse emission control line and having a dual gate structure; a fifth transistor connected between the third node and the fourth node and having a gate electrode connected to the second scan line; a sixth transistor connected between the third node and the fifth node and having a gate electrode connected to the emission control line; a seventh transistor connected between a center node of the fourth transistor having a dual gate structure and a reference line and having a gate electrode connected to the first driving power source; an eighth transistor connected between the fourth node and the fifth node and having a gate electrode connected to the second scan line; a storage capacitor connected between the first driving power source and the second node; and a fifth node and It is characterized by including an organic light-emitting diode connected between the second driving power sources.

According to one embodiment, the second transistor and the sixth transistor are turned off when the light emission control signal transmitted through the light emission control line becomes high.

According to one embodiment, the fourth transistor is characterized in that it is turned on when the reverse emission control signal transmitted through the reverse emission control line becomes low.

According to one embodiment, the first transistor is characterized in that the gate and drain are connected in a diode connection state while the fourth transistor is turned on.

According to one embodiment, the fifth transistor and the eighth transistor are turned on when the second scan signal transmitted through the second scan line becomes low while the emission control signal transmitted through the emission control line is high, and the storage capacitor and the anode of the organic light-emitting diode are reset to a low potential when the initial voltage is input.

According to one embodiment, when a first scan signal transmitted through a first scan line is low while a light emission control signal transmitted through a light emission control line is high, a third transistor is turned on to input a data voltage, and a voltage stored in a storage capacitor is a value in which a threshold voltage of the first transistor is compensated.

According to one embodiment, when the light emission control signal transmitted through the light emission control line becomes low and the reverse light emission control signal transmitted through the reverse light emission control line becomes high, the first transistor is characterized in that a current equal to the data voltage stored in the organic light emitting diode is supplied when the first driving power source is connected.

In one embodiment, the voltage of the center node of the fourth transistor is biased by the reference power supply when the fourth transistor is turned off and the seventh transistor is turned off at the same time.

In one embodiment, the fourth transistor and the fifth transistor are characterized by having a series structure with respect to the initial power supply so as to prevent the voltage stored in the storage capacitor from being discharged due to leakage current.

According to the present invention, there is an effect capable of compensating for leakage current or leakage current of an LPTS TFT.

In addition, according to the present invention, it is possible to develop an OLED product capable of reducing both driving power consumption and emission power consumption.

Figure 1 is a drawing for explaining the V _GD margin of oxide TFT and LTPS TFT.
Fig. 2 (a) is a drawing showing a conventional 7T1C LTPS TFT circuit, and Fig. 2 (b) is an equivalent circuit of Fig. 2 (a).
Figure 3 is a graph showing the leakage current occurring at T4 and T5 when emitting light in a conventional 7T1C LTPS TFT circuit.
FIG. 4 is a schematic block diagram of an organic light-emitting display device according to one embodiment of the present invention.
FIG. 5 is a drawing showing a pixel circuit of an 8T1C LTPS structure according to one embodiment of the present invention.
FIG. 6 is a timing diagram for explaining a driving method of a pixel circuit of an 8T1C LTPS structure according to one embodiment of the present invention.

Hereinafter, with reference to the attached drawings, embodiments of the present invention will be described in detail so that those skilled in the art can easily practice the present invention. The present invention can have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and specifically described in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but should be understood to include all modifications, equivalents, and substitutes included in the spirit and technical scope of the present invention.

In order to clearly explain the present invention, parts that are not related to the description are omitted in the drawings, and similar parts are given similar drawing reference numerals throughout the specification. In addition, when explaining with reference to the drawings, even if the components are indicated by the same name, the drawing numbers may be different depending on the drawings, and the drawing numbers are described only for the convenience of explanation, and the concept, feature, function, or effect of each component is not limited by the drawing numbers.

In describing each drawing, similar reference numerals are used for similar components. Although terms such as first, second, etc. may be used to describe various components, the components should not be limited by the terms. The terms are used only to distinguish one component from another. For example, without departing from the scope of the present invention, the first component could be referred to as the second component, and similarly, the second component could also be referred to as the first component. The term "and/or" includes any combination of a plurality of related listed items or any item among a plurality of related listed items.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless expressly defined in this application.

Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "electrically connected" with another element in between. In addition, when a part is said to "include" a certain component, this should be understood to mean that it may further include other components, unless specifically stated to the contrary, and does not preclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In this specification, a 'part' or 'module' includes a unit realized by hardware or software, and a unit realized using both. One unit may be realized using two or more pieces of hardware, and two or more units may be realized by one piece of hardware.

Before describing the pixel driving circuit according to the present invention in detail, the problems of the 7T1C LTPS circuit will first be explained.

Fig. 2 (a) is a diagram showing a 7T1C LTPS circuit. Referring to Fig. 2 (a), the pixel circuit (200) includes seven transistors (T1, T2, T3, T4, T5, T6, T7), a storage capacitor (210, Cst), and an OLED (220). Fig. 2 (b) is an equivalent circuit of Fig. 2 (a). When Vgs and Vds of transistors (T4) and (T5) are calculated from Fig. 2 (a) and (b), they are as shown in [Table 1] below.

T4 T5 Vgs 4.5V 4.5V Vds -4V -6.5V

Fig. 3 is a graph showing the leakage current occurring in T4 and T5 when the 7T1C LTPS circuit is emitting light. Referring to Fig. 3, it can be seen that the leakage current of T4 and T5 remains large when the conventional 7T1C LTPS circuit is emitting light. Therefore, it can be seen that Vds needs to be lowered in order to solve this problem.

Below, an 8T1C LTPS circuit according to the present invention for solving the above-mentioned problems is described.

FIG. 4 is a schematic block diagram of an organic light-emitting display device according to one embodiment of the present invention.

Referring to FIG. 4, an organic light-emitting display device (400) includes a display panel (410) in which pixels (PXL) for internal compensation are formed, a data driver (430) for driving data lines (460), a gate driver (440) for driving gate lines (470), a timing controller (420) for controlling driving timing of the data driver (430) and the gate driver (440), and a power supply unit (450) for supplying power to a pixel circuit.

In the display panel (410), a plurality of data lines (460) and a plurality of gate lines (470) intersect, and sub-pixels (PXL) for internal compensation are arranged in a matrix form at each intersection area. The sub-pixels (PXL) arranged on the same horizontal line are connected to one gate line (470), and one gate line (470) may include at least one scan line and at least one emission control line.

That is, each sub-pixel (PXL) can be connected to one data line (460) and at least one scan line and an emission control line. The sub-pixels (PXL) can commonly receive a high-potential voltage, a low-potential voltage, and a reference voltage (Vref) from a power supply unit (450). In order to prevent unnecessary emission of the OLED during the initialization period and the sampling period, the reference voltage (Vref) is preferably selected within a voltage range sufficiently lower than the operating voltage of the OLED, and can be set to be equal to or lower than the low-potential voltage.

Each sub-pixel (PXL) may include a plurality of TFTs and a storage capacitor to compensate for threshold voltage (Vth) deviation of the driving TFT. In the present invention, each sub-pixel (PXL) is referred to as a pixel circuit, and its specific configuration will be described later.

The timing controller (420) rearranges digital video data (RGB) input from the outside according to the resolution of the display panel (410) and supplies the data driver (430). In addition, the timing controller (420) generates a data control signal (DDC) for controlling the operation timing of the data driver (430) and a gate control signal (GDC) for controlling the operation timing of the gate driver (440) based on timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a dot clock signal (DCLK), and a data enable signal (DE).

The data driver (430) converts digital video data (RGB) input from the timing controller (420) into analog data voltage based on a data control signal (DDC) and supplies it to a plurality of data lines (460).

The gate driver (440) can generate scan signals (Scan[n-1], Scan[n], Scan[n+1]), an emission control signal (EM), and a reverse emission control signal (Emb) based on a gate control signal (GDC). The gate driver (440) can include a scan driver (not shown) and an emission control signal driver (not shown). The scan driver (not shown) can generate a scan signal in a row-sequential manner and supply it to the scan lines in order to drive at least one or more scan lines connected to each pixel row. The emission control signal driver (not shown) can generate a emission control signal (EM) in a row-sequential manner and supply it to the emission control signal lines in order to drive at least one or more emission control signal lines connected to each pixel row. The gate driver (440) can be formed directly on a non-display area of the display panel (410) according to a GIP (Gate-driver In Panel) method.

FIG. 5 is a drawing showing a pixel circuit of an 8T1C LTPS structure according to one embodiment of the present invention.

Referring to FIG. 5, the pixel circuit (500) includes eight transistors (T1, T2, T3, T4, T5, T6, T7, T8), a storage capacitor (520) (Cst), and an OLED (530). Each of the eight transistors (T1, T2, T3, T4, T5, T6, T7, T8) can be implemented with, for example, an oxide semiconductor thin film transistor and an LTPS (Low Temperature Poly-Silicon) thin film transistor.

The oxide semiconductor thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor thin film transistor has an active layer formed of an oxide semiconductor. Here, the oxide semiconductor can be set as an amorphous or crystalline oxide semiconductor. The oxide semiconductor thin film transistor can be configured as an N-type transistor or a P-type transistor.

The LTPS thin film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin film transistor has an active layer formed of polysilicon. Such an LTPS thin film transistor may be configured as a P-type thin film transistor or an N-type thin film transistor. In the embodiment of the present invention, it is assumed that the LTPS thin film transistor is configured as a P-type transistor, but the present invention is not limited to this embodiment.

In an embodiment of the present invention, a pixel circuit (500) is composed of eight transistors (T1, T2, T3, T4, T5, T6, T7, T8) and one capacitor (520, Cst), and may be referred to as an 8T1C circuit. In addition, each of the eight transistors may be referred to as a first to eighth transistor. The first electrode of the transistors to be described below may mean a source terminal, and the second electrode may mean a drain terminal, but the designation of 'source' and 'drain' may be arbitrary and is not limited to the designated terminals.

In the example circuit of Fig. 5 (a), the first node (N1) to the sixth node (N6) are defined as follows. The first node (N1) is a node to which the first electrode of the first transistor (T1), the first electrode of the second transistor (T2), and the first electrode of the third transistor (T3) are connected. The second node (N2) is a node to which the gate electrode of the first transistor (T1), one terminal of the storage capacitor (530, Cst), and the second electrode of the fourth transistor (T4) are connected. The third node (N3) is a node to which the second electrode of the first transistor (T1), the first electrode of the fourth transistor (T4), the first electrode of the fifth transistor (T5), and the second electrode of the sixth transistor (T6) are connected. The fourth node (N4) is a node to which the second electrode of the fifth transistor (T5), the second electrode of the eighth transistor (T8), and the initialization line are connected. The fifth node (N5) is a node to which the first electrode of the sixth transistor (T6) and the anode electrode of the organic light-emitting diode (OLED) are connected.

A first transistor (T1) may be connected between a first node and a third node, and a gate electrode may be connected to a second node. The first transistor (T1) controls an amount of current supplied from a first driving power supply (ELVDD) to a second driving power supply (ELVSS) via an organic light-emitting diode (OLED) in response to a voltage of the first node (N1). That is, the first transistor (T1) transmits current to the OLED according to a data voltage as a driving TFT. In some embodiments, the first driving power supply (ELVDD) may be higher than the second driving power supply (ELVSS). In some embodiments, the first driving power supply (ELVDD) may represent the highest voltage in the pixel circuit, and the second driving power supply (ELVSS) may represent the lowest voltage in the pixel circuit. In addition, most of the negative power supply terminals in the pixel circuit may be ground terminals.

The second transistor (T2) is connected between the first driving power supply (ELVDD) and the first node (N1), and the gate electrode can be connected to the emission control line (Em). The second transistor (T2) is turned off when an emission control signal is supplied to the emission control line, and is turned on when the emission control signal is not supplied to the second transistor (T2).

The third transistor (T3) is connected between the data line and the first node, has a gate electrode connected to the first scan line, and can perform a function of transmitting or blocking a data voltage. For example, when the first scan signal (Scan[n]) is supplied to the first scan line, the third transistor (T3) is turned off, and when the first scan signal (Scan[n]) is not supplied, the third transistor (T3) is turned on.

The fourth transistor (T4) is connected between the second node (N2) and the third node (N3), and a gate electrode can be connected to a reverse emission control line, and can have a dual gate structure. The fourth transistor (T4) serves to connect the gate and the drain of the first transistor (T1). When a reverse emission control signal is supplied to the reverse emission control line, the fourth transistor is turned off, and when the reverse emission control signal is not supplied, the fourth transistor is turned on. A seventh transistor (T7) that is maintained in a turn-off state by being supplied with a first driving power supply (ELVDD) can be connected to the center node of the fourth transistor (T4). Here, the gate of the seventh transistor (T7) is always maintained in a weakly turned-off state by being connected to the first driving power supply (ELVDD).

The fifth transistor (T5) is connected between the third node (N3) and the fourth node (N4) and a gate electrode can be connected to the second scan line. When the second scan signal (Scan[n-1]) is supplied to the second scan line, the fifth transistor (T5) is turned off, and when the second scan signal (Scan[n-1]) is not supplied, the fifth transistor (T5) is turned on.

The sixth transistor (T6) is connected between the third node (N3) and the fifth node (N5), and a gate electrode can be connected to a light emission control line. When a light emission control signal (Em[n]) is supplied to the light emission control line, the sixth transistor (T6) is turned off, and when the light emission control signal (Em[n]) is not supplied, the sixth transistor (T6) is turned on.

The seventh transistor (T7) is connected between the center node of the fourth transistor (T4) having a dual gate structure and the reference line, and the gate electrode can be connected to the first driving power supply (ELVDD). Here, the gate of the seventh transistor (T7) is always maintained in a weakly turned off state by being connected to the first driving power supply (ELVDD). A voltage having an intermediate value of the data voltage is applied as DC to one node of the seventh transistor (T7).

The eighth transistor (T8) may be connected between the fourth node (N4) and the fifth node (N5) and the gate electrode may be connected to the second scan line. That is, the eighth transistor (T8) may be connected between the anode of the OLED and the initial power supply.

A storage capacitor (520) may be connected between a first driving power source (ELVDD) and a second node (N2). An organic light-emitting diode (530) may be connected between a fifth node (N5) and a second driving power source (ELVSS).

The first transistor (T1) is a driving transistor, and the second transistor (T2) can compensate for the threshold voltage (Vth) deviation of the first transistor (T1) while transmitting or blocking the data voltage. The second transistor (T2) and the sixth transistor (T6) can also control the overall brightness of the screen by controlling the light-emitting time of the organic light-emitting diode (530), and can also block the connection between the first driving voltage (ELVDD) and the organic light-emitting diode (530) when the data voltage is applied and the threshold voltage (Vth) of the first transistor (T1) is extracted.

FIG. 6 is a timing diagram for explaining a driving method of a pixel circuit of an 8T1C LTPS structure according to one embodiment of the present invention.

Referring to Fig. 6, the Em signal and the Emb signal have opposite polarities with the same cycle. When Em becomes High, the second transistor (T2) and the sixth transistor (T6) are turned off, and when Emb becomes Low, the fourth transistor (T4) is turned on. While the fourth transistor (T4) is turned on, the first transistor (T1) is in a diode-connected state in which the gate and drain are connected.

While the Em signal is High, Scan(n-1) first becomes Low, turning on the fifth transistor (T5) and the eighth transistor (T8), and the anode of the storage capacitor (520) and the organic light-emitting diode (530) is reset to a low potential as the initial voltage is input.

While the Em signal is high, if Scan(n) is low, the third transistor (T3) is turned on and the data voltage is input. At this time, the state of the first transistor (T1) is in a diode-connection state, so the voltage stored in the storage capacitor (520) becomes a value that compensates for the threshold voltage (Vth) of the first transistor (T1).

When the Em signal becomes low and the Emb signal becomes high at the same time, the first transistor (T1) is connected to the first driving power supply (ELVDD) and a current equal to the data voltage stored in the organic light-emitting diode (530) is supplied.

When the fourth transistor (T4) is turned off and the seventh transistor (T7) is turned off at the same time, the voltage of the center node of the fourth transistor (T4) is biased toward the reference power supply. Accordingly, the effective Vds of the fourth transistor (T4) approaches 0 V, and the leakage current also becomes extremely low.

In order to prevent the voltage stored in the storage capacitor (530) from being discharged due to leakage current, the parallel leakage current path connected to the storage capacitor (530) is made into a series structure. To this end, the lowest power source, which is the initial power source, is made to have a series structure with the fourth transistor (T4) and the fifth transistor (T5).

In addition, the effective Vds of the fourth transistor (T4) directly connected to the storage capacitor (530) must be lowered. Since the leakage current increases exponentially according to the absolute size of Vds, in order to implement a potential close to 0 V, the fourth transistor (T4) has a dual gate structure and is biased in the off state at an intermediate voltage close to the data voltage.

Although the embodiments of the present invention have been described with reference to the attached drawings, the present invention is not limited to the embodiments described above, but can be manufactured in various different forms, and a person having ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

110: LTPS PMOS 120: Oxide NMOS
200: 7T1C LTPS circuit 210: Storage capacitor
220: Organic light emitting diode 400: Organic light emitting display device
410: Display panel 420: Timing controller
430: Data Driver 440: Gate Driver
450: Power supply 460: Data line
470: Gate line 500: 8T1C LTPS circuit
520: Storage capacitor 530: Organic light emitting diode

Claims (9)

A first transistor connected between the first node and the third node and having a gate electrode connected to the second node;
A second transistor connected between the first driving power source and the first node and having a gate electrode connected to a light emission control line;
A third transistor connected between the data line and the first node, the gate electrode of which is connected to the first scan line, and which transmits or blocks the data voltage;
A fourth transistor connected between the second node and the third node, having a gate electrode connected to a reverse light-emitting control line, and having a dual gate structure;
A fifth transistor connected between the third node and the fourth node and having a gate electrode connected to the second scanning line;
A sixth transistor connected between the third node and the fifth node and having a gate electrode connected to a light emission control line;
A seventh transistor connected between the center node of the fourth transistor having the dual gate structure and the reference line and having a gate electrode connected to the first driving power supply;
An eighth transistor connected between the fourth node and the fifth node and having a gate electrode connected to the second scanning line;
a storage capacitor connected between the first driving power source and the second node; and
An organic light-emitting diode connected between the fifth node and the second driving power source;
A pixel driving circuit, characterized by including a . In paragraph 1,
A pixel driving circuit, characterized in that when the light emission control signal transmitted through the light emission control line becomes high, the second transistor and the sixth transistor are turned off. In paragraph 1,
A pixel driving circuit, characterized in that the fourth transistor is turned on when the reverse emission control signal transmitted through the reverse emission control line becomes low. In the third paragraph,
A pixel driving circuit, characterized in that while the fourth transistor is turned on, the first transistor is in a diode connection state in which the gate and drain are connected. In paragraph 1,
A pixel driving circuit characterized in that the fifth transistor and the eighth transistor are turned on while the second scan signal transmitted through the second scan line becomes low while the light emission control signal transmitted through the light emission control line is high, and the storage capacitor and the anode of the organic light emitting diode are reset to a low potential when an initial voltage is input. In paragraph 1,
A pixel driving circuit characterized in that when the light emission control signal transmitted through the light emission control line is high and the first scan signal transmitted through the first scan line is low, the third transistor is turned on to input the data voltage, and the voltage stored in the storage capacitor is a value in which the threshold voltage of the first transistor is compensated. In paragraph 1,
A pixel driving circuit characterized in that when the light emission control signal transmitted through the light emission control line becomes low and the reverse light emission control signal transmitted through the reverse light emission control line becomes high, the first transistor is connected to the first driving power supply and current equal to the data voltage stored in the organic light emitting diode is supplied. In paragraph 1,
A pixel driving circuit, characterized in that when the fourth transistor is turned off and the seventh transistor is turned off at the same time, the voltage of the center node of the fourth transistor is biased by the reference power supply. In paragraph 1,
A pixel driving circuit, characterized in that the fourth transistor and the fifth transistor have a series structure with respect to the initial power supply so as to prevent the voltage stored in the storage capacitor from being discharged due to leakage current.

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