KR102720350B1 - Gate driving circuit and display device using the same - Google Patents

Abstract

The present invention relates to a gate driving circuit and a display device using the same. The gate driving circuit includes: a shift register that sequentially outputs gate pulses using a plurality of signal transmission units; and a gate control unit that is connected to a start signal input node and an output node of each of the signal transmission units, and selectively supplies any one of a start pulse, a carry signal, and a gate-off voltage to the start signal input node of each of the signal transmission units and receives the carry signal from the output nodes of the signal transmission units.

Description

GATE DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME

The present invention relates to a gate driving circuit and a display device using the same.

Electroluminescent displays are largely classified into inorganic light emitting displays and organic light emitting displays depending on the material of the light emitting layer. An organic light emitting display of the active matrix type includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has the advantages of a fast response speed, high luminous efficiency, high brightness, and large viewing angle. An organic light emitting display has an OLED (Organic Light Emitting Diode, "OLED") formed in each pixel. An organic light emitting display not only has a fast response speed and excellent luminous efficiency, high brightness, and high viewing angle, but also has excellent contrast ratio and color reproducibility because it can express black gradation as complete black.

Organic light-emitting display devices do not require a backlight unit and can be implemented on flexible materials such as plastic substrates, thin glass substrates, and metal substrates. Therefore, a flexible display can be implemented as an organic light-emitting display device.

A flexible display can change the screen size by rolling, folding, or bending a flexible panel. Flexible displays can be implemented as rollable displays, foldable displays, bendable displays, and slidable displays. These flexible displays can be applied to not only mobile devices such as smartphones and tablet PCs, but also TVs, automobile displays, and wearable devices, and their application fields are expanding.

A flexible display can be combined with an information device with a structure that can change the size of the screen by using a flexible panel structure. Since the information device can increase the screen size by adopting a flexible display, it can execute two or more applications or contents to enable multi-tasking and display a lot of information on the screen at the same time. It may be necessary to display different images on the screen or control the frame frequency of the images differently. In this case, the output of the gate driving circuit must be independently controlled for each area within the screen, but the gate driving circuit becomes large and its control circuit becomes complicated.

The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a gate driving circuit and a display device using the same, which can freely adjust an active area in which an image is displayed within a screen and independently control a frame frequency between the active areas.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

The gate driving circuit of the present invention includes a shift register that sequentially outputs gate pulses using a plurality of signal transmission units; and a gate control unit that is connected to a start signal input node and an output node of each of the signal transmission units, and selectively supplies any one of a start pulse, a carry signal, and a gate-off voltage to the start signal input node of each of the signal transmission units and receives the carry signal from the output nodes of the signal transmission units.

Each of the above signal transmission units includes a first control node that is charged according to the gate-on voltage of one of the start pulse and the carry signal, and a pull-up transistor that outputs the gate pulse while the first control node is charged.

The display device of the present invention comprises a display panel capable of displaying two or more different images, including a screen in which data lines and gate lines intersect and pixels into which pixel data of an input image is written are arranged; a data driving unit that supplies a data voltage to the data lines; and a gate driving unit that supplies a gate pulse to the gate lines using the shift register and the gate control unit.

The present invention can divide a screen and drive each of the divided areas with different frame frequencies using a gate control unit. The gate control unit can select a start line and an end line of an activated area, thereby responding to various screen driving modes of an infotainment system of a vehicle, a foldable display, and a rollable display, and providing an optimal driving solution for resolution change and frequency distribution of each of the divided areas on the screen.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Figures 1a and 1b are schematic drawings showing a portion of a pixel array.
Figure 2 is a schematic diagram showing a shift register of a gate driver.
Figures 3a and 3b are schematic drawings showing a pass gate circuit and an edge trigger circuit.
Figure 4 is a waveform diagram showing the first control node voltage, the second control node voltage, and the output voltage of the i signal transmission unit.
Figure 5 is a diagram showing a bidirectional shift register.
Figures 6a and 6b are waveform diagrams showing the bidirectional shift of the gate pulse.
Figure 7 is a schematic diagram showing the scan driving unit and the EM driving unit.
FIG. 8 is a drawing showing an example in which the display device of the present invention is applied to an infotainment system of a vehicle.
Figure 9 is a waveform diagram showing the frame frequency by area of the screen in Figure 8.
FIG. 10 is a drawing showing an example in which the display device of the present invention is applied to a flexible display with an expandable screen.
Figure 11 is a waveform diagram showing the frame frequency by area of the screen in Figure 10.
Figure 12 is a drawing showing in detail the active period and vertical blank period of one frame period.
Figure 13 is a flowchart showing a method of driving a display device according to an embodiment of the present invention.
FIGS. 14a and 14b are block diagrams showing a gate control unit according to an embodiment of the present invention.
Figures 15 to 17 are drawings showing the gate control unit in detail.
FIGS. 18a to 20b are drawings illustrating the operation of a gate driving circuit according to an embodiment of the present invention.
Figure 21 is a diagram showing an example of selection in an active area during one frame period when the screen is divided into three areas and driven.
FIGS. 22 to 27 are drawings showing control signals of a gate driver applied to an active region during one frame period in the example of FIG. 21.
Figure 28 is a drawing showing an example of a variable size active area of a rollable display.
Figures 29a to 29d are drawings showing various screen modes of the rollable display.
Fig. 30 is a drawing showing an example of a method for preventing afterimages in a rollable display.
Fig. 31 is a drawing showing an example of split driving of a screen in a rollable display.
Fig. 32 is a circuit diagram showing another embodiment of a gate control unit.
Figure 33 is a waveform diagram showing the control signal of the gate driver.
Figures 34a and 34b are drawings showing a method of controlling a gate driver when the size of the active area is gradually expanded and reduced.
Figure 35 is a diagram showing an example in which the driving frequency of the activation region is varied when the size of the activation region is varied.
Figure 36 is a drawing showing an example of an active area moving up and down to prevent afterimages in a rollable display.
Figure 37 is a drawing showing a method of controlling a gate driver when the screen moves up and down.
Figure 38 is a waveform diagram showing an example of a gate pulse generated in black tone insertion mode.
Figure 39 is a circuit diagram showing in detail the signal transmission section of the scan driver.
Figure 40 is a waveform diagram showing the input/output signals of the signal transmission unit illustrated in Figure 39.
Figure 41 is a circuit diagram showing the signal transmission section of the EM drive unit in detail.
Figure 42 is a waveform diagram showing the input/output signals of the signal transmission unit illustrated in Figure 40.
FIG. 43 is a block diagram showing a foldable display according to one embodiment of the present invention.
Figures 44a and 44b are drawings showing examples of a flexible display being folded.
Figure 45 is a block diagram showing the drive IC configuration.
Fig. 46 is a circuit diagram showing an example of a pixel circuit.
Fig. 47 is a drawing showing a driving method of the pixel circuit illustrated in Fig. 46.
Figures 48 to 50 are drawings showing a method of operating a screen when folding and unfolding a foldable display.

The advantages and features of the present invention, and the methods for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated. The same reference numerals refer to the same components throughout the specification. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

In the specification, when "includes," "has," and "consists of" are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes the plural unless there is a special explicit description.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on ~', 'above ~', 'below ~', 'next to ~', etc., one or more other parts may be located between the two parts, unless 'right' or 'directly' is used.

In the description of the embodiments, the terms first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component mentioned below may also be a second component within the technical concept of the present invention.

Throughout the specification, identical reference numerals refer to identical components.

The features of the various embodiments may be partially or wholly combined or combined with each other, and various technical connections and operations may be possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the flexible display of the present invention, the pixel circuit and the gate driver may include a plurality of transistors. The transistors may be implemented as an oxide thin film transistor (TFT) including an oxide semiconductor, an LTPS TFT including low temperature poly silicon (LTPS), etc. Each of the transistors may be implemented as a p-channel TFT or an n-channel TFT. In the embodiment, the description will focus on an example in which the transistors of the pixel circuit are implemented as p-channel TFTs, but the present invention is not limited thereto.

A transistor is a three-electrode device that includes a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode through which carriers leave the transistor. In a transistor, the flow of carriers flows from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as first and second electrodes.

The gate pulse swings between a gate on voltage and a gate off voltage. The gate on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while it is turned off in response to the gate off voltage. For an n-channel transistor, the gate on voltage can be a gate high voltage (VGH), and the gate off voltage can be a gate low voltage (VGL). For a p-channel transistor, the gate on voltage can be a gate low voltage (VGL), and the gate off voltage can be a gate high voltage (VGH).

The gate driving circuit of the present invention can be applied to a flat panel display (FPD) that requires a gate driving circuit to shift a gate pulse. The gate pulse can include at least a scan pulse (or a scan signal). The gate pulse can further include an emission control pulse (hereinafter, referred to as "EM pulse"). For example, the present invention can be applied to any display device that requires a gate driving circuit, such as a liquid crystal display (LCD), an organic light emitting display (OLED display), etc. In the following embodiments, flexible displays include foldable displays and rollable displays, but the present invention is not limited thereto.

The active region, inactive region, high-speed drive region, and low-speed drive region described in the examples below are defined as follows.

The active area can be a part or the entire area of the screen where the scan pulse pulse and pixel data are applied to the pixels and the image is displayed. The inactive area can be a part or the entire area of the screen where the pixel data is not written to the pixels because the gate pulse is not applied. The inactive area displays a black gradation or maintains the image written in the previous frame. The size of each of the active area and the inactive area can be variable depending on the input image, and the active area and the inactive area can be integrated and expanded into one active area or inactive area depending on the input image. The high-speed drive area is an active area where the pixel data of the input image is written at a high frame frequency higher than a preset reference frame frequency. The low-speed drive area is an active area or an inactive area driven at a frame frequency lower than the reference frame frequency.

In the high-speed driving region, the scanning speed (or data addressing speed) of the pixels is faster than in the low-speed driving region. On the other hand, in the low-speed driving region, the scanning speed (or data addressing speed) of the pixels is slower than in the high-speed driving region or the scan pulses are not shifted.

The fast-moving region is an active region where a video with many changes in the image or a video with fast movement is displayed. The slow-moving region includes an active region where a still image with little change in the image or a video with relatively slow movement is displayed, and an inactive region where no image is displayed.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

Referring to FIGS. 1A and 1B, the display device of the present invention includes a display panel on which an input image is displayed, and a display panel driver for driving the display panel.

A screen on which an input image is reproduced on a display panel includes data lines (DL1 to DL6), gate lines (GL1, GL2) intersecting the data lines (DL1 to DL6), and a pixel array in which pixels (P) are arranged in a matrix form. The pixel array is driven to an active area or an inactive area depending on the input image. The pixel array may be divided into a plurality of sub-pixel arrays in which a frame frequency adaptively varies depending on the input image. The pixel array may be arranged on a rigid substrate or a flexible substrate of the display panel.

Each of the pixels (P) includes sub-pixels of different colors for color implementation. The sub-pixels include red (hereinafter referred to as “R sub-pixel”), green (hereinafter referred to as “G sub-pixel”), and blue (hereinafter referred to as “B sub-pixel”). Although not shown, a white sub-pixel may be further included. Hereinafter, a pixel may be interpreted as a sub-pixel unless otherwise defined. Each of the sub-pixels may include a pixel circuit.

A pixel circuit of a liquid crystal display (LCD) may include a pixel electrode and a common electrode for applying an electric field to a liquid crystal layer, a switching element connected between a data line and the pixel electrode in response to a gate-on voltage of a gate pulse to supply a data voltage to the pixel electrode, and a capacitor for maintaining the voltage of the pixel electrode for one frame period, etc. A pixel circuit of an organic light emitting display (OLED) may include a light emitting element, a driving element for supplying current to the light emitting element, a plurality of switching elements for programming a conduction condition of the driving element and switching current paths of the driving element and the light emitting element, a capacitor for maintaining a gate voltage of the driving element, etc.

The pixels (P) can be implemented as real color pixels (P) illustrated in FIG. 1a and pentile pixels (P) illustrated in FIG. 1b. In the case of a real color pixel (P), one pixel (P) is composed of R, G, and B sub-pixels as illustrated in FIG. 5. A pentile pixel can implement a higher resolution than a real color pixel by configuring two sub-pixels with different colors into one pixel using a pixel rendering algorithm. The pixel rendering algorithm compensates for the insufficient color expression in each pixel (P) with the color of light emitted from an adjacent pixel.

When the resolution of the pixel array is m*n, the pixel array includes m pixel columns and n pixel lines intersecting the pixel columns. The pixel columns include pixels arranged along the Y-axis direction. The pixel lines include pixels arranged along the X-axis direction. One horizontal period (1H) is a time obtained by dividing one frame period by the number of n pixel lines. In FIGS. 1A and 1B, #1 to #4 represent pixel line numbers.

The display panel driver writes pixel data of an input image to pixels (P). The display panel driver includes a data driver (10) that supplies data voltage of pixel data to data lines (DL1 to DL4), and a gate driver (20) that sequentially supplies gate pulses (GATE1 to GATE4) to gate lines (GL1 to GL4).

Fig. 2 is a schematic diagram showing a shift register of a gate driver (20). Figs. 3a and 3b are schematic diagrams showing a pass gate circuit and an edge trigger circuit.

Referring to FIG. 2, the gate driver (20) may include a shift register. The shift register includes signal transmission units [ST(i-1) to ST(i+2)] that are dependently connected. Each of the signal transmission units [ST(i-1) to ST(i+2)] includes a start signal input node (31), a clock input node (32), and an output node (33).

The present invention controls an activation region, a deactivation region, a high-speed driving region, and a low-speed driving region by selecting a voltage applied to a start signal input node (31) of each of the signal transmission units [ST(i-1) to ST(i+2)]. A start pulse (VST) of a gate-on voltage (VGL), a carry signal (CAR), or a gate high voltage (VGH) can be applied to the start signal input node (31).

Each of the signal transmission units [ST(i-1) to ST(i+2)] can output a gate pulse in an activation region when a start pulse (VST) of a gate-on voltage (VGL) is input to a start signal input node (31). When the first control node (Q) is pre-charged by the gate-on voltage (VGL) of the start pulse (VST) and a shift clock of the gate-on voltage (VGL) is input, a pull-up transistor is turned on so that the gate-on voltage (VGL) is output through the output node. Therefore, the signal transmission unit into which the start pulse (VST) is input may be a first signal transmission unit that outputs a first gate pulse on the entire screen, or a first signal transmission unit that outputs a first gate pulse for each divided area when the screen is divided and driven.

The gate pulse can be a scan pulse and/or an EM pulse. The gate pulse is generated by the gate-on voltage (VGL) to turn on the switch elements of the pixel circuit. The high-speed driving region is driven at a high frame frequency by inputting a high-frequency start pulse (VST). The low-speed driving region is driven at a low frame frequency by inputting a low-frequency start pulse (VST).

Each of the signal transmission units [ST(i-1) to ST(i+2)] can output a next pulse after a previous signal transmission unit outputs a gate pulse when a carry signal (CAR) of a gate-on voltage (VGL) is input to a start signal input node (31). When the first control node (Q) is precharged by the carry signal (CAR) of the gate-on voltage (VGL), when the gate-on voltage (VGL) or the shift clock of the gate-on voltage (VGL) is input to a pull-up transistor, the pull-up transistor is turned on and the gate-on voltage (VGL) is output through the output node. Therefore, the signal transmission unit into which the carry signal (CAR) is input may be a signal transmission unit that sequentially outputs gate pulses after the first gate pulse on the entire screen, or may be a signal transmission unit that sequentially outputs gate pulses after the first gate pulse for each divided area when the screen is split and driven.

Each of the signal transmission units [ST(i-1) to ST(i+2)] cannot output a gate-on voltage when a gate-off voltage (VGH) is input to the input node (31) without a start pulse (VST) and a carry signal (CAR). This is because the first control node (Q) cannot be precharged, and thus the pull-up transistor cannot be turned on. Accordingly, a pixel connected to a signal transmission unit to which a gate-off voltage (VGH) is input without a start pulse (VST) and a carry signal (CAR) during one frame period is not updated with new pixel data, and therefore is a pixel in a low-speed driving area that maintains the data voltage of pixel data charged in the previous frame period, or a pixel in an inactive area that displays a black gradation.

Shift clocks (CLK1 to CLK4) are input to signal front ends [ST(i-1) to ST(i+2)] through clock input nodes (32). A first shift clock (CLK1) may be input to an n-1th signal transmission unit [ST(n-1)], and a second shift clock (CLK2) may be input to an nth signal transmission unit [ST(n)]. A third shift clock (CLK3) may be input to an n+1th signal transmission unit [ST(n+1)], and a fourth shift clock (CLK4) may be input to an n+2th signal transmission unit [ST(n+2)]. In the forward mode, the shift clocks may be phase-shifted in the order of CLK1, CLK2, CLK3, and CLK4 as illustrated in FIG. 6A. In reverse mode, the shift clocks can be phase shifted in the order of CLK4, CLK3 CLK2, and CLK1 as shown in Fig. 6b.

Each of the signal transmission units [ST(i-1) to ST(i+2)] outputs a gate pulse [SRO(i-1) to SRO(i+2)] through the output node (33). The voltage of the first control node (Q) of each of the signal transmission units [ST(i-1) to ST(i+2)] must be pre-charged so that the gate-on voltage (VGL) can be output through the output node (33).

During a driving frame period in which gate pulses are sequentially output from a gate driver, the shift register receives a start pulse (VST) or a carry signal (CAR to CAR4) received from a previous signal transmission unit, outputs gate pulses [SRO(i-1)) to SRO(i+2)] in synchronization with the rising edge of the shift clock (CLK1 to CLK4), and shifts the gate pulses [SRO(i-1)) to SRO(i+2)] in synchronization with the rising edge of the shift clock.

Each of the signal transmission sections of the shift register can be implemented with a pass-gate circuit like that of Fig. 3a or an edge trigger circuit like that of Fig. 3b.

In the pass gate circuit, a clock (CLK) is input to a pull-up transistor (Tup) that is turned on/off according to the voltage of the first control node (Q). In contrast, a gate-on voltage (VGL) is supplied to the pull-up transistor (Tup) of the edge trigger circuit, and a start pulse (VST) and a shift clock (CLK1 to CLK4) are input. The pull-down transistor (Tdn) is turned on/off according to the voltage of the second control node (QB). In the pass gate circuit, the first control node (Q) is floated in a pre-charged state according to the start signal. When the clock (CLK) is applied to the pull-up transistor (Tup) while the first control node (Q) is floating, the voltage of the first control node (Q) is boosted to a voltage (2VGL) greater than the gate-on voltage (VGL) by bootstrapping, as shown in Fig. 4, so that the voltage of the output signal [SRO(i)] changes to the gate-on voltage (VGL).

The edge trigger circuit generates an output signal [SRO(i)] with a waveform identical to the phase of the start signal because the voltage of the output signal [SRO(i)] changes with the voltage of the start signal in synchronization with the edge of the clock (CLK). When the waveform of the start signal is changed, the waveform of the output signal also changes accordingly. In the edge trigger circuit, the input signal can overlap with the output signal.

Fig. 5 is a diagram showing a bidirectional shift register. Fig. 6a is a waveform diagram showing a forward shift of a gate pulse. Fig. 6b is a waveform diagram showing a reverse shift of a gate pulse.

Referring to FIGS. 5 to 7, the gate driver can shift the gate pulse in the forward or reverse direction using a bidirectional shift register. The timing controller instructs the gate driver in the forward mode and the reverse mode.

In the forward mode, the start pulse (VST_F) is input to the first signal transmission section (ST1), and the phases of the shift clocks (CLK1 to CLK4) are shifted in the order of CLK1 to CLK4. At this time, the gate pulses (SRO1 to SROn) output from the bidirectional shift register are sequentially shifted in the order of SRO1, SRO2, ... SRO(n-10), SROn.

In the reverse mode, the start pulse (VST_R) is input to the nth signal transmission section (STn), and the phases of the shift clocks (CLK1 to CLK4) are shifted in the order of CLK4 to CLK1. At this time, the gate pulses (SRO1 to SROn) output from the bidirectional shift register are sequentially shifted in the order of SROn, SRO(n-1), ... SRO2, SRO1.

The gate driving unit of an organic light emitting diode (OLED) display may include first and second shift registers (SR1, SR2) as illustrated in FIG. 7.

Referring to FIG. 7, the gate driver includes a scan driver (SR1) that sequentially outputs scan pulses and an EM driver (SR2) that sequentially outputs EM pulses.

The scan driver (SR1) can sequentially output scan pulses (SCAN1 to SCANn) using a shift register that receives a start pulse (GVST) and a shift clock (GCLK). The scan pulses (SCAN1 to SCANn) swing between a gate-on voltage (VGL) and a gate-off voltage (VGH). In each of the signal transmission units of the scan driver (SR1), the gate-on voltage (VGL) can be output only when the first control node (Q) is charged with the gate-on voltage (VGL).

The EM driving unit (SR2) can sequentially output EM pulses (EM1 to EMn) using a second shift register that receives a start pulse (EVST) and a shift clock (ECLK). The EM pulses (SCAN1 to EMn) swing between a gate-on voltage (VGL) and a gate-off voltage (VGH). In each of the signal transmission units of the EM driving unit (SR2), the gate-on voltage (VGL) can be output only when the first control node (Q) is charged with the gate-on voltage (VGL).

The shift registers of each of the scan driver (SR1) and the EM driver (SR2) can be implemented as bidirectional shift registers.

The display device of the present invention can simultaneously display images of multiple applications or images of multiple content on the screen.

FIG. 8 is a diagram showing an example in which the display device of the present invention is applied to an infotainment system of a vehicle. FIG. 9 is a waveform diagram showing the frame frequency by area of the screen in FIG. 8.

Referring to FIGS. 8 and 9, the display device of the present invention can simultaneously display side mirror images, navigation images, weather information, and other additional service information on the screen when applied to the infotainment (system) of a vehicle. The side mirror images must be reproduced at high speed with a high frame frequency to ensure driving stability. In contrast, weather information can be reproduced at low speed because it has a long update cycle, and power consumption can be reduced by using the low-speed driving method.

The screen can be divided and driven into an A region where a first image (side mirror image) is displayed, a B region where a second image (navigation image) is displayed, and a C region where a third image (weather information) is displayed. The pixels of the A region are a high-speed driving region where the image is updated at a frame frequency of 90 Hz. The pixels of the B region are a normal driving region where the image is updated at a reference frame frequency of 60 Hz. The pixels of the C region are a low-speed driving region where the image is updated at a frame frequency of 30 Hz. In Fig. 9, FR1 to FR90 represent frame numbers. A1 to A90 represent the first to 90th frames of the A region driven at a frame frequency of 90 Hz. B1 to B60 represent the first to 60th frames of the B region driven at a frame frequency of 60 Hz. C1 to C30 represent the first to 30th frames of the C region driven at a frame frequency of 30 Hz.

Flexible displays such as rollable displays, foldable displays, bendable displays, and slidable displays can simultaneously display multiple application videos or multiple content videos in split views on the screen when the screen is expanded.

Fig. 10 is a drawing showing an example in which the display device of the present invention is applied to a flexible display with an expandable screen. Fig. 11 is a waveform diagram showing the frame frequency by area of the screen in Fig. 10.

Referring to FIGS. 10 and 11, the flexible display screen can be divided and driven by region to display two or more images simultaneously. In the example of FIG. 10, the screen can be divided and driven into region A, which is driven at a low speed to display a first image (weather information), region B, which is driven at a high speed to display a second image (movie), and region C, which is driven normally at a reference frame frequency to display a third image (navigation image). The pixels of region A can be driven at a frame frequency of 30 Hz. The pixels of region B can be driven at a frame frequency of 90 Hz. The pixels of region C can be driven at a frame frequency of 60 Hz. In FIG. 11, the timing diagram at the top is an example in which regions A, B, and C are driven at a frame frequency of 60 Hz. The timing diagram at the bottom is an example in which region A has a frame frequency of 30 Hz, region B has a frame frequency of 90 Hz, and region C has a frame frequency of 60 Hz.

The split areas on the screen can have variable frame frequencies depending on the content or application of the input image. The timing controller counts the frame frequency of the input image and synchronizes the data driver and the gate driver with the frame frequency of each area, thereby independently controlling the driving frequency of the pixels for each area.

Figure 12 is a drawing showing in detail the active period and vertical blank period of one frame period.

Referring to Figure 12, one frame period (1 Frame) is divided into an active interval (AT) in which pixel data of an input image is input, and a vertical blank period (VB) in which there is no pixel data.

During the active period (AT), pixel data equivalent to one frame to be written to pixels of the screens (A, B, C) is received by the data driver and written to the pixels (P). When the frame frequency increases, the active period (AT) of one frame period decreases, whereas when the frame frequency decreases, the active period (AT) of one frame period increases.

A vertical blank period (VB) is a blank period during which pixel data is not received by the timing controller between the active period (AT) of the N-1th (where N is a natural number) frame period and the active period (AT) of the Nth frame period. The vertical blank period (VB) may include a vertical sync time (VS), a vertical front porch (FP), and a vertical back porch (BP).

A vertical blank period (VB) is the time between the falling edge of the last pulse of the data enable signal (DE) received in the N-1th frame period and the rising edge of the first pulse of the data enable signal (DE) received in the Nth frame period. The start time of the Nth frame period is the rising timing of the first pulse of the data enable signal (DE).

The vertical synchronization signal (Vsync) defines one frame period and frame frequency. The horizontal synchronization signal (Hsync) defines one horizontal period (Horizontal time). The data enable signal (DE) defines the writing period of valid data including pixel data to be displayed on the screen. The host system can change the vertical synchronization signal (Vsync) according to the frame frequency of each area of the screen.

The pulse of the data enable signal (DE) is synchronized with the pixel data to be written to the pixels of the display panel. One pulse period of the data enable signal (DE) is one horizontal period (1H).

Figure 13 is a flowchart showing a method of driving a display device according to an embodiment of the present invention.

Referring to FIG. 13, the timing controller receives pixel data of an input image from a host system and timing signals (Vsync, Hsync, DE) synchronized with the pixel data (S01). The timing controller can count data enable signals (DE) to generate a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync). In this case, the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may not be received by the timing controller.

The timing controller counts the vertical synchronization signal (Vsync) to determine the frame frequency of the input image, divides the input image by area of the screen, and transmits the same to the data driver (S02 and S03). The timing controller generates a timing signal for controlling the data driver and the gate driver. The timing signal of the gate driver may include a start pulse (VST) and a shift clock (CLK1 to CLK4). The start pulse (VST) may be generated once at the beginning of a frame period during one frame period and may be generated at a frequency substantially identical to that of the vertical synchronization signal (Vsync). The frequencies of the vertical synchronization signal (Vsync) and the start pulse (VST) are the same as the frame frequency. One cycle of the vertical synchronization signal (Vsync) and the start pulse (VST) is the same as one frame period. When the frame frequency varies by area of the screen, the frequencies of the vertical synchronization signal (Vsync) and the start pulse (VST) are changed.

The timing controller synchronizes the driving timing of the data driver and the gate driver, and varies the driving frequency of the data driver and the gate driver according to the frame frequency of each area of the screen. The data driver and the gate driver write pixel data for each area of the screen under the control of the timing controller.

The gate driver is driven at a frame frequency higher than the reference frame frequency when driven in a high-speed driving range under the control of the timing controller (S04 and S05), and is driven at a frame frequency lower than the reference frame frequency when driven in a low-speed driving range (S06 and SO7). The gate driver is driven at the reference frame frequency when driven in a normal driving range under the control of the timing controller (S08).

FIG. 14A and FIG. 14B are block diagrams showing a gate control unit according to an embodiment of the present invention. FIG. 14A shows the transmission direction of a carry signal in the forward mode of the gate driver. FIG. 14B shows the transmission direction of a carry signal in the reverse mode of the gate driver.

Referring to FIGS. 14a and 14b, the gate driving unit includes a gate control unit (140) and a shift register (150).

The shift register (150) may include a plurality of signal transmission units (ST1 to STn) connected between the gate control unit (140) and the gate lines. Each of the signal transmission units (ST1 to STn) includes a start signal input node that receives a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) from the gate control unit (140), a clock input node that inputs a clock signal, and an output node that outputs a gate pulse (SRO1 to SROn).

The gate control unit (140) is connected to the start signal input node (31) and the output node (33) of each of the signal transmission units (ST1 to STn). The gate control unit (140) supplies a start pulse (VST) to the start signal input node (31) of a stage that outputs a first gate pulse in each of the divided areas of the screen. The gate control unit (140) supplies a carry signal (CAR) to the start signal input node (31) of a stage that outputs a gate pulse output after the first gate pulse in each of the divided areas of the screen. The gate control unit (140) supplies a gate off voltage (VGH) to the start signal input node (31) of a stage from which a gate pulse is not output in each of the divided areas.

The signal transmission units (ST1 to STn) output a gate pulse through the first output node via separated output nodes, and a carry signal through the second output node. In this case, the gate control unit (140) receives a carry signal (CAR) from the second output node where the carry signal is output.

Figures 15 to 17 are drawings showing the gate control unit (140) in detail.

Referring to FIGS. 15 to 17, the gate control unit (140) includes a start line selection unit (141), a switch control signal generation unit (142), and a plurality of start signal selection units (1401 to 1402).

The start line selection unit (141) includes a control node into which a selection signal is input, an input node into which a start pulse (VST) is input, and a plurality of output nodes from which the start pulse (VST) is output. The start line selection unit (141) outputs a start pulse (VST) through one or more output nodes selected according to the logic value of the selection signal. The start pulse (VST) output from the start line selection unit (141) is supplied to one or more signal transmission units (ST1 to STn) selected through the start signal selection units. The selection signal may be generated from a timing controller of the display device or a host system and input to the start line selection unit (141). The start pulse may be generated from the timing controller and input to the start line selection unit (141) through a level shifter.

When one of the active areas of the split areas of the screen is driven in one frame period, the start line selection unit (141) can apply a start pulse (VST) to the start signal input node (31) of the first signal transmission unit that outputs the first gate pulse in the active area. When two or more active areas are driven simultaneously, the start line selection unit (141) can apply a start pulse (VST) to the start signal input node (31) of the first stage of each of the active areas simultaneously.

The switch control signal generating unit (142) generates first to third control signals (SW1, SW2, SW3) for controlling the start signal selecting units (1401, 1402). The first control signal (SW1) controls the shift timing of a shift register that outputs a gate pulse following a previous gate pulse. The pulse of the first control signal (SW1) is synchronized with the carry signal (CAR). The pulse of the second control signal (SW2) controls the shift end timing of the shift register that stops the shifting of the gate pulses (SR01 to SROn) and the end line of the activation region. The pulse of the third control signal (SW3) is synchronized with the start pulse (VST) output from the start line selecting unit (141) and instructs the first signal transmitting unit to output the first gate pulse in each of the activation regions, thereby controlling the start timing of the shift register and the start line of the activation region. Each of the first to third control signals (SW1, SW2, SW3) is generated as a pulse of gate-on voltage (VGL).

The first control signal (SW1) is commonly applied to the start signal selection units (1401 to 1402) through the first control signal line (41). The second control signal (SW2) is commonly applied to the start signal selection units (1401 to 1402) through the second control signal line (42). The third control signal (SW3) is commonly applied to the start signal selection units (1401 to 1402) through the third control signal line (43). Since each of the control signals (SW1, SW2, SW3) is input to all the start signal selection units (1401 to 1402) through a single wire, there is almost no increase in the non-display area occupied by the control signal wire on the display panel.

The start line of the active region is the first pixel line among the pixel lines of the active region to which pixel data is written by the first gate pulse. The end line of the active region is the last pixel line to which the last gate pulse is applied.

The start signal selection units (1401 to 1402) correspond to the signal transmission units (ST1 to STn) of the shift register, respectively. Each of the start signal selection units (1401 to 1402) is commonly connected to the start line selection unit (141) and the switch control signal generation unit (142), and is connected to a corresponding signal transmission unit. For example, the first start signal selection unit (1401) is connected to the start line selection unit (141) and the switch control signal generation unit (142), and is connected to the start signal input node (31) and the output node (33) of the first signal transmission unit (ST1). The second start signal selection unit (1402) is connected to the start line selection unit (141) and the switch control signal generation unit (142), and is connected to the start signal input node (31) and the output node (33) of the second signal transmission unit (ST2). The nth start signal selection unit (140n) is connected to the start line selection unit (141) and the switch control signal generation unit (142), and is connected to the start signal input node (31) and output node (33) of the nth signal transmission unit (STn).

Each of the start signal selection units (1401 to 1402) outputs a carry signal (CAR) in response to a pulse of a first control signal (SW1) and outputs a gate-off voltage (VGH) in response to a pulse of a second control signal (SW2). In addition, each of the start signal selection units (1401 to 1402) outputs a start pulse (VST) in response to a pulse of a third control signal (SW3). An output node of each of the start signal selection units (1401 to 1402) is input to a start signal input node (31) of a corresponding signal transmission unit. Therefore, the start pulse (VST), the carry signal (CAR), and the gate-off voltage (VGH) output from the start signal selection units (1401 to 1402) are applied to the start signal input node (31) of a corresponding signal transmission unit in the shift register (150).

For example, the first start signal selection unit (1401) applies one selected from among a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) to the start signal input node (31) of the first signal transmission unit (ST1) under the control of the switch control signal generation unit (142). The second start signal selection unit (1402) applies one selected from among a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) to the start signal input node (31) of the second signal transmission unit (ST2) under the control of the switch control signal generation unit (142).

The n-1 start signal selection unit [1401(n-1)] applies one selected from among a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) to the start signal input node (31) of the n-1 signal transmission unit [ST(n-1)] under the control of the switch control signal generation unit (142). The n-th start signal selection unit (140n) applies one selected from among a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) to the start signal input node (31) of the n-th signal transmission unit (STn) under the control of the switch control signal generation unit (142).

Each of the signal transmission units (ST1 to STn) of the shift register (150) can output a gate pulse when the first control node (Q) is charged with the gate-on voltage (VGL) of the start pulse (VST). Each of the signal transmission units (ST1 to STn) can shift the gate pulse by outputting a gate pulse when the first control node (Q) is charged with the gate-on voltage (VGL) of the carry signal (CAR). Each of the signal transmission units (ST1 to STn) stops the shifting of the gate pulse by outputting a gate-off voltage (VGH) because the first control node (Q) is not charged with the gate-on voltage (VGL) when the gate-off voltage (VGH) is input. A capacitor (C) can be connected to the start signal input node (31) of the signal transmission units (ST1 to STn).

The start line selection unit (141) may include a demultiplexer (DEMUX) (160) as illustrated in FIGS. 16 and 17. The demultiplexer (160) receives a start pulse (VST) and outputs the start pulse (VST) through an output node indicated by the logic value of the selection signal (SEL). Therefore, the start line selection unit (141) inputs the start pulse (VST) to the first signal transmission unit that outputs the first gate pulse among the signal transmission units (ST1 to STn) of the shift register, thereby defining the start position of the divided areas.

The selection signal (SEL) can be generated from a timing controller of a host system or a display device. The selection signal (SEL) can be generated as digital data or as an analog voltage. If the selection signal (SEL) is generated as an analog voltage, the selection signal (SEL) can be converted into digital data through an analog-to-digital converter (ADC) (161) at a control node of a demultiplexer (160), as illustrated in FIG. 17. If the selection signal (SEL) is converted into an analog voltage, the number of selection signal wires connected to the start line selection unit (141) can be reduced to one.

The start line selection unit (141) may be built into the host system or timing controller, or may be configured as a separate circuit and mounted on a PCB (Printed Circuit Board) or FPC (Flexible Printed Circuit). The switch control signal generation unit (142) may be built into the timing controller.

Each of the start signal selection units (1401 to 1402) includes first to third switch elements (M1, M2, M3). The first switch element (M1) is turned on/off according to the voltage level of the first control signal (SW1). The second switch element (M2) is turned on/off according to the voltage level of the second control signal (SW2). The third switch element (M3) is turned on/off according to the voltage level of the third control signal (SW3). The switch elements (M1, M2, M3) may be implemented as p-channel transistors formed on a display panel. The switch elements (M1, M2, M3) may be formed on the display panel together with transistors of a pixel circuit and transistors of a shift register (150).

The first switching element (M1) is turned on according to the gate-on voltage (VGL) of the first control signal (SW1) and applies a carry signal (CAR) input from an output node of a previous signal transmitting unit to a start signal input node (31) of a corresponding second to n-th signal transmitting unit (ST2 to STn). Since there is no signal transmitting unit in front of the first signal transmitting unit (ST1), a start pulse (VST) instead of a carry signal (CAR) is input to the first switching element (M1) connected to the first signal transmitting unit (ST1). The carry signal (CAR) from the previous signal transmitting unit is input to the first switching element (M1) connected to the first signal transmitting units (ST2 to STn) respectively connected to the second to n-th signal transmitting units. The first switching element (M1) transmits the carry signal to the next stage in each of the divided areas of the screen. When the first switching element (M1) is turned off, the gate pulse is no longer shifted. The first switch element (M1) includes a gate connected to a first control signal line (41) to which a first control signal (SW1) is input, a first electrode to which a carry signal (or start pulse) is input, and a second electrode connected to a start signal input node (31) of a corresponding signal transmission section (ST1 to STn).

The second switch element (M2) is turned on according to the gate-on voltage (VGL) of the second control signal (SW2) and applies the gate-off voltage (VGH) to the start signal input node (31) of the signal transmission units (ST1 to STn). When the second switch element (M2) is turned on, the first control node (Q) of the signal transmission units (ST1 to STn) is not charged, so that no gate pulse is output from the corresponding signal transmission unit. On the other hand, when the second switch element (M2) is turned off, the start pulse (VST) or the carry signal (CAR) is input to the corresponding signal transmission unit, so that the gate pulse can be output. Therefore, the second switch element (M2) defines the position of the end line for each area of the screen. The second switch element (M2) includes a gate connected to a second control signal line (42) into which a second control signal (SW2) is input, a first electrode into which a gate high voltage (VGH) is input, and a second electrode connected to a start signal input node (31) of a corresponding signal transmission section (ST1 to STn).

The third control signal (SW3) defines the position of the first signal transmission unit from which the first gate pulse is output in each of the divided regions of the screen. The second control signal (SW2) defines the position of the last signal transmission unit from which the last gate pulse is output in each of the divided regions of the screen. Accordingly, the second and third control signals (SW2, SW3) can define the start position and end position of each divided region, and the size of the divided region.

The third switch element (M3) is turned on according to the gate-on voltage (VGL) of the third control signal (SW3) and applies a start pulse (VST) from the start line selection unit (141) to the start signal input node (31) of the corresponding signal transmission unit (ST1 to STn). Since the selection signal (SEL) of the demultiplexer (160) and the third switch element (M3) are synchronized, the start pulse (VST) is output from the demultiplexer (160) and at the same time, the third switch element (M3) is turned on so that the start pulse (VST) is supplied to the signal transmission unit at the desired position. The third switch element (M3) includes a gate connected to a third control signal line (43) into which a third control signal (SW3) is input, a first electrode connected to an output node of a start line selection unit (141), and a second electrode connected to a start signal input node (31) of a corresponding signal transmission unit (ST1 to STn).

The first to third control signals (SW1, SW2, SW3) are generated as pulses of the gate-on voltage (VGL) one by one at each of the start, shift, and end timings of the gate driver. In other words, two or more of the first to third control signals (SW1, SW2, SW3) are not generated as pulses of the gate-on voltage (VGL) simultaneously. Therefore, at a specific point in time, any one of the start pulse (VST), the carry signal (CAR), and the gate-off voltage (VGH) is input to an arbitrary signal transmission unit.

FIGS. 18a to 20b are drawings illustrating the operation of a gate driving circuit according to an embodiment of the present invention.

Referring to FIGS. 18a and 18b, at time t0 before the start pulse (VST) is generated, the second control signal (SW2) is generated as a pulse of the gate-on voltage (VGL). At this time, the first and third control signals (SW1, SW3) are generated as the gate-off voltage (VGH). At time t0, the signal transmission units (ST1 to ST4) apply the gate-off voltage (VGH) to the start signal input nodes (31) of the signal transmission units (ST1 to ST4). Therefore, since the first control nodes (Q) of the signal transmission units (ST1 to ST4) cannot be charged with the gate-on voltage (VGL) at time t0, the output voltage of the signal transmission units (ST1 to ST4) is the gate-off voltage (VGH).

Referring to FIGS. 19A and 19B, the start pulse (VST) is output through the second output node of the demultiplexer (160) at time t1, and in synchronization therewith, the third control signal (SW3) is generated as a pulse of the gate-on voltage (VGL). At this time, the first and second control signals (SW1, SW2) are generated as the gate-off voltage (VGH). The gate-on voltage (VGL) of the start pulse (VST) output from the demultiplexer (16) at time t1 is applied to the start signal input node (31) of the second signal transmission unit (ST2), so that the first control node (Q) of the second signal transmission unit (ST2) is charged. Therefore, the pull-up transistor of the second signal transmission unit (ST2) is turned on according to the voltage of the first control node (Q), so that the second signal transmission unit (ST2) causes the voltage of the gate pulse to rise to the gate-on voltage (VGL). The first, third and fourth signal transmission sections (ST1, ST3, ST4) maintain their output voltages at the gate-off voltage (VGH) because the voltage of the first control node (Q) is lower than the gate-on voltage (VGL) at time t1.

At time t2, the first control signal (SW1) is inverted to the gate-on voltage (VGL). At this time, the third control signal (SW3) is inverted to the gate-off voltage (VGH) and the second control signal (SW2) maintains the gate-off voltage (VGH). At time T2, a carry signal (CAR) from the output node (33) of the second signal transmission unit (ST2) is applied to the start signal input node (31) of the third signal transmission unit (ST3) through the first switch element (M1), so that the first control node (Q) of the third signal transmission unit (ST2) is charged. Therefore, the pull-up transistor of the third signal transmission unit (ST3) is turned on according to the voltage of the first control node (Q), so that the third signal transmission unit (ST3) raises the voltage of the gate pulse to the gate-on voltage (VGL). At time t2, the voltage of the first control node (Q) of the second signal transmission unit (ST2) changes to the gate-off voltage (VGL) applied through the first switch element (M1), so that the output voltage of the second signal transmission unit (ST1) is inverted to the gate-off voltage (VGH). The output voltages of the first and fourth signal transmission units (ST1, ST4) maintain the gate-off voltage (VGH) because the voltage of the first control node (Q) at time t2 is lower than the gate-on voltage (VGL).

Referring to FIGS. 20A and 20B, the second control signal (SW2) is generated as a pulse of the gate-on voltage (VGL) at time t3 to stop the shift operation of the shift register. At this time, the first control signal (SW1) is inverted to the gate-off voltage (VGH) so that the third control signal (SW3) maintains the gate-off voltage (VGH). At time t3, the gate-off voltage (VGH) is applied to the start signal input node (31) of the first to fourth signal transmission units (ST1 to ST4) through the second switch element (M2), so that the voltage of the first control node (Q) of the second signal transmission unit (ST2) is the gate-off voltage (VGH). Therefore, the signal transmission units (ST1 to ST4) output the gate-off voltage (VGH) at time t3.

In the examples of FIGS. 18a to 20d, the active area includes the second and third pixel lines connected to the output nodes of the second and third signal transmitting units (ST1, ST3).

As illustrated in FIGS. 8 and 9, the screen may be divided and driven into first to third regions (A, B, C) having different frame frequencies to display images of different contents. When the first to third regions (A, B, C) display images as active regions having different frame frequencies, the number of driving frames of the first to third regions (A, B, C) may be six as in FIGS. 21 to 27, but is not limited thereto. In FIGS. 21 to 27, the driving frames of the first to third regions (A, B, C) are exemplified as cases 1 to 6. The frame order may be changed depending on the frame frequency of each region. Therefore, it should be noted that the frame order is not limited to FIGS. 21 to 27.

During any one frame period, pixel data can be written only to the pixels of the first region (A) as illustrated in FIGS. 21 and 22 (Case 1). It is assumed that the first region (A) includes the first to kth (k is a positive integer greater than or equal to 2) pixel lines. During this frame period, scan pulses of a gate-on voltage (VGL) synchronized with a data voltage are sequentially generated through signal transmission units connected to the pixel lines of the first region (A), and the signal transmission units connected to the pixel lines of the second and third regions (B, C) output a gate-off voltage (VGH). At the beginning of this frame period, a third control signal (SW3) is input to the start signal input node (31) of the first signal transmission unit (ST1) connected to the first pixel line in response to the pulse of the gate-on voltage (VGL) through the demultiplexer (160) and the third switch element (M3), so that a first scan pulse is generated from the first signal transmission unit. The first control signal (SW1) is generated as a pulse of the gate-on voltage (VGL) while pixel data is addressed to the 2nd to kth pixel lines, and the carry signal (CAR) is sequentially input to the start signal input nodes (31) of the 2nd to kth signal transmission units, and as a result, the scan pulse is shifted in the first region (A). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the 2nd to kth signal transmission units. In order to stop the shift of the scan pulse in the end line of the first region (A), a pulse of the second control signal (SW2) is generated immediately after the scan pulse is generated from the kth signal transmission unit. Accordingly, as illustrated in FIG. 22, pixel data of the first image is sequentially written to the 1st to kth pixel lines of the first region (A), so that the first image is displayed, and the 2nd and 3rd regions (B, C) display a black color or maintain a previous image. In response to the second control signal (SW2), the gate-off voltage (VGH) is simultaneously input to the start signal input nodes (31) of the signal transmission units connected to the pixel lines of the second and third regions (B, C).

During any one frame period, pixel data can be written only to the pixels of the second region (B) as illustrated in FIGS. 21 and 23 (Case 2). It is assumed that the second region (B) includes the k+1 to 2k pixel lines. During this frame period, scan pulses of a gate-on voltage (VGL) synchronized with a data voltage are sequentially generated through signal transmission units connected to the pixel lines of the second region (B), and the signal transmission units connected to the pixel lines of the first and third regions (A, C) output a gate-off voltage (VGH). At the beginning of this frame period, in response to the pulse of the third control signal (SW3), a start pulse (VST) is input to the k+1-th signal transmission unit (STk+1) connected to the k+1-th pixel line through the demultiplexer (160) and the third switch element (M3), thereby generating a first scan pulse. The first control signal (SW1) is generated as a pulse of the gate-on voltage (VGL) while pixel data is addressed to the k+2 to 2k-th pixel lines, and a carry signal (CAR) is sequentially input to the start signal input nodes (31) of the k+2 to 2k-th signal transmission units, resulting in a shift of the scan pulse in the second region (B). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the k+2 to 2k-th signal transmission units. In order to stop the shift of the scan pulse in the end line of the second region (B), a pulse of the second control signal (SW2) is generated immediately after the scan pulse is generated from the 2k-th signal transmission unit. Accordingly, as illustrated in FIG. 23, pixel data of the second image is sequentially written to the k+1 to 2k-th pixel lines of the second region (B), so that the second image is displayed, and the first and third regions (A, C) display a black color or maintain a previous image. In response to the second control signal (SW2), the gate-off voltage (VGH) is simultaneously input to the start signal input nodes (31) of the signal transmission units connected to the pixel lines of the first and third regions (A, C).

During any one frame period, pixel data can be written only to pixels of the third region (C) as illustrated in FIGS. 21 and 24 (Case 3). It is assumed that the third region (C) includes the 2k+1 to 3k pixel lines. During this frame period, scan pulses of a gate-on voltage (VGL) synchronized with a data voltage are sequentially generated through signal transmission units connected to the pixel lines of the third region (C), and the signal transmission units connected to the pixel lines of the first and second regions (A, B) output a gate-off voltage (VGH). At the beginning of this frame period, in response to the pulse of the third control signal (SW3), a start pulse (VST) is input to the 2k+1 signal transmission unit connected to the 2k+1 pixel line (ST2k+1) through the demultiplexer (160) and the third switch element (M3), thereby generating a first scan pulse. A pulse of a first control signal (SW1) is generated while pixel data is addressed to the 2k+2 to 3k-th pixel lines, so that a carry signal (CAR) is sequentially input to the 2k+2 to 3k-th signal transmitting units, and as a result, a scan pulse is shifted in a third region (C). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the 2k+2 to 3k-th signal transmitting units. In order to stop the shift of the scan pulse in the end line of the third region (C), a pulse of a second control signal (SW2) is generated immediately after the scan pulse is generated from the 3k-th signal transmitting unit. Accordingly, as illustrated in FIG. 24, pixel data of a second image is sequentially written to the 2k+1 to 3k-th pixel lines of the third region (C), so that the third image is displayed, and the first and second regions (A, B) display a black color or maintain a previous image. In response to the second control signal (SW2), a gate-off voltage (VGH) is simultaneously input to the start signal input nodes (31) of the signal transmission units connected to the pixel lines of the first and second regions (A, B).

During any one frame period, pixel data can be written only to pixels in the first and second regions (A, B) as illustrated in FIGS. 21 and 25 (Case 4). During this frame period, scan pulses of gate-on voltage (VGL) synchronized with the data voltage are sequentially generated through signal transmission units connected to the pixel lines of the first and second regions (A, B), and signal transmission units connected to the pixel lines of the third region (C) output gate-off voltage (VGH). At the beginning of this frame period, as illustrated in FIG. 25, in response to the pulse of the third control signal (SW3), a start pulse (VST) is input to the first signal transmission unit (ST1) through the demultiplexer (160) and the third switch element (M3), so that a first scan pulse is generated in the first region (A). A pulse of a first control signal (SW1) is generated while pixel data is addressed to the 2nd to 2kth pixel lines, so that a carry signal (CAR) is sequentially input to the 2nd to 2kth signal transmitting units, and as a result, a scan pulse is shifted in the first and second regions (A, B). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the 2nd to 2kth signal transmitting units. In order to stop the shift of the scan pulse in the end line of the second region (B), a pulse of a second control signal (SW2) is generated immediately after the scan pulse is generated from the 2kth signal transmitting unit. Accordingly, as illustrated in FIG. 25, pixel data of the first and second images are sequentially written to the 1st to 2kth pixel lines of the first and second regions (A, B), so that the first and second images are displayed, and the third region (C) displays a black color or maintains a previous image. In response to the second control signal (SW2), the gate-off voltage (VGH) is simultaneously input to the start signal input nodes (31) of the signal transmission units connected to the pixel lines of the third region (C).

During any one frame period, pixel data can be written only to pixels in the second and third regions (B, C) as illustrated in FIGS. 21 and 26 (Case 5). During this frame period, scan pulses of gate-on voltage (VGL) synchronized with the data voltage are sequentially generated through signal transmission units connected to the pixel lines of the second and third regions (B, C), and signal transmission units connected to the pixel lines of the first region (A) output gate-off voltage (VGH). At the beginning of this frame period, as illustrated in FIG. 26, in response to the pulse of the third control signal (SW3), a start pulse (VST) is input to the 2k+1th signal transmission unit (STk+1) through the demultiplexer (160) and the third switch element (M3), so that a first scan pulse is generated in the second region (B). A pulse of a first control signal (SW1) is generated while pixel data is addressed to the k+1 to 3k-th pixel lines, so that a carry signal (CAR) is sequentially input to the k+1 to 3k-th signal transmitting units, and as a result, a scan pulse is shifted in the second and third regions (B, C). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the k+1 to 3k-th signal transmitting units. In order to stop the shift of the scan pulse in the end line of the third region (C), a pulse of a second control signal (SW2) is generated immediately after the scan pulse is generated from the 3k-th signal transmitting unit. Accordingly, as illustrated in FIG. 26, pixel data of the second and third images are sequentially written to the k+1 to 3k-th pixel lines of the second and third regions (B, C), so that the second and third images are displayed, and the first region (A) displays a black color or maintains a previous image. In response to the second control signal (SW2), the gate-off voltage (VGH) is simultaneously input to the start signal input nodes (31) of the signal transmission units connected to the pixel lines of the first region (A).

As can be seen in FIGS. 25 and 26, when two active regions are driven, a start pulse is input to a signal transmission unit connected to a pixel line where pixel data starts to be written, and a gate pulse (scan pulse) is sequentially shifted. When two active regions are driven in one frame period, a start pulse is input to one signal transmission unit by a third control signal (SW3) so that the gate pulse can be shifted in the two regions, and a carry signal is transmitted to the signal transmission units of the two regions by the first control signal (SW1). Therefore, the two active regions driven in one frame period are adjacent so that a carry signal can be transmitted.

During any one frame period, pixel data can be written only to pixels in the second and third regions (B, C) as illustrated in FIGS. 21 and 27 (Case 6). During this frame period, scan pulses of gate-on voltages (VGL) synchronized with data voltages are sequentially generated through signal transmission units connected to pixel lines in the first to third regions (A, B, C). At the beginning of this frame period, as illustrated in FIG. 27, in response to a pulse of a third control signal (SW3), a start pulse (VST) is input to the first signal transmission unit (ST1) through a demultiplexer (160) and a third switch element (M3), so that a first scan pulse is generated in the first region (A). A pulse of a first control signal (SW1) is generated while pixel data is addressed to the 2nd to 3rd k pixel lines, so that a carry signal (CAR) is sequentially input to the 2nd to 3rd k signal transmitting units, and as a result, a scan pulse is shifted in the first to third areas (A, B, C). During this frame period, scan pulses synchronized with the data voltage are sequentially output from the 1st to 3rd k signal transmitting units. In order to stop the shift of the scan pulse in the last pixel line of the third area (C), a pulse of a second control signal (SW2) is generated immediately after the scan pulse is generated from the 3rd k signal transmitting unit. Therefore, pixel data of the first, second, and third images are sequentially written to the 1st to 3rd k pixel lines of the first to third areas (A, B, C) as illustrated in FIG. 27.

Fig. 28 is a drawing showing an example of a variable size of an active area of a rollable display. Figs. 29a to 29d are drawings showing various screen modes of a rollable display.

Referring to FIG. 28, the rollable display of the present invention includes a flexible panel (100) and rollers (101, 102) around which the flexible panel (100) is wound. The screen of the flexible panel (100) includes a plurality of data lines, a plurality of gate lines intersecting the data lines, and a pixel array in which pixels are arranged in a matrix form. The screen of the flexible panel (100) can be driven by region to display different images by region. The frame frequencies of the regions that are divided and driven can be different.

The rollers (101, 102) can be connected to the top or bottom of the flexible panel (100), or connected to the top and bottom. At least one of the rollers (101, 102) can be rotated in both directions by a motor. The rollers (101, 102) can be rotated so that the active area (100A) of the flexible panel (100) can be expanded or reduced, and its position can be moved.

The active area (100A) can be divided and driven into two or more areas so that images with different frame frequencies can be displayed simultaneously. The inactive area (100B) can be wound around the rollers (101, 102) within a case in which the rollers (101, 102) are not shown, or can be exposed on the screen. The inactive area (100B) can display a black gradation or maintain a previous image.

The rollable display of the present invention can provide various screen modes in which the sizes of the active areas (100A) are set differently, as shown in FIGS. 29A to 29D. FIG. 29A is a drawing showing the screen size in full screen mode (or frame mode). FIGS. 29B to 29D are drawings showing the screen sizes in various partial modes.

The host system can provide various partial modes according to the image content or user command. The screen size of the active area (100A) can be varied according to the number of rotations of the motor. Therefore, the host system can count the number of rotations of the motor to determine the size and movement position of the active area (100A). The host system scales the image data to the screen size of the exposure driving area (NA) according to the mode of the various partial modes and transmits it to the display panel driving unit of the rollable display.

The host system can switch to partial mode according to the content of the input image or a user command. When a TV signal is received or the user selects the TV mode, the host system can drive a motor to automatically adjust the screen ratio (x:y) of the TV mode to 16:9 as shown in Fig. 29b. In the TV mode, the active area (100A) can be 56.25% of the entire screen.

The host system can drive a motor to automatically adjust the screen ratio (x:y) to 21:9 of the screen ratio of the movie mode as shown in Fig. 29c when the video content is a movie or the user selects the movie mode. In the movie mode, the active area (100A) can be 42.86% of the entire screen.

The host system can drive a motor to automatically adjust the screen ratio (x:y) to 10:1 of the information display mode as shown in Fig. 29d when the input signal contains only text information without a video signal or when the user selects the information display mode. In the information display mode, the active area (100A) can be 10% of the entire screen.

When the active area (100A) is driven for a long time, stress on the pixels of the active area (100A) accumulates. In this case, even in images that are not fixed patterns, the lifespan of the pixels in the active area (100A) is reduced, and image quality problems such as reduced brightness and afterimages may occur. For example, when a user mainly uses the movie mode to display a movie for a long time in the active area (100A) with an aspect ratio of 21:9, only the pixels of this active area (100A) deteriorate rapidly. When the user switches to the TV mode and expands the active area (100A) to an aspect ratio of 16:9, a difference in brightness may be seen between the active area (100A) set in the movie mode and the inactive area (100B).

In order to reduce the difference in deterioration between the pixels of the active area (100A) and the pixels of the inactive area (100B), the present invention can drive a motor to move the position of the active area (100B) up and down or reciprocally at a predetermined time cycle as shown in FIG. 30. In this case, the present invention can freely adjust the start timing, shift timing, and shift end timing of the gate pulse as in the above-described embodiment using the control signals (SW1, SW2, and SW3) to enable the size variation or position movement of the active area (100A). Therefore, the present invention can prevent afterimages, stains, brightness deviations, etc. on the screen by dispersing the stress accumulated in the pixels of the active area (100A).

Fig. 31 is a drawing showing an example of split driving of a screen in a rollable display.

Referring to FIG. 31, the rollable display of the present invention can divide the active area into two or more to display different images or information, and can vary the frame frequency according to the displayed image or information. For example, the first area (A) can be a high-speed driving area where a movie is displayed, and the second area (B) can be a low-speed driving area where additional information is displayed.

Assume that the pixel array of the first region (A) includes the first to k-th pixel lines, and the second region (B) includes the k+1 to 2k-th pixel lines. The third control signal (SW3) indicates the start line position of each of the regions (A, B) in synchronization with the start pulse (VST). The first control signal (SW1) indicates a section in which the gate pulse is shifted, that is, a carry signal transmission section. The second control signal (SW2) indicates an end line at which the shifting of the gate pulse stops.

During any one frame period, pixels of the first and second regions (A, B) can be driven. Pulses of the control signals (SW1, SW2, SW3) can be generated for each region so that each of the regions (A, B) can be scanned independently. For example, the first pulse (1a) of the third control signal (SW3) is input to the start signal input node (31) of the first signal transmission unit (ST1) in the t01 period. In response to the first pulse (1a) of the first control signal (SW1), the first signal transmission unit (ST1) applies a gate pulse to the first pixel line of the first region (A). The first pulse (1a) of the first control signal (SW1) is generated in the t02 period. The second to k-1th signal transmission units receive a carry signal in the t02 period and sequentially output gate pulses. At this time, gate pulses are sequentially applied to the second to fourth pixel lines of the first region (A). The first pulse (3a) of the second control signal (SW2) is generated in the t03 section. The kth signal transmission unit outputs a gate-off voltage (VGH) according to the gate high voltage input at t03. At this time, the shift of the gate pulse in the first region ends.

At the start line of the second region (B), the gate pulse begins to be applied again. At the start line, the second pulse (2b) of the third control signal (SW3) is generated. Subsequently, the second pulse (2b) of the first control signal (SW1) is generated, and then the second pulse (3b) of the second control signal (SW2) is generated at the end line of the second region (B).

Fig. 32 is a circuit diagram showing another embodiment of a gate control unit. Components that are substantially the same as those in the embodiment described above in Fig. 32 are given the same drawing reference numerals and a detailed description thereof is omitted.

Referring to FIG. 32, the gate control unit (140) includes a start and end line control unit (320).

The start and end line control unit (320) includes a first control unit (321), a second control unit (322), a third control unit (323), and a start line selection unit (324). The start and end line control unit (320) generates a start pulse (VST) and control signals (SW1, SW2, SW3).

The first control unit (321) generates a control signal that indicates a start line position and an end line position of an active area according to input data (SDATA). The input data (SDATA) may include at least one of panel displacement information of a rollable display and resolution information of an input image. The panel displacement information may be obtained based on the number of rotations of a motor and may include information on the amount of movement of a flexible panel (100) on which a roller is to be rotated. The resolution information of the input image may be generated from a host system or obtained as a result of counting pixel data of the input image. The resolution information of the input image may include information such as a size of an active area, a start line, and an end line of the active area.

The first control unit (321) can generate a start pulse and start data at the driving timing of the start line, and can generate end data at the driving timing of the end line. The first control unit (321) can generate a selection signal that controls the start line selection unit (324).

The second control unit (322) generates a third control signal (SW3) in response to start data from the first control unit (321). The third control unit (323) generates a second control signal (SW2) in response to end data from the first control unit (321). Either of the second and third control units (322, 323) can generate the first control signal (SW1). The second and third control units (322, 323) can shift the control signals (SW1, SW1, SW3) using a bidirectional shift register.

The start line selection unit (324) outputs a start pulse (VST) through an output node indicated by a selection signal. When the start line of the activation area is driven, a start pulse is output from the start line selection unit (324). This start pulse (VST) is input to a signal transmission unit connected to the start line through a third switch element (SW3). The start line selection unit (324) can output the start pulse (VST) to one or more selected signal transmission units through a demultiplexer.

In synchronization with the start pulse (VST), the third control signal (SW3) is generated as a pulse of the gate-on voltage (VGL), and the start pulse can be input only to the signal transmission unit connected to the start line of the activation area. The selected signal transmission unit outputs a gate pulse in response to the start pulse (VST), and pixel data of the image starts to be written from the start line of the activation area to which the gate pulse is applied. When the second switch element (M2) is turned on by the second control signal (SW2) after the gate pulse shifts to the end line of the activation area, the gate pulse is not shifted after the end line. The second and third control units (322, 323) shift the second and third control signals (SW2, SW3) as illustrated in FIG. 33 when the flexible panel is rolled to change the positions of the start line and the end line of the activation area.

When displacement of the display panel occurs, at least one of the second and third control signals (SW2, SW3) can be shifted. Since the pulse of the first control signal (SW1) is generated following the pulse of the third control signal (SW3), the third control signal (SW3) and the first control signal (SW1) can be shifted simultaneously.

Figures 34a and 34b are drawings showing a method of controlling a gate driver when the size of the active area is gradually expanded and reduced.

In a rollable display, an active area may become smaller when a flexible panel is rolled around a roller. When the active area is reduced in the vertical direction, an exposed screen of the flexible panel is reduced, so that a start line moves downward and an end line moves upward, so that a vertical resolution of the active area may be reduced. The second control unit (322) shifts the third control signal (SW3) downward on the flexible panel every frame period, as illustrated in FIG. 34a. The third control unit (323) shifts the second control signal (SW2) upward on the flexible panel every frame period. At this time, the start line of the active area is shifted downward on the time axis, and the end line is shifted upward. The start line and the end line may be moved every frame period (FR1 to FR7) while the flexible panel is rolled.

In a rollable display, an active area can be enlarged when the flexible panel is released from the roller. When the active area is expanded in the vertical direction, the exposed screen of the flexible panel becomes enlarged, so that a start line moves upward and an end line moves downward, so that a vertical resolution of the active area can be increased. The second control unit (322) shifts the third control signal (SW3) upward on the flexible panel every frame period, as illustrated in FIG. 34b. The third control unit (323) shifts the second control signal (SW2) downward on the flexible panel every frame period. At this time, the start line of the active area is shifted upward on the time axis, and the end line is shifted downward. The start line and the end line can be moved every frame period (FR1 to FR7) while the flexible panel is rolled.

When the flexible panel is rolled and the activation area becomes smaller, the resolution of the activation area and the 1 frame period are reduced. Therefore, the start and end line control unit (320) can drive the activation area at high speed by increasing the frame frequency of the activation area without changing 1 horizontal period when the activation area becomes smaller, as shown in FIG. 35. In FIG. 35, FR1 to FR60 represent the first to 60th frame periods at a frame frequency of 60 Hz. FR1 to FR90 represent the first to 90th frame periods at a frame frequency of 90 Hz.

Fig. 36 is a drawing showing an example of an active area moving up and down to prevent afterimages in a rollable display. Fig. 37 is a drawing showing a method of controlling a gate driver when the screen moves up and down.

Referring to FIGS. 36 and 37, an active area (100A) on which an image is displayed can be moved up and down on the screen of the flexible panel (100). The active area (100B) is moved in the opposite direction of the movement direction of the flexible panel (100) when the flexible panel (100) is moved up or down by the roller. Since the active area (100A) is moved in the opposite direction to the physical movement direction of the flexible panel (100), the absolute position of the active area (100A) viewed by the user is fixed. Therefore, the user does not recognize the change in the position of the active area (100A). Although the absolute position of the active area (100B) viewed by the user does not change, since the active area (100B) is moved up and down on the flexible panel (100), stress on the pixels can be distributed.

The second control unit (322) shifts the third control signal (SW3) downward by the amount of movement of the flexible panel (100) during the frame period in which the flexible panel (100) moves upward as illustrated in FIG. 37. The second control unit (322) shifts the third control signal (SW3) upward by the amount of movement of the flexible panel (100) during the frame period in which the flexible panel (100) moves downward. The third control unit (323) shifts the second control signal (SW2) downward by the amount of movement of the flexible panel (100) during the frame period in which the flexible panel (100) moves upward. The third control unit (323) shifts the second control signal (SW2) upward by the amount of movement of the flexible panel (100) during the frame period in which the flexible panel (100) moves downward. At this time, the size of the active area does not change and the start line and the end line can be shifted in the same direction. The start line and end line can be moved in opposite directions every frame period (FR1 to FR7) as the flexible panel (100) moves up and down.

In order to prevent afterimages, Fig. 7 illustrates an example in which the control signals (SW2, SW3) shift upward or downward for each frame period, but is not limited thereto. For example, the control signals (SW2, SW3) may change the shift direction in units of N (N is a positive integer greater than or equal to 2) frame periods or in units of seconds so that the active area may move back and forth in the opposite direction to the movement direction of the display panel. When the sensing result of the accumulated stress amount of pixels or the expected amount of the accumulated stress is reached, the control signals (SW1, SW3) may start to shift in order to prevent afterimages.

According to the gate control method of FIGS. 34a, 34b, and 37, the gate driving unit (20) shifts the positions of gate pulses applied to the start line and the end line of the area where an image is displayed on the screen for each frame period while the display panel is moved.

According to the gate control method of FIGS. 34a and 34b, the gate driving unit (20) can shift the start line of the area where the image is displayed every frame period while the display panel is moved, and shift the positions of the gate pulses applied to the end line of the area in the opposite direction to the shift direction of the gate pulses applied to the start line.

According to the gate control method of Fig. 37, the gate driving unit (20) can shift the gate pulse applied to the gate line of the start line up and down, and shift the gate pulse applied to the gate line of the end line in the same direction as the gate pulse applied to the gate line of the start line. The gate pulse applied to the start line and the gate pulse applied to the end line can be shifted in the opposite direction to the movement direction of the display panel.

In order to shorten the motion picture response time (MPRT) of pixels, a black gray voltage can be applied to pixels in a black gray insertion mode. The black gray insertion mode supplies a black gray voltage to pixels to erase an image of a previous frame. In the black gray insertion mode, light-emitting elements of pixels are turned off to display a black gray. Gate pulses (SR01 to SRO4) are phase-shifted in a block sequential manner as illustrated in FIG. 38 in the black gray insertion mode so that multiple pixel lines are selected simultaneously. The gate pulse is synchronized with the black gray voltage (Vblack). The gate control unit (140) can control signal transmission units so that the gate pulse can be shifted in block units in the black gray insertion mode. In the black gray insertion mode, after the maximum voltage that can be output from the data driving unit is applied to the pixels for two horizontal periods (2H), the black gray voltage (Vblack) can be applied to the pixels. In Fig. 38, IDW is a normal driving period in which pixel data of an input image is written to pixels and the pixels emit light. BDI is a black tone insertion period in which the pixels are turned off.

During the black tone insertion period, the first and third control signals (SW1, SW2) may be generated simultaneously as pulses of the gate-on voltage (VGL) so that the first and third switch elements (M1, M3) may be turned on simultaneously. At this time, the start line selection unit (141) may output a start pulse (VST) to two or more output nodes in synchronization with the pulses of the first and third control signals (SW1, SW2).

Fig. 39 is a circuit diagram showing the signal transmission section of the scan driver (SR1) in detail. Fig. 40 is a waveform diagram showing the input/output signals of the signal transmission section shown in Fig. 39. It should be noted that the signal transmission section circuit of the scan driver (SR1) is not limited to Fig. 39.

Referring to FIGS. 39 and 40, the nth signal transmission unit includes first to eighth transistors (T1 to T8). The transistors (T1 to T8) may be implemented as p-channel TFTs. The signal transmission unit receives a start pulse (GVST) or a carry signal (CAR) through first and second shift clocks (GCLK1, GCLK2), a gate-on voltage (VGL), a gate-off voltage (VGH), and a start signal input node (31). The second shift clock (GCLK2) is delayed by 180° in phase compared to the first shift clock (GCLK1). In the nth signal transmission unit, the first shift clock (GCLK1) may be input to the first clock input node (32a), and the second shift clock (GCLK2) may be input to the second clock input node (32b). In the n+1 signal transmission unit, the first shift clock (GCLK1) can be input to the second clock input node (32b), and the second shift clock (GCLK2) can be input to the first clock input node (32a).

The first transistor (T1) is turned on according to the gate-on voltage (VGL) of the second shift clock (GCLK2) and charges the first control node (Q, Q1) with the gate-on voltage (VGL) of the start pulse (GVST) or the carry signal (CAR). The first control node includes a 1-1 control node (Q) and a 1-2 control node (Q1) separated by an eighth transistor (T8). When the eighth transistor (T8) is turned on during normal driving, the 1-1 control node (Q) and the 1-2 control node (Q1) are connected. The first transistor (T1) includes a gate connected to a second clock input node (32b) to which the second shift clock (GCLK1) is input, a first electrode connected to a start signal input node (31), and a second electrode connected to the 1-1 control node (Q).

The second control node can be divided into a 2-1 control node (QP) and a 2-2 control node (QB). The second transistors (T2a, T2b) are turned on when the 2-1 control node (QP) is charged with the gate-on voltage (VGL) and connect the first clock input node (32a) to which the first shift clock (GCLK1) is input to the 2-2 control node (QB). When the second transistors (T2a, T2b) are turned on and the first shift clock (GCLK1) is at the gate-on voltage (VGL), the third transistor (T3) is turned on and the voltage of the 1-1 control node (Q) changes to the gate-off voltage (VGH).

The second transistors (T2a, T2b) may include second-first and second-second transistors (T2a, T2b) connected with a dual gate to reduce leakage current in the off state. The second-first transistor (T2a) includes a gate connected to the second-first control node (QP), a first electrode connected to the first clock input node (32a), and a second electrode connected to the first electrode of the second-second transistor (T2b). The second-second transistor (T2b) includes a gate connected to the second-first control node (QP), a first electrode connected to the second electrode of the second-first transistor (T2a), and a second electrode connected to the second-second control node (QB).

The third transistor (T3) is turned on according to the gate-on voltage (VGL) of the 2-2 control node (QB) to connect the 1-1 control node (Q) to the VGH node. The third transistor (T3) includes a gate connected to the 2-2 control node (QB), a first electrode connected to the 1-1 control node (Q), and a second electrode connected to the VGH node to which a gate-off voltage (VGH) is applied. A capacitor (CP) may be connected between the 2-1 control node (QP) and the 2-2 control node (QB). The capacitor (CP) may charge a differential voltage between the 2-1 control node (QP) and the 2-2 control node (QB) to set a voltage for controlling on/off of the second transistors (T2a, T2b) when the 2-1 control node (QP) is bootstrapped according to the voltage of the shift clocks (GCLK1, GCLK2).

The fourth transistor (T4) is turned on when the second shift clock (GCLK2) is at the gate-on voltage (VGL) to connect the VGL node to the 2-1 control node (QP). The fourth transistor (T4) includes a gate connected to the second clock input node (32b), a first electrode connected to the VGL node to which the gate-on voltage (VGL) is applied, and a second electrode connected to the 2-1 control node (QP).

The fifth transistor (T5a, T5b) is turned on when the 1-1 control node (Q) is at the gate-on voltage (VGL) to connect the second clock input node (32b) to the 2-1 control node (QP). The fifth transistor (T5a, T5b) may include fifth-first and fifth-second transistors (T5a, T5b) connected with a dual gate to reduce leakage current in the off state. The 5-1 transistor (T5a) includes a gate connected to the 1-1 control node (Q), a first electrode connected to the second clock input node (32b), and a second electrode connected to the first electrode of the 5-2 transistor (T5b). The 5-2 transistor (T5b) includes a gate connected to the 1-1 control node (Q), a first electrode connected to the second electrode of the 5-1 transistor (T5a), and a second electrode connected to the 2-2 control node (QP).

When the first shift clock (GCLK1) changes to the gate-on voltage (VGL) while the first-second control node (Q1) is charged to the gate-on voltage (VGL), the voltage of the first-second control node (Q1) changes to a voltage lower than the gate-on voltage (VGL) by bootstrapping. At this time, the sixth transistor (T6) is turned on so that the voltage of the output node (33) changes to the gate-on voltage (VGL) and a scan pulse (SCAN) is generated. The sixth transistor (T6) is a pull-up transistor that is turned on when the voltage of the first-second control node (Q1) is boosted to a voltage lower than VGL by bootstrapping. The sixth transistor (T6) includes a gate connected to the first-second control node (Q1), a first electrode connected to the first clock input node (32a), and a second electrode connected to the output node (33). A capacitor (CQ) may be connected between the first-second control node (Q1) and the output node (33). The capacitor (CQ) charges the differential voltage between the first-second control node (Q1) and the output node (33). When bootstrapping occurs by the first shift clock (GCLK1), the sixth transistor (T6) is kept in an on state with the voltage of the capacitor (CQ).

The seventh transistor (T7) is a pull-down transistor that is turned on when the 2-1 control node (QP) is at the gate-on voltage (VGL) and connects the output node (33) to the VGH node. The seventh transistor (T7) includes a gate connected to the 2-1 control node (QP), a first electrode connected to the output node (33), and a second electrode connected to the VGH node.

The eighth transistor (T8) is turned on according to the gate-on voltage (VGL) to connect the 1-1 control node (Q) to the 1-2 control node (Q). The eighth transistor (T8) includes a gate connected to the VGL node, a first electrode connected to the 1-1 control node (Q), and a second electrode connected to the 1-2 control node (Q1). The voltage of the 1-1 control node (Q) may be bootstrapped by the second shift clock (GCLK2) to be boosted to a voltage lower than the gate-on voltage (VGL). At this time, the eighth transistor (T8) is turned off to separate the 1-1 control node (Q) and the 1-2 control node (Q1), thereby reducing deterioration of the sixth transistor (T6).

Before the start pulse (GVST) or the carry signal (CAR) is input to the nth signal transmission section, the second transistor (T2a, T2b) is in an on state. At this time, the third transistor (T3) is turned on according to the gate-on voltage (VGL) of the first shift clock (GCLK1) supplied through the second transistor (T2a, T2b) to refresh the voltage of the 1-1 control node (Q) to the gate-off voltage (VGH), thereby stabilizing the voltages of the 1-1 and 1-2 control nodes (Q, Q1) to the gate-off voltage (VGH) and maintaining the sixth transistor (T6) in an off state. The fourth transistor (T4) is turned on in the second shift clock (GCLK2) cycle before the start pulse (GVST) is generated and applies a gate-on voltage (VGL) to the 2-1 control node (QP) to control the second and seventh transistors (T2a, T2b, T7) to an on state. The fifth transistor (T5a, T5b) is maintained in an off state before the start pulse (GVST) or the carry signal (CAR) is input to the nth signal transmission section. Therefore, the voltage of the output node (33) is the gate-off voltage (VGH) before the start pulse (GVST) is input.

When a start pulse (GVST) or a carry signal (CAR) is input to the nth stage (①), the fifth transistor (T5a, T5b) is turned on, the 2-1 control node (QP) is charged with the gate-on voltage (VGL), and the second transistor (T2a, T2b) and the seventh transistor (T7) are turned on.

In a state where the 1st and 1st-2nd control nodes (Q, Q1) are charged with the gate-on voltage (VGL) of the start pulse (GVST) or the carry signal (CAR) (②), the gate-on voltage (VGL) of the first shift clock (GCLK1) is generated, and the 1st-2nd control node (Q1) is boosted to a voltage lower than the gate-on voltage (VGL) due to bootstrapping. At this time, the 6th transistor (T6) is turned on, so that the voltage of the output node (33) changes to the gate-on voltage (VGL), and the scan pulse (SCAN) rises.

Next, when the first shift clock (GCLK1) is inverted to the gate-off voltage (VGH) and the second shift clock (GCLK2) is inverted to the gate-on voltage (VGL) (③), the second transistors (T2a, T2b) and the seventh transistor (T3) are turned on according to the gate-on voltage (VGL) of the 2-1 control node (QP), so that the voltage of the output node (33) is inverted to the gate-off voltage (VGH).

Fig. 41 is a circuit diagram showing the signal transmission unit of the EM driving unit in detail. Fig. 42 is a waveform diagram showing the input/output signals of the signal transmission unit illustrated in Fig. 40. It should be noted that the signal transmission unit circuit of the EM driving unit (SR2) is not limited to Fig. 41. The signal transmission unit receives a start pulse (EVST) or a carry signal (CAR) through a first shift clock (ECLK1), a gate-on voltage (VEL), a gate-off voltage (VEH), and a start signal input node (31). The first shift clock (ECLK1) is input to the nth signal transmission unit, and a second shift clock (not illustrated) may be input to the n+1th signal transmission unit.

The first transistor (T21) is turned on according to the gate-on voltage (VEL) of the shift clock (ECLK1) and charges the first control node (Q) with the gate-on voltage (VEL) of the start pulse (EVST) or the carry signal (CAR) when the sixth transistor (T26) is in the on state. The first transistor (T21) includes a gate connected to a clock input node to which the shift clock (ECLK1) is input, a first electrode connected to a start signal input node (31), and a second electrode connected to the first control node (Q).

The second transistor (T22) is turned on when the first' control node (Q') is charged with the gate-on voltage (VGL) and connects the clock input node (32) to which the shift clock (GCLK1) is input to the second control node (QB). The second transistor (T22) includes a gate connected to the first' control node (Q'), a first electrode connected to the clock input node (32), and a second electrode connected to the second control node (QB).

The third transistor (T23) is turned on according to the gate-on voltage (VGL) of the first control node (Q) to connect the first' control node (Q') to the VEH node. The third transistor (T23) includes a gate connected to the first control node (Q), a first electrode connected to the first' control node (Q'), and a second electrode connected to the VEH node to which a gate-off voltage (VEH) is applied. A capacitor (CQ') may be connected between the clock input node (32) and the first' control node (Q'). The capacitor (CQ') may set a voltage for controlling the on/off of the second transistor (T22) by charging a differential voltage between the clock input node (32) and the first' control node (Q') and by bootstrapping that occurs when the voltage of the shift clock (ECLK1) changes to the gate-on voltage (VEL).

The fourth transistor (T24) is turned on when the voltage of the first control node (Q) is the gate-on voltage (VEL) to connect the second control node (QB) to the VEH node. The fourth transistor (T24) includes a gate connected to the first control node (Q), a first electrode connected to the second control node (QB), and a second electrode connected to the VEH node.

The fifth transistor (T25) is turned on when the voltage of the output node (33) is the gate-on voltage (VEL) to connect the VEL node to the node between the second electrode of the 8-1st transistor (T28a) and the first electrode of the 8-2nd transistor (T28b). The fifth transistor (T25) includes a gate connected to the output node (33), a first electrode connected to the VEL node, and a second electrode connected to the node between the second electrode of the 8-1st transistor (T28a) and the first electrode of the 8-2nd transistor (T28b).

The sixth transistor (T26) is turned on according to the gate-on voltage (VEL) to connect the Q node between the clock input node (32) and the gate of the seventh transistor (T27). The fifth transistor (T25) includes a gate connected to the VEL node, a first electrode connected to the second electrode of the first transistor (T21), and a second electrode connected to the first node (Q).

The seventh transistor (T27) is a pull-up transistor that is turned on when the voltage of the first control node (Q) is boosted to a voltage lower than VGL by bootstrapping. The seventh transistor (T27) includes a gate connected to the first control node (Q), a first electrode connected to the VEL node, and a second electrode connected to the output node (33). A capacitor (CB) may be connected between the first control node (Q) and the output node (33). The capacitor (CB) charges a differential voltage between the first control node (Q) and the output node (33) to stabilize the voltages of these nodes.

The eighth transistor (T28a, T28b) is a pull-down transistor that is turned on when the second control node (QQ) is at the gate-on voltage (VGL) and connects the output node (33) to the VEH node. The eighth transistor (T28a) may include the 8-1 and 8-2 transistors (T28a, T28b) that are connected with a dual gate. The 8-1 transistor (T28a) includes a gate connected to the second control node (QB), a first electrode connected to the output node (33), and a second electrode connected to the second electrode of the fifth transistor (T25) and the first electrode of the 8-2 transistor (T8b). The 8-2 transistor (T28b) includes a gate connected to the second control node (QB), a first electrode connected to the second electrode of the fifth transistor (T25) and the second electrode of the 8-1 transistor (T8b), and a second electrode connected to the VEH node.

When the shift clock (ELCK1) changes to the gate-on voltage (VEL), the voltage of the first control node (Q') is lowered to the gate-on voltage (VEL) by bootstrapping of the capacitor (CQ'), so that the second transistor (T23) is turned on, and the voltage of the second control node (QB) changes to the gate-on voltage (VEL). At this time, the eighth transistor (T28a, T28b) is turned on, so that the voltage of the output node (33) changes to the gate-off voltage (VEH).

When the shift clock (ELCK1) changes from the gate-on voltage (VEL) to the gate-off voltage (VEH), the voltage of the first' control node (Q') is increased to the gate-off voltage (VEH) by bootstrapping of the capacitor (CQ'), so that the second transistor (T23) is turned off and the second control node (QB) is floated. At this time, the eighth transistor (T28a, T28b) is maintained in an on state by the voltage of the floating second control node (QB), so that the voltage of the output node (33) is maintained at the gate-off voltage (VEH).

When the start pulse (EVST) or the carry signal (CAR) is the gate-on voltage (VEL), the third transistor (T23) is turned on, and the voltage of the first' control node (Q) rises to the gate-off voltage (VEH). When the start pulse (EVST) or the carry signal (CAR) is reversed to the gate-off voltage (VEH), the third transistor (T23) is turned off, the voltage of the first' control node (Q') rises, and the second transistor (T28) is turned off. At this time, the eighth transistor (T8a, T8b) is turned off, and when the first and sixth transistors (T21, T26) are turned on, the seventh transistor (T27) is turned on.

Referring to FIGS. 43 to 45, the foldable display includes a flexible panel (600) and a display panel driving unit (520, 300).

The display panel driving unit (520, 300) activates the entire screen of the flexible panel (600) when the flexible panel (600) is unfolded, thereby displaying an image on the maximum screen. The display panel driving unit (520, 300) activates a portion of the screen when the flexible panel (600) is folded, thereby displaying an image on an activated area smaller than the maximum screen, and may display black or maintain a previous image on an inactivated area.

The display panel driving unit (520, 300) includes a data driving unit (506), a gate driving unit (520), and a timing controller (503) that controls the operation timing of the data driving unit (506) and the gate driving unit (520). The data driving unit (506) and the timing controller (503) can be integrated into a drive IC (Integrated Circuit, 300).

The timing controller (503) can determine the folding and unfolding state of the flexible panel (600) based on the enable signal (EN) from the host system (400), and further, can know the folding angle of the flexible panel (600). The timing controller (503) can control the size and resolution of the active area in the unfolded state of the flexible panel (600) to the maximum screen and the maximum resolution. The screen in the unfolded state is a state in which the first and second areas (A, B) are substantially placed on the same plane.

The flexible panel (600) can be folded in the infolding manner illustrated in Fig. 44a or the outfolding manner illustrated in Fig. 44b. In the infolding method, the first and third regions (A, C) of the screen face each other on the inner surface of the folded flexible panel (600). In the infolding method, the first and third regions (A, C) of the screen are not exposed to the outside because they are on the inner surface of the folded flexible panel (600).

In the outfolding method, the flexible panel (600) is folded in a form in which the first region (A) and the third region (C) face each other as shown in Fig. 44b. Therefore, when the outfolding foldable display is folded, the regions (A, B, C) are exposed to the outside.

A second region (B) may be a folding boundary between the first region (A) and the third region (C). A plurality of regions may be folding boundaries on the screen of the flexible panel (600).

Pixels (P) may be arranged at the folding boundary (C). In this case, input images or information may also be displayed on the pixels at the folding boundary. Since the pixels (P) are arranged at the folding boundary, there is no image break between the first and third regions (A, C) in the unfolded state where the first and third regions (A, C) are spread out. The curvature of the folding boundary may vary depending on the folding angle of the flexible panel (600). The resolution and size of the folding boundary are proportional to the radius of curvature of the folding boundary.

When the flexible panel (600) is unfolded and the first region (A), the second region (B), and the folding boundary (C) are all driven, the size and resolution of the screens (A, B, C) can be at their maximum. When the flexible panel (600) is folded in half with the folding boundary between them and either the first region (A) or the third region (C) is driven, the size and resolution of the screen are reduced.

The drive IC (500) drives the pixel array of areas (A, B, C) that display images or information.

The flexible panel (600) can be implemented as a plastic OLED panel. The plastic OLED panel includes a pixel array on an organic thin film adhered to a back plate. A touch sensor array can be formed on the pixel array.

The back plate may be a PET (Polyethylene terephthalate) substrate. An organic thin film is formed on the back plate. A pixel array and a touch sensor array may be formed on the organic thin film. The back plate blocks moisture permeation toward the organic thin film so that the pixel array is not exposed to humidity. The organic thin film may be a thin PI (Polyimide) film substrate. A multilayer buffer film made of an insulating material (not shown) may be formed on the organic thin film. Wires for supplying power or signals applied to the pixel array and the touch sensor array may be formed on the organic thin film.

A gate driver (520) may be mounted on a substrate of a flexible panel (600) together with a pixel array. The gate driver (520) may include a gate control unit (140) as shown in FIGS. 14a and 14b, and a shift register (150). The shift register (150) may include a scan driver (SR1) that outputs a scan pulse, and an EM driver (SR2) that outputs an EM signal.

The gate driver (520) can select a start line and an end line of each region in response to the first to third control signals (SW1, SW2, SW3) and apply a gate pulse to the gate lines. The gate driver (520) can be implemented as a GIP (Gate in panel) circuit directly formed on a flexible panel (600).

The drive IC (500) is connected to the data lines (DL1 to DL6) through the data output channels and supplies the voltage of the data signal to the data lines. The drive IC (500) can output a gate timing signal for controlling the gate driver (520) through the gate timing signal output channels.

The drive IC (500) is connected to the host system (400), the first memory (501), and the flexible panel (600). The drive IC (500) includes a data receiving and calculation unit (508), a timing controller (503), and a data driving unit (506).

The drive IC (500) may further include a gamma compensation voltage generation unit (505), a power supply unit (504), a second memory (502), a gate control unit (507), etc. The gate control unit (507) may include the gate control unit described above and a level shifter omitted in the drawing.

The data reception and calculation unit (508) includes a reception unit (RX) that receives pixel data input as a digital signal from the host system (400), and a data calculation unit that processes the pixel data input through the reception unit (RX) to improve image quality. The data calculation unit may include a data restoration unit that decodes and restores compressed pixel data, an optical compensation unit that adds a preset optical compensation value to the pixel data, and the like. The optical compensation value may be set as a value for correcting the brightness of each pixel data based on the brightness of the screen measured based on a camera image captured during the manufacturing process.

The timing controller (503) provides pixel data of an input image received from the host system (400) to the data driving unit (506). The timing controller (503) generates a gate timing signal for controlling the gate driving unit (520) and a source timing signal for controlling the data driving unit (506), thereby controlling the operation timing of the gate driving unit (520) and the data driving unit (506). The timing controller (503) may include the aforementioned start line selection unit (141), a switch control signal generation unit (142), and a plurality of start signal selection units (1401 to 140n).

The data driving unit (506) converts pixel data (digital signal) received from the timing controller (503) into a gamma compensation voltage through a digital-to-analog converter (hereinafter referred to as “DAC”) and outputs the voltage of the data signal (DATA1 to DATA6) (hereinafter referred to as “data voltage”). The data voltage output from the data driving unit (506) is supplied to the data lines (DL1 to DL6) of the pixel array through an output buffer (Source AMP) connected to the data channel of the drive IC (500).

The gamma compensation voltage generator (505) distributes the gamma reference voltage from the power supply (504) through a voltage divider circuit to generate a gamma compensation voltage for each grayscale. The gamma compensation voltage is an analog voltage whose voltage is set for each grayscale of pixel data. The gamma compensation voltage output from the gamma compensation voltage generator (505) is provided to the data driving unit (506).

The gate control unit (507) includes a circuit configuration substantially the same as that described in the above-described embodiment. The level shifter converts a low level voltage of the gate timing signal into a gate-on voltage (VGL/VEL) and converts a high level voltage of the gate timing signal into a gate-off voltage (VGH/VEH). The gate timing signal includes a start pulse, a shift clock, first to third control signals (SW1, SW2, SW3), etc.

The power supply unit (504) generates power required to drive the pixel array of the flexible panel (600), the gate driver (520), and the driver IC (500) by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit (504) may adjust a DC input voltage from the host system (400) to generate DC power such as a gamma reference voltage, a gate on voltage (VGL), a gate off voltage (VGH), a pixel driving voltage (ELVDD), a low potential power supply voltage (ELVSS), and an initialization voltage (Vini). The gamma reference voltage is supplied to the gamma compensation voltage generator (505). The gate on voltage (VGL) and the gate off voltage (VGH) are supplied to the level shifter (507) and the gate driver (520). Pixel power supplies, such as pixel driving voltage (ELVDD), low-voltage power supply voltage (ELVSS), and initialization voltage (Vini), are supplied commonly to pixels (P).

The initialization voltage (Vini) is set to a DC voltage that is lower than the pixel driving voltage (ELVDD) and lower than the threshold voltage of the light-emitting element (OLED) to suppress light emission of the light-emitting element (OLED). The initialization voltage (Vini) can be continuously applied to the anode of the light-emitting element (OLED) for one frame period or more to a disabled pixel. The light-emitting element (OLED) is initialized when the initialization voltage (Vini) is applied to the anode.

The second memory (502) stores compensation values, register setting data, etc. received from the first memory (501) when power is supplied to the drive IC (500). The compensation values can be applied to various algorithms for improving image quality. The compensation values can include optical compensation values.

The register setting data defines the operation of the data driver (506), the timing controller (503), the gamma compensation voltage generator (505), etc. The first memory (501) may include a flash memory. The second memory (502) may include a static RAM (SRAM).

The host system (400) can be implemented as an AP (Application Processor). The host system (400) can transmit pixel data of an input image to the drive IC (500) through a MIPI (Mobile Industry Processor Interface). The host system (400) can be connected to the drive IC (500) through a flexible printed circuit, for example, an FPC (Flexible Printed Circuit) (310).

The host system (400) can output an enable signal (EN) that controls the operation of the drive IC (400) depending on whether the flexible panel (600) is folded. The enable signal (EN) can include information indicating whether the flexible panel (600) is folded and the folding angle.

The host system (400) can detect a change in the posture of the foldable display using a tilt sensor. The host system (400) can control the drive IC (500) in response to an output signal of the tilt sensor to control ON/OFF of each of the divided areas (A, B, C) on the screen. The tilt sensor can include a gyro sensor or an acceleration sensor. The host system (400) can transmit tilt information of the foldable display panel to the drive IC (500). The host system (400) can control the drive IC (500) in response to an output signal of the acceleration sensor.

When a user folds the foldable display and looks at the first area (A), the drive IC (500) can activate the first area (A) under the control of the host system (400) to display an image in the first area (A), while deactivating the third area (C) on the opposite side to control the first screen as an inactive area displaying a black gradation. Conversely, when the user folds the foldable display and looks at the third area (C), the drive IC (500) can activate the third area (C) under the control of the host system (400) to display an image in the third area (C), while controlling the first area (A) as an inactive area. When the user unfolds the foldable display and looks at the first and third areas (A, C), the drive IC (500) can activate the first area (A), the second area (B), and the third area (C) under the control of the host system (400) to drive the entire screen as an active area. At this time, the frame frequency of each area (A, B, C) may vary depending on the content or application.

Fig. 46 is a circuit diagram showing an example of a pixel circuit. Fig. 47 is a diagram showing a driving method of the pixel circuit shown in Fig. 46. The pixel circuit of the present invention is not limited to Fig. 46.

Referring to FIGS. 46 and 47, the pixel circuit includes a light-emitting element (OLED), a driving element (DT) for supplying current to the light-emitting element (OLED), and an internal compensation circuit for sampling a threshold voltage (Vth) of the driving element (DT) using a plurality of switching elements (M01 to M06) and compensating a gate voltage of the driving element (DT) by the threshold voltage (Vth) of the driving element (DT). Each of the driving element (DT) and the switching elements (M01 to M06) can be implemented as a p-channel TFT.

The operation of the internal compensation circuit is divided into an initialization period in which the fifth and sixth switch elements (M05, M06) are turned on in response to the gate-on voltage (VGL) of the (N-1)th scan pulse [SCAN(N-1)] to initialize the pixel circuit, a sampling period in which the first and second switch elements (M01, M02) are turned on in response to the gate-on voltage (VGL) of the Nth scan pulse [SCAN(N)] to sample the threshold voltage of the driving element (DT) and store it in the capacitor (Cst), a data writing period in which the first to sixth switch elements (M01 to M06) maintain an off state, and a light emitting period in which the third and fourth switch elements (M01, M02) are turned on to emit light. In order to precisely express the luminance of low grayscale by the duty ratio of the EM signal [EM(N)], the EM signal [EM(N)] can swing between the gate-on voltage (VGL) and the gate-off voltage (VGH) at a predetermined duty ratio so that the third and fourth switch elements (M01, M02) can be repeatedly turned on and off.

The light-emitting element (OLED) can be implemented as an organic light-emitting diode or an inorganic light-emitting diode. An example in which the light-emitting element (OLED) is implemented as an organic light-emitting diode will be described below.

The light emitting element (OLED) may include an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light emitting element (OLED) is connected to a fourth node (n4) between the fourth and sixth switching elements (M04, M06). The fourth node (n4) is connected to the anode of the light emitting element (OLED), a second electrode of the fourth switching element (M04), and a second electrode of the sixth switching element (M06). The cathode of the light emitting element (OLED) is connected to a VSS electrode (106) to which a low potential power supply voltage (VSS) is applied. The light emitting element (OLED) emits light with a current (Ids) flowing in accordance with a gate-source voltage (Vgs) of a driving element (DT). The current path of the light-emitting element (OLED) is switched by the third and fourth switching elements (M03, M04).

The storage capacitor (Cst) is connected between the VDD line (104) and the first node (n1). The data voltage (Vdata) compensated for by the threshold voltage (Vth) of the driving element (DT) is charged to the storage capacitor (Cst). Since the data voltage (Vdata) of each sub-pixel is compensated for by the threshold voltage (Vth) of the driving element (DT), the characteristic deviation of the driving element (DT) in the sub-pixels is compensated for.

The first switch element (M01) is turned on in response to the gate-on voltage (VGL) of the Nth scan pulse [SCAN(N)] to connect the second node (n2) and the third node (n3). The second node (n2) is connected to the gate of the driving element (DT), the first electrode of the storage capacitor (Cst), and the first electrode of the first switch element (M01). The third node (n3) is connected to the second electrode of the driving element (DT), the second electrode of the first switch element (M01), and the first electrode of the fourth switch element (M04). The gate of the first switch element (M01) is connected to the first gate line (31) and is supplied with the Nth scan pulse [SCAN(N)]. The first electrode of the first switch element (M01) is connected to the second node (n2), and the second electrode of the first switch element (M01) is connected to the third node (n3).

The second switch element (M02) is turned on in response to the gate-on voltage (VGL) of the Nth scan pulse [SCAN(N)] to supply the data voltage (Vdata) to the first node (n1). The gate of the second switch element (M02) is connected to the first gate line (31) and is supplied with the Nth scan pulse [SCAN(N)]. The first electrode of the second switch element (M02) is connected to the first node (n1). The second electrode of the second switch element (M02) is connected to the data line (102) to which the data voltage (Vdata) is applied. The first node (n1) is connected to the first electrode of the second switch element (M02), the second electrode of the third switch element (M02), and the first electrode of the driving element (DT).

The third switch element (M03) is turned on in response to the gate-on voltage (VGL) of the EM signal [EM(N)] to connect the VDD line (104) to the first node (n1). The gate of the third switch element (M03) is connected to the third gate line (33) and is supplied with the EM signal [EM(N)]. The first electrode of the third switch element (M03) is connected to the VDD line (104). The second electrode of the third switch element (M03) is connected to the first node (n1).

The fourth switching element (M04) is turned on in response to the gate-on voltage (VGL) of the EM signal [EM(N)] to connect the third node (n3) to the anode of the light-emitting element (OLED). The gate of the fourth switching element (M04) is connected to the third gate line (33) and is supplied with the EM signal [EM(N)]. The first electrode of the fourth switching element (M04) is connected to the third node (n3), and the second electrode is connected to the fourth node (n4).

The EM signal [EM(N)] controls the on/off of the third and fourth switch elements (M03, M04) to switch the current path of the light-emitting element (OLED), thereby controlling the on/off time of the light-emitting element (OLED).

The fifth switch element (M05) is turned on in response to the gate-on voltage (VGL) of the N-1th scan pulse [SCAN(N-1)] to connect the second node (n2) to the Vini line (105). The gate of the fifth switch element (M05) is connected to the seconda gate line (32a) and is supplied with the N-1th scan pulse [SCAN(N-1)]. The first electrode of the fifth switch element (M05) is connected to the second node (n2), and the second electrode is connected to the Vini line (105).

The sixth switch element (M06) is turned on in response to the gate-on voltage (VGL) of the N-1th scan pulse [SCAN(N-1)] to connect the Vini line (105) to the fourth node (n4). The gate of the sixth switch element (M06) is connected to the 2b gate line (32b) and is supplied with the N-1th scan pulse [SCAN(N-1)]. The first electrode of the sixth switch element (M06) is connected to the Vini line (105), and the second electrode is connected to the fourth node (n4).

The driving element (DT) controls the current (Ids) flowing through the light-emitting element (OLED) according to the gate-source voltage (Vgs) to drive the light-emitting element (OLED). The driving element (DT) includes a gate connected to a second node (n2), a first electrode connected to a first node (n1), and a second electrode connected to a third node (n3).

During the initialization period (Tini), the N-1th scan pulse [SCAN(N-1)] is generated with the gate-on voltage (VGL). The Nth scan pulse [SCAN(N)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the initialization period (Tini). Therefore, the fifth and sixth switch elements (M05, M06) are turned on during the initialization period (Tini), and the second and fourth nodes (n2, n4) are initialized to Vini. A hold period (Th) can be set between the initialization period (Tini) and the sampling period (Tsam). In the hold period (Th), the gate pulses [SCAN(N-1), SCAN(N), EM(N)] maintain their previous states.

During the sampling period (Tsam), the Nth scan pulse [SCAN(N)] is generated with the gate-on voltage (VGL). The pulse of the Nth scan pulse [SCAN(N)] is synchronized to the data voltage (Vdata) of the Nth pixel line. The N-1th scan pulse [SCAN(N-1)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the sampling period (Tsam). Therefore, the first and second switch elements (M01, M01) are turned on during the sampling period (Tsam).

During the sampling period (Tsam), the gate voltage (DTG) of the driving element (DT) is increased by the current flowing through the first and second switching elements (M01, M02). When the driving element (DT) is turned off, the gate node voltage (DTG) is Vdata - |Vth| because the driving element (DT) is turned off. At this time, the voltage of the first node (n) is also Vdata - |Vth|. During the sampling period (Tsam), the gate-source voltage (Vgs) of the driving element (DT) is |Vgs| = Vdata -(Vdata-|Vth|) = |Vth|.

During the data writing period (Twr), the Nth scan pulse [SCAN(N)] is inverted to the gate-off voltage (VGH). The N-1th scan pulse [SCAN(N-1)] and the EM signal [EM(N)] maintain the gate-off voltage (VGH) during the data writing period (Twr). Therefore, all the switch elements (M01 to M06) remain in the off state during the data writing period (Twr).

During the emission period (Tem), the EM signal [EM(N)] can be generated with the gate-off voltage (VGH). During the emission period (Tem), the EM signal [EM(N)] can be turned on/off with a predetermined duty ratio to swing between the gate-on voltage (VGL) and the gate-off voltage (VGH) in order to improve low-grayscale expressiveness. Accordingly, the EM signal [EM(N)] can be generated with the gate-on voltage (VGL) during at least a portion of the emission period (Tem).

When the EM signal [EM(N)] is the gate-on voltage (VGL), current flows between the ELVDD and the light-emitting element (OLED) so that the light-emitting element (OLED) can emit light. During the light-emitting period (Tem), the N-1th and Nth scan pulses [SCAN(N-1), SCAN(N)] maintain the gate-off voltage (VGH). During the light-emitting period (Tem), the third and fourth switch elements (M03, M04) repeat on/off according to the voltage of the EM signal (EM). When the EM signal [EM(N)] is the gate-on voltage (VGL), the third and fourth switch elements (M03, M04) are turned on so that current flows to the light-emitting element (OLED). At this time, the Vgs of the driving element (DT) is |Vgs| = ELVDD - (Vdata-|Vth|), and the current flowing to the light-emitting element (OLED) is K(ELVDD-Vdata)2. K is a proportional constant determined by the charge mobility of the driving element (DT), parasitic capacitance, and channel capacity.

The gates of the fifth and sixth switch elements (M05, M06) may be connected to different gate lines (32a, 32b). The control signal of the sixth switch element (M06) may be different in the activation region and the deactivation region as shown in FIG. 7a and FIG. 18. In the activation region, the N-1th scan pulse [SCAN(N-1)] may be applied to the gate of the sixth switch element (M06) as shown in FIG. 7a. In the deactivation region, the Nth scan pulse [SCAN(N)] may be applied to the gate of the sixth switch element (M06) as shown in FIG. 18.

In the pixel of the active region, the N-1th scan pulse [SCAN(N-1)] is applied to the gates of the fifth and sixth switch elements (M05, M06). On the other hand, in the case of the inactive region, as illustrated in FIG. 18, after the N-1th scan pulse [SCAN(N-1)] is applied to the gate of the fifth switch element (M05), the Nth scan pulse [SCAN(N)] is applied to the sixth switch element (M06).

In the inactive region, the sixth switch element (M06) lowers the anode voltage of the light-emitting element (OLED) to the initialization voltage (Vini) in response to the Nth scan pulse [SCAN(N)] to suppress the emission of the light-emitting element (OLED). As a result, the pixels in the inactive region maintain the luminance of the black gray scale because the pixels do not emit light. The present invention can control the luminance of the inactive region to the luminance of the black gray scale only by turning on the sixth switch element (M06) during the sampling period (Tsam) and applying the initialization voltage (Vini) to the anode of the light-emitting element (OLED). At this time, in order to block the influence of other nodes connected to the anode of the light-emitting element (OLED), it is preferable that the third and fourth switch elements (M03, M04) are turned off as illustrated in FIG. 18.

Figures 48 to 50 are drawings showing a method of operating a screen when folding and unfolding a foldable display.

Referring to FIG. 48, when the flexible panel (600) is folded, the drive IC (500) drives a screen with a small resolution (S131 and S132). The screen with a small resolution may be an active area viewed by the user among the first and second areas (A, B). The screen with a small resolution may be driven at a reference frame frequency or may be driven at a frequency different from the reference frame frequency. Here, a frequency different from the reference frame frequency means a frame frequency higher or lower than the reference frame frequency.

In the unfolded state where the screen of the flexible panel (600) is spread out, the drive IC (500) drives a screen with a large resolution (S131 and S133). The screen with a large resolution may be an active area of the maximum screen that combines the first area (A), the second area (B), and the third area (C). The screen with a large resolution may be driven at a reference frame frequency or may be driven at a frequency different from the reference frame frequency.

Referring to Fig. 49, when the flexible panel (600) is folded, the drive IC (500) drives a screen with a small resolution (S141 to S144). In the folding state, the frame frequency of the image signal input to the drive IC (500) may change. In this case, the drive IC (500) detects the frame frequency of the input image signal and drives the screen with a small resolution at the changed frequency (S142 and S143). The changed frequency means a frame frequency different from the reference frame frequency. If the input frequency of the drive IC (500) does not change in the folding state, the drive IC (500) drives the screen with a small resolution at the reference frame frequency (S142 and S144).

When the flexible panel (600) is in an unfolding state, the drive IC (500) drives a screen with a large resolution (S145 to S147). In the unfolding state, the frame frequency of the image signal input to the drive IC (500) may change. In this case, the drive IC (500) detects the frame frequency of the input image signal and drives the screen with a large resolution with the changed frame frequency (S145 and S146). When the input frequency of the drive IC (500) does not change in the unfolding state, the drive IC (500) drives the screen with a large resolution with the reference frame frequency (S145 and S147).

The foldable display of the present invention can drive one screen in VR (Virtual Reality) mode when folded. In VR mode, it is necessary to move the image by reflecting the user's movements in real time at a high frame frequency when the user moves so that the user does not feel motion sickness and fatigue.

Referring to FIG. 50, when the flexible panel (600) is folded, the drive IC (500) drives a small resolution screen (S151 to S154).

In the folding state, the user can select the VR mode while the foldable display is folded. At this time, the host system (400) transmits the image signal of the VR content selected by the user to the drive IC (500). The host system (2000) can generate an image signal of a high frame frequency by rendering pixel data in response to the output signal of the tilt sensor to reflect the user's movement and transmit the image signal to the drive IC (500). The drive IC (500) receives an input image signal of a higher frequency than the reference frame frequency in the VR mode and drives a screen of a small resolution at the high frequency. The high frequency can be a frame frequency of 520 Hz (S152 and S153). In the folding state, if it is not the VR mode, the drive IC (500) drives the screen of a small resolution at the reference frame frequency (S152 and S153).

When the flexible panel (600) is in an unfolded state, the drive IC (500) drives a large resolution screen at the reference frame frequency (S151 to S155).

The gate driving circuit according to various embodiments of the present invention can be described as follows.

Example 1: The gate driving circuit includes a shift register (150) that sequentially outputs gate pulses using a plurality of signal transmission units (ST1 to STn) as illustrated in FIGS. 14a and 14b; and a gate control unit (140) that is connected to a start signal input node (31) and an output node (33) of each of the signal transmission units (ST1 to STn), selectively supplies one of a start pulse (VST), a carry signal (CAR), and a gate-off voltage (VGH) to the start signal input node (31) of each of the signal transmission units, and receives the carry signal from the output node (33) of the signal transmission units (ST1 to STn).

Each of the above signal transmission sections (ST1 to STn) includes a first control node that is charged according to the gate-on voltage of one of the start pulse and the carry signal, and a pull-up transistor that outputs the gate pulse in a state where the first control node is charged.

Example 2: The gate control unit (140) may include a start line selection unit (141) that outputs an input start pulse through one or more output nodes selected according to the logic value of a selection signal, as illustrated in FIG. 15; a switch control signal generation unit (142) that generates a first control signal that controls the shift timing of the shift register, a second control signal that controls the shift end timing of the shift register, and a third control signal that controls the start timing of the shift register; and a plurality of start signal selection units (1401 to 1402) that are commonly connected to the start line selection unit and the switch control signal generation unit and are connected to a corresponding signal transmission unit.

Each of the plurality of start signal selection units (1401 to 1402) can apply one selected from the start pulse (VST), the carry signal (CAR), and the gate-off voltage (VGH) to the start signal input node of the corresponding signal transmission unit in response to the first to third control signals.

Example 3: The start signal generating unit (141) may include a demultiplexer that outputs the start pulse through one or more output nodes indicated by the logic value of the selection signal, as illustrated in FIGS. 16 and 17.

Example 4: The gate control unit (140) may include, as illustrated in FIG. 32, a first control unit (321) that receives movement information of a display panel and resolution information of an input image, and outputs start data indicating a start line of an active area on which an input image or information is displayed on the display panel, end data indicating an end line of the active area, the start pulse, and a selection signal; a second control unit (322) that generates first and third control signals (SW1, SW3) in response to the start data; a third control unit (323) that generates a second control signal (SW2) in response to the end data; a start line selection unit (324) that outputs a start pulse input from the first control unit through one or more output nodes selected according to the logic value of the selection signal; and a plurality of start signal selection units (1401 to 1402) that are commonly connected to the start line selection unit and the second and third control units and are connected to a corresponding signal transmission unit.

The first control signal can control the shift timing of the shift register. The second control signal can control the shift end timing of the shift register. The third control signal can control the start timing of the shift register. Each of the plurality of start signal selection units (1401 to 1402) can apply one selected from the start pulse (VST), the carry signal (CAR), and the gate-off voltage (VGH) to the start signal input node of the corresponding signal transmission unit in response to the first to third control signals.

Example 5: Each of the above start signal selection units (1401 to 1402) may include a first switching element that is turned on/off according to the voltage level of the first control signal, a second switching element that is turned on/off according to the voltage level of the second control signal, and a third switching element that is turned on/off according to the voltage level of the third control signal, as illustrated in FIGS. 16, 17, and 32.

A first switching element of a first start signal selection unit may be turned on according to a gate-on voltage of the first control signal to apply the start pulse to a start signal input node of the first signal transmission unit. A first switching element of each of the second to nth (n is a natural number greater than or equal to 3) start signal selection units may be turned on according to a gate-on voltage of the first control signal to apply the carry signal input from an output node of a previous signal transmission unit to a start signal input node of a corresponding signal transmission unit. In each of the first to nth start signal selection units, the second switching element may be turned on according to a gate-on voltage of the second control signal to apply the gate-off voltage to the start signal input node of the corresponding signal transmission unit. In each of the first to nth start signal selection units, the third switch element can be turned on according to the gate-on voltage of the third control signal to apply the start pulse from the start signal generating unit to the start signal input node of the corresponding signal transmitting unit.

Example 6: As shown in FIG. 16, FIG. 17, and FIG. 32, at least one of the second and third control signals may be shifted when displacement of the display panel occurs.

Example 7: The second control unit (322) can shift the first and third control signals (SW1, SW3) using a bidirectional shift register as shown in FIGS. 34a, 34b, and 37, and the third control unit (323) can shift the second control signal (SW2) using a bidirectional shift register.

Example 8: As shown in FIG. 34, the second control unit (322) can shift the first and third control signals (SW1, SW3) every frame period while the display panel is moved, and the third control unit (323) can shift the second control signal (SW2) in a direction opposite to the shift direction of the first and third control signals (SW1, SW3) while the display panel is moved.

Example 9: The second control unit (322) can shift the first and third control signals (SW1, SW3) up and down as illustrated in FIG. 37, and the third control unit (323) can shift the second control signal (SW2) up and down in the same direction as the shift direction of the first and third control signals (SW1, SW3).

Example 10: The first, second and third control signals can be shifted in the opposite direction to the movement direction of the display panel as shown in FIGS. 36 and 37.

Example 11: As illustrated in FIG. 38, the gate control unit can simultaneously apply the start pulse to one or more of the signal transmission units in the BDI section to simultaneously apply gate pulses synchronized with the black gray voltage to adjacent gate lines.

A display device according to various embodiments of the present invention can be described as follows.

Example 1: A display device includes a display panel (100, 600) capable of displaying two or more different images, including a screen in which data lines and gate lines intersect and pixels into which pixel data of an input image is written are arranged; a data driving unit (10, 506) that supplies a data voltage to the data lines; and a gate driving unit (20, 520) that supplies a gate pulse to the gate lines using the gate control unit and the shift register.

Example 2: The screen may include a first region in which a first image is displayed, as shown in FIGS. 21 to 27; and a second region in which a second image is displayed. The frame frequencies of the first and second images may be controlled differently by the gate control unit.

Embodiment 3: The display device may display a black gradation or a previous image in the second area during one frame period in which only pixel data of the first image is written to pixels of the first area as illustrated in FIGS. 22 to 24. The start pulse may be input to a start signal input node of a signal transmission unit connected to a first pixel line of the first area, and the carry signal may be sequentially input to the start signal input nodes of the signal transmission units connected to the remaining pixel lines of the first area. The gate-off voltage may be simultaneously input to the start signal input nodes of the signal transmission units connected to the pixel lines of the second area.

Example 4: During a one-frame period in which pixel data of the first image is written to pixels of the first region and pixel data of the second image is written to pixels of the second region as illustrated in FIGS. 25 to 27, the start pulse may be input to a start signal input node of a signal transmission unit connected to a first pixel line of the first region, and the carry signal may be sequentially input to the start signal input nodes of signal transmission units connected to the remaining pixel lines of the first region and the pixel lines of the second region.

Example 5: As shown in FIGS. 34a, 34b, and 37, the gate driving unit can shift the positions of gate pulses applied to gate lines of the start line and the end line of an area where an image is displayed on the screen for each frame period while the display panel is moved.

Example 6: As shown in FIGS. 34a and 34b, the gate driving unit can shift the gate pulse applied to the gate line of the start line of the area where the image is displayed for each frame period while the display panel is moved, and shift the positions of the gate pulses applied to the gate line of the end line in a direction opposite to the shift direction of the gate pulse applied to the gate line of the start line.

Example 7: The gate driving unit can shift the gate pulse applied to the gate line of the start line up and down as illustrated in FIGS. 36 and 37, and shift the gate pulse applied to the gate line of the end line in the same direction as the gate pulse applied to the gate line of the start line.

Example 8: As shown in FIG. 36 and FIG. 37, the gate pulse applied to the start line and the gate pulse applied to the end line can be shifted in the opposite direction to the movement direction of the display panel.

Example 9: The gate control unit can simultaneously apply the start pulse to one or more of the signal transmission units as illustrated in FIG. 38 to simultaneously apply a gate pulse synchronized with the black gray voltage to adjacent gate lines.

Through the above explanation, those skilled in the art will be able to see that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the patent claims.

10: Data driver 20: Gate driver
140: Gate control unit 141, 324: Start line selection unit
142: Switch control signal generation unit 1401~140n: Start signal selection unit
150: Shift register SW1, SW2, SW3: Control signal
M1, M2, M3: Switch element 321: First control unit
322: Second control unit 323: Third control unit
ST1~STn: Signal transmission unit SR1: Scan driving unit
SR2: EM drive unit 31: Start signal input node
32: Clock input node 33: Output node
100, 600 : Flexible Panel

Claims (20)

A shift register that sequentially outputs gate pulses using multiple signal transmission units; and
A gate control unit is connected to the start signal input node and output node of each of the signal transmission units, and selectively supplies one of a start pulse, a carry signal, and a gate-off voltage to the start signal input node of each of the signal transmission units and receives the carry signal from the output node of the signal transmission units.
A gate driving circuit, wherein each of the signal transmission sections includes a first control node that is charged according to the gate-on voltage of one of the start pulse and the carry signal, and a pull-up transistor that outputs the gate pulse in a state where the first control node is charged. In paragraph 1,
The above gate control unit,
A start line selection unit that outputs an input start pulse through one or more output nodes selected according to the logic value of a selection signal;
A switch control signal generating unit that generates a first control signal that controls the shift timing of the shift register, a second control signal that controls the shift end timing of the shift register, and a third control signal that controls the start timing of the shift register; and
It includes a plurality of start signal selection units that are commonly connected to the above start line selection unit and the switch control signal generation unit and are connected to a corresponding signal transmission unit.
A gate driving circuit in which each of the plurality of start signal selection units applies one selected from the start pulse, the carry signal, and the gate off voltage to the start signal input node of the corresponding signal transmission unit in response to the first to third control signals. In the second paragraph,
The above start line selection section is,
A gate drive circuit including a demultiplexer that outputs the start pulse through one or more output nodes indicated by the logic value of the above selection signal. In paragraph 1,
The above gate control unit,
A first control unit that receives movement information of a display panel and resolution information of an input image, and outputs start data indicating a start line of an active area on which an input image or information is displayed on the display panel, end data indicating an end line of the active area, the start pulse, and a selection signal;
A second control unit generating first and third control signals in response to the above start data;
A third control unit generating a second control signal in response to the above end data;
A start line selection unit that outputs a start pulse input from the first control unit through one or more output nodes selected according to the logic value of the selection signal; and
It comprises a plurality of start signal selectors that are commonly connected to the above start line selector and the second and third control units and are connected to a corresponding signal transmission unit,
The above first control signal controls the shift timing of the shift register,
The second control signal controls the shift end timing of the shift register,
The third control signal controls the start timing of the shift register,
A gate driving circuit in which each of the plurality of start signal selection units applies one selected from the start pulse, the carry signal, and the gate off voltage to the start signal input node of the corresponding signal transmission unit in response to the first to third control signals. In the second paragraph,
Each of the above start signal selection units includes a first switching element that is turned on/off according to the voltage level of the first control signal, a second switching element that is turned on/off according to the voltage level of the second control signal, and a third switching element that is turned on/off according to the voltage level of the third control signal.
The first switch element of the first start signal selection unit is turned on according to the gate-on voltage of the first control signal to apply the start pulse to the start signal input node of the first signal transmission unit,
The first switching element of each of the second to nth (n is a natural number greater than or equal to 3) start signal selection units is turned on according to the gate-on voltage of the first control signal to apply the carry signal input from the output node of the previous signal transmission unit to the start signal input node of the corresponding signal transmission unit,
In each of the first to nth start signal selection units, the second switch element is turned on according to the gate-on voltage of the second control signal and applies the gate-off voltage to the start signal input node of the corresponding signal transmission unit,
A gate driving circuit in which, in each of the first to nth start signal selection units, the third switch element is turned on according to the gate-on voltage of the third control signal to apply the start pulse from the start line selection unit to the start signal input node of the corresponding signal transmission unit. In paragraph 4,
A gate driving circuit in which at least one of the second and third control signals is shifted when displacement of the display panel occurs. In paragraph 4,
The second control unit shifts the first and third control signals using a bidirectional shift register,
The third control unit is a gate driving circuit that shifts the second control signal using a bidirectional shift register. In paragraph 7,
The second control unit shifts the first and third control signals every frame period while the display panel moves,
The third control unit is a gate driving circuit that shifts the second control signal in a direction opposite to the shift direction of the first and third control signals while the display panel is moved. In paragraph 7,
The above second control unit shifts the first and third control signals up and down,
The third control unit is a gate driving circuit that shifts the second control signal up and down in the same direction as the shift direction of the first and third control signals. In Article 9,
A gate driving circuit in which the first, second and third control signals are shifted in the opposite direction to the movement direction of the display panel. In the second paragraph,
The above gate control unit,
A gate driving circuit that simultaneously applies the above start pulse to one or more of the above signal transmission sections. A display panel capable of displaying two or more different images, including a screen in which data lines and gate lines intersect and pixels into which pixel data of an input image is written are arranged;
A data driving unit that supplies data voltage to the above data lines; and
A gate driver for supplying gate pulses to the above gate lines is included,
The above gate driving unit,
A shift register that sequentially outputs gate pulses using multiple signal transmission units; and
A gate control unit is connected to the start signal input node and output node of each of the signal transmission units, and selectively supplies one of a start pulse, a carry signal, and a gate-off voltage to the start signal input node of each of the signal transmission units and receives the carry signal from the output node of the signal transmission units.
A display device, wherein each of the signal transmission sections includes a first control node that is charged according to the gate-on voltage of one of the start pulse and the carry signal, and a pull-up transistor that outputs the gate pulse in a state where the first control node is charged. In Article 12,
The above screen is,
a first area in which a first image is displayed; and
Contains a second area in which a second image is displayed,
A display device in which the frame frequencies of the first and second images are different from each other. In Article 13,
During a one frame period in which only pixel data of the first image is written to pixels of the first area, the second area displays a black gradation or displays a previous image,
The above start pulse is input to the start signal input node of the signal transmission unit connected to the first pixel line of the first region, and the carry signal is sequentially input to the start signal input nodes of the signal transmission units connected to the remaining pixel lines of the first region.
A display device in which the gate-off voltage is simultaneously input to the start signal input nodes of the signal transmission units connected to the pixel lines of the second region. In Article 13,
A display device in which, during a one-frame period in which pixel data of the first image is written to pixels of the first area and pixel data of the second image is written to pixels of the second area, the start pulse is input to a start signal input node of a signal transmission unit connected to a first pixel line of the first area, and the carry signal is sequentially input to the start signal input nodes of signal transmission units connected to the remaining pixel lines of the first area and the pixel lines of the second area. In Article 12,
The above gate driving unit,
A display device that shifts the positions of gate pulses applied to the gate lines of the start line and the end line of the area where an image is displayed on the screen at each frame period while the above display panel is moved. In Article 16,
The above gate driving unit,
While the above display panel is moving, the gate pulse applied to the gate line of the start line of the area where the image is displayed is shifted for each frame period,
A display device that shifts the positions of gate pulses applied to the gate lines of the end line in a direction opposite to the shift direction of the gate pulses applied to the gate lines of the start line. In Article 16,
The above gate driving unit,
Shifting the gate pulse applied to the gate line of the above start line up and down,
A display device that shifts a gate pulse applied to a gate line of the end line in the same direction as a gate pulse applied to a gate line of the start line. In Article 18,
A display device in which a gate pulse applied to the start line and a gate pulse applied to the end line are shifted in the opposite direction to the movement direction of the display panel. In Article 12,
The above gate control unit,
A display device that simultaneously applies the above start pulse to one or more of the above signal transmission sections.