KR102719649B1 - Power semiconductor device with electric field relaxation structure - Google Patents

Abstract

A power semiconductor device having a field relaxation structure is disclosed. The present invention forms a field relaxation semiconductor layer having a lower concentration than a drift layer in a bottom region of a trench, so that when the power semiconductor device is switched to a reverse mode, a depletion layer of the field relaxation semiconductor layer expands more rapidly than that of the drift layer as a voltage applied to a collector increases, thereby reducing the maximum electric field in the bottom region of the trench and alleviating electric field concentration.

Description

Power semiconductor device having electric field relaxation structure {POWER SEMICONDUCTOR DEVICE WITH ELECTRIC FIELD RELAXATION STRUCTURE}

The present invention relates to a power semiconductor device having an electric field relaxation structure, and more specifically, to a power semiconductor device having an electric field relaxation structure in which a field relaxation semiconductor layer having a lower concentration than a drift layer is formed in a bottom region of a trench, so that when the power semiconductor device is switched to a reverse mode, as a voltage applied to a collector increases, a depletion layer of the field relaxation semiconductor layer expands faster than that of the drift layer, thereby reducing the maximum electric field in the bottom region of a trench and alleviating electric field concentration.

Power semiconductor devices, which are important elements in the power electronics field, such as insulated gate bipolar transistors (IGBTs), power metal oxide semiconductor field-effect transistors (power MOSFETs), and various types of thyristors, are being developed to meet the needs of various industries, such as high insulation voltage, low conduction loss, switching speed, and low switching loss.

An insulated gate bipolar transistor generally has an emitter layer of a first conductivity type, a base layer of a second conductivity type, a drift layer of the first conductivity type, a collector layer of the second conductivity type, and a gate electrode formed opposite the base layer and the drift layer through an insulating film.

When the device is turned on, a channel is formed in the base layer through the voltage applied to the gate electrode, and minority carriers (holes) are injected from the collector layer to the drift layer to cause conductivity modulation in the drift layer, thereby reducing the on-voltage during conduction due to a decrease in the resistance value.

Figure 1 is an exemplary diagram showing a power semiconductor device having a trench structure according to conventional technology.

As shown in Fig. 1, the power semiconductor device (10) comprises a first semiconductor layer (11, drift layer), a field stop layer (11a) having a higher doping concentration than the doping concentration of the first semiconductor layer (11) at the lower portion, a second semiconductor layer (12) formed on the first semiconductor layer (11), a charge accumulation layer (13) formed between the first semiconductor layer (11) and the second semiconductor layer (12) to have a higher impurity concentration than the first semiconductor layer (11), a gate insulating film (14') and a gate electrode (14"), and a plurality of trench portions (14, 14a, 14b) formed by penetrating the second semiconductor layer (12) and extending to the first semiconductor layer (11) and formed in parallel and spaced apart from each other by a certain distance, and an n-type emitter region (15') formed in the second semiconductor layer (12) adjacent to the trench portions (14, 14a, 14b) and an ohmic contact. It can be composed of a mesa region (15) composed of a p-type high-concentration region (15") for formation, and a collector layer (16) formed under the first semiconductor layer (11).

However, power semiconductor devices having a trench structure according to conventional technology enter a reverse blocking mode when the device is turned off, and a phenomenon occurs in which an electric field is concentrated at the bottom of the trench gate due to a high voltage applied to the collector layer.

Figure 2(a) is a graph showing the electric field distribution of a power semiconductor device having the trench structure of Figure 1, and Figure 2(b) is a graph showing the concentration distribution.

As can be seen in FIG. 2(a) and FIG. 2(b), when the OFF state is reached during switching operation and voltage is applied to the collector, depletion occurs in the drift layer, which is a low-concentration n-type semiconductor layer, and the maximum electric field occurs in the bottom area (A) of the trench portion, so that the electric field is concentrated, and the electric field decreases as it goes toward the bottom area (A') of the power semiconductor element.

In addition, if the electric field is continuously concentrated on the bottom of the trench gate, there is a problem that the gate oxide in the area where the electric field is concentrated deteriorates, causing a gate short or increasing gate leakage current, thereby lowering the reliability of the power semiconductor device.

To solve this problem, a technology was applied to alleviate the concentration of electric fields at the bottom of the trench gate by forming a p-type shield region, which is a second-challenge semiconductor region, in the trench bottom region.

FIG. 3 is an exemplary diagram showing another power semiconductor device having a trench structure according to the prior art.

As shown in Fig. 3, the improved power semiconductor device (10a) has a p-type shield region (17), which is a second conductive semiconductor region, added to protect the bottom of the trench portion (14, 14a, 14b) in the configuration of the power semiconductor device (10) of Fig. 1.

Fig. 4(a) is a graph showing the electric field distribution of a power semiconductor device having the trench structure of Fig. 3, and Fig. 4(b) is a graph showing the concentration distribution.

Through this, the electric field concentration in the bottom region (B) of the trench portion is alleviated, and the electric field is reduced toward the bottom region (B') of the power semiconductor element. However, if the p-type shield region (17), which is the second conductive semiconductor region, is not optimized, there is a problem in that the breakdown voltage is lowered and the forward conduction loss deteriorates.

U.S. Patent Publication No. US 7456487 B2 (Title of invention: Semiconductor device)

In order to solve these problems, the present invention provides a power semiconductor device having an electric field relaxation structure in which an n-type field relaxation semiconductor layer having a lower concentration than a drift layer is formed in a bottom region of a trench, so that when the power semiconductor device is switched to a reverse mode, as the voltage applied to the collector increases, a depletion layer of the n-type field relaxation semiconductor layer expands more rapidly than that of the drift layer, thereby reducing the maximum electric field in the bottom region of the trench and alleviating electric field concentration.

In order to achieve the above object, one embodiment of the present invention provides a power semiconductor device having an electric field relaxation structure, comprising: a first semiconductor layer having a field stop layer formed thereunder; a second semiconductor layer formed on the first semiconductor layer; a charge accumulation layer formed between the first semiconductor layer and the second semiconductor layer so as to have a higher impurity concentration than the first semiconductor layer; a plurality of trench portions formed so as to extend through the second semiconductor layer and the charge accumulation layer to the first semiconductor layer and are formed in parallel and spaced apart from each other by a predetermined distance; an active mesa region having an n-type emitter region formed to be in contact with the trench portion and a p-type high-concentration region formed between the n-type emitter region for an ohmic contact; a collector layer formed under the first semiconductor layer; and a field relaxation semiconductor layer formed under the trench portion so as to have a lower impurity concentration than the first semiconductor layer.

In addition, the field-mitigating semiconductor layer according to the above embodiment is characterized in that it is formed to surround the bottom area of each trench portion.

In addition, the thickness (T) of the field-relaxing semiconductor layer according to the above embodiment is characterized by being formed from 10 μm to the field stop layer.

In addition, the field-mitigating semiconductor layer according to the above embodiment is characterized in that it is formed to simultaneously surround one or more trench bottom regions adjacent to any trench portion.

In addition, the power semiconductor device having the field relaxation structure according to the above embodiment is characterized in that it further includes one or more dummy trench portions in which the gate electrode is connected to the emitter electrode.

In addition, the dummy trench portion according to the above embodiment is characterized in that the electric field alleviating semiconductor layer is not installed in the bottom area.

In addition, the dummy trench section according to the above embodiment is characterized in that one or more dummy trench sections are installed adjacent to each other in succession.

The present invention has an advantage in that, by forming a field-relaxing semiconductor layer having a lower concentration than a drift layer in the bottom region of a trench, when a power semiconductor device is switched to a reverse mode, the depletion layer of the field-relaxing semiconductor layer expands more rapidly than that of the drift layer as the voltage applied to the collector increases, thereby reducing the maximum electric field in the bottom region of the trench.

In addition, the present invention has the advantage of improving the deterioration of power semiconductor devices and enhancing reliability by alleviating electric field concentration in the trench bottom area.

In addition, the present invention has an advantage of improving the breakdown voltage without deteriorating the forward conduction loss of the power semiconductor device.

Figure 1 is an exemplary diagram showing a power semiconductor device having a trench structure according to conventional technology.
Figure 2 is a graph showing the electric field distribution and concentration distribution of a power semiconductor device having the trench structure of Figure 1.
Figure 3 is an exemplary diagram showing another power semiconductor device having a trench structure according to the prior art.
Figure 4 is a graph showing the electric field distribution and concentration distribution of a power semiconductor device having the trench structure of Figure 3.
FIG. 5 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to one embodiment of the present invention.
Fig. 6 is a graph showing the electric field distribution and concentration distribution of a power semiconductor device having a field relaxation structure according to the embodiment of Fig. 5.
FIG. 7 is a graph showing the results of simulating changes in electric field and breakdown voltage in a trench bottom region of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 5.
FIG. 8 is an exemplary diagram showing a modified embodiment of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 5.
FIG. 9 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to another embodiment of the present invention.
FIG. 10 is an exemplary diagram showing a modified embodiment of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 9.
FIG. 11 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to another embodiment of the present invention.
FIG. 12 is an exemplary diagram showing a modified embodiment of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 11.

Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the present invention and the accompanying drawings, on the premise that like reference numerals in the drawings indicate like components.

Before explaining the specific details for implementing the present invention, it should be noted that components that are not directly related to the technical gist of the present invention have been omitted to the extent that they do not distract from the technical gist of the present invention.

In addition, terms or words used in this specification and claims should be interpreted as meanings and concepts that conform to the technical idea of the invention, based on the principle that the inventor can define the concept of an appropriate term to best describe his or her invention.

The expression in this specification that a part "includes" a certain component does not exclude other components, but rather means that it may include other components.

Additionally, terms such as "‥part", "‥device", and "‥module" refer to a unit that processes at least one function or operation, and this can be classified as hardware, software, or a combination of the two.

Additionally, the term "at least one" is defined as a term including both singular and plural, and it will be apparent that even if the term "at least one" is not present, each component can exist in the singular or plural, and can mean the singular or plural.

Hereinafter, a preferred embodiment of a power semiconductor device having a field mitigation structure according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

(First embodiment)

FIG. 5 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to an embodiment of the present invention, FIG. 6 is a graph showing an electric field distribution and a concentration distribution of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 5, and FIG. 7 is a graph showing the results of simulating changes in an electric field and breakdown voltage in a trench bottom region of a power semiconductor device having a field relaxation structure according to the embodiment of FIG. 5.

As shown in FIGS. 5 to 7, a power semiconductor device (100) having a field relaxation structure according to one embodiment of the present invention may be composed of a silicon substrate, and gate wiring and emitter electrodes may be formed on a surface.

A power semiconductor device (100) having a field-relief structure may be a substrate on which a first semiconductor layer (110) is formed by lightly doping an n-type impurity with a first conductivity type, and the doping concentration of the n-type impurity may be, for example, about 10 ¹³ to 10 ¹⁶ /cm3.

Considering the doping concentration of n-type impurities, the first semiconductor layer (110) can be said to be an n ^- type drift layer.

In addition, the first semiconductor layer (110) may have a field stop layer (111) and a p-type collector layer (160) sequentially formed under the n-type drift layer, and a collector electrode may be formed under the collector layer (160).

The field stop layer (111) may be a layer doped with an n-type impurity, and the concentration of the doped n-type impurity may be higher than the n-type impurity concentration of the first semiconductor layer (110), and the concentration of the impurity may be about 10 ¹⁴ to 10 ¹⁸ /cm3.

That is, the first semiconductor layer (110) is a drift layer and is a low-concentration n-type semiconductor layer, and in the off state, most of the voltage between the collector and the emitter is applied to the first semiconductor layer (110), so the field stop layer (111) prevents expansion of the depletion layer when a reverse voltage is applied.

Through this, the field stop layer (111) can obtain a high breakdown voltage even with a relatively short drift region, thereby improving the forward operation characteristics.

Additionally, a power semiconductor device (100) having a field-relief structure may have a second semiconductor layer (120) formed on top of a first semiconductor layer (110).

The second semiconductor layer (120) may be a region doped with p-type impurities, and the doping concentration of the p-type impurities may be about 10 ¹⁵ to ^{10 19} /cm3, and considering the doping concentration of the p-type impurities, it may be p ⁰ or p ⁺ .

In addition, a power semiconductor device (100) having a field-relief structure may have a charge accumulation layer (Carrier Storage, 130) formed between the first semiconductor layer (110) and the second semiconductor layer (120) and doped with an n-type impurity having a higher impurity concentration than that of the first semiconductor layer (110) to accumulate charges.

The charge accumulation layer (130) is installed between the first semiconductor layer (110) and the second semiconductor layer (120) so that when the device is in the ON state, holes are prevented from flowing through the second semiconductor layer (120) to the emitter electrode, thereby increasing the carrier concentration of the first semiconductor layer (110) in the region directly below the charge accumulation layer (130), thereby lowering the ON voltage.

In addition, a power semiconductor device (100) having a field-relief structure may extend through the second semiconductor layer (120) and the charge accumulation layer (130) to the first semiconductor layer (110) to form a plurality of trench portions (140, 140a, 140b).

In this embodiment, for convenience of explanation, three trench sections (140, 140a, 140b) are described as an example, but it is not limited thereto and can be implemented by changing them as necessary.

Each trench section (140, 140a, 140b) can be formed in a stripe shape in parallel with a certain distance from each other.

Each of the individual trench sections (140, 140a, 140b) can have a gate insulating film (141) formed on the inner wall.

Additionally, individual trench portions (140, 140a, 140b) may be filled with a gate insulating film (141) to form a gate electrode (142) that is insulated from the second semiconductor layer (120) and the active mesa region (150, 150a, 150b).

Additionally, an insulating film (not shown) may be formed so that the gate electrode (142) can be electrically separated from the emitter electrode.

In addition, a power semiconductor device (100) having a field-relief structure may have an active mesa region (150, 150a, 150b) formed with a p-type high-concentration region (152) formed with a higher concentration than the p-type impurity concentration of the second semiconductor layer (120) to form an ohmic contact between the n-type emitter region (151) and the n-type emitter region (151) that contacts both sides of the individual trench portion (140, 140a, 140b).

An emitter electrode can be installed on top of the active mesa region (150, 150a, 150b).

Additionally, a power semiconductor device (100) having a field-relief structure may have a collector layer (160) formed under a first semiconductor layer (110).

The collector layer (160) is doped with a p-type impurity, and the concentration of the doped p-type impurity can be about 10 ¹⁷ to 10 ²¹ /cm3, so that it can become a p ⁺ layer and a collector electrode can be formed.

In addition, a power semiconductor device (100) having a field relaxation structure may have a field relaxation semiconductor layer (170) formed at the bottom of a trench portion (140, 140a, 140b) so as to have an n-type impurity concentration that is relatively lower than the doping concentration of the first semiconductor layer (110).

When the doping concentration of the 'N2', which is the field relaxation semiconductor layer (170), is formed lower than the doping concentration of the 'N1', which is the first semiconductor layer (110), the depletion region of the field relaxation semiconductor layer (170) expands faster than the first semiconductor layer (110), thereby lowering the maximum electric field value at the bottom of the trench portion (140, 140a, 140b).

Accordingly, as the maximum electric field (EF) becomes lower than the conventional maximum electric field (EF1), the electric field value borne by the bottom area of the trench portion (140, 140a, 140b) becomes smaller, so that the operational reliability of the device can be improved.

The field-mitigating semiconductor layer (170) can be formed to surround the bottom area of each trench portion (140, 140a, 140b), that is, the periphery of the end portion of the trench portion (140, 140a, 140b).

In addition, as shown in FIG. 8, a power semiconductor device (100') may be implemented with a field alleviation structure in which a field alleviation semiconductor layer (170') is installed only on the lower surface of each trench portion (140, 140a, 140b).

Referring again to FIG. 5, the field relaxation semiconductor layer (170) can be formed to have a certain thickness (T) from the bottom surface (or lower surface) of the trench portion (140, 140a, 140b) toward the collector layer (160).

The thickness (T) at which the field-mitigating semiconductor layer (170) is formed can be 10 μm to a position (or distance) where it comes into contact with the field stop layer (111).

When the thickness (T1) of the field-relaxing semiconductor layer (170) is 10 ㎛ or less, there is an effect of reducing the field intensity to some extent due to a decrease in the maximum field value, but the breakdown voltage performance is not improved.

Therefore, by forming an n-type semiconductor layer (N2) having a lower concentration than the drift layer (N1) in the bottom region of the trench, the depletion layer of the n-type semiconductor layer expands faster than the drift layer as the voltage applied to the collector increases when the power semiconductor device is switched to the reverse mode, thereby reducing the maximum electric field in the bottom region of the trench.

(Second embodiment)

FIG. 9 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to another embodiment of the present invention.

As shown in FIG. 9, a power semiconductor device (100a) having a field relaxation structure according to the second embodiment may be configured to further include a dummy trench portion (180) formed parallel to and adjacent to a plurality of trench portions (140, 140a) in comparison with the configuration of a power semiconductor device (100, see FIG. 5) having a field relaxation structure according to the first embodiment.

In addition, the power semiconductor device (100a) having the field relaxation structure according to the second embodiment can be formed so that the field relaxation semiconductor layer (170a) surrounds the bottom area of one or more trench portions (140a) formed parallel to and adjacent to the trench portion (140), i.e., the periphery of the ends of a plurality of trench portions (140, 140a) at the same time.

In addition, as shown in Fig. 10, a power semiconductor device (100a') having a field alleviation structure in which a field alleviation semiconductor layer (170a') is installed only on the lower surface of a trench portion (140, 140a) may be implemented.

Referring again to FIG. 9, the dummy trench portion (180) allows the gate electrode (142) to be connected to the emitter electrode, and a field-relaxing semiconductor layer (170a) is not formed in the bottom region of the dummy trench portion (180).

When the device operates and conductivity modulation occurs, the dummy trench portion (180) gathers holes that have risen from the collector layer (160), and as many holes gather, electrons also gather, so that the carrier concentration increases, thereby lowering the forward voltage drop and thus reducing the conduction loss.

(Example 3)

FIG. 11 is an exemplary diagram showing a power semiconductor device having a field relaxation structure according to another embodiment of the present invention.

As shown in FIG. 11, a power semiconductor device (100b) having a field relaxation structure according to the third embodiment may have a plurality of trench portions (140, 140a, 140b) formed continuously and adjacent to a plurality of dummy trench portions (180, 180a) in parallel with each other, as compared to the configuration of a power semiconductor device (100, see FIG. 5) having a field relaxation structure according to the first embodiment.

In addition, a power semiconductor device (100b) having a field relaxation structure according to the third embodiment can be formed so as to simultaneously surround the bottom area of a plurality of trench portions (140, 140a, 140b) in which field relaxation semiconductor layers (170b) are continuously formed, i.e., the periphery of the ends of the trench portions (140, 140a, 140b).

In addition, as shown in Fig. 12, a power semiconductor device (100b') having a field alleviation structure in which a field alleviation semiconductor layer (170b') is installed only on the lower surface of a trench portion (140, 140a) may be implemented.

Referring again to FIG. 11, the dummy trench portion (180, 180a) allows the gate electrode (142) to be connected to the emitter electrode, and a field-relaxing semiconductor layer (170b) is not formed in the bottom region of the dummy trench portion (180, 180a).

Through this, when the device is in operation, the dummy trench portion (180, 180a) does not form a channel, so that holes rising from the collector layer (160) gather at the bottom of the dummy trench, and as many holes gather, electrons also gather, so that the forward voltage drop is lowered as the carrier concentration increases, thereby lowering the conduction loss.

In addition, by forming an n-type semiconductor layer having a lower concentration than the drift layer in the bottom region of the trench, when the power semiconductor device is switched to the reverse mode, the depletion layer of the n-type semiconductor layer expands more quickly than the drift layer as the voltage applied to the collector increases, thereby reducing the maximum electric field in the bottom region of the trench.

In addition, the electric field concentration in the trench bottom region can be alleviated to improve the deterioration of power semiconductor devices and enhance the reliability, and the breakdown voltage can be improved without deterioration of the forward conduction loss of the power semiconductor devices.

As described above, although the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that the present invention can be variously modified and changed within the scope and spirit of the present invention as set forth in the claims below.

In addition, the drawing numbers described in the patent claims of the present invention are only described for the sake of clarity and convenience of explanation and are not limited thereto, and in the process of explaining the embodiments, the thickness of lines and the sizes of components depicted in the drawings may be exaggerated for the sake of clarity and convenience of explanation.

In addition, the terms described above are terms defined in consideration of their functions in the present invention, and may vary depending on the intention or custom of the user or operator. Therefore, the interpretation of these terms should be made based on the contents throughout this specification.

In addition, even if not explicitly illustrated or described, it is obvious that a person having ordinary skill in the art to which the present invention pertains can make various modifications including technical ideas of the present invention from the description of the present invention, and this still falls within the scope of the rights of the present invention.

In addition, the above embodiments described with reference to the attached drawings are described for the purpose of explaining the present invention, and the scope of the rights of the present invention is not limited to these embodiments.

100, 100', 100a, 100a', 100b, 100b' : Field-relief semiconductor devices
110: 1st semiconductor layer
111 : Field stop layer
120: Second semiconductor layer
130: Carrier Storage (CS)
140, 140a, 140b: Trench section
141 : Gate Insulator
142 : Gate electrode
150, 150a, 15b: Active Mesa Area
151: n-type emitter region
152: p-type high concentration region
160 : Collector layer
170, 170', 170a, 170a' 170b, 170b' : Field-relaxing semiconductor layer
180, 180a: Dummy trench section

Claims (7)

A first semiconductor layer (110) having a field stop layer (111) formed at the bottom;
A second semiconductor layer (120) formed on the first semiconductor layer (110);
A charge accumulation layer (130) formed between the first semiconductor layer (110) and the second semiconductor layer (120) to have a higher impurity concentration than the first semiconductor layer (110);
A plurality of trench portions (140, 140a, 140b) formed in parallel and spaced apart from each other by a certain distance, and having a gate electrode (142) and extending through the second semiconductor layer (120) and the charge accumulation layer (130) to the first semiconductor layer (110);
An active mesa region (150, 150a, 150b) having an n-type emitter region (151) formed to be in contact with the trench portion (140, 140a, 140b) and a p-type high-concentration region (152) formed between the n-type emitter region (151);
A collector layer (160) formed on the lower side of the first semiconductor layer (110);
A field relaxation semiconductor layer (170, 170', 170a, 170a' 170b, 170b') formed at the lower portion of the trench portion (140, 140a, 140b) to have a lower impurity concentration than the first semiconductor layer (110); and
The above gate electrode (142) includes one or more dummy trench portions (180) connected to the emitter electrode;
A power semiconductor device having an electric field alleviation structure, characterized in that the above dummy trench portion (180) has no electric field alleviation semiconductor layer (170, 170', 170a, 170a' 170b, 170b') installed in the bottom area. In paragraph 1,
A power semiconductor device having an electric field relaxation structure, characterized in that the above-mentioned electric field relaxation semiconductor layer (170, 170a, 170b) is formed to surround the bottom area of each trench portion (140, 140a, 140b). In paragraph 1,
A power semiconductor device having an electric field relaxation structure, characterized in that the thickness (T) of the above-mentioned electric field relaxation semiconductor layer (170, 170', 170a, 170a' 170b, 170b') is formed from 10 ㎛ to the field stop layer (111). In any one of claims 1 to 3,
A power semiconductor device having an electric field relaxation structure, characterized in that the above-mentioned electric field relaxation semiconductor layer (170a, 170a' 170b, 170b') is formed to simultaneously surround a bottom area of an arbitrary trench portion (140) and one or more adjacent trench portions (140a, 140b). delete delete In paragraph 1,
A power semiconductor device having an electric field mitigation structure, characterized in that the above dummy trench portion (180) is installed in a continuous and adjacent manner with one or more dummy trench portions (180a).

Images