KR102706728B1 - Power compensation circuit for driving pixel and display using the same - Google Patents

Abstract

The present invention relates to a pixel power compensation circuit and a display device using the same, wherein a high-potential pixel driving voltage is applied to pixels through a first input node located in a first pixel line of a pixel array, and a low-potential power voltage is applied to pixels through a second input node located in an n-th pixel line (n is a positive integer greater than or equal to 2) farthest from the first pixel line in the pixel array.

Description

{POWER COMPENSATION CIRCUIT FOR DRIVING PIXEL AND DISPLAY USING THE SAME}

The present invention relates to a pixel power compensation circuit in which pixel power is commonly supplied to pixels where an image is reproduced, and a display device using the same.

Flat panel display devices include liquid crystal displays (LCDs), electroluminescence displays (ELDs), field emission displays (FEDs), and plasma display panels (PDPs).

Electroluminescent displays are largely classified into inorganic light emitting displays and organic light emitting displays, depending on the material of the light emitting layer. An organic light emitting display of the active matrix type includes an organic light emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has the advantages of a fast response speed, high light emitting efficiency, high brightness, and large viewing angle. Since an organic light emitting display can express black gradations as complete black, it can reproduce images at a level superior to that of a contrast ratio and color reproducibility.

A data signal and a gate signal (or a scan signal) are supplied to pixels of a display device. In addition, in order to drive the pixels, a separate pixel power may be supplied to all pixels. For example, pixels of an organic light-emitting display device are supplied with pixel power, such as a high-potential pixel driving voltage (ELVDD) and a low-potential power supply voltage (ELVSS), in common to all pixels so that current can flow to the OLED. However, since the amount of voltage drop (IR Drop) is different depending on the pixel position on the screen, the voltage difference between ELVDD and ELVSS may vary depending on the pixel position. This may cause a difference in the brightness of the OLED depending on the position on the screen, resulting in a phenomenon in which the brightness of an image reproduced on the screen varies depending on the pixel position.

The present invention aims to solve the above-mentioned needs and/or problems.

The present invention provides a power compensation circuit capable of reducing the voltage difference between ELVDD and ELVSS in all pixels of a screen and a display device using the same.

The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

In the pixel power compensation circuit of the present invention, a high-potential pixel driving voltage (ELVDD) is applied to the pixels through a first input node located in a first pixel line of a pixel array, and a low-potential power supply voltage (ELVSS) is applied to the pixels through a second input node located in an n-th pixel line (n is a positive integer greater than or equal to 2) farthest from the first pixel line in the pixel array.

The pixel power compensation circuit includes a first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from a power circuit is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line, and a first output terminal connected to the first inverting input terminal and connected to the first input node; and a second feedback compensation unit including a second non-inverting input terminal to which a low-potential power voltage generated from the power circuit is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line, and an output terminal connected to the second inverting input terminal and connected to the second input node.

The first input node is connected to a first power line connected to all pixels in the pixel array, and the second input node is connected to a second power line connected to all pixels in the pixel array.

The display device of the present invention includes a display panel having first to n-th pixel lines arranged; and a power circuit generating a high-potential pixel driving voltage (ELVDD) and a low-potential power supply voltage (ELVSS). The high-potential pixel driving voltage (ELVDD) is applied to the pixels through a first input node located in the first pixel line, and the low-potential power supply voltage (ELVSS) is applied to the pixels through a second input node located in the n-th pixel line which is furthest from the first pixel line in the pixel array.

According to another embodiment of the present invention, a display device includes a display panel having a pixel array in which first to n-th pixel lines each including first and second power lines are arranged; a power circuit generating a high-potential pixel driving voltage (ELVDD) and a low-potential power supply voltage (ELVSS); and a power compensation unit receiving the high-potential pixel driving voltage, a feedback voltage of the high-potential pixel driving voltage varied by a resistance of the pixel array, the low-potential power supply voltage, and a feedback voltage of the low-potential power supply voltage varied by a resistance of the pixel array, and supplying the compensated high-potential pixel driving voltage and the low-potential power supply voltage to the pixel array.

A high-potential pixel driving voltage output from the power compensation unit is supplied to the pixels of the pixel array through a first input resistor connected to the first power line of the first pixel line. A feedback voltage of the high-potential pixel driving voltage is fed back to the power compensation unit through a first feedback resistor connected to the first power line of the first pixel line. A low-potential power voltage output from the power compensation unit is supplied to the pixels of the pixel array through a second input resistor connected to the second power line of the n-th pixel line which is the farthest from the first pixel line.

The feedback voltage of the low-potential power supply voltage is fed back to the power compensation unit through a second feedback resistor connected to the second power line of the first pixel line.

The present invention sets ELVDD input positions and ELVSS input positions to be opposite to each other with a pixel array interposed therebetween on a display panel in order to reduce the voltage difference between ELVDD and ELVSS in all pixels of a screen. Accordingly, the present invention can reduce the voltage difference between ELVDD and ELVSS in all pixels of a screen.

The present invention can minimize the voltage difference between ELVDD and ELVSS by additionally applying a feedback compensation method to each of ELVDD and ELVSS, thereby preventing voltage changes in each of ELVDD and ELVSS in pixels.

Furthermore, the present invention can compensate for the voltage difference between ELVDD and ELVSS consistently across the entire screen regardless of the variation in the on-pixel ratio by reflecting the variation of ELVDD (ΔELVDD) and the variation of ELVSS (ΔELVDD) to ELVSS supplied to pixels of the display panel.

FIG. 1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
FIGS. 2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention.
Figure 4 is a diagram showing an example in which the voltage difference between ELVDD and ELVSS increases depending on the pixel position when the ELVDD input position and the ELVSS input position are the same.
FIG. 5 is a diagram showing an example in which the voltage difference between ELVDD and ELVSS in the present invention varies depending on the location on the improved pixel array.
FIGS. 6A and 6B are drawings showing a power compensation unit according to an embodiment of the present invention.
Figure 7 is a circuit diagram showing in detail a power compensation unit according to the first embodiment of the present invention.
Figures 8 to 10 are diagrams showing an EVDD input node, an ELVDD feedback node, an EVSS input node, and an ELVSS feedback node.
Figure 11 is a diagram showing an example in which the voltage difference between ELVDD and ELVSS becomes uneven due to variation in the on-pixel ratio.
Figure 12 is a diagram showing an example of reflecting the variation of ELVDD in the compensation of ELVSS in the example of Figure 11.
Figure 13 is a circuit diagram showing in detail a power compensation unit according to the second embodiment of the present invention.
Figures 14 to 16 are drawings explaining why a buffer is required in the subtraction section shown in Figure 13.
Figure 17 is a drawing showing an example in which ELVSS is applied to the top and bottom of the display panel.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and the present invention is not limited to the matters illustrated in the drawings. The same reference numerals throughout the specification refer to substantially the same components. In addition, in explaining the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

In the specification, when the terms "comprises," "includes," "has," and "consists of," are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it can be interpreted as plural unless there is a special explicit statement.

When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

When describing a positional relationship, for example, when a positional relationship is described between two components as 'on', 'above', 'below', 'next to', etc., one or more other components may intervene between those components where 'directly' or 'directly' is not used.

Although the terms 1st, 2nd, etc. may be used to distinguish components, the function or structure of these components is not limited by the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and may be technically capable of various interconnections and operations. Each embodiment may be implemented independently of each other, or may be implemented together in a related relationship.

In the electroluminescent display device of the present invention, the pixel circuit and the GIP circuit may include at least one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode through which carriers exit the transistor. In the transistor, the flow of carriers flows from the source to the drain. In the case of the n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In the n-channel transistor, the direction of current flows from the drain to the source. In the case of the p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first and second electrodes.

A gate signal applied to the pixels swings between a gate on voltage and a gate off voltage. The gate on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate on voltage, while it is turned off in response to the gate off voltage. For an n-channel transistor, the gate on voltage may be a gate high voltage (VGH), and the gate off voltage may be a gate low voltage (VGL). For a p-channel transistor, the gate on voltage may be a gate low voltage (VGL), and the gate off voltage may be a gate high voltage (VGH).

Each pixel of an organic light-emitting display device includes an OLED, which is a light-emitting element, and a driving element that supplies current to the OLED according to a gate-source voltage (Vgs) to drive the OLED. The OLED includes an anode and a cathode, and an organic compound layer formed between these electrodes. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), and the like. When current flows through the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML), whereby excitons are formed, and as a result, the emission layer (EML) can emit visible light.

The driving element can be implemented as a transistor such as a MOSFET (metal oxide semiconductor field effect transistor). The driving element must have uniform electrical characteristics among all pixels, but there may be differences among pixels due to process deviation and element characteristic deviation and may change over the display driving time. In order to compensate for such deviation in the electrical characteristics of the driving element, an internal compensation method and/or an external compensation method can be applied to the organic light emitting display device. The internal compensation method samples the electrical characteristics between sub-pixels in real time within the sub-pixel and compensates the pixel data voltage within the sub-pixel by the electrical characteristics of the sub-pixel. The electrical characteristics of the sub-pixel include the threshold voltage or mobility of the driving element, etc. The external compensation method senses the current or voltage of the pixel that changes according to the electrical characteristics of the sub-pixel in real time and modulates the pixel data (digital data) of the input image in an external circuit based on the electrical characteristics sensed for each sub-pixel, thereby compensating for the change or deviation in the electrical characteristics of each sub-pixel. The present invention can be applied to an organic light emitting display device to which the internal compensation method and/or the external compensation method are applied. In the following examples, a pixel circuit to which an internal compensation method is applied is exemplified, but the present invention is not limited thereto. The external compensation method can reduce the number of transistors and pixel power supplies required in a pixel circuit compared to the internal compensation method.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the embodiments below, the display device is described mainly as an organic light-emitting display device including an organic light-emitting material, but the present invention is not limited thereto. For example, the technical idea of the present invention may be applied to a display device in which two or more power sources with different voltage levels are applied to pixels.

Referring to FIG. 1, the display device of the present invention includes a display panel (100) and a display panel driving circuit for writing data into pixels (101) of the display panel (100).

The display panel (100) includes a screen (A/A) on which an input image is reproduced. The screen (A/A) includes a pixel array in which pixel data of the input image is written and in which the input image is displayed. When the resolution of the pixel array is m*n, the pixel array includes m pixel columns (Column) and n pixel lines (L1 to Ln) intersecting the pixel columns. The pixel columns include pixels arranged along the Y-axis direction. The pixel lines include pixels arranged along the X-axis direction. 1 horizontal period (1H) is a time obtained by dividing 1 frame period by the number of n pixel lines (L1 to Ln).

The pixel array includes a plurality of data lines (102), a plurality of gate lines (103) intersecting the data lines (103), and pixels arranged in a matrix form.

Each of the pixels can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels can further include a white sub-pixel. Each of the sub-pixels (101) includes a pixel circuit. Hereinafter, a pixel can be interpreted to have the same meaning as a sub-pixel.

The pixel circuit includes a light-emitting element, a driving element, one or more switching elements, and a capacitor, as in the examples of FIGS. 2 and 3. The driving element and the switching element may be implemented with a TFT (Thin Film Transistor). It should be noted that the pixel circuit is not limited to FIGS. 2 and 3. For example, FIGS. 2 and 3 may exemplify a pixel circuit implemented based on a p-channel transistor, but the pixel circuit may also be implemented with a pixel circuit based on a known n-channel transistor. The pixel circuit is connected to a data line (102) and a gate line (103).

All pixels of the display panel (100) are commonly supplied with pixel power as illustrated in FIGS. 2 and 3. The pixel power is generated from a power circuit (150) and includes a pixel driving voltage (ELVDD) and a low-potential power voltage (ELVSS) that are commonly applied to the pixels so that current can flow to the OLED in each pixel. The power circuit (150) may be implemented as a power IC. The low-potential power voltage (ELVSS) is a voltage lower than the pixel driving voltage (ELVDD). In general, ELVDD and ELVSS are generated as a DC voltage, but are not limited thereto. The pixel power may be further added depending on the pixel circuit. For example, the pixel power may further include a power such as a reference voltage or an initialization voltage (Vref, Vini) for the pixel circuits illustrated in FIGS. 2 and 3.

In FIGS. 2 and 3, the pixel circuit may further include a first power line (41) for supplying ELVDD to the sub-pixels (101), a second power line (43) for supplying ELVSS to the pixels, a third power line (42) for supplying Vref (or Vini) to the sub-pixels (101), etc.

Touch sensors may be arranged on the display panel (100). Touch input may be sensed using separate touch sensors or may be sensed through pixels. The touch sensors may be implemented as in-cell type touch sensors arranged on the screen of the display panel as an on-cell type or an add on type or built into a pixel array.

The display panel driving circuit comprises a data driving unit (110) and a gate driving unit (120). The display panel driving circuit further comprises a demultiplexer (112) arranged between the data driving unit (110) and data lines (102).

The display panel driving circuit writes data of an input image to pixels of the display panel (100) under the control of a timing controller (TCON) (130). The display panel driving circuit may further include a touch sensor driving unit for driving touch sensors. The touch sensor driving unit is omitted in FIG. 1. In a mobile device, the display panel driving circuit, the timing controller (130), and the power circuit (150) may be integrated into a single integrated circuit.

The display panel driving circuit can operate in a low-speed driving mode. The low-speed driving mode can be set to reduce power consumption of the display device when the input image does not change by a preset number of frames by analyzing the input image. In other words, the low-speed driving mode can reduce power consumption by controlling the data writing cycle of the pixels to be long by lowering the refresh rate of the pixels when a still image is input for a certain period of time or longer. The low-speed driving mode is not limited to when a still image is input. For example, the display panel driving circuit can operate in the low-speed driving mode when the display device operates in a standby mode or when a user command or an input image is not input to the display panel driving circuit for a certain period of time or longer.

The data driving unit (110) converts pixel data (digital data) of an input image received from a timing controller (130) into a gamma compensation voltage for each frame period and generates a voltage of a data signal (hereinafter, “data voltage”). The data driving unit (110) outputs the data voltage through an output buffer in each channel.

A demultiplexer (112) is arranged between a data driving unit (110) and data lines (102) using a plurality of switch elements to time-divisionally distribute data voltages output from the data driving unit (110) to the data lines (102). In the data driving unit (110), one channel can be connected to neighboring N (N is a positive integer greater than or equal to 2) through the multiplexer (112). Therefore, because the number of channels of the data driving unit (110) is reduced due to the demultiplexer (112), the number of drive ICs (200) in which the data driving unit (110) is integrated can be reduced. The demultiplexer (112) can be formed directly on a substrate of the display panel (100) or can be integrated into the drive IC (200) together with the data driving unit (110).

The gate driver (120) may be formed directly on the bezel area (Bezel, BZ) on the display panel (100) together with the TFT array of the pixel array. The gate driver (120) outputs gate signals to the gate lines (103) under the control of the timing controller (130). The gate driver (120) may sequentially supply the signals to the gate lines (103) by shifting the gate signals using a shift register. The gate signal includes a scan signal for selecting pixels of a line in which data is to be written, and a light emission control signal (hereinafter, referred to as “EM signal”) for defining the light emission time of pixels charged with a data voltage.

The gate driver (120) may include a first gate driver (121) and a second gate driver (122). The first gate driver (121) outputs a scan signal and sequentially shifts the scan signal according to a shift clock. The second gate driver (122) outputs an EM signal and sequentially shifts the EM signal according to a shift clock. In order to reduce the bezel size, at least a portion of the gate driver (120) may be distributed and arranged within the pixel array.

The timing controller (130) receives digital video data (DATA) of an input image from a host system that is not shown, and a timing signal synchronized therewith. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE in FIG. 7).

The timing controller (130) can control the operation timing of the display panel driver (110, 112, 120) with a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz by multiplying the input frame frequency by i. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) method and 50 Hz in the PAL (Phase-Alternating Line) method. The timing controller (130) can lower the frame frequency to a frequency between 1 Hz and 30 Hz in order to lower the refresh rate of pixels in the low-speed driving mode.

The timing controller (130) generates a data timing control signal for controlling the operation timing of the data driver (110), a switch control signal for controlling the operation timing of the demultiplexer (112), and a gate timing control signal for controlling the operation timing of the gate driver (120) based on a timing signal (Vsync, Hsync, DE) received from the host system. The voltage level of the gate timing control signal output from the timing controller (130) can be converted into a gate-on voltage and a gate-off voltage through a level shifter (not shown) and supplied to the gate driver (120). The level shifter converts a low level voltage of the gate timing control signal into a gate low voltage (VGL) and converts a high level voltage of the gate timing control signal into a gate high voltage (VGH).

The host system may be a main circuit board of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device. In a mobile device or a wearable device, a timing controller (130), a data driver (110), and a level shifter may be integrated into one drive IC (200 of FIGS. 6A and 6B).

FIGS. 2 and 3 are circuit diagrams showing examples of pixel circuits applicable to the present invention. The pixel circuits illustrated in FIGS. 2 and 3 are examples in which an internal compensation circuit is applied that senses a threshold voltage (Vth) of a driving element and compensates for a data voltage (Vdata) by the threshold voltage (Vth). The internal compensation circuit is built into each pixel circuit and samples the threshold voltage of the driving element in each sub-pixel in real time and compensates for the data voltage applied to the gate of the driving element by the threshold voltage of the driving element in real time.

Meanwhile, it should be noted that the present invention is not limited to the pixel circuit illustrated in FIGS. 2 and 3. For example, the pixel circuit of the present invention can be applied as an internal compensation circuit that senses the mobility (μ) of a driving element and compensates the data voltage (Vdata) by the mobility.

Referring to FIG. 2, the pixel circuit includes a light-emitting element (EL), a plurality of TFTs (Thin Film Transistors) (T1 to T5, DT), a capacitor (Cst), etc. The driving element (DT) and the switching elements (T1 to T5, DT) may be implemented as p-channel transistors (PMOS), but are not limited thereto.

The switch elements (T1 to T5) are turned on/off according to the gate signal from the gate lines (31 to 33) to initialize the pixel circuit, then connect the source and drain of the driving element (DT), and then supply the data voltage to the capacitor (Cst). In addition, the switch elements (T1 to T5) switch the current pass between the driving element (DT) and the light-emitting element (DT). When the gate and drain of the driving element (DT) are connected, the driving element (DT) operates in a diode form, and the voltage between the source and gate of the driving element (DT) rises to the threshold voltage of the driving element (DT), which is sampled by the capacitor (Cst).

The light emitting element (EL) can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the OLED is connected to the fourth and fifth switching elements (T4, T5) through the fourth node (n4). The cathode of the OLED is connected to the second power line (43) to which ELVSS is applied. The driving element (DT) supplies current to the OLED to drive the OLED. The OLED emits light with an amount of current controlled by the driving element (DT) according to the data voltage (Vdata). The current path of the OLED is switched by the fourth switching element (T4).

A capacitor (Cst) is connected between a first node (n1) and a second node (n2). The first node (n1) is connected to a second electrode of a first switching element (T1), a first electrode of a third switching element (T3), and a first electrode of the capacitor (Cst). The second node (n2) is connected to the second electrode of the capacitor (Cst), a gate of a driving element (DT), and a first electrode of the second switching element (T2). A data voltage (Vdata) compensated for by a threshold voltage (Vth) of the sampled driving element (DT) is charged to the capacitor (Cst). Accordingly, since the data voltage (Vdata) of each of the sub-pixels is compensated for by the threshold voltage (Vth) of the driving element (DT), a characteristic deviation of the driving element in the sub-pixels is compensated, so that the sub-pixels can be driven with uniform driving characteristics.

The first switch element (T1) is a switch element that supplies a data voltage (Vdata) to a first node (n1) in response to a gate-on voltage of a first scan signal (SCAN1). The first switch element (T1) includes a gate connected to a first gate line (31), a first electrode connected to a data line (21), and a second electrode connected to the first node (n1). The first scan signal (SCAN1) can be simultaneously applied to pixels arranged in two lines of a pixel array through the first gate line (31). The first scan signal (SCAN1) defines a compensation period for sampling a threshold voltage of a driving element (DT) in the pixels arranged in the two lines and charging a data voltage to the pixels. The first scan signal (SCAN1) can be generated as a pulse of a gate-on voltage.

The second switching element (T2) connects the gate of the driving element (DT) and the second electrode in response to the gate-on voltage of the second scan signal (SCAN2). The second switching element (T2) includes a gate connected to the second gate line (32), a first electrode connected to the second node (n2), and a second electrode connected to the third node (n3).

The third switching element (T3) supplies Vref to the first node (n1) in response to the gate-on voltage of the EM signal (EM), thereby initializing the first node (n1) to Vref. The third switching element (T3) includes a gate connected to the third gate line (33), a first electrode connected to the first node (n1), and a second electrode connected to the third power line (42). The EM signal (EM) defines the light-emitting time of the light-emitting element (EL).

The fourth switching element (T4) switches the current path of the light-emitting element (EL) in response to the EM signal (EM). The gate of the fourth switching element (T4) is connected to the third gate line (33). The first electrode of the fourth switching element (T4) is connected to the third node (n3), and the second electrode of the fourth switching element (T4) is connected to the fourth node (n4).

The fifth switching element (T5) initializes the voltage of the fourth node (n4) connected to the anode of the light-emitting element (EL) to Vref in response to the second scan signal (SCAN2). The fifth switching element (T5) includes a gate connected to the second gate line (32), a first electrode connected to the third power line (42), and a second electrode connected to the fourth node (n4).

The driving element (DT) is a driving element that controls the current flowing to the light-emitting element (EL) according to the gate-source voltage (Vgs). The driving element (DT) includes a gate connected to a second node (n2), a first electrode connected to a first power line (41), and a second electrode connected to a third node (n3). ELVDD is supplied to the pixels through the first power line (41).

Referring to FIG. 3, the pixel circuit includes a light-emitting element (EL), a plurality of TFTs (T11 to T16, DT), a capacitor (Cst), etc. The TFTs (T11 to T16, DT) may be implemented as p-channel transistors (PMOS), but are not limited thereto.

A capacitor (Cst) is connected between a first node (n1) and a second node (n2). ELVDD is supplied to the pixel circuit through a first power line (41). The first node (n1) is connected to the first power line (41) to which ELVDD is applied, a first electrode of a third switch element (T13), and a first electrode of the capacitor (Cst). The second node (n2) is connected to a second electrode of the capacitor (Cst), a gate of a driving element (DT), and a first electrode of a fifth switch element (T15).

The first switching element (T11) connects the gate of the driving element (DT) and the second electrode in response to the Nth (N is a positive integer) scan signal (SCAN(N)). The first switching element (T11) includes a gate connected to the first gate line (31), a first electrode connected to the gate of the driving element (DT), and a second electrode connected to the second electrode of the driving element (DT). The Nth scan signal (SCAN(N)) is applied to the pixel circuit through the first gate line (31).

The second switching element (T12) applies a data voltage (Vdata) to the first electrode of the driving element (DT) in response to the Nth scan signal (SCAN(N)). The second switching element (T12) includes a gate connected to the first gate line (31), a first electrode connected to the first electrode of the driving element (DT), and a second electrode connected to the data line (21).

The third switching element (T13) applies ELVDD to the first electrode of the driving element (DT) in response to the EM signal (EM(N)). The third switching element (T13) includes a gate connected to the third gate line (33), a first electrode connected to the first power line (41), and a second electrode connected to the first electrode of the driving element (DT). The EM signal (EM(N)) is applied to the pixel circuit through the third gate line (33).

The fourth switching element (T14) connects the second electrode of the driving element (DT) to the anode of the light-emitting element (EL) in response to the EM signal (EM(N)). The gate of the fourth switching element (T14) is connected to the third gate line (33). The first electrode of the fourth switching element (T14) is connected to the second electrode of the driving element (DT) and the second electrode of the first switching element (T11), and the second electrode of the fourth switching element (T14) is connected to the anode of the light-emitting element (EL).

The fifth switching element (T15) connects the second node (n2) to the third power line (42) in response to the N-1 scan signal (SCAN(N-1)). Vini is applied to the pixel circuit through the third power line (42). The fifth switching element (T15) includes a gate connected to the second gate line (32), a first electrode connected to the second node (n2), and a second electrode connected to the third power line (42).

The sixth switching element (T16) connects the third power line (42) to the anode of the light-emitting element (EL) in response to the Nth scan signal (SCAN(N)). The sixth switching element (T16) includes a gate connected to the first gate line (31), a first electrode connected to the third power line (42), and a second electrode connected to the anode of the light-emitting element (EL).

The light emitting element (EL) can be implemented as an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The anode of the OLED is connected to the fourth and sixth switching elements (T14, T16). The cathode of the OLED is connected to a second power line (43) to which ELVSS is applied.

The driving element (DT) controls the current flowing to the light-emitting element (EL) according to the gate-source voltage (Vgs). The driving element (DT) includes a gate connected to a second node (n2), a first electrode connected to a first electrode of a second switching element (T12) and a second electrode of a third switching element (T13), and a second electrode connected to a second electrode of the first switching element (T11) and a first electrode of a fourth TFT (T14).

ELVDD, ELVSS, and Vini can be DC voltages of ELVDD = 7 V to 8 V, ELVSS = 0 V, and Vini = 1 V, but are not limited thereto. Vdata can be a voltage of 0 V to 5 V output from the data driving unit (110), but is not limited thereto.

The pixel power generated from the power circuit (150) may vary depending on the location on the pixel array. ELVDD and ELVSS may have a voltage drop (IR drop) depending on the current*resistance on the display panel (100). The voltage drop of ELVDD can be expressed as ELVDD-IR, and the voltage drop of ELVSS can be expressed as ELVSS+IR. Here, I is current and R is resistance. The larger the voltage drop of ELVDD, the lower the voltage of ELVDD. On the other hand, the larger the voltage drop of ELVSS, the higher the voltage of ELVSS.

ELVDD and ELVSS can be input at the same position on the pixel array. When ELVDD and ELVSS are input at the top of the display panel close to the first pixel line (L1) and applied to all pixels of the pixel array, as illustrated in FIG. 4, ELVDD applied to the pixels of the first pixel line (L1) has low resistance and thus a small voltage drop, but ELVDD applied to the pixels of the n-th pixel line, which is far from the ELVDD input position (or input node), has high resistance and thus a large voltage drop of the ELVDD. The first pixel line (L1) is arranged at the top of the display panel (100), and the n-th pixel line (Ln) is arranged at the bottom of the display panel (100). ELVSS applied to the pixels of the first pixel line (L1) has a small voltage drop, but the voltage drop of the ELVSS increases as it goes toward the n-th pixel line (Ln). As a result, as illustrated in FIG. 4, the voltage of ELVDD decreases as it goes toward the nth pixel line (Ln), whereas the voltage of ELVSS increases as it goes toward the nth pixel line (Ln). In this case, the voltage difference (ΔVn) between ELVDD and ELVSS applied to the pixels of the nth pixel line (Ln) becomes smaller than the voltage difference (ΔV1) between ELVDD and ELVSS applied to the pixels of the first pixel line (L1), so that the amount of current flowing to the light-emitting element (EL) may vary depending on the pixel position.

The scan signal output from the gate driver (120) may be applied starting from the first pixel line (L1) in the forward scan and may be sequentially shifted from the second pixel line (L2) to the nth pixel line (Ln). In this case, the scan signal is applied first to the first pixel line (L1) in one frame period, and the scan signal is applied last to the nth pixel line (Ln).

The present invention sets ELVDD input positions and ELVSS input positions to be opposite positions on the display panel (100) with a pixel array interposed therebetween in order to reduce the voltage difference between ELVDD and ELVSS in all pixels of the screen. For example, when ELVDD is input to the upper part of the display panel (100) near the first pixel line (L1), ELVSS is input to the lower part of the display panel (100) near the nth pixel line (Ln). When ELVDD is input to the lower part of the display panel (100), ELVSS is input to the upper part of the display panel (100).

Referring to FIG. 5, when ELVDD is input to an ELVDD input node located at a first pixel line (L1) of the display panel (100) and ELVSS is input to an ELVSS input node located at an n-th pixel line (Ln) of the display panel (100), the direction of current flowing from ELVDD to ELVSS in all pixels of the pixel array is the same and the voltage difference (ΔV) between ELVDD and ELVSS is maintained at substantially the same level. In the first pixel line (L1) of the display panel (100), ELVDD has almost no voltage drop, whereas ELVSS has a large voltage drop and thus rises to a voltage higher than the input voltage. In contrast, in the n-th pixel line (Ln) of the display panel (100), ELVDD has a large voltage drop and thus falls to a voltage lower than the input voltage, whereas ELVSS has almost no voltage drop.

Based on the position of the drive IC (200), the first pixel line (L1) is the closest pixel line to the drive IC (200), and the nth pixel line (Ln) is the farthest pixel line.

The present invention can minimize the voltage difference between ELVDD and ELVSS by additionally applying a feedback compensation method to each of ELVDD and ELVSS, thereby preventing voltage changes in each of ELVDD and ELVSS in pixels.

FIGS. 6A and 6B are drawings showing a power compensation unit according to an embodiment of the present invention.

Referring to FIGS. 6A and 6B, the display device of the present invention includes a second circuit board (60) connecting a first circuit board (50) to an upper portion of a display panel (100), and a third circuit board (62) connecting the PCB (50) to a lower portion of the display panel (100). The upper portion of the display panel (100) is close to the first pixel line (L1) and the drive IC (200). The lower portion of the display panel (100) is close to the nth pixel line (Ln).

The first circuit board (50) may be implemented as a printed circuit board (PCB). The first circuit board (50) may include a timing controller (130), a power circuit (150), feedback compensation units (52, 54), a level shifter, etc. The power circuit (150) and the feedback compensation units (52, 54) may be integrated into one power IC.

The second circuit board (60) may be a flexible circuit board such as a COF (Chip on film) or FPC (Flexible Printed Circuit) on which the drive IC (200) is mounted. When the drive IC (200) is directly bonded to the substrate of the display panel (100) by a COG (Chip on glass) process, the drive IC (200) is bonded to the upper part of the substrate of the display panel (100), and the second circuit board (60) may be replaced with an FPC.

At least two of the first circuit board (50), the second circuit board (60), and the third circuit board (62) may be integrated to reduce the number of individual circuit boards. For example, the second and third circuit boards (62, 64) may be manufactured as one FPC. Feedback compensation units (52, 54) may also be mounted on the second circuit board (60).

The input pads of the second circuit board (60) can be electrically connected to the PCB (50) through a connector on the PCB (50). The output pads of the second circuit board (60) can be electrically connected to pads on the display panel (60) through an ACF (Anisotropic Conductive Film) bonding process. The pads on the display panel (100) can include pads connected to power lines (41, 42, 43) to which pixel power is supplied, pads connected to data lines to which data voltage is supplied, and pads to which gate timing signals are applied.

The third circuit board (60) supplies the ELVSS applied from the first circuit board (50) to the third power line (43). The third circuit board (60) may be implemented as a flexible circuit board such as an FPC, as illustrated in FIG. 6A. The third circuit board (62) may be connected to the second circuit board (60) or to the first circuit board (50). In addition, the third circuit board (62) may be connected to the first circuit board (50) and the display panel (100) via the second circuit board (60). The third circuit board (62) electrically connects the top and bottom of the display panel (100) outside the display panel (100) to provide a current path that bypasses the display panel (100).

One end of the third circuit board (62) may be connected to the first circuit board (50) and the upper end of the display panel (100) via the second circuit board (60). The other end of the third circuit board (62) may be connected to the lower end of the display panel (100). Pads at the other end of the third circuit board (62) may be connected to pads arranged at the lower end of the display panel (100) by an ACF bonding process. The third power line (43) of the pixels may be connected to the lower pad of the display panel (100) via the third circuit board (62).

As illustrated in FIG. 6b, ELVSS wiring (160) may be formed along the edge of the display panel (100). The ELVSS wiring (160) may be formed as a long stripe wiring between the top and bottom of the display panel (100) along one edge or both edges of the display panel (100). The ELVSS wiring (160) may be formed along the edge of the display panel (100) in parallel with the clock wiring that supplies the shift clock to the gate driver (120).

The ELVSS wiring (160) is connected to the third power line (43) of the pixels. The ELVSS wiring (160) is connected to the first circuit board (50) via the second circuit board (60) to supply ELVSS from the first circuit board (50) to the third power line (43).

As shown in Fig. 6b, when the ELVSS wiring (160) is formed on the substrate of the display panel (100), the third power line (43) can be omitted. In this case, the circuit board cost is reduced.

The power compensation unit of the present invention may include feedback compensation units (52, 54) as shown in FIGS. 6a and 6b.

The feedback compensation units (52, 54) include an ELVDD feedback compensation unit (52) and an ELVSS feedback compensation unit (54) as illustrated in FIG. 7.

The operational amplifier (AMP) of the ELVDD feedback compensation unit (52) includes a non-inverting input terminal (+) connected to the ELVDD output terminal of the power circuit (150) through a resistor, an inverting input terminal (-) connected to the ELVDD feedback node through a resistor, and an output terminal connected to the inverting input terminal (-) through a resistor and connected to the ELVDD input node of the pixel array. In Fig. 7, the ELVDD input voltage (ELVDD_IC) is an ELVDD output from the power circuit (150).

The ELVDD feedback voltage (ELVDD_FB) is input from the ELVDD feedback node connected to the pixels of the display panel (100).

The ELVDD output voltage (ELVDD OUTPUT) is applied to the ELVDD input node on the display panel (100). The ELVDD input node is located close to the first pixel line (Ln). The ELVDD input node is connected to all pixels of the pixel array through the first power line (41). In FIGS. 8 to 10, nodes A and C are connected to the first power line (41), the ELVDD input node, and the ELVDD feedback node.

The ELVDD feedback compensation unit (52) receives the ELVDD feedback voltage (ELVDD_FB) and the ELVDD input voltage (ELVDD_IC), adds the reverse polarity voltage of the difference to the ELVDD input voltage (ELVDD_IC), and outputs the feedback-compensated ELVDD. The output voltage (ELVDD OUTPUT) of the ELVDD feedback compensation unit (52) is supplied to the first power line (41) of the pixels through the ELVDD input terminal resistance. The ELVDD input terminal resistance includes the resistance between the output terminal of the power circuit (150) and the ELVDD input node.

The ELVDD feedback compensation unit (52) compensates for the change in the ELVDD output voltage (ELVDD OUTPUT) applied to the pixels of the pixel array due to the voltage drop with a reverse polarity voltage equal to the difference between the ELVDD input voltage (EVDD INPUT) and the ELVDD feedback voltage (ELVDD_FB). For example, if the ELVDD feedback voltage (ELVDD_FB) decreases due to the voltage drop caused by the wiring resistance of the pixel array, the ELVDD feedback compensation unit (52) increases the ELVDD output voltage (ELVDD OUTPUT) by adding the amount of change in the ELVDD feedback voltage (ELVDD_FB) to the ELVDD input voltage (ELVDD_IC).

An operational amplifier (AMP) of the ELVSS feedback compensation unit (52) includes a non-inverting input terminal (+) connected to the ELVSS output terminal of the power circuit (150) through a resistor, an inverting input terminal (-) connected to the ELVSS feedback node through a resistor, and an output terminal connected to the inverting input terminal (-) through a resistor and connected to the ELVSS input node of the pixel array. In FIGS. 8 to 10, nodes B and D are connected to the second power line (43), the ELVSS input node, and the ELVSS feedback node.

The ELVSS feedback voltage (ELVDD_FB) is a voltage input from an ELVDD feedback node where an ELVSS voltage is detected on the display panel (100). The ELVSS output voltage (ELVSS OUTPUT) is an ELVSS voltage applied to an ELVSS input node on the display panel (100). The ELVSS input node is connected to all pixels of the pixel array through a second power line (43).

The ELVSS feedback compensation unit (54) receives the feedback voltage (ELVSS_FB) from the ELVSS feedback node and the ELVSS input voltage (ELVSS), and outputs the feedback-compensated ELVSS by adding the ELVSS input voltage (ELVSS) with the reverse polarity voltage of the difference. The output voltage (ELVSS OUTPUT) of the ELVSS feedback compensation unit (54) is supplied to the second power line (43) of the pixels through the ELVSS input terminal resistance. The ELVSS input terminal resistance includes the resistance of the third circuit board (62) or the ELVSS wiring (160).

The ELVSS feedback compensation unit (54) compensates for changes in the ELVSS output voltage (ELVSS OUTPUT) applied to the EVSS input node of the pixel array. For example, when the ELVDSS feedback voltage (ELVSS_FB) increases due to a voltage drop caused by the wiring resistance of the pixel array, the ELVSS feedback compensation unit (54) adds the amount of change in the ELVSS feedback voltage (ELVSS_FB) to the ELVSS input voltage (ELVSS) to lower the ELVSS output voltage (ELVSS OUTPUT).

The ELVDD input node, the ELVDD feedback node, and the ELVSS feedback node can be located in a first pixel line (L1) in the pixel array. The ELVSS input node can be located in an n-th pixel line (Ln) that is furthest from the first pixel line (L1) where the ELVDD input node, the ELVDD feedback node, and the ELVSS feedback node are located.

FIGS. 8 to 10 are diagrams showing an EVDD input node, an ELVDD feedback node, an EVSS input node, and an ELVSS feedback node. FIG. 8 shows a current of a pixel array when a scan signal is applied to the pixels of the first pixel line (L1) and the driving elements (DT) of these pixels are turned on. FIG. 9 shows a current of a pixel array when a scan signal is applied to the pixels of the n-th pixel line (Ln) and the driving elements (DT) of these pixels are turned on. In FIGS. 8 to 10, “Rin1” is a first input terminal resistor that is connected to the first power line (41) of the first pixel line (L1) and to which ELVDD is applied. “Rin2” is a second input terminal resistor that is connected to the second power line (43) of the n-th pixel line (Ln) and to which ELVSS is applied. “Rfb1” is a first feedback resistor connected to the first power line (41) of the first pixel line (L1) and to which an ELVDD feedback voltage is applied. “Rfb2” is a second feedback resistor connected to the second power line (43) of the first pixel line (L1) and to which an ELVSS feedback voltage is applied.

Through the second input resistor connected to the second power line of the nth pixel line.

Referring to FIGS. 8 and 9, the pixel array includes first to nth pixel lines (L1 to Ln) into which pixel data of an input image is written. The nth pixel line (L1) is a pixel line located farthest from the first pixel line (L1) on the pixel array. For example, when the first pixel line (L1) is the topmost pixel line in the pixel array, the nth pixel line (Ln) is the bottommost pixel line in the pixel array.

In FIGS. 8 and 9, the ELVDD input node and the ELVDD feedback node may be connected to the first power line (41) at node A of the first pixel line (L1), and the ELVSS feedback input node may be connected to the second power line (43) at node B of the first pixel line (L1). In this case, the ELVSS input node is connected to the second power line (43) at node D of the n-th pixel line (Ln) that is furthest from the first pixel line (L1) on the pixel array. The ELVSS input node may be connected to the output terminal of the ELVSS feedback compensation unit (54) through the third circuit board (62). The first power line (41) is connected from the ELVDD input node to the ELVDD output terminal of the ELVDD feedback compensation unit (52) and is connected to all pixels. The second power line (43) is connected from the ELVSS input node to the ELVSS output terminal of the ELVSS feedback compensation unit (54) and is connected to all pixels.

The voltage at node A is ELVDD-(R*I), the voltage at node B is ELVSS+(3R*I), the voltage at node C is ELVDD-(3R*I), and the voltage at node D is ELVSS+(R*I).

Referring to FIG. 10, the ELVDD input node and the ELVDD feedback node may be connected to the first power line (41) at the node C of the nth pixel line (Ln), and the ELVSS feedback input node may be connected to the second power line (43) at the node D of the nth pixel line (Ln). The ELVSS input node is connected to the second power line (43) at the node B of the first pixel line (L1) that is furthest from the nth pixel line (Ln) on the pixel array.

The ELVDD input node, the ELVDD feedback node, and the ELVSS feedback input node can be connected to the output terminal of the ELVSS feedback compensation unit (54) through the third circuit board (62).

As described above, the present invention can make the fluctuation direction of ELVDD and ELVSS the same across the entire screen (A/A) of the display panel (100) by changing the supply path of ELVSS. As a result, the deviation of the drain-source voltage (Vds) of the driving elements (DT) across the entire screen (A/A) can be compensated for.

The amount of current flowing through the pixel array and the load of the display panel (100) may vary depending on the data voltage applied to the pixels. If ELVSS is not compensated in real time by the amount of variation in ELVDD, the deviation of the drain-source voltage (Vds) due to variation in the on-pixel ratio that emits light may not be ideally and quickly compensated. An on-pixel is a pixel that emits light.

As in the example of Fig. 11, after all pixels are turned off (not emitting light) in the first frame period (F1) and the screen (A/A) appears black (black), all pixels can emit light with a white gradation brightness from the second frame period (F2). In this example, there is a large difference in the ratio of pixels that are on in the first frame period (F1) and the subsequent frame periods (F2-F4). In this case, the voltage difference between ELVDD and ELVSS becomes uneven between the first to third frame periods (F1 to F3), which may cause a deviation in the drain-source voltage (Vds) of the driving elements (DT), and the voltage difference between ELVDD and ELVSS may become the same from the third frame period (F3).

Fig. 12 is a diagram showing an example of reflecting the variation of ELVDD in the compensation of ELVSS in the example of Fig. 11. Fig. 13 is a circuit diagram showing in detail a power compensation unit according to the second embodiment of the present invention.

Referring to FIGS. 12 and 13, the power compensation unit of the present invention reflects the variation amount of ELVDD (ΔELVDD) and the variation amount of ELVSS (ΔELVDD) to the ELVSS supplied to the pixels of the display panel (100), thereby enabling the voltage difference between ELVDD and ELVSS to be constantly compensated for across the entire screen (A/A) regardless of the variation amount of the on-pixel ratio. As a result, the present invention can ideally compensate for not only the variation in the drain-source voltage (Vds) of the driving elements (DT) between the upper and lower ends of the display panel (100), but also the variation in the drain-source voltage (Vds) according to the variation in the on-pixel ratio. In FIG. 12, the dotted line represents ELVSS before compensation, and the solid line represents ELVSS reflecting ΔELVDD and ΔELVSS.

The power compensation unit includes a subtraction unit (1100) that detects ΔELVDD, an addition unit (1200) that adds ELVSS to ΔELVDD, and an ELVSS feedback compensation unit (1300) as shown in Fig. 13. In Fig. 13, the resistors can be set to the same resistance value.

The reduction unit (1100) includes a first operational amplifier (AMP1).

The ELVDD input voltage (ELVDD_IC) is input to the inverting input terminal (-) of the first operational amplifier (AMP1) through the resistor (R). The ELVDD feedback voltage (ELVDD_FB) is input to the non-inverting input terminal (+) of the first operational amplifier (AMP1) through a buffer (BUF) and a voltage divider circuit. The voltage divider circuit includes a voltage divider node between resistors connected in series between the buffer (BUF) and a base voltage source (GND). The voltage divider node of the voltage divider circuit is connected to the non-inverting input terminal (+) of the first operational amplifier (AMP1). The voltage divider circuit adjusts the non-inverting input voltage by a voltage division ratio of the inverting input voltage of the first operational amplifier (AMP1). The non-inverting input voltage of the first operational amplifier (AMP1) can be ELVDD_FB/2.

A resistor (R) is connected between the output terminal of the first operational amplifier (AMP1) and the inverting input terminal (-). The output voltage (Amp Out) of the first operational amplifier (AMP1) is Amp Out = ΔELVDD = ELVDD_FB - ELVDD_IC. Therefore, the first operational amplifier (AMP1) outputs the difference between the ELVDD input voltage (ELVDD_IC) generated from the power circuit (150) and the ELVDD feedback voltage (ELVDD_FB) fed back from the pixels of the display panel (100).

The buffer (BUF) blocks the current flowing through the resistor of the ELVSS feedback line, thereby supplying ELVDD_FB to the first operational amplifier (AMP1) without additional voltage drop effect of the ELVDD due to this current. The ELVSS feedback line includes the resistor of the third circuit board (62) or the ELVSS wiring (160). The effect of the buffer (BUF) will be described later with reference to FIGS. 14 to 16.

The adder (1200) includes a second operational amplifier (AMP2).

The non-inverting input terminal (+) of the second operational amplifier (AMP2) is connected to the voltage division node of the voltage division circuit. The voltage division circuit connected to the non-inverting input terminal (+) of the second operational amplifier (AMP2) outputs a divided voltage between the output voltage Amp Out = ΔELVDD of the first operational amplifier (AMP1) and the ELVSS input voltage (ELVSS_IC) by using two series-connected resistors (R). The inverting input terminal (-) of the second operational amplifier (AMP2) is connected to the base voltage source (GND) through the resistor (R) and to the output terminal of the second operational amplifier (AMP2) through the resistor (R). The output voltage of the second operational amplifier (AMP2) is a voltage that reflects the ELVSS input voltage (ELVSS_IC) to ΔELVDD.

The ELVSS feedback compensation unit (1300) includes a third operational amplifier.

The inverting input terminal (-) of the third operational amplifier (AMP3) receives a feedback voltage (ELVSS_FB) through the ELVSS input terminal resistor. The non-inverting input terminal (+) of the third operational amplifier (AMP3) receives the output voltage of the second operational amplifier (AMP2). The output voltage of the third operational amplifier (AMP3) is connected to the second power wiring (43) of the pixel array through the ELVSS input terminal resistor, and supplies ELVSS in which ΔELVDD and ΔELVSS are reflected to the second power wiring (43). The third operational amplifier (AMP3) receives ELVSS_FB and the output voltage of the second operational amplifier (AMP2), adds the reverse polarity voltage of the difference to the second operational amplifier (AMP2), and outputs the feedback-compensated ELSS.

Figures 14 to 16 are drawings explaining why a buffer is required in the subtraction section shown in Figure 13.

In the case of the negative feedback amplifier illustrated in Fig. 14, since no current (Ia, Ib) flows through the input terminals, it is not affected by the resistance of the ELVSS feedback line.

If the buffer (BUF) in the subtraction unit (110) is not connected to the voltage divider circuit, as illustrated in FIG. 25, a voltage drop occurs through the resistance of the ELVSS feedback line because of the resistance of the ELVDD feedback line and the current (I_Divide) flowing in the voltage divider circuit. If the voltage drop due to the resistance of the ELVSS feedback line affects the input voltage of the first operational amplifier (AMP1), a voltage fluctuation greater than the voltage drop of the ELVDD within the pixel array affects the input voltage of the first operational amplifier (AMP1), and ΔELVDD cannot be detected in the accurate subtraction unit.

As shown in Fig. 16, when the buffer (BUF) is connected to the voltage divider circuit, the current flowing through the resistor of the feedback line of the ELVDD is blocked, so that the ELVDD feedback voltage (ELVDD_FB), which is a voltage drop within the pixel array, can be accurately detected.

ELVDD can be compensated through an ELVDD feedback compensation unit as shown in Fig. 7.

In another embodiment of the present invention, ELVSS can be applied simultaneously to the upper and lower sides of the display panel (100). The ELVSS applied to the lower side can be set to a lower voltage than the ELVSS applied to the upper side. In this case, the current path of the pixel array becomes the same as in the above-described embodiments, and the voltage gradient of the ELVSS can be adjusted so that the voltage difference between ELVDD and ELVSS is the same throughout the screen (A/A). For example, the upper ELVSS can be applied to the second power line (43) of the nth pixel line (Ln) through the upper ELVSS input terminal resistor, and at the same time, the lower ELVSS lower than the upper ELVSS can be applied to the second power line (43) of the first pixel line (L1) through the lower ELVSS input terminal resistor.

The above-described embodiments may be applied alone or in combination.

Various embodiments of the pixel power compensation circuit of the present invention can be described as follows.

Embodiment 1: A high-potential pixel driving voltage (ELVDD) is applied to the pixels through a first input node located in a first pixel line of a pixel array, and a low-potential power supply voltage (ELVSS) is applied to the pixels through a second input node located in an n-th pixel line (n is a positive integer greater than or equal to 2) farthest from the first pixel line within the pixel array.

Example 2: The pixel power compensation circuit may include a first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from a power circuit is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line, and a first output terminal connected to the first inverting input terminal and connected to the first input node; and a second feedback compensation unit including a second non-inverting input terminal to which a low-potential power voltage generated from the power circuit is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line, and an output terminal connected to the second inverting input terminal and connected to the second input node.

Example 3: Each of the pixel lines may include a first power line to which the high-potential pixel driving voltage is applied, and a second power line to which the low-potential power voltage is applied. The first input node may be connected to the first power line of the pixels. The second input node may be connected to the second power line of the pixels.

Example 4: The low-potential power voltage may be applied to the second power line of the nth pixel line at the same time as the low-potential power voltage is applied to the second power line of the first pixel line. The low-potential power voltage applied to the nth pixel line may be lower than the low-potential voltage applied to the first pixel line.

Various embodiments of the display device of the present invention can be described as follows.

Example 1: A display device includes a display panel having first to nth pixel lines (n is a positive integer greater than or equal to 2) arranged; and a power circuit that generates a high-potential pixel driving voltage (ELVDD) and a low-potential power supply voltage (ELVSS).

The high-potential pixel driving voltage (ELVDD) is input to a first input node located in the first pixel line. The low-potential power supply voltage (ELVSS) is input to a second input node located in the n-th pixel line that is furthest from the first pixel line in the pixel array.

Embodiment 2: The display device may further include a first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from the power circuit is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line, and a first output terminal connected to the first inverting input terminal and connected to the first input node; and a second feedback compensation unit including a second non-inverting input terminal to which a low-potential power voltage generated from the power circuit is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line, and an output terminal connected to the second inverting input terminal and connected to the second input node.

Example 3: The display device may further include a bypass circuit board (62) that connects one side of the display panel near the first pixel line and the other side of the display panel near the nth pixel line outside the display panel.

The second input node may be connected to an output terminal of the second feedback compensation unit through the bypass circuit board.

Example 4: The display panel may further include a gate driver configured to receive a shift clock and sequentially supply gate signals to gate lines connected to the pixel lines; a clock wire arranged along an edge of the display panel to supply the shift clock to the gate driver; and a power wire formed parallel to the clock wire and connected to the second input node to supply the low-potential power voltage (ELVSS) to the second input node.

Example 5: Each of the pixel lines may include a first power line to which the high-potential pixel driving voltage is applied, and a second power line to which the low-potential power voltage is applied. The first input node may be connected to the first power line of the pixels. The second input node may be connected to the second power line of the pixels.

Example 6: The low-potential power voltage may be applied to the second power line of the nth pixel line at the same time as the low-potential power voltage is applied to the second power line of the first pixel line. The low-potential power voltage applied to the nth pixel line may be lower than the low-potential voltage applied to the first pixel line.

Example 7: Each of the pixels of the pixel lines may include a light-emitting element; and a driving element supplying current to the light-emitting element according to a gate-source voltage. The first input node may be connected to a first power line of the pixels. The second input node may be connected to a second power line of the pixels. In each of the pixels, the first power line may be connected to the driving element, and the second power line may be connected to a cathode of the light-emitting element.

Example 8: Each of the pixel lines may include a first power line to which the high-potential pixel driving voltage is applied, and a second power line to which the low-potential power voltage is applied. The first input node may be connected to the first power line of the pixels. The second input node may be connected to the second power line of the pixels.

Example 9: The low-potential power voltage may be applied to the second power line of the nth pixel line at the same time as the low-potential power voltage is applied to the second power line of the first pixel line. The low-potential power voltage applied to the nth pixel line may be lower than the low-potential voltage applied to the first pixel line.

Example 10: The display device includes a display panel having a pixel array in which first to nth (n is a positive integer greater than or equal to 2) pixel lines each including first and second power lines are arranged; a power circuit for generating a high-potential pixel driving voltage (ELVDD) and a low-potential power supply voltage (ELVSS); and a power compensation unit for receiving the high-potential pixel driving voltage, a feedback voltage of the high-potential pixel driving voltage varied by a resistance of the pixel array, the low-potential power supply voltage, and a feedback voltage of the low-potential power supply voltage varied by a resistance of the pixel array, and supplying the compensated high-potential pixel driving voltage and the low-potential power supply voltage to the pixel array.

A high-potential pixel driving voltage output from the power compensation unit is supplied to the pixels of the pixel array through a first input resistor connected to the first power line of the first pixel line. A feedback voltage of the high-potential pixel driving voltage is fed back to the power compensation unit through a first feedback resistor connected to the first power line of the first pixel line. A low-potential power voltage output from the power compensation unit is supplied to the pixels of the pixel array through a second input resistor connected to the second power line of the n-th pixel line which is the farthest from the first pixel line. A feedback voltage of the low-potential power voltage is fed back to the power compensation unit through a second feedback resistor connected to the second power line of the first pixel line.

Example 11: The power compensation unit may include a first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from the power circuit is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line, and a first output terminal connected to the first inverting input terminal and connected to the first input node to supply a high-potential pixel driving voltage compensated for by a feedback voltage of the high-potential pixel driving voltage to a first power line of the pixel lines through the first input terminal resistor.

Example 12: The power compensation unit may further include a second feedback compensation unit including a second non-inverting input terminal to which a low-potential power voltage generated from the power circuit is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line, and an output terminal connected to the second inverting input terminal and connected to the second input node.

Example 13: The power compensation unit may further include a second feedback compensation unit that outputs a low-potential power voltage in which the amount of change (ΔELVDD) of the high-potential pixel driving voltage and the amount of change (ΔELVSS) of the low-potential power voltage are reflected.

Example 14: The second feedback compensation unit may include a subtraction unit that receives a high-potential pixel driving voltage from the power circuit and a feedback voltage of the high-potential pixel driving voltage and detects a variation (ΔELVDD) of the high-potential pixel driving voltage; an adding unit that adds the low-potential power supply voltage to the variation of the high-potential pixel driving voltage; and a feedback compensation unit that receives an output voltage of the adding unit and a feedback voltage of the low-potential power supply voltage and outputs a low-potential power supply voltage that reflects the variation of the high-potential pixel driving voltage.

Example 15: The subtraction unit may include a first operational amplifier including a first inverting input terminal to which a high-potential pixel driving voltage from the power circuit is input, a first non-inverting input terminal to which a feedback voltage of the high-potential pixel driving voltage is input via a buffer and a first voltage divider circuit, and a first output terminal connected to the first inverting input terminal via a first resistor.

The above-described additional unit may include a second operational amplifier including a second inverting input terminal connected to a base voltage source, a second non-inverting input terminal to which an output voltage of the first operational amplifier is input via a second voltage divider circuit, and an output terminal connected to the second inverting input terminal via a second resistor.

The above feedback compensation unit may include a third inverting input terminal into which a feedback voltage of the low-potential power supply voltage is input through the second feedback resistor, a third non-inverting input terminal into which an output voltage of the second operational amplifier is input, and a third operational amplifier that supplies a low-potential power supply voltage in which a change amount (ΔELVDD) of the high-potential pixel driving voltage and a change amount of the low-potential power supply voltage (ΔELVSS) are reflected through the second input terminal resistor to the second power wiring of the pixel lines.

Example 16: The display panel may further include a bypass circuit board (62) that connects one side of the display panel near the first pixel line and the other side of the display panel near the nth pixel line outside the display panel.

The above second input terminal resistor can be connected to the output terminal of the second feedback compensation unit through the bypass circuit board.

Example 17: The display panel may further include a gate driver configured to receive a shift clock and sequentially supply gate signals to gate lines connected to the pixel lines; a clock wire arranged along an edge of the display panel to supply the shift clock to the gate driver; and a power wire formed parallel to the clock wire and connected to the second input terminal resistor to supply the low-potential power voltage (ELVSS) to the second input terminal resistor.

Example 18: The low-potential power voltage may be applied to the second power line of the nth pixel line at the same time as the low-potential power voltage is applied to the second power line of the first pixel line. The low-potential power voltage applied to the nth pixel line may be lower than the low-potential voltage applied to the first pixel line.

Example 19: Each of the pixels of the pixel lines may include a light-emitting element; and a driving element that supplies current to the light-emitting element according to a gate-source voltage.

The first input terminal resistor can be connected to the first power line. The second input terminal resistor can be connected to the second power line.

In each of the above pixels, the first power line may be connected to the driving element, and the second power line may be connected to the cathode of the light-emitting element.

Through the above explanation, those skilled in the art will be able to see that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the patent claims.

21, 102: Data lines 31~33, 103: Gate lines
41, 42, 43: Power line 50: First circuit board
52: ELVDD feedback compensation unit 54: ELVSS feedback compensation unit
60: Second circuit board 62: Third circuit board
100: Display panel 101: Sub pixel (pixel circuit)
110: Data drive unit 112: Demultiplexer
120: Gate driver 130: Timing controller
150 : Power circuit 160 : ELVSS wiring
1100: Subtraction section 1200: Addition section
1300: ELVSS Feedback Reward Unit

Claims (21)

A first feedback compensation unit for applying a compensation high-potential pixel driving voltage to pixels through a first input node located in a first pixel line of a pixel array; and,
A second feedback compensation unit is included that applies a compensation low-potential power supply voltage to the pixels through a second input node located at an n-th pixel line (n is a positive integer greater than or equal to 2) farthest from the first pixel line within the pixel array,
The first feedback compensation unit outputs the compensation high-potential pixel driving voltage by using the first high-potential pixel driving voltage generated from the power circuit and the second high-potential pixel driving voltage detected from the pixels.
The second feedback compensation unit is a pixel power compensation circuit that outputs the compensation low-potential power voltage by using the first low-potential power voltage generated from the power circuit and the second low-potential power voltage detected from the pixels. In the first paragraph,
The first feedback compensation unit includes a first non-inverting input terminal to which the first high-potential pixel driving voltage is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line and to which the second high-potential pixel driving voltage is supplied, and a first output terminal connected to the first inverting input terminal and connected to the first input node.
The second feedback compensation unit includes a second non-inverting input terminal to which the first low-potential power supply voltage is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line and to which the second low-potential power supply voltage is supplied, and an output terminal connected to the second inverting input terminal and connected to the second input node.
Each of the first and nth pixel lines includes a first power line to which the compensation high-potential pixel driving voltage is applied and a second power line to which the compensation low-potential power voltage is applied,
The first input node is connected to the first power line of the pixels,
The second input node is a pixel power compensation circuit connected to the second power line of the pixels. In the first paragraph,
At the same time that the compensation low-potential power voltage is applied to the second power line of the nth pixel line, the compensation low-potential power voltage is applied to the second power line of the first pixel line,
A pixel power compensation circuit in which a compensation low-potential power voltage applied to the nth pixel line is lower than a compensation low-potential voltage applied to the first pixel line. A display panel including a pixel array in which first to nth (n is a positive integer greater than or equal to 2) pixel lines are arranged;
Power circuit that generates high-potential pixel drive voltage and low-potential power supply voltage:
A first feedback compensation unit that applies a compensation high-potential pixel driving voltage to pixels through a first input node located in the first pixel line; and
A second feedback compensation unit is included that applies a compensation low-potential power supply voltage to the pixels through a second input node located in the n-th pixel line that is furthest from the first pixel line within the pixel array,
The first feedback compensation unit outputs the compensation high-potential pixel driving voltage by using the first high-potential pixel driving voltage generated from the power circuit and the second high-potential pixel driving voltage detected from the pixels.
A display device in which the second feedback compensation unit outputs the compensation low-potential power voltage by using the first low-potential power voltage generated from the power circuit and the second low-potential power voltage detected from the pixels. In paragraph 4,
The first feedback compensation unit includes a first non-inverting input terminal to which the first high-potential pixel driving voltage is supplied, a first inverting input terminal connected to a first feedback node located in the first pixel line and to which the second high-potential pixel driving voltage is supplied, and a first output terminal connected to the first inverting input terminal and connected to the first input node.
The second feedback compensation unit includes a second non-inverting input terminal to which the first low-potential power supply voltage is supplied, a second inverting input terminal connected to a second feedback node located in the first pixel line and to which the second low-potential power supply voltage is supplied, and an output terminal connected to the second inverting input terminal and connected to the second input node.
Further comprising a bypass circuit board connecting one side of the display panel near the first pixel line and the other side of the display panel near the nth pixel line outside the display panel,
A display device in which the second input node is connected to the output terminal of the second feedback compensation unit through the bypass circuit board. In paragraph 5,
The above display panel,
A gate driver that receives a shift clock and sequentially supplies gate signals to gate lines connected to the first and nth pixel lines;
Clock wiring arranged along the edge of the display panel to supply the shift clock to the gate driver; and
A display device further comprising a power wiring formed parallel to the clock wiring and connected to the second input node to supply the compensation low-potential power voltage to the second input node. In paragraph 4,
Each of the first and nth pixel lines includes a first power line to which the compensation high-potential pixel driving voltage is applied and a second power line to which the compensation low-potential power voltage is applied,
The first input node is connected to the first power line of the pixels,
The second input node is connected to the second power line of the pixels,
At the same time that the compensation low-potential power voltage is applied to the second power line of the nth pixel line, the compensation low-potential power voltage is applied to the second power line of the first pixel line,
A display device in which a compensation low-potential power supply voltage applied to the nth pixel line is lower than a compensation low-potential voltage applied to the first pixel line. In paragraph 7,
Each of the pixels of the first and nth pixel lines
light emitting element; and
It includes a driving element that supplies current to the light-emitting element according to the gate-source voltage,
The first input node is connected to the first power line of the pixels,
The second input node is connected to the second power line of the pixels,
In each of the above pixels,
The above first power line is connected to the driving element,
A display device in which the second power line is connected to the cathode of the light-emitting element. A display panel having a pixel array in which first to nth (n is a positive integer greater than or equal to 2) pixel lines each including first and second power lines are arranged;
A power circuit that generates a high-potential pixel driving voltage and a low-potential power supply voltage; and
A power compensation unit is included that receives the high-potential pixel driving voltage, the feedback voltage of the high-potential pixel driving voltage varied by the resistance of the pixel array, the low-potential power supply voltage, and the feedback voltage of the low-potential power supply voltage varied by the resistance of the pixel array, and compensates for the high-potential pixel driving voltage and the low-potential power supply voltage to supply the same to the pixel array.
A high-potential pixel driving voltage output from the power compensation unit is supplied to the pixels of the pixel array through a first input terminal resistor connected to the first power line of the first pixel line,
The feedback voltage of the high-potential pixel driving voltage is fed back to the power compensation unit through the first feedback resistor connected to the first power line of the first pixel line,
A low-potential power voltage output from the power compensation unit is supplied to the pixels of the pixel array through a second input terminal resistor connected to the second power line of the nth pixel line furthest from the first pixel line,
A display device in which the feedback voltage of the low-potential power supply voltage is fed back to the power compensation unit through a second feedback resistor connected to the second power line of the first pixel line. In Article 9,
The above power compensation unit,
A first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from the power circuit is supplied, a first inverting input terminal connected to the first feedback resistor, and a first output terminal connected to the first inverting input terminal and connected to the first input terminal resistor to supply a high-potential pixel driving voltage compensated for by the feedback voltage of the high-potential pixel driving voltage to the first power line of the first and nth pixel lines; and
A display device including a second feedback compensation unit including a second non-inverting input terminal to which a low-potential power voltage generated from the power circuit is supplied, a second inverting input terminal connected to the second feedback resistor, and an output terminal connected to the second inverting input terminal and connected to the second input resistor. In Article 9,
The above power compensation unit,
A first feedback compensation unit including a first non-inverting input terminal to which a high-potential pixel driving voltage generated from the power circuit is supplied, a first inverting input terminal connected to the first feedback resistor, and a first output terminal connected to the first inverting input terminal and connected to the first input terminal resistor to supply a high-potential pixel driving voltage compensated for by the feedback voltage of the high-potential pixel driving voltage to the first power line of the first and nth pixel lines; and
A display device including a second feedback compensation unit that outputs a low-potential power supply voltage in which the amount of change in the high-potential pixel driving voltage and the amount of change in the low-potential power supply voltage are reflected. In Article 11,
The second feedback compensation unit is,
A subtraction unit that receives a high-potential pixel driving voltage from the power circuit and a feedback voltage of the high-potential pixel driving voltage and detects a change in the high-potential pixel driving voltage;
An adding unit that adds the low-potential power supply voltage to the amount of change in the high-potential pixel driving voltage; and
A display device including a feedback compensation unit that receives the output voltage of the above-described adding unit and the feedback voltage of the low-potential power supply voltage and outputs a low-potential power supply voltage that reflects the amount of change in the high-potential pixel driving voltage. In Article 12,
The above reduction part is,
A first operational amplifier including a first inverting input terminal to which a high-potential pixel driving voltage from the power circuit is input, a first non-inverting input terminal to which a feedback voltage of the high-potential pixel driving voltage is input through a buffer and a first voltage divider circuit, and a first output terminal connected to the first inverting input terminal through a first resistor,
The above additional portion is,
A second operational amplifier including a second inverting input terminal connected to a base voltage source, a second non-inverting input terminal to which an output voltage of the first operational amplifier is input through a second voltage divider circuit, and an output terminal connected to the second inverting input terminal through a second resistor,
The above feedback compensation section is,
A display device including a third inverting input terminal into which a feedback voltage of the low-potential power supply voltage is input through the second feedback resistor, a third non-inverting input terminal into which an output voltage of the second operational amplifier is input, and a third operational amplifier that supplies a low-potential power supply voltage in which a change in the high-potential pixel driving voltage and a change in the low-potential power supply voltage are reflected through the second input terminal resistor to the second power wiring of the first and nth pixel lines. In clause 10 or 11,
Further comprising a bypass circuit board connecting one side of the display panel near the first pixel line and the other side of the display panel near the nth pixel line outside the display panel,
A display device in which the second input terminal resistor is connected to the output terminal of the second feedback compensation unit through the bypass circuit board. In clause 10 or 11,
The above display panel,
A gate driver that receives a shift clock and sequentially supplies gate signals to gate lines connected to the first and nth pixel lines;
Clock wiring arranged along the edge of the display panel to supply the shift clock to the gate driver; and
A display device further comprising a power wiring formed parallel to the clock wiring and connected to the second input terminal resistor to supply the low-potential power voltage to the second input terminal resistor. delete delete delete delete delete delete