KR102704795B1 - Naf memory device combining nand flash memory and flip-flop and operation method thereof - Google Patents

Abstract

The present invention relates to an NAF memory device combining a NAND flash memory and a flip-flop, and an operating method thereof. By configuring an NAF memory that fuses a flip-flop to a NAND memory string, unlike the existing von Neumann structure, data of a register configured with a flip-flop can be directly loaded into a non-volatile memory through a transmission unit without going through a separate input/output processor and data bus, and vice versa. Therefore, it is possible to eliminate the bottleneck phenomenon of the existing structure and to increase the data transmission efficiency.

Description

NAF MEMORY DEVICE COMBINING NAND FLASH MEMORY AND FLIP-FLOP AND OPERATION METHOD THEREOF

The present invention relates to a memory device for efficiently transmitting data between units in a computing system, and more specifically, to an NAF memory device combining a NAND flash memory and a flip-flop, and an operating method thereof.

In computing systems, the existing computer architecture follows the von Neumann architecture in which processing units and memory units are separated.

The processing unit, represented by the CPU (central processing unit), is responsible for performing logic operations and transmitting commands to retrieve data from memory, and stores intermediate and result values of these functions in registers.

In the memory unit, the values of these registers are selectively stored in a cache memory device such as SRAM (static random-access memory), a main memory device such as DRAM (dynamic random access memory), or a non-volatile memory device such as an HDD (hard disk drive) or SSD (solid-state drive).

Data transfer between these processing units and memory units or between memory units utilizes a data bus and an I/O processor.

Figure 1 shows the data flow in the computing system of the existing von Neumann structure described above. The data flow in the existing computing system causes a bottleneck phenomenon that causes a problem of overall system performance limitation due to the difference in the fast operation speed of the processing unit and the slow operation speed of the memory unit. In addition, the data transmission speed is limited according to the bandwidth of the system due to the characteristics of the transmission system through the data bus in the data transmission between the processing unit and the memory unit or between the memory units. In particular, when transmitting a large amount of data, the data is transmitted by dividing it into certain units, which increases inefficiency in terms of speed and power. In order to improve this, a memory structure is required to efficiently transmit data between each unit.

Korean Patent Registration No. 10-2154352 (2020.09.10)

Accordingly, the present invention proposes a NAF memory ( NA ND flash memory + F lip-flop) that integrates a flip-flop constituting a register and a highly integrated and non-volatile NAND flash memory array for efficient data transmission. Specifically, the present invention provides a NAF memory device that combines a NAND flash memory and a flip-flop, which can store data of a register directly in a non-volatile memory without going through a separate input/output processor and data bus by fusing a NAND flash memory array to individual flip-flop outputs, and conversely, can directly load data of a non-volatile memory into a register, and an operating method thereof.

In order to achieve the above object, the NAF memory device according to the present invention is characterized by comprising: a nonvolatile memory device including a NAND memory string; a flip-flop connected to the NAND memory string; and a transmission unit inserted between the NAND memory string and the flip-flop so as to transmit and receive data between them.

The above transmission unit may be composed of a plurality of transistors connected between one contact of the NAND memory string and an output terminal or an inverting output terminal of the flip-flop.

The above contact point is a reference node to which a cell element of the NAND memory string and a ground selection transistor are connected, and the plurality of transistors may include an FNT transistor connected between the reference node and an output terminal of the flip-flop and switched by an FNE control signal, a first NFT transistor and a second NFT transistor connected in series between ground and an inverting output terminal of the flip-flop and switched by a voltage of the reference node and an NFE control signal, respectively.

The plurality of transistors may further include a third NFT transistor connected between the reference node and the gate of the first NFT transistor and opened and closed by the NFE control signal.

In another embodiment, the contact point may be a reference node to which a cell element of the NAND memory string and a ground selection transistor are connected, and the plurality of transistors may include an FNT transistor connected between the reference node and an output terminal of the flip-flop and switched by an FNE control signal, a first NFT transistor and a second NFT transistor connected in series between a V _DD supply voltage and the output terminal of the flip-flop and switched by a voltage of the reference node and an NFE control signal, respectively.

The operating method of the NAF memory device according to the present invention is an NFT (NAND to Flip-flop Transfer) mode operating method using the above-described NAF memory device, comprising: a step of: turning on the first NFT transistor and the second NFT transistor while the FNT transistor is turned off, and transferring data stored in the NAND memory string to the output terminal of the flip-flop, while turning on the ground select transistor while the voltage of the output terminal of the flip-flop is 0 V, to initialize the voltage of the reference node to 0 V; a step of stopping the CP (clock pulse) of the flip-flop, turning off the ground select transistor while the voltage of the output terminal is 0 V, and applying voltages for a read operation to the NAND memory string so that the voltage of the reference node is determined according to the memory state of a specific cell element to be read; a step of turning on the second NFT transistor with the NFE control signal to transfer data stored in the specific cell element to the output terminal of the flip-flop; And it is characterized in that it sequentially proceeds including the step of turning off the second NFT transistor with the NFE control signal.

The operating method of the NAF memory device according to the present invention is an FNT (Flip-flop to NAND Transfer) mode operating method using the above-described NAF memory device, characterized in that it sequentially includes the steps of: turning on the FNT transistor while the second NFT transistor is turned off and transferring output terminal data of the flip-flop to the NAND memory string, while erasing and initializing the memory state of at least a specific cell element to be written in the NAND memory string; turning on the FNT transistor with the FNE control signal while stopping the CP of the flip-flop to maintain the voltage of the output terminal and applying voltages for a write operation to the NAND memory string so that the data of the output terminal is stored in the specific cell element; and turning off the FNT transistor with the FNE control signal.

The present invention configures a NAF memory that combines a flip-flop with a NAND memory string, so that, unlike the existing von Neumann structure, data of a register configured with a flip-flop can be directly loaded into a non-volatile memory through a transmission unit without going through a separate input/output processor and data bus, and vice versa, data stored in a non-volatile memory can be directly loaded into a register, thereby eliminating the bottleneck phenomenon of the existing structure and increasing the data transmission efficiency.

Figure 1 is a block diagram showing the flow of data between registers in a CPU (central processing unit) and non-volatile memory devices (cache, main memory, HDD, SSD) through a data bus in a conventional computing system.
FIG. 2 is a block diagram showing data flow in a register structure within a CPU utilizing a NAF memory device according to one embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of a NAF memory device according to one embodiment of the present invention.
FIG. 4 is a circuit diagram showing an internal structure according to one embodiment of FIG. 3.
FIG. 5 is a circuit diagram showing a specific embodiment of the NAND memory string of FIG. 4.
Figure 6 is a graph showing the definition of memory state and the distribution of threshold voltage ( V _TH ) according to state depending on whether charge is injected into the cell elements of the NAND memory string of Figure 4.
Figure 7 is a circuit diagram showing an overview of the NFT mode operation in Figure 4.
Figure 8 is an operation timing diagram for each unit in the NFT mode in Figure 7.
Figure 9 is a circuit diagram showing an overview of the FNT mode operation in Figure 4.
Figure 10 is an operation timing diagram for each unit in the FNT mode in Figure 9.
Figure 11 shows a 4-bit register utilizing the NAF memory of Figure 4.
Figure 12 shows a 4-bit shift register utilizing the NAF memory of Figure 4.
Figure 13 shows a 4-bit general-purpose shift register utilizing the NAF memory of Figure 4.
Fig. 14 is a circuit diagram showing an internal structure according to another embodiment of Fig. 3.
Fig. 15 is a circuit diagram showing an internal structure according to another embodiment of Fig. 3.
Figure 16 shows a 4-bit register utilizing the NAF memory of Figure 15.
Figure 17 shows a 4-bit shift register utilizing the NAF memory of Figure 15.
Figure 18 shows a 4-bit general-purpose shift register utilizing the NAF memory of Figure 15.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

Referring to FIG. 2, the NAF memory device according to one embodiment of the present invention is configured to include a NAF memory ( NA ND flash memory + F lip-flop) that integrates a flip-flop constituting a register and a highly integrated and nonvolatile NAND flash memory array. By doing so, data of the register can be directly stored in the nonvolatile memory without going through a separate input/output processor and data bus within the CPU, and data of the nonvolatile memory can be directly loaded into the register. Such data transfer can be performed by a transfer unit having a simple structure as described below. The advantage of this embodiment is that data of the register can be stored in the nonvolatile memory in parallel through individual operations of the NAF memory, thereby increasing the efficiency of data transfer. In addition, it can be utilized to efficiently execute flip-flop and register data backup in a power gating technique (cutting off the power of the circuit during standby time) to reduce recent leakage power. Hereinafter, the structure and operation method of the specific NAF memory device of the present invention will be described.

Referring to FIGS. 3 and 4, an NAF memory device according to one embodiment of the present invention comprises: a nonvolatile memory device including a NAND memory string (10); a flip-flop (30) connected to the NAND memory string; and a transmission unit (20) inserted between the NAND memory string (10) and the flip-flop (30) so as to transmit and receive data between them.

Here, the nonvolatile memory device may be configured to include a NAND flash memory, and the NAND flash memory has a structure in which a string of NAND flash string units (10) (hereinafter referred to as 'NAND memory strings') is connected to the output of a flip-flop (30) via a transmission unit (20), as shown in FIGS. 3 and 4. The number of flash memory cells (hereinafter referred to as 'cell elements') of the NAND memory string may be 1 or plural (NV1, NV2, ..., NVn; 14) as shown in FIG. 4.

The form of the cell element (14) can be any form of flash memory such as floating-gate memory, CTF (charge-trap memory), and e-flash memory (embedded flash memory). Among them, e-flash memory that is compatible with the CMOS (complementary metal-oxide-semiconductor) logic process used in flip-flop and CPU manufacturing may be the most preferable. Fig. 5 shows that the cell element (14) can be implemented with two forms of e-flash memory. In the case of a 2Tr e-flash NAND cell (14a), the operating voltage (program voltage, V _PP or erase voltage or read voltage, V _read ) of the WL (word line) is applied to the CC (coupling capacitor) to couple the operating voltage to the FG (floating gate) so that charges are injected or removed from the FG to determine the cell memory state or read the memory state. For example, as shown in Fig. 6, a state in which a charge is injected and the threshold voltage ( V _TH ) of the cell element is increased can be defined as '0', and a state in which a charge is removed and the threshold voltage is decreased can be defined as '1'. In the case of a 3Tr e-flash NAND cell (14b), in addition to the CC, an EC (erase capacitor) is configured in parallel with the CC to remove the charge of the FG. It is preferable that the size of the CC be structured to be approximately 8 times larger than that of the EC so that the FG is coupled only by the CC, and the EC only performs the role of removing the charge. Through this structure, a lower operating voltage can be achieved compared to the former 2Tr e-flash NAND cell structure. In addition, the e-flash memory that can be used in the present invention may include all e-flash forms such as a 1.5Tr structure.

The above flip-flop (30) is illustrated as a rising edge trigger D-flip-flop in Fig. 4, but is not limited thereto and is generally composed of a plurality of gates (AND, NOR, NAND gates, etc.) and a feed back circuit, and is configured to output a Q output terminal and an inverted output terminal (Q bar,) according to the rising edge or falling edge of the CP (clock pulse). ) Any register that is configured as a 1-bit memory element with a stable output is included in this.

The above transmission unit (20) is connected to one contact (18) of the NAND memory string (10) and the output terminal (Q, 36) or inverting output terminal ( , 38) can be composed of multiple transistors connected between them.

As a specific embodiment of the above transmission unit (20), referring to FIG. 4, FIG. 7 and FIG. 9, the contact point (18) is a reference node (Node G) to which the cell element (14) of the NAND memory string (10) and the ground selection transistor (16) are connected, and the plurality of transistors may be configured to include an FNT transistor (22) connected between the reference node (18) and the output terminal (36) of the flip-flop (30) and opened and closed by an FNE control signal, a first NFT transistor (24) and a second NFT transistor (26) connected in series between the ground and the inverting output terminal (38) of the flip-flop (30) and opened and closed by the voltage ( V _{Node G} ) of the reference node (18) and an NFE control signal, respectively.

The operation of the NAF memory device configured as above is divided into the following three modes. There are three modes: NFT (NAND to Flip-flop Transfer) in which data is transferred from a NAND memory string (10) to a flip-flop (30); FNT (Flip-flop to NAND Transfer) in which data is transferred from a flip-flop (30) to a NAND memory string (10); and FNT mode in which the connection between the NAND memory string (10) and the flip-flop (30) is disconnected and the flip-flop (30) operates independently. The NFT mode is similar to the read operation of a NAND flash, and the FNT mode is similar to the write operation of a NAND flash. The NAF memory device of the present invention normally operates as an independent flip-flop (30) and functions as a register, and when data transfer to the non-volatile memory of the NAND memory string (10) is required or, conversely, when data is loaded from the non-volatile memory of the NAND memory string (10), it operates in the FNT and NFT modes, respectively. Below, the operation method of the NAF memory device described above will be examined.

First, referring to FIGS. 7 and 8, a method of operating in NFT (NAND to Flip-flop Transfer) mode is described.

The NFT mode operation of the NAF memory device is basically performed by turning on the first NFT transistor (24) and the second NFT transistor (26) while the FNT transistor (22) is turned off, and transmitting data stored in the NAND memory string (10) to the output terminal (36) of the flip-flop (30).

This is, with reference to FIG. 8, a step (T 1 ~T 2) of turning on the ground selection transistor (16) while the voltage ( V _{Node Q} ) of the output terminal (36) of the flip-flop ( ₃₀ ) is 0 V to initialize the voltage ( V _{Node G} ) of the reference node ( ₁₈ ) to 0 V; stopping the CP (clock pulse) of the flip-flop (30) to turn off the ground selection transistor (16) while the voltage ( V _{Node Q} ) of the output terminal (36) is 0 V and applying voltages for a read operation to the remaining NAND memory strings (10), for example, a bit line (BL _flash ) is V _DD , The method may be sequentially performed, including: a _step (T ₂ to T 3) of determining the voltage (V Node G ) of the reference node (18) according to the memory state (Flash State: '1'/ ' 0') of the selected specific cell element (e.g., NV2) to be read by applying V _DD to the string select transistor (12), V pass to the non-selected cell elements (NV1, NVn), and V read to the selected cell element (NV2); a step (T ₃ to _{T 4} ) of turning on the second NFT transistor (26) with the NFE control signal (e.g., V _DD ) to transfer data stored in the specific cell element (NV2) to the output terminal ( ₃₆ ) of the flip-flop (30); and a step (T ₄ to T ₅ ) of turning off the second NFT transistor ( ₂₆ ) with the NFE control signal (e.g., 0 V).

By doing this, data stored in a specific cell element (NV2) of the NAND memory string (10) can be transmitted to the output terminal (36) of the flip-flop (30).

To explain the NFT mode operation of the above NAF memory device in more detail, the NFT mode is an operation to transfer data stored in a specific cell element (NV2) of the NAND memory string (10) to a flip-flop (30) and output it. As shown in FIG. 7, the NFT operation is performed as a NAND flash read operation in the NAND memory string (10). The voltage ( V _{Node G} ) of the reference node (18) changes according to the V _TH of the selected cell element (NV2), so that the data of the NAND memory string (10) is input to the output terminal (36) of the flip-flop (30) through the transmission unit (20). The detailed operation of the operation can be explained in detail through the timing diagram of FIG. 8. The input of the NAF memory device performing the initial independent flip-flop operation is initialized by applying 0 V (T ₁ to T ₂ ). The voltage ( V _{Node G} ) of the reference node (18) at this moment is initialized to 0 V. Thereafter, the CP is stopped and a read operation is performed on the NAND memory string (10) to determine the voltage ( V _{Node G} ) of the reference node (18) according to the memory state of the selected cell element (NV2). In the case of the read operation, V _read is applied to the selected cell element (NV2) and V _pass is applied to the WL of the unselected cell elements (NV1, NVn). V DD (~1 V, the voltage value may vary depending on the situation, such as the applicable system and application field) is applied to the bit line (BL flash) of the NAND memory string (10), and V _{SS (} approximately ₀ V) is input to the gate line (GSL) of the ground select transistor (16) connected to the ground, and the V _DD signal is input to the gate line (SSL) of the string select transistor (12) connected to the bit line (BL) to turn on the string select transistor (12). When the memory state of the selected cell element (NV2) is '1', the voltage ( V _{Node G} ) of the reference node (18) can be increased to V _DD - V _TH through a read operation, and at this time, the first NFT transistor (24) of the transmission unit (20) is turned on. On the other hand, when the memory state is '0', the voltage ( V _{Node G} ) of the reference node (18) is maintained at 0 V, and the first NFT transistor (24) is maintained in the off state (T ₂ to T ₃ ). Thereafter, V _DD is applied to the gate control signal (NFE) of the second NFT transistor (26) connected in series to the first NFT transistor (24), thereby causing the transmission unit (20) to operate. At this time, if the first NFT transistor (24) is on and in the '1' state, a ground signal is applied to the inverting output terminal (38) of the flip-flop (30), so that the output terminal (36) of the flip-flop (30) outputs a 'High' signal corresponding to V _DD , and if the first NFT transistor (24) is off and in the '0' state, no signal is applied to the flip-flop (30), so that it is maintained in the initial 0 V state (T ₃ to T ₄ ). After the value of the output terminal (36) of the flip-flop (30) changes according to the memory state, the signals of the transmission unit (20) and the NAND memory string (10) are blocked to prepare for independent operation of the flip-flop (30). At this time, the ground selection transistor (16) connected to the ground of the NAND memory string (10) is turned on with the GSL signal ( V _DD ) to initialize the reference node (18) as well and turn the first NFT transistor (24) off (T ₄ ~T ₅ ). When all the transmission units (20) are turned off and initialized, the CP is applied to the flip-flop (30) again to perform an independent flip-flop operation and the NFT mode operation ends.

Next, referring to FIGS. 9 and 10, a method of operating in FNT (Flip-flop to NAND Transfer) mode is described.

The above second NFT transistor (26) is turned off and the FNT transistor (22) is turned on to transmit data from the output terminal (36) of the flip-flop (30) to the NAND memory string (10).

This includes, with reference to FIG. 10, a step (T ₁ to T ₂ ) of erasing and initializing the memory state of at least a specific cell element (NV2) to be written in the NAND memory string (10); a step (T 2 to T 4) of stopping the CP of the flip-flop (30) to maintain the voltage of the output terminal (36) and turning on the FNT transistor (22) with the FNE control signal ( V _DD ) and applying voltages for a write operation to the NAND memory string (10), for example, applying V _SS to a bit line (BL _flash ) to be floated or turned off, V _SS to a string select transistor (12), V _pass to non-selected cell elements (NV1, _NVn ), and V _PP to a selected cell element (NV2), so that data of the output terminal (36) is stored in the specific cell element ( _NV2 ); And it can be implemented by sequentially proceeding with a step (T ₄ to T ₅ ) of turning off the FNT transistor (22) with the FNE control signal (0 V).

By doing this, the output terminal (36) data of the flip-flop (30) can be transferred to a specific cell element (NV2) of the NAND memory string (10) and stored therein.

To explain the FNT mode operation of the above NAF memory device in more detail, the FNT mode is an operation of transferring and storing data of an output terminal (36) output from a flip-flop (30) to a specific cell element (NV2) of a NAND memory string (10). As shown in FIG. 9, the channel voltage ( V _channel ) of the NAND memory string (10) is determined by the output of the flip-flop (30). The V _channel is self-boosted (when the output of the flip-flop is 'High') or becomes V _SS (approximately 0 V, when the output of the flip-flop is 'Low'). The voltage state of the V _channel suppresses or generates the FN program when V _PP (~ 20 V) is applied to the gate of the selected cell element (NV2). Through this operation, the output state of the flip-flop (30) can be stored in the selected cell element (NV2). The detailed operating principle can be explained through the timing diagram shown in FIG. 10. In the initial operation, the output of the flip-flop outputs the value to be stored in the NAND memory string (10) (T ₁ to T ₂ ). Thereafter, V _DD is applied to the gate control signal (FNE) of the FNT transistor (22) of the transmission unit (20) to turn it on, and V _pass is input to the WL of all the cell elements of the NAND memory string (10) so that the entire V _channel is set to the signal of the flip-flop output terminal (36). At this time, CP is stopped to maintain the output of the flip-flop (30). In addition, in order to connect the channel only to the output of the flip-flop (30), V _SS is applied to SSL and GSL to turn off the string selection transistor (12) and the ground selection transistor (16) (T2 to T3). Thereafter, V _PP is applied to the WL of the selected cell element (NV2) to perform the FN program operation. If the V _channel value is self-boosted by the output of the flip-flop (30), the difference between the gate voltage and the channel voltage of the selected cell element (NV2) is not large, so the FN program is 'inhibited' and the initial state '1' is maintained. On the contrary, if the V _channel value is fixed to V _SS by the output of the flip-flop (30), the difference between the gate voltage and the channel voltage of the selected cell element (NV2) is large, so the FN program occurs and the state is 'programmed' as '0'. A summary of the operation is as shown in Table 1 below ( V _channel and selected cell element state according to flip-flop output in FNT mode) (T ₃ to T ₄ ). After the output value of the flip-flop (30) is transmitted to the selected cell element (NV2), all transmission units (20) are turned off and then V _DD is input to the GSL to initialize the V _channel to the ground state (T4 to T5). After that, all signals of the NAND memory string (10) are turned off and CP is re-applied to return to independent flip-flop operation and finish the FNT operation (after T ₅ ).

We present a method for utilizing the NAF memory device described above in widely used registers. The utilization methods presented below are only partial examples and can be utilized in all registers that can be configured with flip-flops.

(1) 4-bit register

A schematic diagram utilizing an NAF memory device in the simplest 4-bit register consisting of only D flip-flops is shown in Fig. 11. This register can input and store input data ( I _A , I _B , I _C , I _D ) at the rising edge of CP, and output data at the outputs ( O _A , O _B , O _C , O _D ). By utilizing the FNT mode of the NAF memory, data input in parallel to each flip-flop can be stored separately, and by utilizing the NFT mode, data stored in the NAF memory device can be individually output.

(2) 4-bit shift register

A schematic diagram utilizing a NAF memory device in a 4-bit shift register constructed using D flip-flops is shown in Fig. 12. Whenever CP is input, the input data is shifted to the right by one bit and stored ( I → Q _A , Q _A → Q _B , Q _B → Q _C , Q _C → Q _D ). During the shifting process, data can be stored in a NAND memory string using the FNT mode, and conversely, data stored in an ND memory string can be input to the flip-flop individually or in parallel using the NFT mode, and serial output can be achieved through the shift register.

(3) 4-bit universal shift register

A schematic diagram of a 4-bit general-purpose shift register using a D flip-flop and utilizing an NAF memory device is shown in Fig. 13. The 4-bit general-purpose shift register can shift serial input data in both directions and output the shifted data in parallel. Conversely, data input in parallel can be shifted serially and output in parallel. This operation enables a shift operation or a parallel operation by changing the input of each flip-flop according to the control signal (S ₁ , S ₀ ) of a multiplexer (MUX). The operation is shown in detail in Table 2 (Control Table of a 4-bit General-Purpose Shift Register) below. Utilizing an NAF memory device in the general-purpose shift register enables not only data storage during the shift process in FNT mode but also parallel input data to be stored in a NAND memory string. In addition, data stored in a NAND memory string can be shifted in NFT mode as well as parallel output.

As examples utilizing the NAF memory device of the present invention above, a 4-bit register, a 4-bit shift register, and a 4-bit general-purpose shift register have been described, but it is obvious that the present invention is not limited to 4 bits and can be configured with any N-bit register, N-bit shift register, and N-bit general-purpose shift register (N is a natural number greater than or equal to 2), respectively.

According to an embodiment of the present invention, as shown in FIG. 14, the transmission unit (20') of the NAF memory device of the present invention may be provided with a third NFT transistor (28) further connected between the reference node (18) and the gate of the first NFT transistor (24) in the embodiment of FIG. 4 described above so as to be opened and closed by an NFE control signal together with the second NFT transistor (26). By doing so, in the embodiment of FIG. 4, when the Q value of the output terminal (36) of the flip-flop (30) is 1 during the FNE operation and the NAND memory string (10) is self-boosted, the problem that the NAND memory string (10) has difficulty in increasing to the self-boosting voltage when the gate capacitor of the first NFT transistor (24) is much larger than the capacitor of the NAND memory string (10) can be solved. That is, in the present embodiment, a third NFT transistor (28) is added to the transmission unit (20') to suppress self-boosting interference of the NAND memory string (10) caused by the gate capacitor of the first NFT transistor (24). The third NFT transistor (28) exists between the gate of the first NFT transistor (24) and the NAND memory string (10), and the opening and closing of the third NFT transistor (28) is determined by the NFE control signal. In the FNT mode, the NFE control signal is applied as a signal to turn off the second NFT transistor (26) and the third NFT transistor (28), so that the gate capacitor of the first NFT transistor (24) can be viewed as being open with respect to the NAND memory string (10). Thus, regardless of the gate capacitance of the first NFT transistor (24), interference of self-boosting is prevented, thereby enabling smooth FNT mode operation.

Referring to FIG. 15, in another embodiment of the NAF memory device according to the present invention, the contact (18) may be configured to include a reference node to which the cell element (14) of the NAND memory string (10) and the ground selection transistor (16) are connected, as in the above-described embodiment, but a plurality of transistors forming the transmission unit (20") may be configured to include an FNT transistor (22) connected between the reference node (18) and the output terminal (36) of the flip-flop (30) and switched by the FNE control signal, a first NFT transistor (24) and a second NFT transistor (26) connected in series between the V _DD supply voltage (21) and the output terminal (36) of the flip-flop and switched by the voltage of the reference node (18) and the NFE control signal, respectively. By doing so, in the embodiment of FIG. 4, in the NFT mode, the data of the NAND memory string (10) is transmitted as inverted data to the inverted output terminal (38) of the flip-flop through the ground connected to the first NFT transistor (24). As the input is made, the output of the output terminal (36) of the flip-flop matches the data of the NAND memory string (10). In this embodiment, the V _DD supply voltage (21) is connected to the first NFT transistor (24) so that the data of the NAND memory string (10) is input directly to the output terminal (36) of the flip-flop without inversion. According to this embodiment, there is an advantage of being able to simplify the structure and operation by using a flip-flop without an inversion output, but a delay time may occur in pulling up the output Q of the flip-flop to V _DD due to the voltage drop that occurs in the first NFT transistor (24). Since FIGS. 16 to 18 are embodiments of registers utilizing the NAF memory device presented above, there is a difference in that only the output Q of the flip-flop is used in FIGS. 11 to 13, and therefore, a repeated explanation is omitted.

10: NAND memory string 12: String select transistor
14: Cell element 16: Ground select transistor
18: Reference node 20: Transmission unit
21: V _DD supply voltage 22: FNT transistor
24: 1st NFT transistor 26: 2nd NFT transistor
28: 3rd NFT transistor 30: Flip-flop
32: Data input terminal 34: CP input terminal
36: Output terminal 38: Inverting output terminal

Claims (10)

A nonvolatile memory device containing a NAND memory string;
a flip-flop connected to the above NAND memory string; and
A NAF memory device characterized by comprising a transmission unit inserted between the NAND memory string and the flip-flop so as to be able to transmit and receive data between them.
In paragraph 1,
An NAF memory device, wherein the transmission unit comprises a plurality of transistors connected between one contact of the NAND memory string and an output terminal or an inverting output terminal of the flip-flop.
In the second paragraph,
The above contact point is a reference node to which the cell element of the NAND memory string and the ground selection transistor are connected,
An NAF memory device characterized in that the plurality of transistors include an FNT transistor connected between the reference node and an output terminal of the flip-flop and switched by an FNE control signal, a first NFT transistor and a second NFT transistor connected in series between ground and an inverting output terminal of the flip-flop and switched by a voltage of the reference node and an NFE control signal, respectively.
In the third paragraph,
An NAF memory device characterized in that the plurality of transistors further includes a third NFT transistor connected between the reference node and the gate of the first NFT transistor and opened and closed by the NFE control signal.
In the second paragraph,
The above contact point is a reference node to which the cell element of the NAND memory string and the ground selection transistor are connected,
An NAF memory device characterized in that the plurality of transistors include an FNT transistor connected between the reference node and the output terminal of the flip-flop and switched by an FNE control signal, a first NFT transistor and a second NFT transistor connected in series between the V _DD supply voltage and the output terminal of the flip-flop and switched by the voltage of the reference node and an NFE control signal, respectively.
In the operating method of the NAF memory device according to Article 3,
The FNT transistor is turned off, and the first NFT transistor and the second NFT transistor are turned on to transmit data stored in the NAND memory string to the output terminal of the flip-flop.
A step of turning on the ground selection transistor while the voltage of the output terminal of the flip-flop is 0 V to initialize the voltage of the reference node to 0 V;
A step of stopping the CP (clock pulse) of the flip-flop, turning off the ground selection transistor while the voltage of the output terminal is 0 V, and applying voltages for a read operation to the NAND memory string so that the voltage of the reference node is determined according to the memory state of a specific cell element to be read;
A step of turning on the second NFT transistor with the NFE control signal to transfer data stored in the specific cell element to the output terminal of the flip-flop; and
An operating method of an NAF memory device, characterized in that the method sequentially proceeds, including the step of turning off the second NFT transistor with the NFE control signal.
In the operating method of the NAF memory device according to Article 3,
The second NFT transistor is turned off, and the FNT transistor is turned on to transmit the output data of the flip-flop to the NAND memory string.
A step of initializing by erasing the memory state of at least a specific cell element to be written in the above NAND memory string;
A step of stopping the CP of the flip-flop, maintaining the voltage of the output terminal, turning on the FNT transistor with the FNE control signal, and applying voltages for a write operation to the NAND memory string so that data of the output terminal is stored in the specific cell element; and
An operating method of an NAF memory device, characterized in that the method sequentially proceeds, including the step of turning off the FNT transistor with the FNE control signal.
N NAF memory devices according to clause 3 or clause 5 are arranged in a row,
An N-bit register, characterized in that the CP input terminals of each flip-flop of the N NAF memory devices are connected to one CP input line.
N NAF memory devices according to clause 3 or clause 5 are arranged in a row,
The CP input terminal of each flip-flop of the above N NAF memory devices is connected to one CP input line,
An N-bit shift register, characterized in that the output terminal of each flip-flop of the N NAF memory devices is connected to the data input terminal of an adjacent flip-flop, except for the NAF memory devices located at one end of the row.
N NAF memory devices according to clause 3 or clause 5 are arranged in a row,
The CP input terminal of each flip-flop of the above N NAF memory devices is connected to one CP input line,
The data input terminal of each flip-flop of the above N NAF memory devices is exclusively connected to the output terminal of one of the N multiplexers,
An N-bit general-purpose shift register, characterized in that the N multiplexers are connected in parallel to the first and second control signal lines.