KR102701385B1 - Operation method of Flash memory storage device - Google Patents

Abstract

The present invention provides a method for operating a flash memory storage device, comprising: a step in which a host interface controller receives a RW (Read/Write) command including a read LBA (Logical Block Addressing), a write LBA (Logical Block Addressing) and a host buffer address output from a buffer manager that manages host memory; a step in which the host interface controller stores host data stored in a host frame corresponding to the host buffer address in a temporary buffer frame; a step in which the host interface controller stores read page data stored in a buffer frame of a first flash memory chip corresponding to the read LBA in the host frame; and a step in which a NAND device controller stores the host data stored in the temporary buffer frame in a buffer frame of a second flash memory chip corresponding to the write LBA.

Description

Operation method of Flash memory storage device

The present invention relates to an operating method of a flash memory storage device, and more specifically, to an operating method of a flash memory storage device which facilitates parallel reading and writing of data to a storage device with a single RW (Read/Write) command.

Flash memory storage devices are non-volatile memory storage devices that move with electrical signals, so they exhibit very fast read/write performance.

With the rapid development of flash memory technology in the past few years, flash memory storage devices such as solid state drives (SSDs) are replacing hard disk drives (HDDs) in all computing sectors, including mobile devices, desktops, data centers, and cloud computing.

Additionally, flash memory storage devices have a characteristic in that read IOPS (I/O Per Second) are higher than write IOPS, so there is an asymmetry between read and write speeds, unlike hard disks.

One of the core technologies of a database management system (DBMS) is the buffer manager. The buffer manager plays an important role because it implements both the buffer replacement policy that is important for high performance and the interaction with the storage device.

A closely related protocol is the Read-After-Write (RAW) protocol. When the page to be read is not in the buffer cache (Page Miss), the buffer manager selects a victim page according to the buffer replacement policy.

If the victim page is a modified dirty page, the victim page is first written synchronously to storage, the corresponding frame is emptied, and the page data to be read is read from storage and stored in the emptied frame.

This protocol is used for buffer cache management in all DBMSs, and is also commonly used in other systems that use the buffer cache concept, such as OS/file systems.

Meanwhile, a process in a page-missing situation in the RAW protocol may experience a read stall problem. That is, when a page is missed, the process must wait until the synchronous write for the dirty victim page is completed before it can read the page it wants to read.

Therefore, the order of processing write and read operations is serialized, which ultimately leads to problems in which the performance of the storage device is not fully utilized and CPU utilization is also reduced.

If these serialized write-read operations can be processed in parallel, it can solve the read latency problem and improve system performance, so research is needed.

The purpose of the present invention is to provide an operating method of a flash memory storage device that facilitates parallel reading and writing of data to the storage device with a single RW (Read/Write) command.

In addition, an object of the present invention is to provide an operating method of a flash memory storage device that improves performance within the storage device by alleviating read delay by performing reading and writing in parallel according to a RW (Read/Write) command.

The purposes of the present invention are not limited to the purposes mentioned above, and other purposes and advantages of the present invention which are not mentioned can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. In addition, it will be easily understood that the purposes and advantages of the present invention can be realized by the means and combinations thereof indicated in the claims.

An operating method of a flash memory storage device according to the present invention may include a step in which a host interface controller receives an RW (Read/Write) command including a read LBA (Logical Block Addressing), a write LBA (Logical Block Addressing) and a host buffer address output from a buffer manager managing host memory, a step in which the host interface controller stores host data stored in a host frame corresponding to the host buffer address in a temporary buffer frame, a step in which the host interface controller stores read page data stored in a buffer frame of a first flash memory chip corresponding to the read LBA in the host frame, and a step in which a NAND device controller stores the host data stored in the temporary buffer frame in a buffer frame of a second flash memory chip corresponding to the write LBA.

Before the step of storing the acquired host data in a temporary buffer frame, the host interface controller may further include a step of acquiring the temporary buffer frame for storing the host data from the NAND device controller.

The step of storing the acquired host data in a temporary buffer frame may include having the host interface controller perform DMA (Direct Memory Access) to read the host data and store it in the temporary buffer frame.

The step of storing the read page data in the host frame may include storing the read page data in a buffer frame of the first flash memory chip obtained from the NAND device controller for a read operation on the read page data by the host interface controller, and performing the DMA (Direct Memory Access) to store the read page data in the host frame.

After the step of storing the read page data in the host frame, the host interface controller may further include a step of outputting an interrupt notifying the buffer manager of the completion of an operation for the RW command.

The operating method of the flash memory storage device according to the present invention has the advantage of improving system performance by processing read and write requests in parallel.

The operating method of a flash memory storage device according to the present invention has the advantage of alleviating a read delay problem by simply calling a RW (Read/Write) command when a page is missed.

The operating method of a flash memory storage device according to the present invention has the advantage of reducing the number of I/O interrupts and the number of context switches resulting from them by processing read and write requests with a single RW (Read/Write) command.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

Figure 1 is a flow chart showing an operating method of a flash memory storage device according to the present invention.
Figure 2 is a conceptual diagram for explaining the operation of a flash memory storage device according to the present invention.
Figure 3 is an exemplary diagram comparing the processing process of a flash memory storage device according to the present invention.

The present invention can have various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. In describing each drawing, similar reference numerals are used for similar components.

The terms first, second, A, B, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and/or includes any combination of a plurality of related described items or any item among a plurality of related described items.

When it is said that a component is "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. On the other hand, when it is said that a component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" and the like are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in this application. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a flowchart showing an operation method of a flash memory storage device according to the present invention, and FIG. 2 is a conceptual diagram explaining the operation of a flash memory storage device according to the present invention.

Referring to FIGS. 1 and 2, a host interface controller of a flash memory storage device can receive a RW (Read/Write) command (RW) including a read LBA (Logical Block Addressing), a write LBA (Logical Block Addressing), and a host buffer address output from a buffer manager (Buffer Manager) that manages host memory (S110).

Here, the buffer manager can manage the host memory of the host system.

When the buffer manager attempts to read a read page (PR), but a miss occurs due to the absence of a stored read page (PR), and unnecessary host data (Dirty Victim Page, PW) in the host memory becomes a target for replacement, the buffer manager can generate a RW command (RW) and transmit it to the host interface controller.

Here, the RW command (RW) may include a read LBA (Logical Block Addressing, PR_LBA), a write LBA (Logical Block Addressing, PW_LBA), and a host buffer address (buf).

Read LBA (Logical Block Addressing, PR_LBA) is a logical block address where read data to be read into host memory is located, write LBA (Logical Block Addressing, PW_LBA) is a logical block address of a data page to be written to the flash memory chip, and the host buffer address (buf) is a virtual address of the host memory that stores the host data (PW), and can indicate the host frame address of the host memory that reads and stores the read data.

When receiving a RW command (RW), the host interface controller can obtain a temporary buffer frame for storing host data (PW) from the NAND device controller (S120).

That is, the host interface controller can obtain a temporary buffer frame (①) from the flash storage buffer for storing host data (PW) from the NAND device controller, as shown in Fig. 2.

The host interface controller can store host data (PW) stored in a host frame corresponding to a host buffer address (buf) in a temporary buffer frame (S130).

That is, the host interface controller can perform DMA (Direct Memory Access) to store or copy (②) host data (PW) to a temporary buffer frame.

The host interface controller can store read page data stored in a buffer frame of the first flash memory chip corresponding to the read LBA in the host frame (S140).

That is, the host interface controller can store the read page data (④) obtained from the NAND device controller in the buffer frame (③) of the first flash memory chip for a read operation, and perform the DMA (Direct Memory Access) to store the read page data in the host frame (⑤).

Thereafter, the host interface controller can output an interrupt to notify the buffer manager of the completion of the operation for the RW command (RW) (S150).

That is, the host interface controller can send an interrupt (⑥) to the buffer manager to notify that the RW command has been successfully completed.

The NAND device controller can store the host data stored in the temporary buffer frame in the buffer frame of the second flash memory chip corresponding to the write LBA (S170).

That is, the NAND device controller can write the host data asynchronously regardless of the read operation (⑦).

Figure 3 is an exemplary diagram comparing the processing process of a flash memory storage device according to the present invention.

Figure 3 is a diagram comparing the I/O processing process when using the basic command set and when using the extended command set when processing write and read commands.

Before explaining Figure 3, since the host interface controller does not have a command matching the RW command (RW), the RW interface was implemented on the firmware of Cosmos+ OpenSSD.

To implement the RW command (RW), the NVM command set (NVM Command Set) was extended. Cosmos+ OpenSSD supports the NVM Express (NVMe) interface, and a custom opcode for RW was added to the basic command set supported by the NVMe interface.

The RW command (RW) is defined as 0x66, and when the host calls the RW command with the specified opcode, the host interface controller of OpenSSD identifies the given NVM command set and prepares each read and write operation.

The RW command allows the host system to request two operations (a read and a write) from the SSD using a single I/O request.

The RW command provides the SSD with separate storage device addresses for read operations and write operations.

That is, because the addresses to read data from and write data to within the storage device are different, the NAND device controller can perform both operations independently using multiple channels within the SSD.

However, since one host request can only contain one address information for the host memory buffer, one constraint must be maintained to ensure data consistency. This exists during the data transfer process between the host memory buffer and the storage buffer inside the SSD. Data transfer between the host memory buffer and the storage buffer for a read operation must be performed only after the write data of the host memory buffer is completely written to the storage buffer.

As shown in Figure 3, when using the basic command set, host request A for a write operation and host request B for a read operation can occur sequentially because new data can be read only after an empty buffer frame is created in the MySQL buffer.

In this case, the write and read operations are performed sequentially.

On the other hand, when using the extended command set, only a host request C is issued for calling the RW instruction (RW).

In this case, read and write operations can be processed in parallel, except for the write data transfer process between the host memory buffer and the SSD internal storage buffer, which can reduce the I/O processing time.

The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented in other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

In addition, although the above has been described focusing on embodiments, these are merely examples and do not limit the present invention, and those with ordinary skill in the art to which the present invention pertains will recognize that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiments can be modified and implemented. And, the differences related to such modifications and applications should be interpreted as being included in the scope of the present invention defined in the appended claims.

Claims (5)

A step in which a host interface controller receives a RW (Read/Write) command including a read LBA (Logical Block Addressing), a write LBA (Logical Block Addressing) and a host buffer address output from a buffer manager that manages host memory;
A step in which the host interface controller stores host data stored in a host frame corresponding to the host buffer address in a temporary buffer frame;
The step of the host interface controller storing the read page data stored in the buffer frame of the first flash memory chip corresponding to the read LBA in the host frame; and
The NAND device controller comprises a step of storing the host data stored in the temporary buffer frame in a buffer frame of a second flash memory chip corresponding to the write LBA,
The above RW command is,
It can be generated by adding a custom opcode for RW through an extended NVM command set, and is characterized by separately including a storage device address for a read operation and a storage device address for a write operation, thereby performing read and write through a single host request.
How a flash memory storage device operates. In paragraph 1,
Before the step of storing the acquired host data in a temporary buffer frame,
The host interface controller further comprises a step of obtaining the temporary buffer frame for storing the host data from the NAND device controller.
How a flash memory storage device operates. In the first paragraph,
The step of storing the acquired host data in a temporary buffer frame is:
The host interface controller performs DMA (Direct Memory Access) to read the host data and store it in the temporary buffer frame.
How a flash memory storage device operates. In paragraph 1,
The step of storing the above read page data in the above host frame is:
The host interface controller stores the read page data in a buffer frame of the first flash memory chip obtained from the NAND device controller for a read operation on the read page data, and performs DMA (Direct Memory Access) to store the read page data in the host frame.
How a flash memory storage device operates. In paragraph 1,
After the step of storing the above read page data in the above host frame,
The host interface controller further comprises a step of outputting an interrupt to the buffer manager notifying completion of an operation for the RW command.
How a flash memory storage device operates.