KR102696294B1 - Semiconductor memory device having calibration circuit and training method thereof - Google Patents

Abstract

The semiconductor device may include, in a training mode, a transmitter circuit which sequentially outputs pulses corresponding to first to Nth output clocks to a data strobe pad; a receiver circuit which generates a rising signal and a falling signal which are activated respectively at a rising edge and a falling edge of the pulses input to the data strobe pad; a calibration circuit which sequentially stores detection codes corresponding to a phase difference of the rising signal and the falling signal in first to Nth registers according to an interval signal, calculates an average value of the first to Nth stored values, and re-stores a deviation of the average value and the first to Nth stored values in the first to Nth registers; and a clock generation circuit which corrects a duty ratio of the first to Nth output clocks using the re-stored values of the first to Nth registers.

Description

SEMICONDUCTOR MEMORY DEVICE HAVING CALIBRATION CIRCUIT AND TRAINING METHOD THEREOF

The present invention relates to semiconductor design technology, and more particularly, to a calibration circuit for a semiconductor device that inputs and outputs data according to a strobe signal.

In general, a semiconductor device is provided with a data output buffer for data output operation. And the data output buffer performs a function of synchronizing data transmitted through a global input/output line with a strobe signal and outputting it. The strobe signal can be generated using a rising clock that is activated according to a rising edge of the output clock or a falling clock that is activated according to a falling edge of the output clock. A strobe signal generation circuit can be provided to generate the strobe signal.

In general, a delay locked loop (DLL) circuit generates an output clock that has a phase that is a predetermined amount of time ahead of an external clock in order to compensate for the delay values of the delay elements inside a semiconductor device, divides it into a rising clock and a falling clock, and then adjusts the duty ratio of each to 50%. Therefore, ideally, the duty ratios of the rising clock and the falling clock transmitted to the strobe signal generation circuit should not change, but in reality, each duty ratio changes due to process, voltage, temperature (PVT) fluctuations, resistance in the clock transmission line, and noise. If a strobe signal is generated in a situation where the duty ratio of the rising clock and the falling clock is not 50%, the activation section of the strobe signal changes, making it impossible to accurately control the operation of the data output buffer. In severe cases, a malfunction may occur in which the data output operation is not performed.

Embodiments of the present invention provide a semiconductor device including a calibration circuit capable of generating a strobe signal having an accurate duty ratio.

According to one embodiment of the present invention, a semiconductor device may include: a transmitter circuit which sequentially outputs pulses corresponding to first to Nth output clocks to a data strobe pad in a training mode; a receiver circuit which generates a rising signal and a falling signal which are activated respectively at a rising edge and a falling edge of the pulses input to the data strobe pad; a calibration circuit which sequentially stores detection codes corresponding to a phase difference of the rising signal and the falling signal in first to Nth registers according to an interval signal, calculates an average value of the first to Nth stored values, and re-stores a deviation of the average value and the first to Nth stored values in the first to Nth registers; and a clock generation circuit which corrects a duty ratio of the first to Nth output clocks using the re-stored values of the first to Nth registers.

According to one embodiment of the present invention, a calibration circuit may include, in a training mode, a step of sequentially outputting pulses corresponding to first to Nth output clocks to a data strobe pad; a step of generating a rising signal and a falling signal, which are activated respectively at a rising edge and a falling edge of the pulses input to the data strobe pad; a step of sequentially storing detection codes corresponding to a phase difference of the rising signal and the falling signal in first to Nth registers, and generating a sum signal by accumulating and summing the first to Nth stored values; a step of calculating an average value of the first to Nth stored values based on the sum signal, and re-storing a deviation between the average value and the first to Nth stored values in the first to Nth registers; and a step of correcting a duty ratio of the first to Nth output clocks using the re-stored values of the first to Nth registers.

A training method for a semiconductor device according to one embodiment of the present invention may include: a detection unit which detects a phase difference between a rising signal and the falling signal to generate a detection code; a storage unit which selects the detection code or the accumulated deviation code according to an interval signal, and stores the selected code in first to Nth registers according to first to Nth register control signals; an accumulative summation unit which accumulates and sums first to Nth storage values stored in the first to Nth registers according to the first to Nth register control signals and the interval signal, and outputs a summation signal or accumulates and sums deviation codes and outputs the accumulated deviation code; an average calculation unit which calculates an average based on the summation signal; and a deviation calculation unit which selects one of the first to N-1th storage values according to a selection signal, and outputs a difference between the average value and the selected storage value as the deviation code.

A semiconductor device according to the proposed embodiment can maintain a constant 1-bit pulse width of a strobe signal finally output through a data strobe pad.

In addition, the semiconductor device according to the proposed embodiment can improve the reliability of data output operation by providing a strobe signal having an accurate duty ratio.

FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.
FIG. 2a and FIG. 2b are waveform diagrams for explaining the operation of the transmitter circuit of FIG. 1.
Figure 3 is a circuit diagram of the pattern generation unit of Figure 1.
Figure 4 is a waveform diagram for explaining the operation of the pattern generation unit of Figure 3.
Figure 5 is a detailed block diagram of the calibration circuit and calibration control circuit of Figure 1.
Figure 6 is a block diagram of the trimming controller of Figure 5.
Fig. 7 is a circuit diagram of the periodic generator of Fig. 6.
Fig. 8 is a circuit diagram of the code converter of Fig. 6.
Fig. 9 is a circuit diagram of the initial section setting section of Fig. 6.
Fig. 10 is a circuit diagram of the code output device of Fig. 6.
Figure 11 is a circuit diagram of the storage unit and mean-deviation calculation unit of Figure 5.
Figure 12 is a detailed block diagram of the calibration control circuit of Figure 5.
Figure 13 is a circuit diagram of the section definition part of Figure 12.
Figure 14 is a waveform diagram for explaining the operation of the interval definition part of Figure 13.
Figure 15 is a detailed circuit diagram of the control signal generation unit of Figure 12.
FIG. 16a and FIG. 16b are waveform diagrams for explaining the operation of the calibration circuit and calibration control circuit of FIG. 5.
FIG. 17 is a flowchart for explaining a training operation of a semiconductor device according to an embodiment of the present invention.
Figure 18 is a diagram showing duty correction of output clocks according to the training operation of Figure 17.

Hereinafter, in order to enable a person having ordinary skill in the art to easily implement the technical idea of the present invention, the most preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a block diagram of a semiconductor device (100) according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device (100) may include a clock generation circuit (110), a transmission circuit (120), a reception circuit (130), and a calibration circuit (140).

The clock generation circuit (110) can generate output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) based on a clock (CLK) input from the outside through a clock pad (CLK_P). The output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) can be multi-phase clocks activated with a predetermined phase difference. Hereinafter, a case in which the output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) are 4-phase clocks will be described as an example. In this case, the output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) can include first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) activated with a phase difference of 4-phase (i.e., 90 degrees).

In more detail, the clock generation circuit (110) may include a clock buffer (112) and a clock generation unit (114).

The clock buffer (112) can buffer a clock (CLK) input from the outside through a clock pad (CLK_P) and output an internal clock (CLKI). The clock generation unit (114) can generate first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) that are activated with a phase difference of 4 phases (i.e., 90 degrees) based on the internal clock (CLKI). The clock generation unit (114) of the clock generation circuit (110) according to the embodiment of the present invention can correct the duty ratios of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) according to the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>), respectively.

The transmitter circuit (120) can, during normal operation (i.e., read operation), latch the first to fourth input data (BL0 to BL3) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) and generate a strobe signal (DQS) that toggles at a constant cycle. The transmitter circuit (120) can output the strobe signal (DQS) to a data strobe pad (DQS_P). Each of the first to fourth input data (BL0 to BL3) can be a signal that maintains a logic high level or a logic low level.

Referring to FIG. 2a, the operation of the transmitter circuit (120) during lead operation is illustrated.

As illustrated in FIG. 2A, when the burst length (BL) is 16, the first and third input data (BL0, BL2) at a logic high level and the second and fourth input data (BL1, BL3) at a logic low level can be provided. The transmitting circuit (120) can generate a strobe signal (DQS) that toggles 16 times in the order of H-L-H-L-H-L-H-L-H-L-H-L-H-L-H-L-L by latching the first to fourth input data (BL0 to BL3) four times each according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK). The data output buffer (not shown) can sequentially output 16 output data (D0 to D15) to the outside through the data input/output (DQ) pad according to the rising edge and falling edge of the strobe signal (DQS). At this time, it can be seen that the output data (D0, D4, D8, D12) are output in synchronization with the first output clock (R1DOCLK), the output data (D1, D5, D9, D13) are output in synchronization with the second output clock (F1DOCLK), the output data (D2, D6, D10, D14) are output in synchronization with the third output clock (R2DOCLK), and the output data (D3, D7, D11, D15) are output in synchronization with the fourth output clock (F1DOCLK).

Referring back to FIG. 1, the transmitter circuit (120) can sequentially output pulses corresponding to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) to the data strobe pad (DQS_P) in the training mode. The transmitter circuit (120) can generate the first to fourth pattern data (BL0_CALP to BL3_CALP) according to the first and second test signals (R1DOA, R2DOA) in the training mode, and latch the first to fourth pattern data (BL0_CALP to BL3_CALP) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) to generate a training signal (TRS) activated in a predetermined pattern. The transmitter circuit (120) can output a training signal (TRS) to a data strobe pad (DQS_P). Each of the first to fourth pattern data (BL0_CALP to BL3_CALP) can be a signal that sequentially maintains a logic high level during a predetermined period of the first and second test signals (R1DOA, R2DOA). Each of the first to fourth pattern data (BL0_CALP to BL3_CALP) can have an activation section that does not overlap each other.

Referring to FIG. 2b, the operation of the transmitter circuit (120) in training mode is illustrated.

As illustrated in FIG. 2B, in the training mode, the first and second test signals (R1DOA, R2DOA) are input with a predetermined phase difference in the same period. The first and second test signals (R1DOA, R2DOA) may have a period that is twice that of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK). The transmitting circuit (120) may generate the first pattern data (BL0_CALP) that is activated during the predetermined period of the first test signal (R1DOA). The transmitting circuit (120) may generate the second pattern data (BL1_CALP) that is activated during the predetermined period of the first test signal (R1DOA) after the first pattern data (BL0_CALP) is deactivated. The transmitter circuit (120) can generate third pattern data (BL2_CALP) that is activated during a predetermined period of the second test signal (R2DOA) after the second pattern data (BL1_CALP) is deactivated. The transmitter circuit (120) can generate fourth pattern data (BL3_CALP) that is activated during a predetermined period of the second test signal (R2DOA) after the third pattern data (BL2_CALP) is deactivated.

The transmitter circuit (120) can latch the first to fourth pattern data (BL0_CALP to BL3_CALP) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK), respectively, to generate a training signal (TRS) activated in a predetermined pattern. That is, the training signal (TRS) can be output as a pulse of H-L-L-L during the activation period of the first pattern data (BL0_CALP), as a pulse of L-H-L-L during the activation period of the second pattern data (BL1_CALP), as a pulse of L-L-H-L during the activation period of the third pattern data (BL2_CALP), and as a pulse of L-L-L-H during the activation period of the fourth pattern data (BL3_CALP).

Referring again to FIG. 1, the transmitter circuit (120) may include a pattern generation unit (122), a serialization unit (124), and an output driver (126).

The pattern generation unit (122) can be enabled according to a training mode signal (CAL_EN) that is activated in the training mode, and can be disabled according to a training end signal (CAL_OFF) that notifies that the training operation is terminated. The pattern generation unit (122) can generate first to fourth pattern data (BL0_CALP to BL3_CALP) using the first and second test signals (R1DOA, R2DOA). For example, the pattern generation unit (122) can generate first and second pattern data (BL0_CALP, BL1_CALP) that are sequentially activated during a predetermined period of the first test signal (R1DOA), and then generate third and fourth pattern data (BL2_CALP, BL3_CALP) that are sequentially activated during a predetermined period of the second test signal (R2DOA). Each of the first to fourth pattern data (BL0_CALP to BL3_CALP) can have activation sections that do not overlap each other.

The serialization unit (124) can latch the first to fourth input data (BL0 to BL3) or the first to fourth pattern data (BL0_CALP to BL3_CALP) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK), respectively, and serialize the latched signals to generate a pull-up control signal (PU) and a pull-down control signal (PD). The serialization unit (124), during a read operation, can latch the first to fourth input data (BL0 to BL3) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK), respectively, and serialize the latched signals to generate a pull-up control signal (PU) and a pull-down control signal (PD). On the other hand, the serialization unit (124) can, in training mode, latch the first to fourth pattern data (BL0_CALP to BL3_CALP) according to the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK), and serialize the latched signals to generate a pull-up control signal (PU) and a pull-down control signal (PD).

The output driver (126) can drive the data strobe pad (DQS_P) according to the pull-up control signal (PU) and the pull-down control signal (PD) to output a strobe signal (DQS) or a training signal (TRS).

The receiving circuit (130) can generate a rising signal (IDQS) and a falling signal (QDQS) that are activated at the rising edge and the falling edge of a strobe signal (DQS) input to a data strobe pad (DQS_P) during a normal operation (i.e., a write operation), or a training signal (TRS) input to the data strobe pad (DQS_P) during a training mode, respectively. At this time, the receiving circuit (130) can generate the rising signal (IDQS) and the falling signal (QDQS) so that they have a period twice that of the strobe signal (DQS). In general, the receiving circuit (130) is activated only during a write operation, but the receiving circuit (130) according to the embodiment of the present invention is enabled even during the training mode to receive the training signal (TRS) input to the data strobe pad (DQS_P).

In more detail, the receiving circuit (130) may include an input buffer (132) and a divider (134).

The input buffer (132) can output an internal strobe signal (DQSI) by buffering a strobe signal (DQS) input to a data strobe pad (DQS_P) during light operation or a training signal (TRS) input to a data strobe pad (DQS_P) during training mode. The input buffer (132) can be enabled according to a training mode signal (CAL_EN).

The divider (134) can divide the frequency of the internal strobe signal (DQSI) by a predetermined number (for example, 2) and generate a rising signal (IDQS) and a falling signal (QDQS) that are activated at the rising edge and the falling edge of the divided signal, respectively. For reference, the divider (134) can divide the frequency of the internal strobe signal (DQSI) by 2 to generate a first rising signal (IDQS) that is activated at the rising edge of the internal strobe signal (DQSI), invert the first rising signal (IDQS) to generate a second rising signal (IDQSB), generate a first falling signal (QDQS) that is activated at the falling edge of the internal strobe signal (DQSI), and invert the first falling signal (QDQS) to generate a second falling signal (QDQSB). In an embodiment of the present invention, a case in which the divider (134) uses the first rising signal (IDQS) and the first falling signal (QDQS) during a training operation is described as an example.

The calibration circuit (140) can sequentially store detection codes (not shown) corresponding to the phase difference of the rising signal (IDQS) and the falling signal (QDQS) in the first to fourth registers (not shown) according to the interval signal (SAR_EN). The calibration circuit (140) can calculate an average value of the first to fourth storage values of the first to fourth registers according to the interval signal (SAR_EN) and re-store a deviation between the average value and the first to fourth storage values in the first to fourth registers, respectively. The first to fourth storage values re-stored in the first to fourth registers can be output as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>). The calibration circuit (140) can be activated according to the training mode signal (CAL_EN).

Meanwhile, the semiconductor device (100) may further include a calibration control circuit (150) for controlling the calibration circuit (140). The calibration control circuit (150) may be activated according to a training mode signal (CAL_EN) and may generate an interval signal (SAR_EN) and first to fourth register control signals (REG0P to REG3P) that are sequentially activated according to a seed signal (SEED) that is activated at a predetermined cycle according to at least one of a rising signal (IDQS) and a falling signal (QDQS). For example, the calibration control circuit (150) may be activated according to a training mode signal (CAL_EN) and may generate an interval signal (SAR_EN) that is deactivated after the seed signal (SEED) is activated a predetermined number of times. Additionally, the calibration control circuit (150) can generate a training end signal (CAL_OFF) that is activated after the calibration circuit (140) re-stores the deviations of the first to fourth storage values in the first to fourth registers.

The calibration circuit (140) can sequentially store detection codes in the first to fourth registers according to the first to fourth register control signals (REG0P to REG3P) when the interval signal (SAR_EN) is activated, and generate a sum signal (not shown) by accumulating and adding the first to fourth storage values. In addition, the calibration circuit (140) can calculate an average value based on the sum signal when the interval signal (SAR_EN) is deactivated, and sequentially re-store deviations corresponding to the first to fourth storage values in the first to fourth registers according to the first to fourth register control signals (REG0P to REG3P). Finally, the first to fourth registers can output the restored first to fourth storage values as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>). Hereinafter, in the embodiment of the present invention, a case in which the calibration circuit (140) calculates an average value of the first to fourth storage values, re-stores the deviations between the average value and the first to third storage values in the first to third registers, and outputs the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>) will be described as an example. However, the proposed invention is not limited thereto, and the calibration circuit (140) can re-store the deviations between the average value and the first to fourth storage values in the first to fourth registers in various ways.

Meanwhile, FIG. 1 illustrates that the calibration circuit (140) generates a seed signal (SEED) in response to at least one of the rising signal (IDQS) and the falling signal (QDQS), and the calibration control circuit (150) generates first to fourth register control signals (REG0P to REG3P) and an interval signal (SAR_EN) in response to the seed signal (SEED). However, the proposed invention is not limited thereto, and the calibration control circuit (150) may generate the seed signal (SEED) in response to at least one of the rising signal (IDQS) and the falling signal (QDQS). In addition, the calibration control circuit (150) may generate control signals for controlling the calibration circuit (140) in addition to the first to fourth register control signals (REG0P to REG3P) and the interval signal (SAR_EN). This will be described in detail in Fig. 5.

As described above, the semiconductor device according to the embodiment of the present invention can, in the training mode, sequentially output a training signal composed of pulses corresponding to each output clock to the data strobe pad, and receive a feedback of the training signal finally transmitted through the data strobe pad. In addition, the phase difference between the rising signal (IDQS) and the falling signal (QDQS) corresponding to the rising edge and falling edge of the fed-back pulses can be measured to detect each pulse width of the fed-back pulses. The detected pulse widths are stored in registers, and the average value and the deviation are calculated using the stored values to individually correct the duty ratio of each output clock, thereby maintaining the 1-bit pulse width of the strobe signal constant.

Figure 3 is a circuit diagram of the pattern generation unit (122) of Figure 1.

Referring to FIG. 3, the pattern generation unit (122) may include a first frequency divider (210), a second frequency divider (220), a first signal generator (230), a second signal generator (240), and a pattern combiner (250). In addition, the pattern generation unit (122) may further include a reset controller (260) that generates a pattern interval signal (PT) by performing a logic NAND operation on an inverted signal of a training mode signal (CAL_EN) and a training end signal (CAL_OFF). The first frequency divider (210), the second frequency divider (220), the first signal generator (230), and the second signal generator (240) may be initialized according to the pattern interval signal (PT).

The first frequency divider (210) can divide the frequency of the first test signal (R1DOA) by a predetermined period (for example, 2) to generate a first divided clock (R1DOACLK). The second frequency divider (220) can divide the frequency of the second test signal (R2DOA) by a predetermined period (for example, 2) to generate a second divided clock (R2DOACLK). The first frequency divider (210) and the second frequency divider (220) can be configured as a D flip-flop that receives a corresponding signal among the first and second test signals (R1DOA, R2DOA) as a clock terminal, receives an inverted signal of an output terminal (Q) as an input terminal (D), and receives a pattern interval signal (PT) as a reset signal (R).

The first signal generator (230) can generate first to seventh shift signals (D0 to D6) that are sequentially activated according to the first divided clock (R1DOACLK). The first signal generator (230) can be composed of first to seventh shifters (231 to 237) that are connected in series and output the first to seventh shift signals (D0 to D6) respectively in synchronization with the falling edge of the first divided clock (R1DOACLK). Each of the first to seventh shifters (231 to 237) can be composed of a D flip-flop that receives an inverted signal of the first divided clock (R1DOACLK) as a clock terminal, a signal of an output terminal (Q) of a front terminal as an input terminal (D), and receives a pattern interval signal (PT) as a reset signal (R). The first shifter (231) can receive power voltage (VDD) as input terminal (D).

The second signal generator (240) can receive the output of the first signal generator (230) (i.e., the seventh shift signal (D6)) and generate the eighth to eleventh shift signals (D7 to D10) that are sequentially activated according to the second divided clock (R2DOACLK). The second signal generator (240) can be composed of the eighth to eleventh shifters (241 to 244) that are connected in series and output the eighth to eleventh shift signals (D7 to D10) respectively in synchronization with the falling edge of the second divided clock (R2DOACLK). Each of the eighth to eleventh shifters (241 to 244) may be configured as a D flip-flop that receives an inversion signal of a second divided clock (R2DOACLK) as a clock terminal, a signal of an output terminal (Q) of a previous stage as an input terminal (D), and a pattern interval signal (PT) as a reset signal (R). The eighth shifter (241) may receive a seventh shift signal (D6) as an input terminal (D).

The pattern combiner (250) can output the first to fourth pattern data (BL0_CALP to BL3_CALP) by combining at least two of the first to eleventh shift signals (D0 to D10). Preferably, the pattern combiner (250) can output the first to fourth pattern data (BL0_CALP to BL3_CALP) by combining one of the first to seventh shift signals (D0 to D6) output from the first signal generator (230) and one of the eighth to eleventh shift signals (D7 to D10) output from the second signal generator (240). For example, the pattern combiner (250) can generate first pattern data (BL0_CALP) by performing a logic-AND operation on the inverted signals of the first shift signal (D0) and the fifth shift signal (D4), generate second pattern data (BL1_CALP) by performing a logic-AND operation on the inverted signals of the fifth shift signal (D4) and the seventh shift signal (D6), generate third pattern data (BL2_CALP) by performing a logic-AND operation on the inverted signals of the seventh shift signal (D6) and the ninth shift signal (D8), and generate fourth pattern data (BL3_CALP) by performing a logic-AND operation on the ninth shift signal (D8) and the battery voltage (VSS).

Figure 4 is a waveform diagram for explaining the operation of the pattern generation unit (122) of Figure 3.

Referring to FIG. 4, the reset controller (260) can generate a pattern interval signal (PT) at a logic low level according to a training mode signal (CAL_EN).

When the pattern interval signal (PT) becomes a logic low level, the first frequency divider (210) divides the first test signal (R1DOA) by two to generate a first divided clock (R1DOACLK), and the second frequency divider (220) divides the second test signal (R2DOA) by two to generate a second divided clock (R2DOACLK). The first signal generator (230) can sequentially activate and output the first to seventh shift signals (D0 to D6) according to the falling edge of the first divided clock (R1DOACLK). The second signal generator (240) can sequentially activate and output the eighth to eleventh shift signals (D7 to D10) according to the falling edge of the second divided clock (R2DOACLK) after the activation of the seventh shift signal (D6).

The pattern combiner (250) can generate first pattern data (BL0_CALP) having an activation section between the rising edge of the first shift signal (D0) and the rising edge of the fifth shift signal (D4), generate second pattern data (BL1_CALP) having an activation section between the rising edge of the fifth shift signal (D4) and the rising edge of the seventh shift signal (D6), generate third pattern data (BL2_CALP) having an activation section between the rising edge of the seventh shift signal (D6) and the rising edge of the ninth shift signal (D8), and generate fourth pattern data (BL3_CALP) having an activation section between the rising edge of the ninth shift signal (D8) and the rising edge of the training mode signal (CAL_EN).

After this, the reset controller (260) can generate a pattern interval signal (PT) of a logic high level as the training end signal (CAL_OFF) is activated to a logic high level.

The first frequency divider (210), the second frequency divider (220), the first signal generator (230), and the second signal generator (240) are initialized according to the pattern interval signal (PT), so that the first to fourth pattern data (BL0_CALP to BL3_CALP) can be initialized.

As described above, the pattern generation unit (122) can generate first to fourth pattern data (BL0_CALP to BL3_CALP) that are sequentially activated using the first and second test signals (R1DOA, R2DOA) but have activation sections that do not overlap each other.

Meanwhile, as illustrated in FIG. 4, the first pattern data (BL0_CALP) and the fourth pattern data (BL3_CALP) can be activated for at least twice as long as the second and third pattern data (BL1_CALP, BL2_CALP). This is because the initial section of the activation section of the first pattern data (BL0_CALP) is allocated to perform the initial trimming setting operation of the calibration circuit (140), and the latter section of the fourth pattern data (BL3_CALP) is allocated to perform the deviation calculation operation. A detailed description thereof will be described with reference to FIG. 5.

Fig. 5 is a detailed block diagram of the calibration circuit (140) and calibration control circuit (150) of Fig. 1.

Referring to FIG. 5, the calibration circuit (140) may include a detection unit (310), a storage unit (320), and an average-deviation calculation unit (330).

The detection unit (310) can detect the phase difference between the rising signal (IDQS) and the falling signal (QDQS) and generate a detection code (DOUT<0:3>).

In more detail, the detection unit (310) may include a first trimmer (312), a second trimmer (314), a comparator (316), and a trimming controller (318).

The first trimmer (312) may be implemented as a delay line whose delay amount is adjusted according to a trimming code (D_TRIM<0:5>), and the second trimmer (314) may be implemented as a delay line whose delay amount is adjusted according to a detection code (DOUT<0:3>). The first trimmer (312) and the second trimmer (314) may be connected in series to delay a rising signal (IDQS) by a predetermined time and output a delayed rising signal (IDQSD). The comparator (316) may compare a phase difference between the delayed rising signal (IDQSD) and the falling signal (QDQS) and output a comparison signal (COMP). Preferably, the comparator (316) may be configured as a D flip-flop which receives the delayed rising signal (IDQSD) as an input terminal, receives the falling signal (QDQS) as a clock signal, and outputs the comparison signal (COMP) as an output terminal. That is, the comparator (316) can latch the delayed rising signal (IDQSD) according to the polling signal (QDQS) and output it as the comparison signal (COMP). The trimming controller (318) can generate a seed signal (SEED) and first to seventh pulse signals (P0 to P6) that are activated at a predetermined cycle according to the polling signal (QDQS) when the training mode signal (CAL_EN) is activated. The trimming controller (318) can generate a trimming code (D_TRIM<0:5>) and a detection code (DOUT<0:3>) corresponding to the comparison signal (COMP) according to the seed signal (SEED) and the first to seventh pulse signals (P0 to P6).

The storage unit (320) may include first to fourth registers (not shown) that are activated according to the first to fourth register control signals (REG0P to REG3P), respectively. When the interval signal (SAR_EN) is activated, the storage unit (320) may sequentially store the detection code (DOUT<0:3>) in the first to fourth registers according to the first to fourth register control signals (REG0P to REG3P). When the interval signal (SAR_EN) is deactivated, the storage unit (320) may sequentially store the accumulated deviation code (FB_DEV<0:3>) provided from the average-deviation calculation unit (330) in the first to fourth registers according to the first to fourth register control signals (REG0P to REG3P).

The mean-deviation calculation unit (330) can generate a sum signal by accumulating the first to fourth storage values according to the first to fourth register control signals (REG0P to REG3P) and the accumulation clock (ACC_CLK) when the interval signal (SAR_EN) is activated. The mean-deviation calculation unit (330) can calculate an average value based on the sum signal according to the accumulation clock (ACC_CLK), the accumulation reset signal (ACC_RST), the average calculation signal (REG_QW), and the selection signal (REG_SEL<0:2>) when the interval signal (SAR_EN) is deactivated, and can calculate an accumulated deviation code (FB_DEV<0:3>) corresponding to a deviation between the average value and the first to fourth storage values and provide the calculated average value to the storage unit (320).

Meanwhile, the calibration control circuit (150) is activated according to the training mode signal (CAL_EN) and can generate the first to fourth register control signals (REG0P to REG3P), an interval signal (SAR_EN), an accumulation clock (ACC_CLK), an accumulation reset signal (ACC_RST), an average calculation signal (REG_QW), and a selection signal (REG_SEL<0:2>) according to some signals (e.g., the third pulse signal (P2) and the fifth pulse signal (P4)) among the seed signal (SEED) and the first to seventh pulse signals (P0 to P6). A detailed description thereof will be given with reference to FIG. 8.

For reference, during the initial section of the activation section of the first pattern data (BL0_CALP) described in FIG. 4, the delay amount of the first trimmer (312) can be set according to the trimming code (D_TRIM<0:5>). Thereafter, during the latter section of the activation section of the first pattern data (BL0_CALP), the activation sections of the second and third pattern data (BL1_CALP, BL2_CALP) and the initial section of the activation section of the fourth pattern data (BL3_CALP), the delay amount of the second trimmer (314) can be adjusted according to the detection code (DOUT<0:3>). Hereinafter, the operation of setting the delay amount of the first trimmer (312) is defined as the initial trimming setting operation, and the operation of adjusting the delay amount of the second trimmer (314) is defined as the phase detection operation. After this, the average-deviation calculation operation of the average-deviation calculation unit (330) can be performed during the latter section of the activation section of the fourth pattern data (BL3_CALP).

As described above, when the training mode signal (CAL_EN) is activated, the detection unit (310) of the calibration circuit (140) performs an initial trimming setting operation to set the delay amount of the first trimmer (312), and then adjusts the delay amount of the second trimmer (314) through a phase detection operation. When the interval signal (SAR_EN) is activated, the storage unit (320) can sequentially store the detection code (DOUT<0:3>) in the first to fourth registers. Thereafter, when the interval signal (SAR_EN) is deactivated, the mean-deviation calculation unit (330) can calculate an average value of the first to fourth storage values, and calculate an accumulated deviation code (FB_DEV<0:3>) corresponding to a deviation between the average value and the first to fourth storage values, and provide the calculated accumulated deviation code to the storage unit (320). The storage unit (320) can sequentially re-store the accumulated deviation code (FB_DEV<0:3>) provided from the mean-deviation calculation unit (330) in the first to third registers. The first to third storage values restored to the first to third registers can be output as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>), respectively.

FIG. 6 is a block diagram of the trimming controller (318) of FIG. 5.

Referring to FIG. 6, the trimming controller (318) may include a cycle generator (410), a code converter (420), an initial interval setter (430), and a code outputter (440).

The period generator (410) can sequentially activate the seed signal (SEED) and the first to seventh pulse signals (P0 to P6) according to the inverted polling signal (QDQSB) when the training mode signal (CAL_EN) is activated. The seed signal (SEED) and the first to seventh pulse signals (P0 to P6) can be pulse signals that are activated for a predetermined period at a logic low level. Meanwhile, in the present embodiment, the period generator (410) is described as using the inverted polling signal (QDQSB), but the proposed invention is not limited thereto, and according to an embodiment, either the polling signal (QDQS) or the inverted polling signal (QDQSB) can be used.

In more detail, the period generator (410) may include a seed signal generator (412) and a pulse generator (414).

The seed signal generator (412) can activate the seed signal (SEED) at a constant cycle according to the inverted polling signal (QDQSB) and the seventh pulse signal (P6) when the training mode signal (CAL_EN) is activated. The pulse generator (414) can generate the first pulse signal (P0 to P6) that is sequentially activated according to the deactivation of the seed signal (SEED).

The code converter (420) can convert the comparison signal (COMP) into a preliminary code (DOUT_PRE<0:5>) according to the seed signal (SEED) and the first to seventh pulse signals (P0 to P6). The code converter (420) is initialized when the seed signal (SEED) is activated, and can convert the comparison signal (COMP) sequentially input according to the first to seventh pulse signals (P0 to P6) into a preliminary code (DOUT_PRE<0:5>).

The initial section setting unit (430) can generate a trimming section signal (TRIM) according to the training mode signal (CAL_EN) and the seventh pulse signal (P6). The initial section setting unit (430) can generate a trimming section signal (TRIM) that is set to a logic high level during an inactive section of the training mode signal (CAL_EN), i.e., before a training operation, and is inactivated to a logic low level according to the seventh pulse signal (P6). In addition, the trimming section signal (TRIM) can be inverted to generate an inverted trimming section signal (TRIMB). The trimming section signal (TRIM) is a signal for distinguishing an initial trimming setting operation from a phase detection operation, and can be activated to a logic high level during an initial section of an active section of the first pattern data (BL0_CALP) described in FIG. 4.

The code output unit (440) can output the preliminary code (DOUT_PRE<0:5>) as a trimming code (D_TRIM<0:5>) or a detection code (DOUT<0:3>) according to the trimming interval signal (TRIM) and the inverted trimming interval signal (TRIMB). The code output unit (440) can output the preliminary code (DOUT_PRE<0:5>) as a trimming code (D_TRIM<0:5>) during the initial trimming setting operation in which the trimming interval signal (TRIM) is activated, and can store the preliminary code (DOUT_PRE<0:5>) in an internal latch (not shown) in synchronization with the seventh pulse signal (P6). The code output device (440) can output the code stored in the latch as a trimming code (D_TRIM<0:5>) and output the reserve code (DOUT_PRE<0:5>) as a detection code (DOUT<0:3>) during a phase detection operation in which the trimming interval signal (TRIM) is deactivated.

Fig. 7 is a circuit diagram of the period generator (410) of Fig. 6.

Referring to FIG. 7, the seed signal generator (412) may include serially connected first and second D-flip-flops (412A, 412B), a seed signal outputter (412C), and a set combiner (412D).

The first D flip-flop (412A) can receive a ground voltage (VSS) as an input terminal (D), receive an inverted falling signal (QDQSB) as a clock signal, and receive a set combination signal (S3) as a set bar signal (SB) to output a first output signal (S1) to an output terminal (Q). The second D flip-flop (412B) can receive a first output signal (S1) as an input terminal (D), receive an inverted falling signal (QDQSB) as a clock signal, and receive a set combination signal (S3) as a set bar signal (SB) to output a second output signal (S2) to an output terminal (Q). The seed signal output unit (412C) can combine the first output signal (S1) and the second output signal (S2) and output a seed signal (SEED). The seed signal output unit (412C) can output a seed signal (SEED) that is activated to a logic low level when the first output signal (S1) is at a logic high level and the second output signal (S2) is at a logic low level. The set combiner (412D) can generate a set combination signal (S3) by performing a logic NAND operation on the training mode signal (CAL_EN) and the seventh pulse signal (P6). That is, the set combiner (412D) can output the set combination signal (S3) of a logic high level when at least one of the training mode signal (CAL_EN) and the seventh pulse signal (P6) becomes a logic low level.

With the above configuration, the seed signal generator (412) can output a seed signal (SEED) that is set to a logic high level during the deactivation period of the training mode signal (CAL_EN), i.e., before the training operation, and is activated to a logic low level at a predetermined cycle according to the seventh pulse signal (P6).

The pulse generator (414) may include third to ninth D-flip-flops (414A to 414G) connected in series.

The third to ninth D flip-flops (414A to 414G) can receive a training mode signal (CAL_EN) as a set bar signal (SB) and an inverted polling signal (QDQSB) as a clock signal. The third D flip-flop (414A) can receive a seed signal (SEED) as an input terminal (D) and output a first pulse signal (P0) as an output terminal (Q). The fourth to ninth D flip-flops (414B to 414G) can receive an output signal of a previous stage as an input terminal (D) and sequentially output the second to seventh pulse signals (P1 to P6) as an output terminal (Q).

With the above configuration, the pulse generator (414) can output the first to seventh pulse signals (P0 to P6) that are set to a logic high level during the inactive section of the training mode signal (CAL_EN), i.e., before the training operation, and are sequentially activated to a logic low level according to the toggling of the inverted polling signal (QDQSB) after the seed signal (SEED) of a logic low level is input.

Fig. 8 is a circuit diagram of the code converter (420) of Fig. 6.

Referring to FIG. 8, the code converter (420) may include first to seventh D-flip-flops (420A to 420G).

The first to seventh D flip-flops (420A to 420G) can receive a comparison signal (COMP) as an input terminal (D), a seed signal (SEED) as a reset bar signal (RB), and the seventh to first pulse signals (P6 to P0) as a set bar signal (SB), respectively. The first D flip-flop (420A) can receive a ground voltage (VSS) as a clock signal, and the second to seventh D flip-flops (420B to 420G) can receive a signal of an output terminal (Q) of the first to sixth D flip-flops (420A to 420F) as a clock signal and output a preliminary code (DOUT_PRE<0:5>).

With the above configuration, the code converter (420) is initialized to a logic low level when the seed signal (SEED) is activated, and can convert and output the comparison signal (COMP) sequentially input according to the first to seventh pulse signals (P0 to P6) into the reverse order of the preliminary code (DOUT_PRE<0:5>) (i.e., DOUT_PRE<5:0>).

Fig. 9 is a circuit diagram of the initial section setting unit (430) of Fig. 6.

Referring to FIG. 9, the initial section setting unit (430) may include a D flip-flop (432) and an inverter (434).

The D flip-flop (432) can receive a ground voltage (VSS) as an input terminal (D), a training mode signal (CAL_EN), a set bar signal (SB), and a seventh pulse signal (P6) as a clock signal to output a trimming interval signal (TRIM). The inverter (434) can invert the trimming interval signal (TRIM) and output an inverted trimming interval signal (TRIMB).

With the above configuration, the initial section setting unit (430) can generate a trimming section signal (TRIM) that is set to a logic high level before the training operation, i.e., the deactivation section of the training mode signal (CAL_EN), and is deactivated to a logic low level according to the activation of the seventh pulse signal (P6).

Fig. 10 is a circuit diagram of the code output device (440) of Fig. 6.

Referring to FIG. 10, the code output unit (440) may include a timing controller (442), a latch (444), and a selection output unit (446).

The timing controller (442) can output a timing signal (T1) by inverting the seventh pulse signal (P6) during the activation period of the trimming interval signal (TRIM). The timing controller (442) can include an inverter (442A) and a first AND gate (442B). The inverter (442A) can invert the seventh pulse signal (P6), and the first AND gate (442B) can perform a logic AND operation on the output of the inverter (442A) and the trimming interval signal (TRIM).

The latch (444) can store a preliminary code (DOUT_PRE<0:5>) according to the timing signal (T1).

The selection output unit (446) can output the preliminary code (DOUT_PRE<0:5>) as the trimming code (D_TRIM<0:5>) or the detection code (DOUT<0:3>) according to the trimming interval signal (TRIM) and the inverted trimming interval signal (TRIMB). The selection output unit (446) can include second to fourth AND gates (446A to 446C) and an OR gate (446D). The second AND gate (446A) can perform a logic AND operation on the inverted trimming interval signal (TRIMB) and the preliminary code (DOUT_PRE<0:5>) and output the detection code (DOUT<0:3>). The third AND gate (446B) can perform a logic AND operation on the trimming interval signal (TRIM) and the preliminary code (DOUT_PRE<0:5>), and the fourth AND gate (446C) can perform a logic AND operation on the inverted trimming interval signal (TRIMB) and the code stored in the latch (444). The OR gate (446D) can perform a logic OR operation on the outputs of the third AND gate (446B) and the fourth AND gate (446C) and output the trimming code (D_TRIM<0:5>).

With the above configuration, the code output unit (440) can output the preliminary code (DOUT_PRE<0:5>) as a trimming code (D_TRIM<0:5>) when the trimming interval signal (TRIM) is activated, and store the trimming code (D_TRIM<0:5>) in the latch (444) according to the timing signal (T1). On the other hand, when the trimming interval signal (TRIM) is deactivated, the code output unit (440) can output the preliminary code (DOUT_PRE<0:5>) as a detection code (DOUT<0:3>), and output the code stored in the latch (444) as a trimming code (D_TRIM<0:5>).

Figure 11 is a circuit diagram of the storage unit (320) and the average-deviation calculation unit (330) of Figure 5.

Referring to FIG. 11, the storage unit (320) may include a storage selector (321) and first to fourth registers (322 to 325).

The storage selector (321) can select and output a detection code (DOUT<0:3>) provided from the detection unit (310) when the interval signal (SAR_EN) is activated, and select and output an accumulated deviation code (FB_DEV<0:3>) provided from the average-deviation calculation unit (330) when the interval signal (SAR_EN) is deactivated. The first to fourth registers (322 to 325) can be sequentially activated according to the first to fourth register control signals (REG0P to REG3P) to store the output of the storage selector (321).

The mean-deviation calculation unit (330) may include a cumulative summation unit (332), an average calculation unit (334), and a deviation calculation unit (336).

The cumulative summing unit (332) can output a sum signal (SUM<0:3>) by cumulatively summing the first to fourth storage values stored in the first to fourth registers (322 to 325) according to the first to fourth register control signals (REG0P to REG3P) and the cumulative clock (ACC_CLK) when the interval signal (SAR_EN) is activated. The cumulative summing unit (332) can output a cumulative deviation code (FB_DEV<0:3>) by cumulatively summing the deviation code (DEV<0:3>) provided from the deviation calculation unit (336) according to the cumulative clock (ACC_CLK) and the cumulative reset signal (ACC_RST) when the interval signal (SAR_EN) is deactivated.

In more detail, the cumulative adder (332) may include a first cumulative selector (332A), a second cumulative selector (332B), an adder (332C), and a D-flip-flop (332D).

The first accumulation selector (332A) can select and output the first to fourth storage values according to the first to fourth register control signals (REG0P to REG3P). The second accumulation selector (332B) can select and output the output of the first accumulation selector (332A) or the deviation code (DEV<0:3>) output from the deviation calculation unit (336) according to the interval signal (SAR_EN). The adder (332C) can add the output of the second accumulation selector (332B) and the output of the D flip-flop (332D). The D flip-flop (332D) is initialized according to the accumulation reset signal (ACC_RST) and can store the output of the adder (332C) according to the accumulation clock (ACC_CLK). With the above configuration, the cumulative adder (332) can sequentially cumulatively add the first to fourth storage values of the first to fourth registers (322 to 325) according to the cumulative clock (ACC_CLK) when the interval signal (SAR_EN) is activated and output the sum signal (SUM<0:3>). In addition, the cumulative adder (332) can sequentially cumulatively add the deviation codes (DEV<0:3>) according to the cumulative clock (ACC_CLK) and output the cumulative deviation codes (FB_DEV<0:3>) when the interval signal (SAR_EN) is deactivated.

The average calculation unit (334) can output an average value, i.e., an average code (AVG<0:3>), by dividing the sum signal (SUM<0:3>) by the number of the first to fourth registers (322 to 325) (i.e., 4) according to the average calculation signal (REG_QW). Preferably, the average calculation unit (334) can be implemented as a shifter that shifts each bit of the sum signal (SUM<0:3>) to the right a number of times (2 times) corresponding to the number of the first to fourth registers (322 to 325) (i.e., 4), according to the average calculation signal (REG_QW), and outputs the average code (AVG<0:3>). The deviation calculation unit (336) can calculate a deviation code (DEV<0:3>) by subtracting the first to third storage values from the average code (AVG<0:3>) according to the selection signal (REG_SEL<0:2>).

The deviation calculation unit (336) may include a deviation selector (336A) and a subtractor (336B). The deviation selector (336A) may select and output one of the first to third storage values according to a selection signal (REG_SEL<0:2>). The subtractor (336B) may output the difference between the average code (AVG<0:3>) and the output of the deviation selector (336A) as a deviation code (DEV<0:3>).

As described above, the mean-deviation calculation unit (330) can sequentially accumulate the first to fourth storage values according to the first to fourth register control signals (REG0P to REG3P) and the accumulation clock (ACC_CLK) when the interval signal (SAR_EN) is activated to generate a sum signal (SUM<0:3>). In addition, the mean-deviation calculation unit (330) can calculate an average code (AVG<0:3>) based on the sum signal (SUM<0:3>) according to the average calculation signal (REG_QW) when the interval signal (SAR_EN) is deactivated, and can calculate an average code (AVG<0:3>) and an accumulated deviation code (FB_DEV<0:3>) of the first to third storage values according to a selection signal (REG_SEL<0:2>) and provide the result to the storage unit (320). Meanwhile, the mean-deviation calculation unit (330) described in Fig. 11 has been described as providing the accumulated deviation code (FB_DEV<0:3>) calculated by accumulating the deviation code (DEV<0:3>) to the storage unit (320), but the proposed invention is not limited thereto. According to an embodiment, the mean-deviation calculation unit (330) may provide the deviation code (DEV<0:3>) to the storage unit (320) without accumulating it.

Figure 12 is a detailed block diagram of the calibration control circuit (150) of Figure 5.

Referring to FIG. 12, the calibration control circuit (150) may include an interval definition unit (510) and a control signal generation unit (520).

The interval definition unit (510) can generate first to sixth interval definition signals (C0_C1 to C5_C6) that are activated for each period of the seed signal (SEED) when the training mode signal (CAL_EN) is activated. For example, the interval definition unit (510) can generate a first interval definition signal (C0_C1) that has an activation period between the first rising edge and the second rising edge of the seed signal (SEED), and can generate a second interval definition signal (C1_C2) that has an activation period between the second rising edge and the third rising edge. The first to sixth interval definition signals (C0_C1 to C5_C6) can be signals that are activated at a logic low level. In addition, the interval definition unit (510) can generate an interval signal (SAR_EN) that is activated according to a training mode signal (CAL_EN) and deactivated according to one of the first to sixth interval definition signals (C0_C1 to C5_C6). Preferably, the interval definition unit (510) can deactivate the interval signal (SAR_EN) according to a fifth interval definition signal (C4_C5) among the first to sixth interval definition signals (C0_C1 to C5_C6).

The control signal generation unit (520) can generate the first to fourth register control signals (REG0P to REG3P) according to the first to sixth section definition signals (C0_C1 to C5_C6) and the section signal (SAR_EN).

In more detail, the control signal generator (520) may include first to third control signal generators (522 to 526). The first control signal generator (522) may generate first to fourth register control signals (REG0P to REG3P) according to the first to sixth interval definition signals (C0_C1 to C5_C6), the interval signal (SAR_EN), the third pulse signal (P2), and the fifth pulse signal (P4). The second control signal generator (524) may generate an average calculation signal (REG_QW), a selection signal (REG_SEL<0:2>), and a training end signal (CAL_OFF) according to the first to sixth interval definition signals (C0_C1 to C5_C6), the interval signal (SAR_EN), and the third pulse signal (P2). The third control signal generator (526) can generate an accumulated clock (ACC_CLK) and an accumulated reset signal (ACC_RST) according to the first to sixth interval definition signals (C0_C1 to C5_C6), an interval signal (SAR_EN), a third pulse signal (P2), and a seed signal (SEED).

Fig. 13 is a circuit diagram of the section definition part (510) of Fig. 12.

Referring to FIG. 13, the interval definition unit (510) may include first to eighth D-flip-flops (511 to 518), first to sixth comparators (511A to 511F), and a clock combiner (511G).

The first to seventh D flip-flops (511 to 517) are connected in series, and can receive a training mode signal (CAL_EN) as a set bar signal (SB) and a seed signal (SEED) as a clock signal to output the first to seventh reserve section signals (C0 to C6). The first D flip-flop (511) can receive an inverted signal of an output terminal (Q) of the seventh D flip-flop (517) as an input terminal (D) and output the first reserve section signal (C0) as an output terminal (Q). The second to seventh D flip-flops (512 to 517) can receive an output signal of a previous stage as an input terminal (D) and sequentially output the second to seventh reserve section signals (C1 to C6) as an output terminal (Q).

The first to sixth comparators (511A to 511F) can compare two adjacent reserve section signals (C1 to C6) to output the first to sixth section defining signals (C0_C1 to C5_C6). The first to sixth comparators (511A to 511F) can be implemented as XNOR gates that perform a logic XNOR operation on two adjacent reserve section signals (C1 to C6) to output the first to sixth section defining signals (C0_C1 to C5_C6). For example, the first comparator (511A) can output the first section defining signal (C0_C1) that becomes a logic low level when the first reserve section signal (C0) and the second reserve section signal (C1) have different logic levels.

The clock combiner (511G) can generate an interval clock (T2) by performing a logic OR operation on the fifth interval defining signal (C4_C5) and the seed signal (SEED). That is, the clock combiner (511G) can output an interval clock (T2) at a logic low level when both the fifth interval defining signal (C4_C5) and the seed signal (SEED) are at a logic low level.

The 8th D flip-flop (518) can receive a training mode signal (CAL_EN) as a set bar signal (SB), a ground voltage (VSS) as an input terminal (D), and an interval clock (T2) as a clock signal to output an interval signal (SAR_EN).

Figure 14 is a waveform diagram for explaining the operation of the interval definition part (510) of Figure 13.

Referring to FIG. 14, during the deactivation period of the training mode signal (CAL_EN), i.e., before the training operation, the first to eighth D flip-flops (511 to 518) are set to the first to seventh reserve period signals (C0 to C6) and the period signal (SAR_EN) to a logic high level.

When the training mode signal (CAL_EN) is activated, the first to seventh D flip-flops (511 to 517) can sequentially output the first to seventh reserve section signals (C0 to C6) at a logic low level according to the rising edge of the seed signal (SEED). The first to sixth comparators (511A to 511F) can output the first to sixth section defining signals (C0_C1 to C5_C6) at a logic low level when two adjacent reserve section signals (C1 to C6) have different logic levels.

The clock combiner (511G) can output an interval clock (T2) at a logic low level when both the fifth interval definition signal (C4_C5) and the seed signal (SEED) are at a logic low level. The eighth D flip-flop (518) can output an interval signal (SAR_EN) by deactivating it to a logic low level in synchronization with the rising edge of the interval clock (T2).

Fig. 15 is a circuit diagram of the control signal generation unit (520) of Fig. 12.

Referring to FIG. 15, the first control signal generator (522) may include first to fourth combiners (522A to 522D).

The first combiner (522A) can output the first register control signal (REG0P) according to the second interval definition signal (C1_C2) and the fifth pulse signal (P4) when the interval signal (SAR_EN) is activated, and can output the first register control signal (REG0P) according to the third interval definition signal (C2_C3) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. The first combiner (522A) can output the first register control signal (REG0P) when the second interval definition signal (C1_C2) and the fifth pulse signal (P4) are both at a logic low level when the interval signal (SAR_EN) is activated, and can output the first register control signal (REG0P) when the third interval definition signal (C2_C3) and the third pulse signal (P2) are both at a logic low level when the interval signal (SAR_EN) is deactivated. The second combiner (522B) can output the second register control signal (REG1P) according to the third interval definition signal (C2_C3) and the fifth pulse signal (P4) when the interval signal (SAR_EN) is activated, and can output the second register control signal (REG1P) according to the fourth interval definition signal (C3_C4) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. The third combiner (522C) can output the third register control signal (REG2P) according to the fourth interval definition signal (C3_C4) and the fifth pulse signal (P4) when the interval signal (SAR_EN) is activated, and can output the third register control signal (REG2P) according to the fifth interval definition signal (C4_C5) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. The fourth combiner (522D) can output the fourth register control signal (REG3P) according to the fifth interval definition signal (C4_C5) and the fifth pulse signal (P4) when the interval signal (SAR_EN) is activated.

The second control signal generator (524) may include fifth to eighth combiners (524A to 524D).

The fifth combiner (524A) can output the first bit (REG_SEL<0>) of the selection signal (REG_SEL<0:2>) according to the first interval defining signal (C0_C1) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. That is, the fifth combiner (524A) can output the first bit (REG_SEL<0>) when both the first interval defining signal (C0_C1) and the third pulse signal (P2) become logic low levels. At this time, the fifth combiner (524A) can output the average calculation signal (REG_QW) having the same logic level as the first bit (REG_SEL<0>). The sixth combiner (524B) can output the second bit (REG_SEL<1>) of the selection signal (REG_SEL<0:2>) according to the third interval definition signal (C2_C3) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. The seventh combiner (524C) can output the third bit (REG_SEL<2>) of the selection signal (REG_SEL<0:2>) according to the fourth interval definition signal (C3_C4) and the third pulse signal (P2) when the interval signal (SAR_EN) is deactivated. The 8th combiner (524D) can generate a clock pulse signal (CAL_OFFP) according to the 6th interval definition signal (C5_C6) and the 3rd pulse signal (P2) when the interval signal (SAR_EN) is deactivated, and can activate and output a training end signal (CAL_OFF) to a logic high level according to the clock pulse signal (CAL_OFFP).

The third control signal generator (526) may include a ninth combiner (526A) and a tenth combiner (526B).

The ninth combiner (526A) can output an accumulation clock (ACC_CLK) according to the second to fifth interval definition signals (C1_C2 to C4_C5) and the seed signal (SEED) when the interval signal (SAR_EN) is activated, and can output an accumulation clock (ACC_CLK) according to the second to fourth interval definition signals (C1_C2 to C3_C4) and the seed signal (SEED) when the interval signal (SAR_EN) is deactivated. That is, the ninth combiner (526A) can output an accumulation clock (ACC_CLK) when the seed signal (SEED) becomes a logic low level when any one of the second to fifth interval definition signals (C1_C2 to C4_C5) is at a logic low level when the interval signal (SAR_EN) is activated. In addition, the 8th combiner (526A) can output an accumulated clock (ACC_CLK) when the seed signal (SEED) becomes a logic low level when any one of the 2nd to 4th interval defining signals (C1_C2 to C3_C4) is at a logic low level when the interval signal (SAR_EN) is deactivated. The 10th combiner (526B) can output an accumulated reset signal (ACC_RST) according to the 2nd interval defining signal (C1_C2) and the 3rd pulse signal (P2) when the interval signal (SAR_EN) is deactivated.

Meanwhile, the logics of the first to tenth combiners (522A to 522D, 524D to 524C, 526A, 526B) illustrated in FIG. 15 are only an example and the proposed invention is not limited thereto, and can be implemented with various logics for controlling the timing of the calibration circuit (140) and the calibration control circuit (150).

Hereinafter, the operation of the calibration circuit (140) and the calibration control circuit (150) will be described with reference to FIGS. 5 to 16b.

FIGS. 16A and 16B are waveform diagrams for explaining the operation of the calibration circuit (140) and the calibration control circuit (150) of FIG. 5. For reference, although not shown in FIGS. 16A and 16B, as shown in FIG. 14, the first to sixth interval defining signals (C0_C1 to C5_C6) may have sequential activation intervals between adjacent rising edges of the seed signal (SEED). For example, the first interval defining signal (C0_C1) may be activated to a logic low level in the interval between the first rising edge and the second rising edge of the seed signal (SEED) and in the interval between the seventh rising edge and the eighth rising edge.

Referring to FIG. 16A, the seed signal (SEED) and the first to seventh pulse signals (P0 to P6) are sequentially activated according to the inverted falling signal (QDQSB). The phase difference of the delayed rising signal (IDQSD) and the falling signal (QDQS) is compared to output the comparison signal (COMP), and according to the seed signal (SEED) and the first to seventh pulse signals (P0 to P6), the comparison signal (COMP) is converted into the reverse order (i.e., DOUT_PRE<5:0>) of the preliminary code (DOUT_PRE<0:5>) and output. At this time, according to the trimming section signal (TRIM) of the logic high level, the preliminary code (DOUT_PRE<0:5>) is output as the trimming code (D_TRIM<0:5>), so that the delay amount of the first trimmer (312) is set. The above operations may be repeatedly performed whenever a rising signal (IDQS) and a falling signal (QDQS) are input, so that a trimming code (D_TRIM<0:5>) may be finally output. The above operations may be defined as an initial trimming setting operation performed during an initial section (i.e., one period of the seed signal (SEED)) of the activation section of the first pattern data (BL0_CALP) described in Fig. 4.

After this, the trimming interval signal (TRIM) is deactivated to a logic low level according to the activation of the 7th pulse signal (P6).

During the latter period of the activation period of the first pattern data (BL0_CALP) (i.e., the next period of the seed signal (SEED)), a preliminary code (DOUT_PRE<0:5>) corresponding to the phase difference between the rising signal (IDQS) and the falling signal (QDQS) is output as a detection code (DOUT<0:3>) according to a trimming period signal (TRIM) of a logic low level, so that the delay amount of the second trimmer (314) is adjusted. When the first register control signal (REG0P) is activated, the detection code (DOUT<0:3>) is finally stored in the first register (322), and the first storage value stored in the first register (322) is output as a sum signal (SUM<0:3>) according to the accumulation clock (ACC_CLK).

During the activation section of the second pattern data (BL1_CALP) (i.e., the next cycle of the seed signal (SEED)), a preliminary code (DOUT_PRE<0:5>) corresponding to the phase difference between the rising signal (IDQS) and the falling signal (QDQS) is output as a detection code (DOUT<0:3>), so that the delay amount of the second trimmer (314) is adjusted. The detection code (DOUT<0:3>) is finally stored in the second register (323) according to the second register control signal (REG1P), and according to the accumulation clock (ACC_CLK), the existing sum signal (SUM<0:3>) (i.e., the first storage value) and the second storage value stored in the second register (323) can be cumulatively added and output as a sum signal (SUM<0:3>). Similarly, during the activation period of the third pattern data (BL2_CALP) (i.e., one cycle following the seed signal (SEED)), according to the third register control signal (REG2P) and the accumulation clock (ACC_CLK), the existing sum signal (SUM<0:3>) (i.e., the sum of the first and second storage values) and the third storage value stored in the third register (324) may be cumulatively added and output as the sum signal (SUM<0:3>). Finally, during the initial period of the activation period of the fourth pattern data (BL3_CALP) (i.e., one cycle following the seed signal (SEED)), the first to fourth storage values may be cumulatively added and finally output as the sum signal (SUM<0:3>).

As described above, during the latter period of the activation period of the first pattern data (BL0_CALP), the activation periods of the second and third pattern data (BL1_CALP, BL2_CALP) and the early period of the activation period of the fourth pattern data (BL3_CALP), an operation of storing a detection code (DOUT<0:3>) corresponding to the phase difference between the rising signal (IDQS) and the falling signal (QDQS) in each register can be defined as a phase detection operation.

Thereafter, the interval signal (SAR_EN) is deactivated to a logic low level. Accordingly, the average-deviation calculation operation of the average-deviation calculation unit (330) can be performed.

Referring to FIG. 16b, the first bit (REG_SEL<0>) of the average calculation signal (REG_QW) and the selection signal (REG_SEL<0:2>) is activated. Based on the sum signal (SUM<0:3>) according to the average calculation signal (REG_QW), an average code (AVG<0:3>) can be calculated, and based on the first bit (REG_SEL<0>), a deviation code (DEV<0:3>) can be calculated by subtracting a first storage value from the average code (AVG<0:3>).

Meanwhile, the accumulated reset signal (ACC_RST) may be activated so that the summation signal (SUM<0:3>) may be initialized. The deviation code (DEV<0:3>) is output as the summation signal (SUM<0:3>) according to the accumulated clock (ACC_CLK). At this time, the summation signal (SUM<0:3>) may be provided as the accumulated deviation code (FB_DEV<0:3>). The first register control signal (REG0P) may be activated according to the third pulse signal (P2) so that the accumulated deviation code (FB_DEV<0:3>) may be re-stored in the first register (322). At the same time, the second bit (REG_SEL<1>) of the selection signal (REG_SEL<0:2>) may be activated, and the deviation code (DEV<0:3>) may be calculated by subtracting the second storage value from the average code (AVG<0:3>). According to the accumulated clock (ACC_CLK), the deviation code (DEV<0:3>) and the existing sum signal (SUM<0:3>) can be accumulated and output as the accumulated deviation code (FB_DEV<0:3>). When the second register control signal (REG1P) is activated, the accumulated deviation code (FB_DEV<0:3>) can be re-stored in the second register (323). Similarly, when the third bit (REG_SEL<2>) of the selection signal (REG_SEL<0:2>) and the accumulation clock (ACC_CLK) are sequentially activated, the deviation code (DEV<0:3>) and the existing summation signal (SUM<0:3>) are cumulatively added and output as the accumulated deviation code (FB_DEV<0:3>), and the accumulated deviation code (FB_DEV<0:3>) can be restored in the third register (324) according to the third register control signal (REG2P).

According to the above mean-deviation calculation operation, the accumulated deviation code (FB_DEV<0:3>) can be stored in the first to third registers (322 to 324), respectively. The accumulated deviation code (FB_DEV<0:3>) stored in the first to third registers (322 to 324) can be output as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>), respectively, and can be used to correct the duty ratios of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK).

FIG. 17 is a flowchart for explaining a training operation of a semiconductor device according to an embodiment of the present invention. FIG. 18 is a diagram showing duty correction of output clocks according to the training operation of FIG. 17.

Referring to FIG. 17, the transmitting circuit (120) outputs a training signal (TRS) to the data strobe pad (DQS_P) as a pulse of H-L-L-L corresponding to the first output clock (R1DOCLK) during the activation period of the first pattern data (BL0_CALP) in the training mode (S1701). The receiving circuit (130) generates a rising signal (IDQS) and a falling signal (QDQS) that are activated at the rising edge and falling edge of the training signal (TRS) input to the data strobe pad (DQS_P), respectively (S1702).

As described in FIG. 16a, during the initial section of the activation section of the first pattern data (BL0_CALP), the calibration circuit (140) performs an initial trimming setting operation that sets the delay amount of the first trimmer (312) using the trimming code (D_TRIM<0:5>) corresponding to the phase difference of the rising signal (IDQS) and the falling signal (QDQS) (S1703).

Thereafter, during the latter period of the activation period of the first pattern data (BL0_CALP), the calibration circuit (140) performs a phase detection operation of storing a detection code (DOUT<0:3>) corresponding to the phase difference between the rising signal (IDQS) and the falling signal (QDQS) in the first register (322) (S1704).

Thereafter, during the activation section of the second pattern data (BL1_CALP), the training signal (TRS) is output to the data strobe pad (DQS_P) as a corresponding L-H-L-L pulse corresponding to the second output clock (F1DOCLK) (S1706). The receiving circuit (130) generates a rising signal (IDQS) and a falling signal (QDQS) which are activated at the rising edge and the falling edge of the training signal (TRS), respectively (S1707). The calibration circuit (140) performs a phase detection operation of storing a detection code (DOUT<0:3>) corresponding to the phase difference between the rising signal (IDQS) and the falling signal (QDQS) in the second register (323) (S1704).

Similarly, during the activation period of the third pattern data (BL2_CALP), the training signal (TRS) is output to the data strobe pad (DQS_P) as a pulse of L-L-H-L corresponding to the third output clock (R2DOCLK) (S1706), and the receiving circuit (130) generates a rising signal (IDQS) and a falling signal (QDQS) which are activated at the rising edge and the falling edge of the training signal (TRS), respectively (S1707). The calibration circuit (140) performs a phase detection operation of storing a detection code (DOUT<0:3>) corresponding to the phase difference of the rising signal (IDQS) and the falling signal (QDQS) in the third register (324) (S1704).

Finally, during the activation period of the fourth pattern data (BL3_CALP), the training signal (TRS) is output to the data strobe pad (DQS_P) as a pulse of L-L-L-H corresponding to the fourth output clock (F2DOCLK) (S1706). The receiving circuit (130) generates a rising signal (IDQS) and a falling signal (QDQS) which are activated at the rising edge and the falling edge of the training signal (TRS), respectively (S1707). The calibration circuit (140) performs a phase detection operation of storing a detection code (DOUT<0:3>) corresponding to the phase difference of the rising signal (IDQS) and the falling signal (QDQS) in the fourth register (325) (S1704). When the phase detection operation is performed, the first to fourth storage values stored in the first to fourth registers (322 to 325) can be accumulated and finally output as a sum signal (SUM<0:3>).

After this, when the interval signal (SAR_EN) is deactivated to a logic low level (S1705), the average-deviation calculation operation can be performed. The calibration circuit (140) calculates the average code (AVG<0:3>) based on the sum signal (SUM<0:3>) (S1708). The calibration circuit (140) can re-store the deviation code (DEV<0:3>) obtained by subtracting the first storage value from the average code (AVG<0:3>) in the first register (322), add the deviation code (DEV<0:3>) obtained by subtracting the second storage value from the average code (AVG<0:3>) and the previous accumulated deviation code to re-store the new accumulated deviation code (FB_DEV<0:3>) in the second register (323), and add the deviation code (DEV<0:3>) obtained by subtracting the third storage value from the average code (AVG<0:3>) and the previous accumulated deviation code to re-store the new accumulated deviation code (FB_DEV<0:3>) in the third register (324) (S1709). The first to third stored values that have been restored can be output as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>), respectively. Thereafter, the clock generation circuit (110) can correct the duty ratio of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) according to the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>) (S1710).

Referring to FIG. 18, it is assumed that before the training operation, the duty ratios of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) are different so that the 1-bit pulse width of the strobe signal (DQS) is output as 254 ps - 215 ps - 248 ps - 203 ps. Since the strobe signal (DQS) is generated according to the four output clocks, the 4-bit pulse width can be constant. That is, the 4-bit pulse width is fixed to 254 + 215 + 248 + 203 = 950 ps, and the ideal 1-bit pulse width can be 230 ps. At this time, even if there is an offset (err) that may occur as the strobe signal (DQS) passes through the input/output path, since it passes through the same path, the 1-bit pulse width of the strobe signal (DQS) can be 254+err ps - 215+err ps - 248+err ps - 203+err ps.

In an embodiment of the present invention, the calibration circuit (140) can produce an average code (AVG<0:3>) of 230+err based on a sum signal (SUM<0:3>) of 950+4*err. The calibration circuit (140) re-stores the -24 ps accumulated deviation code (FB_DEV<0:3>) obtained by subtracting the first storage value of 254+err from the average code (AVG<0:3>) into the first register (322), adds the 15 ps deviation code (DEV<0:3>) obtained by subtracting the second storage value of 215+err from the average code (AVG<0:3>) and the previous -24 ps accumulated deviation code to re-store the -9 ps accumulated deviation code (FB_DEV<0:3>) into the second register (323), and adds the -18 ps deviation code (DEV<0:3>) obtained by subtracting the third storage value of 248+err from the average code (AVG<0:3>) and the previous -9 ps accumulated deviation code to generate the -27 ps accumulated deviation. The code (FB_DEV<0:3>) can be re-saved to the third register (324).

The first to third stored values (-24 ps, -9 ps, -27 ps) that have been restored are output as the first to third calibration codes (R1_F1<0:3>, F1_R2<0:3>, R2_F2<0:3>), respectively, so that the duty ratio of the first to fourth output clocks (R1DOCLK, F1DOCLK, R2DOCLK, F2DOCLK) can be corrected.

As described above, the semiconductor device according to the embodiment of the present invention can maintain the 1-bit pulse width of the strobe signal constant, thereby improving the reliability of the data output operation.

Although the technical idea of the present invention has been specifically described according to the above preferred embodiments, it should be noted that the above embodiments are for the purpose of explanation and not for the purpose of limitation. In addition, a person skilled in the art of the present invention will be able to understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the logic gates and transistors exemplified in the above-described embodiments may have to be implemented in different positions and types depending on the polarity of the input signal.

Claims (20)

A transmitter circuit that sequentially outputs pulses corresponding to the first to Nth output clocks to the data strobe pad in training mode;
A receiving circuit which generates a rising signal and a falling signal which are activated respectively at the rising edge and the falling edge of the pulse input to the data strobe pad;
A calibration circuit that sequentially stores detection codes corresponding to the phase difference of the rising signal and the falling signal in the first to Nth registers according to the interval signal, calculates an average value of the first to Nth stored values, and re-stores the deviation between the average value and the first to Nth stored values in the first to Nth registers; and
A clock generation circuit that corrects the duty ratio of the first to Nth output clocks by using the restored values of the first to Nth registers
A semiconductor device comprising:
In paragraph 1,
In the training mode, a calibration control circuit that generates the first to Nth register control signals that are sequentially activated with the interval signal according to a seed signal that is activated at a predetermined cycle according to at least one of the rising signal and the falling signal.
A semiconductor device further comprising:
In the second paragraph,
The above calibration circuit,
When the above-mentioned section signal is activated, the detection code is sequentially stored in the first to Nth registers according to the first to Nth register control signals, and the first to Nth stored values are accumulated to generate a sum signal.
When the above-mentioned interval signal is deactivated, the average value is calculated based on the above-mentioned sum signal, and the deviation between the average value and the first to Nth storage values is re-stored in the first to Nth registers.
Semiconductor devices.
In the second paragraph,
The above calibration control circuit,
An interval defining unit that generates a plurality of interval defining signals that are activated for each period of the seed signal, and generates the interval signal that is activated according to a training mode signal and deactivated according to one of the plurality of interval defining signals; and
A control signal generation unit that generates the first to Nth register control signals according to the above-mentioned interval signals and the above-mentioned interval definition signals.
A semiconductor device comprising:
In paragraph 1,
The above calibration circuit,
A detection unit that detects the phase difference between the rising signal and the falling signal and generates the detection code;
A storage unit that sequentially stores the detection code in the first to Nth registers according to the first to Nth register control signals when the above-mentioned interval signal is activated, and sequentially stores the deviation in the first to Nth registers according to the first to Nth register control signals when the above-mentioned interval signal is deactivated; and
When the above-mentioned interval signal is activated, the first to Nth storage values are accumulated and added according to the first to Nth register control signals to generate a sum signal, and when the above-mentioned interval signal is deactivated, the average value is calculated based on the sum signal, and an average-deviation calculation unit calculates the deviation between the average value and the first to Nth storage values.
A semiconductor device comprising:
In paragraph 5,
The above detection unit,
A first trimmer for delaying the rising signal, the delay amount being set according to the trimming code;
A second trimmer, which adjusts the delay amount according to the above detection code and delays the output of the first trimmer to output a delayed rising signal;
A comparator for comparing the phase difference between the delayed rising signal and the falling signal and outputting a comparison signal; and
A trimming controller that generates a seed signal that is activated at a predetermined cycle according to the polling signal, and generates the trimming code and the detection code corresponding to the comparison signal according to the seed signal.
A semiconductor device comprising:
In paragraph 6,
The above trimming controller,
A period generator for generating the seed signal and a plurality of pulse signals that are sequentially activated according to the polling signal;
A code converter that converts the comparison signal into a preliminary code according to the seed signal and the pulse signals;
An initial interval setting unit for generating a trimming interval signal according to one of the above pulse signals; and
A code output device that outputs the preliminary code as the trimming code or the detection code according to the trimming section signal.
A semiconductor device comprising:
In paragraph 5,
The above storage unit is,
A storage selector for selecting the detection code when the above-mentioned interval signal is activated and for selecting and outputting the deviation when the above-mentioned interval signal is deactivated; and
The first to Nth registers are sequentially activated according to the first to Nth register control signals and store the output of the storage selector.
A semiconductor device comprising:
In paragraph 5,
The above mean-deviation calculation section,
An accumulative summing unit that accumulates and sums the first to Nth storage values according to the first to Nth register control signals and outputs the summing signal when the above-mentioned interval signal is activated;
When the above-mentioned interval signal is deactivated, an average calculation unit that calculates the average value based on the above-mentioned sum signal; and
A deviation calculation unit that calculates the deviation by subtracting the first to Nth storage values from the average value.
A semiconductor device comprising:
In paragraph 1,
The above transmitting circuit,
A pattern generation unit that is enabled according to a training mode signal, sequentially activated using the first and second test signals, and generates first to Nth pattern data having non-overlapping activation sections;
A serialization unit that latches the first to Nth pattern data according to the first to Nth output clocks, and serializes the latched signals to generate a pull-up control signal and a pull-down control signal; and
An output driver that drives the data strobe pad according to the pull-up control signal and the pull-down control signal.
A semiconductor device comprising:
In Article 10,
The above pattern generating unit,
A frequency divider that divides the frequencies of the first and second test signals into predetermined cycles according to the training mode signal to generate a first divided clock and a second divided clock;
A first signal generator generating a plurality of shift signals sequentially activated according to the first divided clock;
A second signal generator that receives the last shift signal of the first signal generator and generates a plurality of shift signals that are sequentially activated according to the second divided clock; and
A pattern combiner that outputs the first to Nth pattern data by combining at least two of the above shift signals.
A semiconductor device comprising:
In Article 11,
The above pattern combiner is,
A semiconductor device that combines one of the shift signals provided from the first signal generator and one of the shift signals provided from the second signal generator to output one of the first to Nth pattern data.
In paragraph 1,
The above receiving circuit,
An input buffer that buffers the pulse input to the data strobe pad according to the training mode signal and outputs an internal strobe signal; and
A divider that divides the frequency of the internal strobe signal into a predetermined number and generates the rising signal and the falling signal, which are activated at the rising edge and the falling edge of the divided signal, respectively.
A semiconductor device comprising:
A step of sequentially outputting pulses corresponding to the first to Nth output clocks to the data strobe pad in training mode;
A step of generating a rising signal and a falling signal, which are activated respectively at the rising edge and falling edge of the pulse input to the data strobe pad;
A step of sequentially storing detection codes corresponding to the phase difference of the rising signal and the falling signal in the first to Nth registers, and generating a sum signal by accumulating and adding the first to Nth stored values;
A step of calculating an average value of the first to Nth storage values based on the above sum signal, and re-storing the deviation between the average value and the first to Nth storage values in the first to Nth registers; and
A step of correcting the duty ratio of the first to Nth output clocks using the restored values of the first to Nth registers.
A training method for a semiconductor device including a .
In Article 14,
The step of sequentially outputting pulses corresponding to the first to Nth output clocks to the data strobe pad is:
In the above training mode, a step of generating first to Nth pattern data having activation sections that are sequentially activated and do not overlap each other; and
A step of latching the first to Nth pattern data according to the first to Nth output clocks and outputting them to the data strobe pad.
A training method for a semiconductor device including a .
In Article 14,
The above N is 4, and the pulse corresponding to the first output clock has a pattern of HLLL,
The pulse corresponding to the above second output clock has a pattern of LHLL,
The pulse corresponding to the third output clock has a pattern of LLHL,
The pulse corresponding to the above fourth output clock is the pattern of LLLH
A training method for a semiconductor device having a .
In Article 14,
A step of first delaying the rising signal according to a trimming code;
A step of generating a delayed rising signal by delaying the first delayed signal a second time according to the detection code;
A step of comparing the phase difference between the delayed rising signal and the falling signal and outputting a comparison signal; and
A step of generating a seed signal that is activated at a predetermined cycle according to the polling signal, and generating the trimming code and the detection code corresponding to the comparison signal according to the seed signal.
A training method for a semiconductor device further comprising:
A detection unit that detects the phase difference between a rising signal and a falling signal to generate a detection code;
A storage unit which selects the detection code or the accumulated deviation code according to the interval signal and stores the selected code in the first to Nth registers according to the first to Nth register control signals;
An accumulative adding unit that cumulatively adds the first to Nth storage values stored in the first to Nth registers according to the first to Nth register control signals and the interval signal and outputs a sum signal, or cumulatively adds deviation codes and outputs the accumulated deviation code;
An average calculation unit that calculates an average value based on the above sum signal; and
A deviation calculation unit that selects one of the first to N-1 storage values according to a selection signal and outputs the difference between the average value and the selected storage value as the deviation code.
A calibration circuit including:
In Article 18,
The above cumulative sum is,
A first accumulator selector for selecting and outputting one of the first to Nth storage values according to the first to Nth register control signals;
A second accumulator selector that selects and outputs one of the outputs of the first accumulator selector and the deviation code according to the above-mentioned interval signal;
An adder for adding the output of the second cumulative selector and the sum signal or the cumulative deviation code; and
A flip-flop that stores the output of the adder according to the cumulative clock.
A calibration circuit including:
In Article 18,
The above deviation calculation section,
A deviation selector for selecting one of the first to third storage values according to the selection signal; and
A subtractor that outputs the difference between the above average value and the output of the above deviation selector as the above deviation code.
A calibration circuit including: