KR102648973B1 - Display Having Thermoelectric Cooling System - Google Patents

Abstract

The present invention relates to a flat panel display device with a thermoelectric cooling system. The display device according to the present invention includes a display panel, a gate driving circuit, a light-shielding metal layer, an N-type semiconductor pattern, a P-type semiconductor pattern, a first electrode, and a second electrode. The display panel has a display area and a non-display area disposed on the outer periphery of the display area. The gate driving circuit is disposed in a non-display area of the display panel. The light-shielding metal layer is disposed below the gate driving circuit. The N-type semiconductor pattern is connected to one side of the light-shielding metal layer. The P-type semiconductor pattern is connected to the other side of the light-shielding metal layer. The first electrode is connected to the N-type semiconductor pattern. The second electrode is connected to the P-type semiconductor pattern.

Description

Display device having a thermoelectric cooling system {Display Having Thermoelectric Cooling System}

The present invention relates to a flat panel display device with a thermoelectric cooling system. In particular, the present invention relates to a flat panel display device that improves the thermal reliability of thin film transistors by providing a thermoelectron cooling system using the Peltier Effect.

Various thin flat display devices are being developed that can reduce the weight and volume, which are disadvantages of the cathode ray tube. These thin film display devices include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Organic Light Emitting Display device. ; OLED), etc.

Because thin film display devices are thin and light, they are widely used as display devices in mobile communication terminals and portable information processors. In particular, in portable or mobile devices, the demand for display panels that are thinner, lighter, and consume less power is increasing.

Figure 1 is a diagram schematically showing a liquid crystal display device, a type of flat panel display device according to the prior art. Referring to FIG. 1, a liquid crystal display according to the prior art includes a display panel (DP) in which a display area (AA) and a non-display area (NA) are defined. The display area AA is defined in the central area of the display panel DP. The non-display area (NA) is defined around the display area (AA).

A plurality of pixels (PXL) are arranged in a matrix manner in the display area (AA) of the display panel (DP). Pixels PXL are defined by a plurality of gate lines GL extending in the horizontal direction and data lines DL extending in the vertical direction. One thin film transistor (T) is disposed in each pixel (PXL).

At least one thin film transistor T is formed at each intersection of the data lines DL and the gate lines GL. The thin film transistor T supplies the data voltage from the data line DL to the pixel electrode P in response to the gate pulse from the gate line GL. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode P, which charges a data voltage through the thin film transistor T, and the common electrode C, to which a common voltage Vcom is applied. A storage capacitance (Cst) that maintains the voltage of the liquid crystal cell for one frame period may be connected to the liquid crystal cell (Clc).

A drive IC is disposed in the non-display area (NA) of the display panel (DP). The drive IC includes a data drive IC (SIC) and a gate drive IC (GIP1, GIP2). The drive IC is a circuit for driving pixels (PXL) arranged in the display area (AA) of the display panel (DP). A data drive IC (SIC) can be mounted together on a flexible circuit board, such as a chip on film (COF). The input terminal of the COF may be bonded to a printed circuit board (PCB), and the output terminal of the COF may be bonded to the lower substrate of the display panel (PNL). The gate drive ICs (GIP1, GIP2) may be placed directly on the bezel area of the display panel (DP) according to the GIP (Gate-driver In Panel) circuit.

The data drive IC (SIC) samples digital video data of the input image under the control of a timing controller (not shown), latches it, and converts it into data in a parallel data system. The data drive IC (SIC) generates a data voltage by converting digital video data into an analog gamma compensation voltage using a digital to analog converter (ADC) under the control of a timing controller and transmits the data voltage to the data wires. (DL).

The gate drive ICs (GIP1, GIP2) sequentially supply gate pulses (or scan pulses) synchronized to the data voltage from the first gate line to the nth gate line under the control of a timing controller. According to the gate pulse generated from the gate drive IC (GIP1, GIP2), the image information supplied from the data drive IC (SIC) is transmitted to the pixel (PXL) to display the image.

In particular, by forming the gate drive ICs GIP1 and GIP2 on the display panel DP at the same time as the thin film transistor T in the display area AA, the non-display area NA in the display panel DP is formed. The area it occupies can be made smaller. On the other hand, gate drive ICs (GIP1, GIP2) operate at high speeds, so they are devices that generate a lot of heat. Therefore, due to the heat generated in a small area, the functions of the elements constituting the gate drive ICs (GIP1 and GIP2) may be degraded due to heat.

The purpose of the present invention is to overcome the above problems and to provide a display device having a cooling structure. Another object of the present invention is to provide a thin film display device that forms a drive IC together and has a system for cooling the heat generated by the drive IC. Another object of the present invention is to provide a flexible and/or ultra-thin display device that cools heat generated by a drive IC using a thermoelectric effect.

To achieve the above object, a display device according to the present invention includes a display panel, a gate driving circuit, a light-shielding metal layer, an N-type semiconductor pattern, a P-type semiconductor pattern, a first electrode, and a second electrode. The display panel has a display area and a non-display area disposed on the outer periphery of the display area. The gate driving circuit is disposed in a non-display area of the display panel. The light-shielding metal layer is disposed below the gate driving circuit. The N-type semiconductor pattern is connected to one side of the light-shielding metal layer. The P-type semiconductor pattern is connected to the other side of the light-shielding metal layer. The first electrode is connected to the N-type semiconductor pattern. The second electrode is connected to the P-type semiconductor pattern.

In one example, a (+) voltage is applied to the first electrode. A (-) voltage is applied to the second electrode.

Additionally, the display device according to the present invention includes a display panel, a gate driving circuit, two light-shielding metal layers, a first N-type semiconductor pattern, a first P-type semiconductor pattern, a first electrode, and a second electrode. The display panel has a display area and a non-display area disposed on the outer periphery of the display area. The gate driving circuit is disposed in a non-display area of the display panel. The two light-shielding metal layers are disposed separately from each other under the gate driving circuit. The first N-type semiconductor pattern is connected to one side of the first light-shielding metal layer. The first P-type semiconductor pattern is connected to the other side of the first light-shielding metal layer. The first electrode is connected to the first N-type semiconductor pattern. The second electrode is connected to the first P-type semiconductor pattern.

For example, it further includes a second N-type semiconductor pattern, a second P-type semiconductor pattern, and a third electrode. The second N-type semiconductor pattern is connected to one side of the second light-shielding metal layer. The second P-type semiconductor pattern is connected to the other side of the second light-shielding metal layer. The third electrode is connected to the second P-type semiconductor pattern. The second N-type semiconductor pattern is connected to the second electrode.

In one example, a (+) voltage is applied to the first electrode. A (-) voltage is applied to the third electrode.

Additionally, the display device according to the present invention includes a display panel, a gate driving circuit, a plurality of light-shielding metal layers, a plurality of N-type semiconductor patterns, a plurality of P-type semiconductor patterns, and a plurality of electrodes. The display panel has a display area on a substrate and a non-display area disposed on the outer periphery of the display area. The gate driving circuit is disposed in a non-display area of the display panel. The n light-shielding metal layers are arranged separately from each other under the gate driving circuit. The n-th N-type semiconductor pattern is connected to one side of the n-th light-shielding metal layer. The n-th P-type semiconductor pattern is connected to the other side of the n-th light-shielding metal layer. The nth electrode is connected to the nth N-type semiconductor pattern. The (n+1)th electrode is connected to the nth P-type semiconductor pattern.

For example, the (n+1)th N-type semiconductor pattern is connected to the (n+1)th electrode.

In one example, a (+) voltage is applied to the first electrode. To the last electrode, (-) voltage is applied.

For example, N-type semiconductor patterns are arranged separately on a substrate. The P-type semiconductor patterns are arranged separately from the N-type semiconductor patterns. The light-shielding metal layers are disposed on the insulating film covering the N-type semiconductor patterns and the P-type semiconductor patterns. The electrodes are disposed on the insulating film.

For example, N-type semiconductor patterns are arranged separately on a substrate. The P-type semiconductor patterns are arranged separately between the N-type semiconductor patterns on a first insulating film covering the N-type semiconductor patterns. The light-shielding metal layers are disposed on the second insulating film covering the N-type semiconductor patterns and the P-type semiconductor patterns. The electrodes are disposed on the second insulating film.

For example, it further includes a heat dissipation member. The electrodes are arranged at a certain distance apart from the light-shielding metal layer toward the outer side of the substrate. The heat dissipation member is spaced apart from the N-type semiconductor patterns and the P-type semiconductor patterns and contacts the upper part of the electrodes.

The present invention provides a display device in which a driver IC is formed together with a thin film transistor of a display device, and a cooling system is provided to discharge heat generated from the driver IC to the outside. The present invention provides a display device including a cooling system using a thermoelectric effect in contact with a driver IC disposed at the periphery of a display panel. The present invention provides a display device having a means for cooling down heat generation while maintaining the thickness of the panel in a thin film type display device. In addition, a flexible display device is provided that has a means for cooling down heat while maintaining the flexible characteristics of the panel.

1 is a diagram schematically showing a display device according to the prior art.
Figure 2 is a plan view schematically showing a display device having a thermoelectric cooling system according to a first embodiment of the present invention.
Figure 3 is a plan view schematically showing a display device having a thermoelectric cooling system according to a second embodiment of the present invention.
Figure 4 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a third embodiment of the present invention.
Figure 5 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a fourth embodiment of the present invention.
Figure 6 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a fifth embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Additionally, the component names used in the following description may have been selected in consideration of ease of specification preparation, and may be different from the component names of the actual product.

<First embodiment>

Hereinafter, with reference to FIG. 2, a first embodiment of the present invention will be described. Figure 2 is a plan view schematically showing a display device having a thermoelectric cooling system according to a first embodiment of the present invention.

Referring to FIG. 2 , a display device having a thermoelectric cooling system according to a first embodiment of the present invention includes a display panel DP with a display area AA and a non-display area NA defined. The display area AA is defined in the central area of the display panel DP. The non-display area (NA) is defined around the display area (AA).

A plurality of pixels (PXL) are arranged in a matrix manner in the display area (AA) of the display panel (DP). Pixels PXL are defined by a plurality of gate lines GL extending in the horizontal direction and data lines DL extending in the vertical direction. One thin film transistor (T) is disposed in each pixel (PXL).

At least one thin film transistor T is formed at each intersection of the data lines DL and the gate lines GL. The thin film transistor T supplies the data voltage from the data line DL to the pixel electrode P in response to the gate pulse from the gate line GL. Each of the liquid crystal cells Clc is driven by the voltage difference between the pixel electrode P, which charges a data voltage through the thin film transistor T, and the common electrode C, to which a common voltage Vcom is applied. A storage capacitance (Cst) that maintains the voltage of the liquid crystal cell for one frame period may be connected to the liquid crystal cell (Clc).

A drive IC is disposed in the non-display area (NA) of the display panel (DP). The drive IC includes a data drive IC (not shown) and a gate drive IC (GIP). The drive IC is a circuit for driving pixels (PXL) arranged in the display area (AA) of the display panel (DP). The gate drive IC (GIP) may be placed directly on the bezel area of the display panel (DP) according to the GIP (Gate-driver In Panel) circuit method.

In particular, the first embodiment of the present invention further includes a thermal transfer cooling system for cooling heat generated from the gate drive IC (GIP). The thermal transfer cooling system is a cooling system that uses the thermal transfer effect or the Peltier effect (Thermoelectric Effect). The heat transfer effect refers to the effect that when an N-type/P-type heat transfer material is placed between two metal layers spaced a certain distance apart and an electric current flows through the metal layers, heat from one metal layer is transferred to the other metal layer.

To be described in more detail with reference to FIG. 2, the thermal transfer cooling system includes a light-shielding metal layer (LS), an N-type semiconductor pattern (N), a P-type semiconductor pattern (P), a first electrode (T+), and a second electrode. Includes electrode (T-). The light-shielding metal layer (LS) is stacked on the lower part of the gate drive IC (GIP). An N-type semiconductor pattern (N) is in contact with one side of the light-shielding metal layer (LS). A P-type semiconductor pattern (P) is in contact with the other side of the light-shielding metal layer (LS). The first electrode (T+) is in contact with the N-type semiconductor pattern (N). The second electrode (T-) is in contact with the P-type semiconductor pattern (P).

In this structure, when a positive voltage is applied to the first electrode (T+) and a - voltage is applied to the second electrode (T-), the N-type semiconductor pattern (N), the light-shielding metal layer (LS), and the P It flows to the second electrode (T-) through the semiconductor pattern (P). In this process, the heat of the light-shielding metal layer LS moves toward the first electrode (T+) and the second electrode (T-). As a result, heat generated from the gate drive IC (GIP) formed by stacking on top of the light-shielding metal layer LS is discharged to the left side of the display panel DP. At this time, a heat dissipation member HS may be further attached to the left side of the display panel DP for heat dissipation effect. The heat dissipation member (HS) is preferably made of a non-conductive material and is in contact with the first electrode (T+) and the second electrode (T-).

In the first embodiment, the light-shielding metal layer LS is arranged long along one side of the display panel DP, and each of the N-type semiconductor pattern N and the P-type semiconductor pattern P is a part of the light-shielding metal layer LS. It has a structure in which one side and the other side are in contact. Therefore, the path of the current showing the thermoelectric effect between the first electrode (T+) and the second electrode (T-) is very short. The thermoelectric effect appears in the N-type semiconductor pattern (N) and the P-type semiconductor pattern (P), with one N-type semiconductor pattern (N) and one P-type semiconductor pattern (P) on one side of the display panel (DP). This is because only the As a result, the thermoelectric effect may be reduced. Below, a display device equipped with a thermoelectric cooling system that is more efficient than the first embodiment will be described.

<Second Embodiment>

Hereinafter, with reference to FIG. 3, a second embodiment of the present invention will be described. Figure 3 is a plan view schematically showing a display device having a thermoelectric cooling system according to a second embodiment of the present invention.

Referring to FIG. 3 , a display device having a thermoelectric cooling system according to a second embodiment of the present invention includes a display panel DP with a display area AA and a non-display area NA defined. The display area AA is defined in the central area of the display panel DP. The non-display area (NA) is defined around the display area (AA).

A plurality of pixels (PXL) are arranged in a matrix manner in the display area (AA) of the display panel (DP). Pixels PXL are defined by a plurality of gate lines GL extending in the horizontal direction and data lines DL extending in the vertical direction. One thin film transistor (not shown) is disposed in each pixel (PXL). Since the detailed structure of the display area AA may be the same as that of the first embodiment, redundant description will be omitted.

A drive IC is disposed in the non-display area (NA) of the display panel (DP). The drive IC includes a data drive IC (not shown) and a gate drive IC (GIP). The drive IC is a circuit for driving pixels (PXL) arranged in the display area (AA) of the display panel (DP). The gate drive IC (GIP) may be placed directly on the bezel area of the display panel (DP) according to the GIP (Gate-driver In Panel) circuit method.

The thermal transfer cooling system according to the second embodiment includes a plurality of light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ), a plurality of N-type semiconductor patterns (N1, N2, ... Nn, Nn+1, N _last ), multiple P-type semiconductor patterns (P1, P2, ... Pn, Pn+1, P _last ), multiple electrodes (T1, T2, ... Tn, Tn+ 1, T _last ). Multiple light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) are stacked on the lower part of the gate drive IC (GIP). A plurality of light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) are arranged apart from each other at regular intervals.

The n-th N-type semiconductor pattern (Nn) is in contact with one side of the n-th light-shielding metal layer (LSn). Likewise, the nth P-type semiconductor pattern (Pn) is in contact with the other side of the nth light-shielding metal layer (LSn). The nth electrode (Tn) is in contact with the nth N-type semiconductor pattern (Nn). The n+1th electrode (Tn+1) is in contact with the nth P-type semiconductor pattern (Pn).

In this structure, when a + voltage is applied to the first electrode (T1) and a - voltage is applied to the last electrode (T _last ), the n-th N-type semiconductor pattern (Nn), the n-th light-shielding metal layer (LSn), and It flows through the nth P-type semiconductor patterns (Pn) in succession to the last electrode (T _last ). In this process, a row of multiple light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) is connected to multiple electrodes (T1, T2, ... Tn, Tn+1, T _last ). moves in the direction As a result, the heat generated from the gate drive IC (GIP) stacked on top of the multiple light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) is transferred to the left side of the display panel (DP). is emitted as

At this time, a heat dissipation member HS may be further attached to the left side of the display panel DP for heat dissipation effect. The heat dissipation member HS includes a non-conductive material and is preferably attached so as to contact a plurality of electrodes (T1, T2, ... Tn, Tn+1, T _last ). Heat generated from the gate driver IC (GIP) is absorbed by the light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) and transferred to the electrodes through the N-type and P-type semiconductor patterns. It is emitted to the outside through the heat dissipation member (HS) attached to the electrodes.

In the second embodiment, a plurality of light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) are arranged at regular intervals along one side of the display panel DP. In addition, a plurality of N-type semiconductor patterns (N1, N2, ... Nn, Nn+1, N _last ) and a plurality of P-type semiconductor patterns (P1, P2, ... Pn, Pn+1, P _last ) Each has a structure in contact with one side and the other side of each light-shielding metal layer (LS1, LS2, ... LSn, LSn+1, LS _last ). Therefore, the path of the current showing the thermoelectric effect between the first electrode (T1) and the last electrode (T _last ) is very long. As a result, very excellent thermoelectric effects can be obtained.

In addition, the light-shielding metal layers (LS1, LS2, ... LSn, LSn+1, LS _last ) are placed below the gate driver IC (GIP) to block all light flowing into the gate driver IC (GIP) from the outside of the bottom. You can. As a result, it is possible to prevent the gate driver IC (GIP) from being deteriorated by external light.

Until now, various embodiments of the present invention have been described, focusing on the structure on a plan view. Below, the structure in cross-sectional view will be described. In particular, the structure of a display device with a thermoelectric cooling system according to the second embodiment will be described.

<Third Embodiment>

Hereinafter, with reference to FIG. 4, a third embodiment of the present invention will be described. Figure 4 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a third embodiment of the present invention. Figure 4 is a cross-sectional view taken along line II' in Figure 3.

Referring to FIG. 4, the first buffer layer B1 is applied over the entire surface of the substrate SUB. The first buffer layer B1 is used to secure interfacial adhesion properties when depositing semiconductor materials on the substrate SUB. N-type semiconductor patterns (N1, N2) and P-type semiconductor patterns (P1, P2) are formed on the first buffer layer (B1). The N-type semiconductor patterns (N1, N2) and P-type semiconductor patterns (P1, P2) are alternately arranged and spaced apart from each other at a certain interval.

An insulating film IN covers the entire surface of the substrate SUB on the N-type semiconductor patterns N1 and N2 and the P-type semiconductor patterns P1 and P2. Electrodes T1, T2, and T3 and light-shielding metal layers LS1 and LS2 are formed on the insulating film IN. The electrodes (T1, T2, T3) and the light-shielding metal layers (LS1, LS2) are connected to the N-type semiconductor patterns (N1, N2) and the P-type semiconductor patterns (P1, P2) through contact holes penetrating the insulating film (IN). ) is connected to.

For example, the first electrode T1 is connected to one side of the first N-type semiconductor pattern N1. The first light-shielding metal layer LS1 is connected to the other side of the first N-type semiconductor pattern N1 and one side of the first P-type semiconductor pattern P1. The second electrode T2 is connected to the other side of the first type semiconductor pattern P1 and one side of the second N-type semiconductor pattern N2. The second light-shielding metal layer LS2 is connected to the other side of the second N-type semiconductor pattern N2 and to one side of the second P-type semiconductor pattern P2. Additionally, the third electrode T3 is connected to the other side of the second P-type semiconductor pattern P2.

The second buffer layer B2 covers the entire surface of the substrate SUB on the electrodes T1, T2, and T3 and the light-shielding metal layers LS1 and LS2. A gate driver IC (GIP) is formed on the second buffer layer (B2). Although not shown in the drawing, thin film transistors and pixel elements are formed in the display area AA.

On the gate driver IC (GIP), a protective film (PAS) covers the entire surface of the substrate (SUB). The protective film (PAS) also covers elements formed in the display area (AA). An electrode terminal (TT) is formed on the protective film (PAS). The electrode terminal (TT) is connected to the first electrode (T1) through the protective film (PAS) and the second buffer layer (B2). The electrode terminal TT is a terminal for applying a (+) voltage to the first electrode T1. Although not shown in the drawing, a terminal for applying a (-) voltage may be connected to the last electrode (T _last ).

In the display device with the thermoelectric cooling system according to the third embodiment, N-type semiconductor patterns and P-type semiconductor patterns are formed in the same layer. This can be formed by depositing and patterning the semiconductor material and then doping it with an N-type material and a P-type material, respectively, using a screen mask.

<Fourth Embodiment>

Hereinafter, with reference to FIG. 5, a fourth embodiment of the present invention will be described. Figure 5 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a fourth embodiment of the present invention. Figure 5 is also a cross-sectional view taken along the cutting line II' in Figure 3.

Referring to FIG. 5, the first buffer layer B1 is applied over the entire surface of the substrate SUB. The first buffer layer B1 is used to secure interfacial adhesion properties when depositing semiconductor materials on the substrate SUB. N-type semiconductor patterns N1 and N2 are formed on the first buffer layer B1. The N-type semiconductor patterns N1 and N2 are arranged at regular intervals.

The first insulating film IN1 covers the entire surface of the substrate SUB on the N-type semiconductor patterns N1 and N2. P-type semiconductor patterns P1 and P2 are formed on the first insulating film IN1. The P-type semiconductor patterns (P1, P2) are arranged at regular intervals. In particular, each of the P-type semiconductor patterns P1 and P2 is preferably disposed between the N-type semiconductor patterns N1 and N2.

The second insulating film IN2 covers the entire surface of the substrate SUB on the P-type semiconductor patterns P1 and P2. Electrodes T1, T2, and T3 and light-shielding metal layers LS1 and LS2 are formed on the second insulating film IN2. The electrodes (T1, T2, T3) and the light-shielding metal layers (LS1, LS2) are connected to the N-type semiconductor patterns (N1, N2) through contact holes penetrating the second insulating film (IN2) and the first insulating film (IN1). It is connected to P-type semiconductor patterns (P1, P2).

For example, the first electrode T1 is connected to one side of the first N-type semiconductor pattern N1. The first light-shielding metal layer LS1 is connected to the other side of the first N-type semiconductor pattern N1 and one side of the first P-type semiconductor pattern P1. The second electrode T2 is connected to the other side of the first type semiconductor pattern P1 and one side of the second N-type semiconductor pattern N2. The second light-shielding metal layer LS2 is connected to the other side of the second N-type semiconductor pattern N2 and one side of the second P-type semiconductor pattern P2. Additionally, the third electrode T3 is connected to the other side of the second P-type semiconductor pattern P2.

The second buffer layer B2 covers the entire surface of the substrate SUB on the electrodes T1, T2, and T3 and the light-shielding metal layers LS1 and LS2. A gate driver IC (GIP) is formed on the second buffer layer (B2). Although not shown in the drawing, thin film transistors and pixel elements are formed in the display area AA.

On the gate driver IC (GIP), a protective film (PAS) covers the entire surface of the substrate (SUB). The protective film (PAS) also covers elements formed in the display area (AA). An electrode terminal (TT) is formed on the protective film (PAS). The electrode terminal (TT) is connected to the first electrode (T1) through the protective film (PAS) and the second buffer layer (B2). The electrode terminal TT is a terminal for applying a (+) voltage to the first electrode T1. Although not shown in the drawing, a terminal for applying a (-) voltage may be connected to the last electrode (T _last ).

In the display device with the thermoelectric cooling system according to the fourth embodiment, N-type semiconductor patterns and P-type semiconductor patterns are formed in different layers. This involves first depositing and patterning an N-type semiconductor material, and then applying the first insulating film IN1. Thereafter, N-type semiconductor patterns and P-type semiconductor patterns can be formed by depositing and patterning a P-type semiconductor material on the first insulating film IN1.

<Embodiment 5>

The above embodiments have been described focusing on the structure of the formation positions of the N-type semiconductor pattern and the P-type semiconductor pattern. In these embodiments, the heat dissipation effect can be further improved by placing the electrodes on the top layer of the substrate. Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG. 6. Figure 6 is a cross-sectional view schematically showing a display device having a thermoelectric cooling system according to a fifth embodiment of the present invention. Figure 6 is a cross-sectional view taken along line II' in Figure 3.

Referring to FIG. 6, the first buffer layer B1 is applied over the entire surface of the substrate SUB. The first buffer layer B1 is used to secure interfacial adhesion properties when depositing semiconductor materials on the substrate SUB. N-type semiconductor patterns (N1, N2) and P-type semiconductor patterns (P1, P2) are formed on the first buffer layer (B1). The N-type semiconductor patterns (N1, N2) and P-type semiconductor patterns (P1, P2) are alternately arranged and spaced apart from each other at a certain interval.

An insulating film IN covers the entire surface of the substrate SUB on the N-type semiconductor patterns N1 and N2 and the P-type semiconductor patterns P1 and P2. Light-shielding metal layers LS1 and LS2 are formed on the insulating film IN. The light-shielding metal layers LS1 and LS2 are connected to the N-type semiconductor patterns N1 and N2 and the P-type semiconductor patterns P1 and P2 through contact holes penetrating the insulating film IN. For example, the first light-shielding metal layer LS1 is connected to the other side of the first N-type semiconductor pattern N1 and to one side of the first P-type semiconductor pattern P1. The second light-shielding metal layer LS2 is connected to the other side of the second N-type semiconductor pattern N2 and to one side of the second P-type semiconductor pattern P2.

The second buffer layer B2 covers the entire surface of the substrate SUB on the light-shielding metal layers LS1 and LS2. A gate driver IC (GIP) is formed on the second buffer layer (B2). Although not shown in the drawing, thin film transistors and pixel elements are formed in the display area AA. On the gate driver IC (GIP), a protective film (PAS) covers the entire surface of the substrate (SUB). The protective film (PAS) also covers elements formed in the display area (AA).

Electrodes T1, T2, and T3 are formed on the protective film PAS. The electrodes T1, T2, and T3 penetrate the protective film PAS and the second buffer layer B2 and are connected to the N-type semiconductor patterns N1, N2 and the P-type semiconductor patterns P1, P2. . For example, the first electrode T1 is connected to one side of the first N-type semiconductor pattern N1. The second electrode T2 is connected to the other side of the first type semiconductor pattern P1 and one side of the second N-type semiconductor pattern N2. Additionally, the third electrode T3 is connected to the other side of the second P-type semiconductor pattern P2.

A (+) voltage is applied to the first electrode (T1). Although not shown in the drawing, a (-) voltage is applied to the last electrode (T _last ). Meanwhile, a heat dissipation member HS is attached to the electrodes Tn except for the ends of the first electrode T1 and the last electrode T _last . Heat generated from the gate drive IC (GIP) is absorbed by the light-shielding metal layer (LSn), and this heat is transferred to the electrodes (Tn) through the N-type and P-type semiconductor patterns (Nn, Pn). Finally, the heat collected in the electrodes Tn is discharged to the outside of the substrate SUB through the heat dissipation member HS.

The display device with the thermoelectric cooling system according to the fifth embodiment represents a case in which electrodes are formed on the uppermost layer of the substrate SUB in the third embodiment in which N-type semiconductor patterns and P-type semiconductor patterns are disposed on the same layer. Although not described in detail, the fifth embodiment can also be applied to the fourth embodiment.

Through the above-described content, those skilled in the art will be able to make various changes and modifications without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be determined by the scope of the patent claims.

GIP: Gate driver IC LS: Light-shielding metal layer
N: N-type semiconductor pattern P: P-type semiconductor pattern
T+: first electrode T-: second electrode
T1: first electrode Tlast: last electrode
HS: Heat dissipation member

Claims (11)

A display panel having a display area on a substrate where pixels are arranged and a non-display area disposed on an outer periphery of the display area;
a gate driving circuit disposed in the non-display area on the substrate;
a light-shielding metal layer disposed below the gate driving circuit on the substrate;
an N-type semiconductor pattern connected to one side of the light-shielding metal layer;
a P-type semiconductor pattern connected to the other side of the light-shielding metal layer;
a first electrode connected to the N-type semiconductor pattern;
a second electrode connected to the P-type semiconductor pattern;
thin film transistors of the pixels disposed in the display area on the substrate; and
A display device comprising a protective film covering the light-shielding metal layer, the N-type semiconductor pattern, the P-type semiconductor pattern, the first electrode, the second electrode, and the thin film transistors.
According to claim 1,
A (+) voltage is applied to the first electrode,
The second electrode is a display device to which a (-) voltage is applied.
A display panel having a display area on a substrate where pixels are arranged and a non-display area disposed on an outer periphery of the display area;
a gate driving circuit disposed in the non-display area on the substrate;
two light-shielding metal layers disposed separately from each other on the substrate and below the gate driving circuit;
A first N-type semiconductor pattern connected to one side of the first light-shielding metal layer;
a first P-type semiconductor pattern connected to the other side of the first light-shielding metal layer;
a first electrode connected to the first N-type semiconductor pattern;
a second electrode connected to the first P-type semiconductor pattern;
thin film transistors of the pixels disposed in the display area on the substrate; and
A display device comprising a protective film covering the light-shielding metal layers, the first N-type semiconductor pattern, the first P-type semiconductor pattern, the first electrode, the second electrode, and the thin film transistors.
According to claim 3,
a second N-type semiconductor pattern connected to one side of the second light-shielding metal layer;
a second P-type semiconductor pattern connected to the other side of the second light-shielding metal layer; and
Further comprising a third electrode connected to the second P-type semiconductor pattern,
The second N-type semiconductor pattern is connected to the second electrode.
According to claim 4,
A (+) voltage is applied to the first electrode,
The third electrode is a display device to which a (-) voltage is applied.
A display panel having a display area on a substrate where pixels are arranged and a non-display area disposed on an outer periphery of the display area;
a gate driving circuit disposed in the non-display area on the substrate;
n light-shielding metal layers disposed separately from each other on the substrate and below the gate driving circuit;
an n-th N-type semiconductor pattern connected to one side of the n-th light-shielding metal layer;
an n-th P-type semiconductor pattern connected to the other side of the n-th light-shielding metal layer;
an n-th electrode connected to the n-th N-type semiconductor pattern;
(n+1)th electrode connected to the nth P-type semiconductor pattern; and
thin film transistors of the pixels disposed in the display area on the substrate; and
A display device comprising a protective film covering the light-shielding metal layers, the n-th N-type semiconductor pattern, the n-th P-type semiconductor pattern, the n-th electrode, the (n+1)-th electrode, and the thin film transistors.
According to claim 6,
The (n+1)th N-type semiconductor pattern is connected to the (n+1)th electrode of the display device.
According to claim 6,
To the first electrode, a (+) voltage is applied,
A display device in which a (-) voltage is applied to the last electrode.
According to claim 6,
The N-type semiconductor patterns are,
disposed separately on the substrate,
The P-type semiconductor patterns are,
It is arranged separately between the N-type semiconductor patterns,
The light-shielding metal layers are,
disposed on an insulating film covering the N-type semiconductor patterns and the P-type semiconductor patterns,
A display device wherein the electrodes are disposed on the insulating film.
According to claim 6,
The N-type semiconductor patterns are,
disposed separately on the substrate,
The P-type semiconductor patterns are,
disposed separately between the N-type semiconductor patterns on a first insulating film covering the N-type semiconductor patterns,
The light-shielding metal layers are,
disposed on a second insulating film covering the N-type semiconductor patterns and the P-type semiconductor patterns,
A display device wherein the electrodes are disposed on the second insulating film.
According to claim 6,
The electrodes are,
It is disposed at a certain distance from the light-shielding metal layer toward the outer side of the substrate,
A display device further comprising a heat dissipation member in contact with upper portions of the electrodes.

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