KR102637825B1 - Display device and driving method - Google Patents

Abstract

Embodiments of the present invention provide a display device and driving method that can resolve uneven brightness by improving the charging rate for subpixels of a display panel. In an embodiment of the present invention, in N-phase driving in which N subpixels are driven as one subpixel group, a precharging period is additionally secured before driving the next subpixel group, thereby creating a subpixel group and a subpixel group. Provided is a display device and driving method that can resolve luminance unevenness that may occur between the display devices and the display device.

Description

Display device and driving method {DISPLAY DEVICE AND DRIVING METHOD}

Embodiments of the present invention relate to a display device and a driving method.

As the information society develops, various demands for display devices that display images are increasing, and various types such as Liquid Crystal Display (LCD), Organic Light Emitting Diode Display (OLED Display), etc. of display devices are being used.

Among these display devices, organic light emitting display devices use organic light emitting diodes that emit light on their own, so they have advantages in terms of fast response speed, contrast ratio, luminous efficiency, luminance, and viewing angle.

This organic light emitting display device includes organic light emitting diodes arranged in each of a plurality of sub-pixels (SP) arranged on a display panel, and each organic light emitting diode emits light by controlling the current flowing through the organic light emitting diodes. An image can be displayed by controlling the luminance expressed by the subpixels (SP).

These subpixels (SP) are driven by the scan signal (SCAN) applied through the gate line (GL), and the data voltage (Vdata) applied through the data line (DL) in accordance with the timing when the scan signal (SCAN) is applied. ) to display the image by expressing the gradation according to the gradation. At this time, the data line DL to which the data voltage Vdata is applied may be arranged one by one for each column of the subpixel SP.

Meanwhile, recently, one data line (DL) has been installed between two adjacent subpixels (SP) to reduce the number of source driver integrated circuits (SDIC) that drive the data line (DL). A DRD (Double Rate Driving) structure is being applied in which one data line (DL) drives two subpixels (SP) arranged on both sides.

In the DRD-type subpixel (SP) structure, a data voltage (Vdata) for driving two subpixels (SP) is applied through the data line (DL) during one horizontal period. At this time, a display device driven by the DRD method may apply a data voltage (Vdata) whose polarity is reversed to each row of the subpixel (SP) in order to minimize flicker and reduce power consumption. Accordingly, the data voltage Vdata applied to the subpixel SP may be a signal having the same polarity as the data voltage Vdata applied to the previous subpixel SP, or a signal with the polarity reversed may be applied. It may be possible.

For example, in the case of an organic light emitting display device with a resolution of 2,160 ) will be placed at each point where subpixels (SP) intersect.

At this time, the organic light emitting display device may output a scan signal (SCAN) sequentially from the first gate line (GL1) to the 2,160th gate line (GL2,160) for the 2,160 gate lines (GL), and may output a scan signal (SCAN) sequentially for the 2,160 gate lines (GL). For the pixel SP, the scan signal SCAN is sequentially output from the first gate line GL1 to the fourth gate line GL4, and then, after a certain period of time, from the fifth gate line GL5 to the eighth gate As in the case of sequentially outputting the scan signal SCAN up to the line GL8, the scan signal SCAN may be sequentially output for each of the four gate lines GL.

In the above case, the case of sequentially outputting the scan signal (SCAN) from the first gate line (GL1) to the 2,160th gate line (GL2,160) as one group is called 2,160 phase driving, The case of sequentially outputting the scan signal SCAN from the first gate line GL1 to the fourth gate line GL4 as one group is called 4-phase driving. Of course, the group of gate lines (GL) that sequentially output the scan signal (SCAN) can be changed to 4, 8, or 256 groups. In other words, the case where the scan signal (SCAN) is sequentially output for each of the N gate lines (GL) can be referred to as N-phase driving.

This N-phase driving can be changed in various ways depending on the size or performance of the display device, the frame time for displaying an image on the display panel varies, and taking into account afterimages that appear in the user's field of view or deterioration of circuit elements, etc.

At this time, in N-phase driving in which the subpixels (SP) that continuously output the scan signal (SCAN) are divided into N subpixel groups and driven, the subpixels (SP) are charged within the same group. In this case and in the case of charging a new group of subpixels (SP), the charging rate varies because the time of the data voltage (Vdata) applied to the subpixel (SP) is different. As a result, a problem of non-uniform luminance may occur between a subpixel group composed of N subpixels (SP) and a subpixel group.

The purpose of an embodiment of the present invention is to provide a display device and a driving method that can eliminate uneven brightness by improving the charging rate for subpixels of a display panel.

The purpose of the embodiment of the present invention is to add a precharging period before driving the next subpixel group in N-phase driving in which N subpixels are driven as one subpixel group, thereby creating a subpixel group and a subpixel group. The goal is to provide a display device and driving method that can eliminate luminance unevenness that may appear between the display devices and the display device.

In one aspect, an organic light emitting display device according to an embodiment of the present invention includes a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, driving the plurality of gate lines, and N rows of subpixels. A gate driving circuit that sequentially applies scan signals by dividing pixels into subpixel groups, a data driving circuit that drives a plurality of data lines, and a driving voltage applied to the gate driving circuit and the data driving circuit are controlled, and the subpixel group It may include a controller that controls the gate driving circuit to secure an additional precharging section before applying the scan signal to the first subpixel.

The subpixel includes an organic light emitting diode, a driving transistor for driving the organic light emitting diode, a switching transistor electrically connected between the gate node of the driving transistor and the data line, and between the source node or drain node of the driving transistor and the reference voltage line. It may include a storage capacitor electrically connected between an electrically connected sensing transistor, a gate node of the switching transistor, and a source node or drain node.

N may be any natural number.

The scan signal may be applied at intervals of 1 horizontal period.

The controller may control the data driving circuit so that the data voltage for precharging is applied to the first subpixel of the subpixel group during the precharging period.

The precharging section may have one horizontal cycle.

The data line may operate in a double rate driving (DRD) method in which one data line is placed between two adjacent subpixels, and two subpixels placed on both sides are driven by one data line.

In another aspect, a method of driving an organic light emitting display device according to an embodiment of the present invention includes a plurality of data lines and a plurality of gate lines, and a plurality of sub arrays arranged in an area where the plurality of data lines and the gate lines intersect. A method of driving an organic light emitting display device including a display panel composed of a pixel and a plurality of subpixels, a data driving circuit for driving the plurality of data lines, and a gate driving circuit for driving the plurality of gate lines. , sequentially applying a scan signal through a gate driving circuit using N rows of subpixels as a first subpixel group, and N rows adjacent to the N rows of first subpixel groups and having different colors. In the second subpixel group, additionally securing a precharging section before applying a scan signal to the first subpixel, and sequentially applying a scan signal to the second subpixel group through a gate driving circuit. May include steps.

According to an embodiment of the present invention, in N-phase driving of the DRD method, sufficient time for the data voltage (Vdata) to be applied to the first subpixel of the subpixel group can be secured, thereby preventing blurring that occurs in a specific line of the display panel. It has the effect of minimizing the phenomenon.

Figure 1 is a diagram showing the schematic configuration of an organic light emitting display device according to an embodiment of the present invention.
Figure 2 is a system diagram of an organic light emitting display device according to an embodiment of the present invention.
Figure 3 is a circuit structure diagram of a subpixel (SP) arranged in an organic light emitting display device according to an embodiment of the present invention.
Figure 4 shows an example of a subpixel structure when driven in the DRD method in an organic light emitting display device according to an embodiment of the present invention.
FIG. 5 shows a signal timing diagram according to 4-phase driving in which a scan signal (SCAN) is continuously applied to four rows of subpixels (SP) as one group in DRD driving of an organic light emitting display device.
FIG. 6 is an example diagram of a case in which a storage capacitor within a subpixel is not sufficiently charged in DRD driving of an organic light emitting display device.
FIG. 7 shows an example screen in which blurring occurs for every N+1 line in the case of N-phase driving in an organic light emitting display device driving DRD.
FIG. 8 is a diagram illustrating a signal timing diagram when a precharging section is secured when a scan signal transitions to a subpixel group of a different color in an organic light emitting diode device according to an embodiment of the present invention.
9 shows the subpixel (SP5) in the fifth row and the subpixel (SP5) in the ninth row when the driving method of the present invention is applied to DRD-type 4-phase driving in an organic light emitting display device according to an embodiment of the present invention. This figure shows an example in which the phenomenon of image quality deterioration in the subpixels (SP 4N+1) of rows SP9) to 4N+1 has been resolved.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the essence, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Figure 1 is a diagram showing the schematic configuration of an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1, an organic light emitting display device 100 according to an embodiment of the present invention includes a display panel 110 in which a plurality of subpixels (SP) are arranged in a row, and a gate for driving the display panel 110. It may include a driving circuit 120 and a data driving circuit 130, and a controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130.

A plurality of gate lines (GL) and a plurality of data lines (DL) are arranged in the display panel 110, and a subpixel (SP) is arranged in an area where the gate lines (GL) and the data lines (DL) intersect. For example, in the case of an organic light emitting display device with a resolution of 2,160 DL) may be provided.

The gate driving circuit 120 is controlled by the controller 140, and sequentially outputs a scan signal (SCAN) to a plurality of gate lines (GL) arranged on the display panel 110 to a plurality of subpixels (SP). Controls the driving timing for At this time, the gate driving circuit 120 may include one or more gate driver integrated circuits (GDIC). Depending on the driving method, it may be located only on one side of the display panel 110 or on both sides. It may be located. Alternatively, the gate driving circuit 120 may be built into the bezel area of the display panel 110 and implemented in a GIP (Gate In Panel) form.

Meanwhile, the data driving circuit 130 receives image data from the controller 140 and converts the received image data into an analog data voltage (Vdata). Then, by outputting the data voltage (Vdata) to each data line (DL) in accordance with the timing when the scan signal is applied through the gate line (GL), each subpixel (SP) connected to the data line (DL) Displays a light emitting signal with corresponding brightness according to the data voltage (Vdata).

Likewise, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), which may use a Tape Automated Bonding (TAB) method or a Chip On (COG) method. It may be connected to a bonding pad of the display panel 110 using a glass method or may be placed directly on the display panel 110. In some cases, each source driver integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented in a COF (Chip On Film) method. In this case, each source driver integrated circuit (SDIC) is mounted on a circuit film and displays the display panel through the circuit film. It may be electrically connected to the data line (DL) of (110).

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the controller 140 controls the gate driving circuit 120 to output a scan signal (SCAN) according to the timing implemented in each frame, and on the other hand, the externally received image data is sent to the data driving circuit 130. It is converted to fit the data signal format used and the converted image data is transmitted to the data driving circuit 130.

At this time, the controller 140 sends video data along with various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (Data Enable; DE), and a clock signal (CLK). Receive signals from outside (e.g. host system). Accordingly, the controller 140 generates a control signal using various timing signals received from the outside and transmits it to the gate driving circuit 120 and the data driving circuit 130.

For example, the controller 140 uses a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (Gate Output) to control the gate driving circuit 120. Outputs various gate control signals including Enable; GOE). Here, the gate start pulse (GSP) controls the timing at which one or more gate driver integrated circuits (GDIC) constituting the gate driving circuit 120 start operating. Additionally, the gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits (GDIC), and controls the shift timing of the scan signal (SCAN). Additionally, the gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits (GDIC).

Additionally, the controller 140 uses a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (Source Output Enable) to control the data driving circuit 130. Outputs various data control signals including SOE), etc. Here, the source start pulse (SSP) controls the timing at which one or more source driver integrated circuits (SDICs) constituting the data driving circuit 130 start sampling data. The source sampling clock (SSC) is a clock signal that controls the timing of sampling data in the source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

This organic light emitting display device 100 is a power management integrated circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, etc., or controls the various voltages or currents to be supplied. may further include.

Meanwhile, the subpixel SP is located at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, the organic light emitting display device 100 includes a light emitting device such as a light emitting diode (LED) or an organic light emitting diode (OLED) in each subpixel (SP), and emits light to the light emitting device according to the data voltage (Vdata). Images can be displayed by controlling the flowing current.

Figure 2 is a system diagram of an organic light emitting display device according to an embodiment of the present invention.

In the organic light emitting display device 100 of FIG. 2, the source driver integrated circuit (SDIC) included in the data driving circuit 130 is implemented in a COF (Chip On Film) method among various methods (TAB, COG, COF, etc.). , This shows a case where the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

A plurality of source driver integrated circuits (SDICs) included in the data driving circuit 130 may each be mounted on a source-side circuit film (SF), and one side of the source-side circuit film (SF) is connected to the display panel 110 and the Can be electrically connected. Additionally, wires for electrically connecting the source driver integrated circuit (SDIC) and the display panel 110 may be disposed on the source side circuit film SF.

This organic light emitting display device 100 includes at least one source printed circuit board (SPCB), control components, and It may include a control printed circuit board (CPCB) for mounting various electrical devices.

At this time, the other side of the source side circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source side circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

A controller 140 and a power management integrated circuit (Power Management IC (PMIC) 210) may be mounted on a control printed circuit board (CPCB). The controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management integrated circuit 210 supplies various voltages or currents, including driving voltages, to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, or controls the supplied voltages or currents. You can.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected circuitously through at least one connecting member, for example, a flexible printed circuit (FPC). , it may be made of a flexible flat cable (FFC), etc. Additionally, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The organic light emitting display device 100 may further include a set board 230 electrically connected to a control printed circuit board (CPCB). At this time, the set board 230 may also be referred to as a power board. This set board 230 may include a main power management circuit (M-PMC, 220) that manages the overall power of the organic light emitting display device 100. The main power management circuit 220 may be interconnected with the power management integrated circuit 210.

In the case of the organic light emitting display device 100 configured as above, the driving voltage EVDD is generated on the set board 230 and transmitted to the power management integrated circuit 210 in the control printed circuit board (CPCB). The power management integrated circuit 210 transmits the driving voltage (EVDD) required during the image driving period or the degradation sensing period to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage (EVDD) delivered to the source printed circuit board (SPCB) is supplied to emit or sense a specific subpixel (SP) in the display panel 110 through the source driver integrated circuit (SDIC).

At this time, each subpixel (SP) arranged on the display panel 110 in the organic light emitting display device 100 includes a light emitting device, an Organic Light Emitting Diode (OLED), and a driving transistor (Driving) for driving the organic light emitting diode (OLED). It may be composed of circuit elements such as transistors.

The type and number of circuit elements constituting each subpixel (SP) may be determined in various ways depending on the provided function and design method.

Figure 3 is a circuit structure diagram of a subpixel (SP) arranged in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 3, a subpixel (SP) disposed in the organic light emitting display device 100 of the present invention may include one or more transistors and a capacitor, and an organic light emitting diode (OLED) may be disposed as a light emitting device. .

For example, the subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and an organic light emitting diode (OLED).

The driving transistor DRT has a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be a gate node to which the data voltage Vdata is applied through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the organic light emitting diode (OLED) and may be a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL to which the driving voltage EVDD is applied, and may be a drain node or a source node.

Here, during the image driving period, the driving voltage EVDD required for image driving may be supplied through the driving voltage line DVL. For example, the driving voltage EVDD required for image driving may be 27V.

The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and supplied through the gate line (GL). It operates according to the scan signal (SCAN). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transferring the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT). I do it.

The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and the gate line (GL) is connected to the gate node to transmit data through the gate line (GL). It operates according to the supplied scan signal (SCAN). When the sensing transistor (SENT) is turned on, the sensing reference voltage (Vref) supplied through the reference voltage line (RVL) is transmitted to the second node (N2) of the driving transistor (DRT).

That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage of the first node (N1) and the voltage of the second node (N2) of the driving transistor (DRT) are controlled, which causes the organic light emitting diode Ensure that current to drive (OLED) is supplied.

These switching transistors (SWT) and sensing transistors (SENT) may be connected to the same gate line (GL) or may be connected to different signal lines. Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to the same gate line (GL) is shown as an example. In this case, the scan signal (SCAN) transmitted through one gate line (GL) is shown as an example. By doing this, the switching transistor (SWT) and sensing transistor (SENT) can be controlled simultaneously and the aperture ratio of the subpixel (SP) can be improved.

Meanwhile, the transistor disposed in the subpixel SP may be made of not only an n-type transistor but also a p-type transistor, and here, the case of being made of an n-type transistor is shown as an example.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintains the data voltage Vdata for one frame.

This storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT depending on the type of the driving transistor DRT. The anode electrode of the organic light emitting diode (OLED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and the base voltage (EVSS) may be applied to the cathode electrode of the organic light emitting diode (OLED). You can. Here, the base voltage (EVSS) may be ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive voltage (EVSS) may vary depending on the driving state. For example, the base voltage (EVSS) at the time of image driving and the base voltage (EVSS) at the time of sensing driving may be set differently.

The structure of the subpixel (SP) described above as an example is a 3T (Transistor) 1C (Capacitor) structure, which is only an example for explanation, and may further include one or more transistors or, in some cases, one or more capacitors. More may be included. Alternatively, each of the multiple subpixels (SP) may have the same structure, or some of the multiple subpixels (SP) may have a different structure.

Figure 4 shows an example of a subpixel structure when driven in the DRD method in an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 4, the subpixels (SP) of the organic light emitting display device 100 according to an embodiment of the present invention include a red subpixel (R), a green subpixel (G), a blue subpixel (B), and a white subpixel (SP). This shows a case composed of subpixels (W).

In the organic light emitting display device 100 driven by the DRD method, the display panel 110 has one data line (DL) arranged in each of two subpixel (SP) columns, and two subpixels (SP) in each row at the top and bottom. Gate lines (GL) may be arranged. Here, the white subpixel (W) and red subpixel (R) share one data line (DL11), and the green subpixel (G) and blue subpixel (B) share one data line (DL12). This shows the case where it is being done. Additionally, the white subpixel (W) and green subpixel (G) share the same gate line (GL11, GL21, GL31, GL41, GL51, ??), and the red subpixel (R) and blue subpixel (B) ) share the same gate line (GL12, GL22, GL32, GL42, ??).

The subpixel (SP) structure sharing the data line (DL) and gate line (GL) can be changed in various ways, such as white subpixel (W) and green subpixel (G), or red subpixel (R) and blue. Each subpixel (B) may share a data line (DL), or the white subpixel (W) and the red subpixel (R) may share one gate line (GL).

During one horizontal period (Horizontal Time), data voltage (Vdata) is supplied to two subpixels (SP) through one data line (DL), and the gate line (GL) operates at twice the frequency compared to normal operation. It is driven to apply a scan signal (SCAN) to each subpixel (SP).

In addition, in order to minimize the occurrence of flicker and reduce power consumption, the scan signal (SCAN) is controlled so that the data voltage (Vdata) is applied alternately to the subpixels (SP) arranged on both sides of one data line (DL). You might be able to do it.

FIG. 5 shows a signal timing diagram according to 4-phase driving in which a scan signal (SCAN) is continuously applied to four rows of subpixels (SP) as one group in DRD driving of an organic light emitting display device.

Referring to FIG. 5, for 4-phase driving, scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, and SCAN_GL41) are sequentially applied from the white subpixel (W1) in the first row to the white subpixel (W4) in the fourth row. , scan signals (SCAN_GL12, SCAN_GL22, SCAN_GL32, and SCAN_GL42) may be sequentially applied from the adjacent red subpixel (R1) in the first row to the red subpixel (R4) in the fourth row. At this time, the timing interval of the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) can be set to 1 horizontal period (1H).

When the scan signal (SCAN) is applied to the white subpixel (W1, W2, W3, W4) or red subpixel (R1, R2, R3, R4), the data voltage (Vdata_DL11) is transmitted through the data line (DL11). Then, the subpixel corresponding to the section where the scan signal (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) and the data voltage (Vdata_DL11) overlap will display the color corresponding to the data voltage (Vdata_DL11). will be.

For example, consider a case in which the display panel 110 emits light from the red subpixel (R1) in the first row to the red subpixel (R4) in the fourth row. At this time, in the section where the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41) are applied at a high level from the white subpixel (W1) in the first row to the white subpixel (W4) in the fourth row, the data voltage (Vdata_DL11) is Although not supplied, the data voltage (Vdata_DL11) is at a high level in the section where the scan signals (SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) are applied from the red subpixel (R1) in the first row to the red subpixel (R4) in the fourth row. will be supplied.

If the organic light emitting display device 100 has a resolution of 2,160 Since the data voltage (Vdata) is supplied, in order to drive the entire frame of the display panel 110 once, a scan signal (SCAN) must be applied to 2,160 + 2,160 subpixels (SP). If the organic light emitting display device 100 is driven at a frequency of 120 Hz, one horizontal period (1H) of the scan signal (SCAN) has a time of 1/[120*(2,160+2,160)] = 1.8 μs.

That is, in the section where the scan signal (SCAN_GL12) is applied to the red subpixel (R1) in the first row after the scan signal (SCAN_GL41) is applied to the white subpixel (W4) in the fourth row, one horizontal period (1H) During the period, the data voltage (Vdata_DL11) is supplied, and in the section where the scan signal (SCAN_GL22) is applied to the red subpixel (R2) in the second row, the data voltage (Vdata_DL11) is supplied for 2 horizontal periods (2H). In addition, in the section where the scan signal (SCAN_GL32) is applied to the red subpixel (R3) in the third row, the data voltage (Vdata_DL11) is supplied for 3 horizontal periods (3H), and to the red subpixel (R4) in the fourth row. In the section where the scan signal (SCAN_GL42) is applied, the data voltage (Vdata_DL11) is supplied for 4 horizontal periods (4H).

As described above, in the case of the organic light emitting display device 100, which is driven at a frequency of 120 Hz and has a resolution of 2,160 ) charges the storage capacitor (Cst) during this time. That is, because the red subpixel (R1) in the first row takes a shorter time to charge the storage capacitor (Cst) than the red subpixels (R2) in the second row to the subpixels (R4) in the fourth row, the storage capacitor (Cst) Cst) is not sufficiently charged.

This is because the time for the data voltage (Vdata) to be transmitted to the gate node (N1) of the driving transistor (DRT) when the switching transistor (SWT) is turned on by the scan signal (SCAN) is too short, This phenomenon occurs because the storage capacitor (Cst) connected to the gate node (N1) is not sufficiently charged.

For example, as shown in FIG. 6, when the data voltage (Vdata) is applied at 10V and the time for which the switching transistor (SWT) remains in the turn-on state is short as 1 horizontal period (1H), the driving Since sufficient current is not supplied to the storage capacitor (Cst) through the gate node (N1) of the transistor (DRT), the voltage charged to the storage capacitor (Cst) is lower than the data voltage (Vdata) of 10V, for example, only up to 9.8V. This phenomenon occurs.

As a result, between any subpixel group consisting of four subpixels, such as the fifth row subpixel SP5 and the ninth row subpixel SP9 of the display panel 110, and other subpixel groups distinguished therefrom. When a disconnection of the scan signal (SCAN) appears, blurring occurs due to the low charging rate of the storage capacitor (Cst) in each fourth subpixel (SP 4N+1) line.

FIG. 7 shows an example screen in which blurring occurs for every N+1 line in the case of N-phase driving in an organic light emitting display device driving DRD.

In the case of FIG. 7, in the case of four-phase driving in which the scan signal (SCAN) is sequentially applied from the subpixel (SP1) in the first row to the subpixel (SP) in the fourth row, the subpixel (SP5) in the fifth row ), the subpixel (SP9) in the 9th row to the subpixel (SP 4N+1) in the 4N+1 row show a phenomenon of deterioration in image quality.

This blurring phenomenon is a quality degradation phenomenon that occurs in N-phase driving of the DRD method. In the case of 8-phase driving, the subpixels in the 9th row (SP9), the subpixels in the 17th row (SP17) to the 8N+1 rows This blurring phenomenon may occur in subpixels (SP 8N+1). In the case of N-phase driving, N can be any natural number.

As explained above, this phenomenon occurs in N-phase driving, which sequentially applies a scan signal (SCAN) to N rows of subpixels (SP) as one subpixel group, and the scan signal is transmitted to subpixels (SP) of different colors. In the process of (SCAN) transition, it can be seen as a phenomenon that occurs due to insufficient charging of the storage capacitor (Cst) that constitutes the first subpixel (SP) among the subpixel group to which the scan signal (SCAN) is first applied. there is.

Therefore, in the organic light emitting display device 100 in which N-phase driving is performed, at the time of transitioning the scan signal (SCAN) for each subpixel group consisting of N subpixels (SP), the first subpixel (SP) of the subpixel group This problem can be solved by securing a pre-charging section before applying the scan signal (SCAN) to ensure sufficient time for the storage capacitor (Cst) to be charged.

Figure 8 shows a signal timing diagram for securing a precharging section when a scan signal transitions to a subpixel group of a different color in an organic light emitting diode device according to an embodiment of the present invention.

FIG. 8 shows an example of applying the driving method according to the embodiment of the present invention to the four-phase drive of the DRD method shown in FIG. 5 in order to compare the technical effect according to the embodiment of the present invention with the conventional problems. will be.

Referring to FIG. 8, for four-phase driving, scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, and SCAN_GL41) are sequentially applied from the white subpixel (W1) in the first row to the white subpixel (W4) in the fourth row. Thereafter, scan signals (SCAN_GL12, SCAN_GL22, SCAN_GL32, and SCAN_GL42) may be sequentially applied from the adjacent red subpixel (R1) in the first row to the red subpixel (R4) in the fourth row. The timing interval of the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) can be set to 1 horizontal period (1H).

As described above, when the scan signal (SCAN) is applied to the white subpixels (W1, W2, W3, W4) or the red subpixels (R1, R2, R3, R4), the data voltage is transmitted through the data line (DL11). When (Vdata_DL11) is transmitted, the subpixel corresponding to the section where the scan signal (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41, SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42) and the data voltage (Vdata_DL11) overlap is the subpixel corresponding to the data voltage (Vdata_DL11). Color will be displayed.

At this time, after applying the scan signals (SCAN_GL11, SCAN_GL21, SCAN_GL31, SCAN_GL41) from the white subpixel (W1) in the first row to the white subpixel (W4) in the fourth row, the red subpixel (R1) in the first row ) to the red subpixel (R4) in the 4th row at the time of applying the scan signal (SCAN_GL12, SCAN_GL22, SCAN_GL32, SCAN_GL42), the scan signal (SCAN_GL12) applied to the red subpixel (R1) in the 1st row is 1 It is applied with a delay equal to the precharging section (Tpr) of the horizontal period (1H). That is, after the scan signal (SCAN_GL41) is applied to the white subpixel (W4) in the fourth row, the scan signal (SCAN_GL12) is applied to the red subpixel (R1) in the first row two horizontal periods (2H) later. In order to delay the scan signal (SCAN) applied to the subpixel (SP) by the precharging period (Tpr), the clock signal (CLK), especially the gate shift clock (GSC) commonly input to the gate driver integrated circuit (GDIC) This is possible by counting and applying a scan signal (SCAN) delayed by the precharging period (Tpr) after N gate shift clocks (GSC) are generated according to the N-phase drive type, and this control operation is performed by the controller 140. It can be done in

As a result, the time for applying the data voltage (Vdata_DL11) to the red subpixel (R1) in the first row increases from the conventional 1 horizontal period (1H) to 2 horizontal periods (2H), and the red subpixel (R1) in the first row increases. Sufficient charging time can be secured to charge the storage capacitor (Cst) belonging to the subpixel (R1). At this time, the controller 140 may control the data driving circuit 130 so that the data voltage for precharging is applied to the red subpixel R1 in the first row during the precharging period Tpr. The data voltage for precharging may have a different value from the data voltage (Vdata) for image driving.

Accordingly, the charging rate for the storage capacitor Cst constituting the subpixel SP can be improved, thereby minimizing blurring that may appear on a specific line of the display panel 110.

At this time, since a precharging period (Tpr) of 1 horizontal period (1H) is additionally secured before applying the scan signal (SCAN_GL12) to the red subpixel (R1) in the first row, the organic light emitting display panel 110 ), 1 horizontal period (1H) for the entire frame changes.

For example, when the organic light emitting display device 100 with a resolution of 2,160 120*(2,160+2,160)] = 1.8 μs. However, when applying the driving method of the present invention, a precharging section of 1 horizontal period (1H) is added to each 4 rows of subpixels, so the vertical subpixel line is 1/4 of 2,160 lines (540 lines). ) has an increasing effect, so one horizontal period (1H) becomes 1/[120*(2,160+540+2,160+540)] = 1.5 μs.

Therefore, when the driving method of the present invention is applied to the 4-phase driving of the DRD method, the time for which the data voltage (Vdata) is applied to the first subpixel in the subpixel group consisting of 4 subpixels (SP) is 1.5. It becomes 3 μs, which corresponds to 2 horizontal periods (2H) of μs. This is 1.67 times longer than the 1.8 μs for which the data voltage (Vdata) is applied to the first subpixel among the subpixel group consisting of four subpixels (SP) when the driving method of the present invention is not applied. Therefore, when the driving method of the present invention is applied to 4-phase driving of the DRD method, sufficient time for the data voltage (Vdata) to be applied to the first subpixel among the subpixel group can be secured, so that the storage of the corresponding subpixel Since the capacitor Cst is sufficiently charged, blurring occurring in a specific line of the display panel 110 can be minimized.

9 shows the subpixel (SP5) in the fifth row and the subpixel (SP5) in the ninth row when the driving method of the present invention is applied to DRD-type 4-phase driving in an organic light emitting display device according to an embodiment of the present invention. This shows as an example a case where the phenomenon of image quality deterioration in the subpixels (SP 4N+1) of rows SP9) to 4N+1 has been resolved.

Above, the organic light emitting display device 100 was described as an example of operating in a DRD-type 4-phase drive. However, in addition to 4-phase drive, the present invention can also be applied to 8-phase drive, 16-phase drive, and various other types of N-phase drive. It is obvious that it is possible to apply the driving method of .

In addition, when applying the driving method of the present invention to the organic light emitting display device 100, before applying the scan signal (SCAN) to the first subpixel among the subpixel group consisting of N rows of subpixels, 1 It is possible to secure a precharging section of a horizontal cycle (1H), but considering the size and performance of the display device 100, it is necessary to secure a precharging section of 0.5 horizontal cycle (0.5H) or 2 horizontal cycle (2H). It would also be possible.

Meanwhile, the gate driving circuit 120, which sequentially outputs the scan signal (SCAN) to the plurality of gate lines (GL) disposed on the display panel 110, is controlled by the controller 140, so that the N rows of sub The period of the scan signal (SCAN) applied to the first subpixel among the subpixel group consisting of pixels may be controlled by the controller 140. Of course, it would be possible to additionally configure a circuit that can adjust the period of the scan signal (SCAN) in the form of a module inside the gate driving circuit 120.

In addition, here, the switching transistor (SWT) and the sensing transistor (SENT) are connected to one gate line (GL), so that the switching transistor (SWT) and the sensing transistor (SENT) are connected by the scan signal (SCAN) transmitted through this. The case of turning on or off at the same time is shown, but as described above, a scan signal (SCAN) is applied to the gate node of the switching transistor (SWT), and a sense signal (SENSE) is applied to the gate node of the sensing transistor (SENT). It would be possible to apply the same in the case of a separation structure where .

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: Organic light emitting display device 110: Display panel
120: gate driving circuit 130: data driving circuit
140: Controller 210: Power management integrated circuit
220: main power management circuit 230: set board

Claims (13)

A display panel on which a plurality of gate lines, a plurality of data lines and a plurality of subpixels are arranged;
a gate driving circuit that drives the plurality of gate lines and sequentially applies scan signals to N rows of subpixels as subpixel groups;
a data driving circuit that drives the plurality of data lines; and
Controlling the driving voltage applied to the gate driving circuit and the data driving circuit, and controlling the gate driving circuit to additionally secure a precharging period before applying a scan signal to the first subpixel of the subpixel group Contains a controller,
Does not include the precharging period before applying a scan signal to subpixels after the first subpixel among the subpixel group,
The organic light emitting display device wherein the scan signal applied to the first subpixel is delayed by the precharging period compared to the scan signal applied to subpixels after the first subpixel.
According to paragraph 1,
The subpixel is
organic light emitting diode;
A driving transistor driving the organic light emitting diode;
a switching transistor electrically connected between the gate node of the driving transistor and the data line;
A sensing transistor electrically connected between the source node or drain node of the driving transistor and a reference voltage line; and
An organic light emitting display device comprising a storage capacitor electrically connected between a gate node of the switching transistor and a source node or drain node.
According to paragraph 1,
An organic light emitting display device where N is any natural number.
According to paragraph 1,
An organic light emitting display device wherein the scan signal is applied at intervals of 1 horizontal cycle.
According to paragraph 1,
The controller controls the data driving circuit to apply a data voltage for precharging to a first subpixel of the subpixel group during the precharging period.
According to paragraph 1,
The precharging period is an organic light emitting display device having one horizontal period.
According to paragraph 1,
The data line is
An organic light emitting display device that operates in the DRD (Double Rate Driving) method in which one data line is placed between two adjacent subpixels and the two subpixels placed on both sides are driven by one data line.
A display panel including a plurality of data lines and a plurality of gate lines, a plurality of subpixels arranged in an area where the plurality of data lines and the gate lines intersect, a plurality of subpixels, and the plurality of data lines. A method of driving an organic light emitting display device including a data driving circuit for driving, a gate driving circuit for driving the plurality of gate lines, and a controller for controlling driving signals applied to the gate driving circuit and the data driving circuit. In
Using N rows of subpixels as a first subpixel group, sequentially applying scan signals through the gate driving circuit;
additionally securing a precharging period before applying a scan signal to a first subpixel in a second subpixel group of N rows that is adjacent to the first subpixel group of N rows and has a different color; and
sequentially applying a scan signal to the second subpixel group through the gate driving circuit,
In the step of additionally securing the precharging section, the precharging section is not included before applying a scan signal to a subpixel after the first subpixel among the second subpixel group,
In the step of sequentially applying the scan signal, the scan signal applied to the first subpixel is applied with a delay by the precharging period compared to the scan signal applied to subpixels after the first subpixel. Driving method.
According to clause 8,
A method of driving an organic light emitting display device, wherein N is an arbitrary natural number.
According to clause 8,
A method of driving an organic light emitting display device, wherein the scan signal is applied at intervals of 1 horizontal cycle.
According to clause 8,
A method of driving an organic light emitting display device in which a data voltage for precharging is applied to a first subpixel of the subpixel group during the precharging period.
According to clause 8,
A method of driving an organic light emitting display device in which the precharging section has one horizontal period.
According to clause 8,
The data line is
A driving method of an organic light emitting display device operating in a double rate driving (DRD) method in which one data line is disposed between two adjacent subpixels and the two subpixels disposed on both sides are driven by one data line.

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