KR102635444B1 - Decoder, operating method thereof and memory system including the decoder for decoding non-binary low-density parity check code - Google Patents

Abstract

The present invention relates to a non-binary low-density parity check code decoder, an operating method thereof, and a memory system according to an embodiment of the present invention, wherein the method for decoding a non-binary low-density parity check code includes a code composed of N hard decision symbols from a semiconductor memory. Words (Codewords) are received, and based on the hard decision symbols constituting the received codewords, the smaller the Hamming distance is, the larger the Hamming distance is for each hard decision symbol and the remaining symbols in the Galois field, excluding each hard decision symbol. generating information; and determining an error correction codeword based on the similar soft decision information.

Description

Non-binary low-density parity check code decoder, its operating method and memory system {DECODER, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE DECODER FOR DECODING NON-BINARY LOW-DENSITY PARITY CHECK CODE}

The present invention relates to a technology for decoding a nonbinary low-density parity-check (NB-LDPC), and more specifically, to a nonbinary low-density parity check using similar soft decision information for NAND flash memory. It relates to a code decoder, its operation method and memory system.

The present invention relates to low-density parity check codes, and more specifically, to technology for decoding non-binary low-density parity check codes.

Low Density Parity Check Codes (LDPC Codes) are error correction codes first proposed in 1962 and are forward error correction codes belonging to Linear Block Code. ) is a type of At the time this code was proposed, vacuum tubes were beginning to be replaced by transistors, and at that time, this code was not put into practical use due to the enormous amount of calculations required for simulation to verify the code and the difficulties in its implementation. However, thanks to the development of information and communication technology over the past 30 years, the recent emergence of high-performance processors, and the need to provide high-quality services in the field of multimedia mobile communications, the utility of this code has recently been re-recognized, and the characteristics of this code and its encoding have been changed. /Research on decryption methods is gaining momentum. This code is also being proposed as a channel coding method in the 4th generation mobile communication system to replace Turbo Codes.

The LDPC code, like the turbo code, is known to show excellent performance approaching Shannon's channel capacity (Shannon Limit). The LDPC code has superior performance compared to the turbo code, the implementation of the decoder is not very complicated, and parallel operation is possible, enabling high-speed processing, and like the turbo code, a stochastic iterative decoding technique can be applied, resulting in a low error rate and It is known to be suitable for mobile communication systems that require high-speed data processing. These LDPC codes are binary LDPC codes in which the components of the H matrix corresponding to the parity check matrix are binary elements, and non-binary LDPC codes in which the components of the H matrix are not binary elements. It can be divided into codes (Non-Binary LDPC Codes). Binary LDPC codes show weaknesses in terms of bit error rate for short or medium-length codewords, while non-binary LDPC codes show excellent performance even for short-length codewords. Even at low error rates, it generally shows superior performance to binary LDPC codes, including no error floor phenomenon.

However, the non-binary LDPC code has the disadvantage that its complexity increases as the row weight of the H matrix or the order q of the Galois Field (GF) increases during the decoding process. Accordingly, research on methods to reduce the amount of computation in the decoding process by simplifying the decoding process without significantly reducing the performance of the LDPC decoder is being actively conducted.

The object of the present invention is to provide a decoding method for non-binary LDPC codes that enables high-speed decoding while minimizing performance degradation of the non-binary LDPC decoder.

Another object of the present invention is to provide a method for decoding non-binary LDPC codes that can reduce the amount of computation and computation delay at check nodes of a non-binary LDPC decoder.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. Therefore, a decoding method that can reduce decoding complexity and prevent deterioration of error rate performance is required.

The present invention seeks to provide a decoding method and device that can reduce decoding complexity and improve error rate performance.

The problem to be solved by the present invention is not limited to the problem(s) mentioned above, and other problem(s) not mentioned will be clearly understood by those skilled in the art from the description below.

A method of decoding a non-binary low-density parity check code according to an embodiment of the present invention to achieve the above object includes receiving codewords consisting of hard decision symbols from a semiconductor memory; Generating pseudo-soft decision information that becomes larger as the Hamming distance decreases for each hard decision symbol and the remaining symbols excluding the hard decision symbols in the Galois field, based on N hard decision symbols constituting the received codeword; It is characterized by comprising the step of performing a variable node and check node operation and comparing the similar soft decision information with a preset threshold to determine an error correction codeword (corrected codeword).

In one embodiment, the step of generating the pseudo soft decision information includes multiplying a value considering the Hamming distance between the hard decision symbol and the remaining symbols excluding the hard decision symbol among the always received codewords by a column weight to generate pseudo soft decision information. It is characterized by generating.

In one embodiment, the step of determining the error correction codeword includes M check nodes having a connection relationship with the N variable nodes, which are determined by the parity check matrix (H) of the low-density parity check code, and The received codeword is decrypted by repetitive message exchange between N variable nodes.

In one embodiment, the non-binary low-density parity check code is characterized as a code defined for a Galois field GF(q) of order q.

In one embodiment, the step of determining the codeword (corrected codeword) includes a syndrome check, check node update, and variable node update as one set, and the set is repeatedly executed a preset number of times.

In one embodiment, the check node update performs EXI (Extrinsic information sum) operation every time, and when updating the similar soft decision information of the symbol obtained as a result of the EXI operation, the weight coefficient calculated based on the Hamming distance is used. It is characterized by its use.

In one embodiment, the check node update is characterized by updating similar soft decision information about the hard decision symbol received from the variable node without performing the EXI operation when the result value of the ith syndrome check is 0 every time. do.

A non-binary low-density parity check code decoder according to another embodiment of the present invention receives a codeword consisting of N hard decision symbols from a semiconductor memory, and the hard decision symbols and the remaining symbols in the GF excluding the hard decision symbols. An initialization module that generates similar soft decision information that becomes larger as the Hamming distance decreases; and a node processor that determines a corrected codeword using symbols with the largest value among the pseudo soft decision information.

A semiconductor memory system according to an embodiment of the present invention includes a semiconductor memory that stores a codeword, which is encoded data; a decoder that generates decoded data by decoding the codeword stored in the semiconductor memory through a parity check matrix composed of submatrices; and a channel connecting the semiconductor memory and the decoder and providing the codeword of the semiconductor memory device to the decoder.

The semiconductor memory according to an embodiment of the present invention is characterized as a NAND flash memory.

The present invention has the effect of improving BER (Bit Error Rate) performance and reducing the amount of calculation.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Figure 1 is a diagram for explaining the configuration of a decoder for a non-binary low density parity check (NB-LDPC) code according to an embodiment of the present invention.
Figure 2 is an example diagram for explaining a parity check matrix according to an embodiment of the present invention.
FIG. 3 is a diagram showing the parity check matrix shown in FIG. 2 as a Tanner graph.
Figure 4 is a diagram showing an algorithm for decoding according to an embodiment of the present invention.
Figure 5 is a diagram for explaining the reliability of hard decision information according to an embodiment of the present invention.
Figure 6 is a diagram showing an algorithm for decoding according to another embodiment of the present invention.
Figure 7 is a flowchart explaining a method of decoding a non-binary low-density parity check code according to an embodiment of the present invention.
Figure 8 is a configuration diagram showing the schematic configuration of a semiconductor memory system according to an embodiment of the present invention.

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention. While describing each drawing, similar reference numerals are used for similar components.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention. The term and/or includes any of a plurality of related stated items or a combination of a plurality of related stated items.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless explicitly defined in the present application, should not be interpreted in an ideal or excessively formal sense. No.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

A decoder according to an embodiment of the present invention can receive a signal corresponding to a codeword from a channel and perform error correction decoding on the received signal.

The decoder according to an embodiment of the present invention can perform error correction decoding using various algorithms that adopt an iterative decoding scheme. The decoder according to an embodiment of the present invention can perform error correction decoding using a message passing algorithm (MPA), also called a belief propagation algorithm (BPA). As a message passing algorithm, a bit flipping algorithm, symbol flipping algorithm, min-sum algorithm, or sum-product algorithm may be used.

The decoder according to an embodiment of the present invention can perform error correction decoding within a set maximum iteration number (I). Here, I may be a natural number. The error correction decoder converts the generated valid codeword into a decoded code when a valid codeword that satisfies the constraints of the parity check matrix of the error correction code is generated within the maximum number of repetitions (I). It can be output as a word (decoded codeword).

If a valid codeword that satisfies the constraints of the parity check matrix of the error correction code is not generated within the maximum number of repetitions (I), the decoder according to an embodiment of the present invention sends a fail signal indicating that error correction decoding has failed. ) signal can be output.

Figure 1 is a diagram for explaining the configuration of a decoder for a non-binary low density parity check (NB-LDPC) code according to an embodiment of the present invention, and Figure 2 is an example of the present invention. This is an example diagram for explaining a parity check matrix according to an embodiment.

Referring to FIG. 1, the decoder 200 may include an initialization module 210, a variable node processing module 220, a check node processing module 230, and a syndrome check module 240. The variable node processing module 220, the check node processing module 230, and the syndrome check module 240 can all be referred to as a node processor.

Initialization module 210 may receive a read vector corresponding to the codeword from the channel. The initialization module 210 may configure initial symbols to be assigned to variable nodes by grouping read values included in the read vector.

Additionally, the initialization module 210 may generate soft decision information (also referred to as reliability) based on initial symbols. Similar soft decision information may be generated using the Hamming distance based on hard decision values. In one embodiment, pseudo soft decision information is calculated by multiplying the Hamming distance by the column weight dv.

The initialization module 210 may initialize variable nodes using initial symbols received from the initialization module 210 before the first repetition is performed. That is, the initialization module 210 may generate similar soft decision values of the variable nodes based on each of the initial symbols forming the codeword and assign them to each of the variable nodes.

The variable node processing module 220 and the check node processing module 230 exchange messages between variable nodes and check nodes. Through this, it is possible to generate results that converge to the codeword.

More specifically, the variable node processing module 220 generates a variable-to-check (V2C) message transmitted from the variable node to the check node and delivers it to the check node processing module 230.

The check node processing module 230 generates a check-to-variable (C2V) message transmitted from the check node to the variable node and delivers it to the variable node processing module 220.

In the first iteration, the variable node processing module 220 generates V2C messages so that similar soft decision values of the variable nodes can be delivered to the check nodes, and each variable node based on the C2V messages received from the check node. The pseudo soft decision value of can be updated.

In one embodiment, the output of the variable node processing module 220 becomes an input value corresponding to columns in which element values of the row have non-zero values (variable nodes) for each row of each parity check matrix.

The check node processing module 230 generates C2V messages based on V2C messages received from the variable node in each iteration except the first iteration.

In one embodiment, the output of the check node processing module 230 is similar to the output of the variable node processing module 220, the value of the row having a non-zero value in each column based on the columns of the parity check matrix (H) are output, and this is input to the variable node processing module 220.

In another embodiment, the check node processing module 230 may update the next reliability with a value obtained by adding a weight coefficient θ based on the Hamming distance to the reliability. This will be explained in detail with reference to FIG. 6, which will be described later.

The syndrome check module 240 may perform a syndrome check on the hard decision values of the variable node in response to the i-th repetition. For example, the syndrome check can be performed by checking whether the value calculated by Equation 1, which is the syndrome check equation, is 0.

[Equation 1]

Here, z ^(k) is the hard decision value correspondingly generated at the kth iteration, and H is the parity check matrix of the error correction code.

Hard decision symbol at kth iteration is passed from the jth variable node to the neighboring channel node.

EXI (extrinsic information sum) passed from the ith channel node to the jth variable node is It is expressed as is calculated as in Equation 2.

[Equation 2]

Here, Ni connected to the ith channel node means a set of variable nodes, is a subset of Ni, meaning the set excluding the jth variable node (0≤i<M, 0≤j<N) from Ni.

derived Based on , the variable node updates the hard decision vector z ^(k) as shown in Equation 3.

[Equation 3]

In another embodiment, the syndrome check module 240 outputs the decision value of the variable node where all result values of the syndrome check are 0 as a codeword.

Referring to Figure 2, an example of a parity check matrix (H) defining an (n, k) code is shown. The (n, k) code can be defined as a parity check matrix with a size of (n-k)×n. In one embodiment, a 3×4 parity check matrix is illustrated for convenience of explanation, but the present invention is not limited thereto. Each entry of the parity check matrix can be expressed as elements belonging to a Galois field.

The Galois field (GF(q)) is a finite field composed of q elements, where q=2 ^p and p is a positive integer.

Elements of the Galois field (GF(q)) can be expressed as {0, α ⁰ , α ¹ , ..., α ^q-2 }.

If all entries calculated by Equation 1, which is the syndrome check equation, are 0, it means that the syndrome check has passed, and if there is a non-zero entry among all entries in the syndrome vector (S _i ), the syndrome check has failed. It may mean that (failed).

If the syndrome check passes, the syndrome check module 240 may output the hard decision vector as a decoded codeword.

If the syndrome check does not pass within the maximum number of repetitions (Imax), the node processor 220 may output a fail signal indicating that error correction decoding has failed.

A codeword consisting of N symbols received by repetitive message exchange between M check nodes having a connection relationship with N variable nodes and the N variable nodes is decoded.

FIG. 3 is a diagram showing the parity check matrix shown in FIG. 2 as a Tanner graph.

The parity check matrix as shown in FIG. 2 can be expressed as a Tanner graph, which is an equivalent bipartite graph representation. A Tanner graph can be represented by check nodes, variable nodes, and edges. Check nodes correspond to rows of the parity check matrix, and variable nodes correspond to columns of the parity check matrix. Each edge connects one check node and one variable node, and corresponds to a non-zero entry in the parity check matrix.

In a Tanner graph, the degree of a node, which is the number of adjacent nodes, corresponds to the number of non-zero elements in a column or row and is called the weight of the matrix. These NB-LDPC codes have column weights dv and row weights dc.

For an NB-LDPC code with a length of N, when the codeword of C is c=[c ₀ , c ₁ , c ₂ ,..., c _N-1 ], the channel input vector and reception vector are respectively x=[x ₀ , x ₁ , x ₂ ,..., x _N-1 ] and y=[y ₀ , y ₁ , y ₂ ,..., y _N-1 ]. Here, vector y is a vector in which noise is added to x. Based on Y, the hard decision vector of the kth decoded received symbol is z ^(k) = [ , , ..., ]. Therefore, z ⁽⁰⁾ consists of the hard decision symbols of the channel output and is the input of the decoder. The goal of decoding repetition is to ensure that z ^(k) satisfies 0 as the calculation result of Equation 1, which is the syndrome check equation. This means that z ^(k), which sets the syndrome check equation to 0, is a codeword.

FIG. 4 is a diagram illustrating an algorithm for decoding according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating the reliability of hard decision information according to an embodiment of the present invention.

As can be seen with reference to Figure 4, the algorithm for decoding is largely divided into 1. initialization step 2. syndrome check 3. check node update 4. variable node update.

The above algorithm is repeatedly executed a preset number of times (Imax). Accordingly, it can be seen that channel node update (CN update) and variable update (VN update) are also repeated.

More specifically, in the initialization step, dv × p represents the highest reliability among all symbols at initialization. Here p is calculated as log ₂ q. The reliability of all other symbols is set as in Equation 4.

[Equation 4]

The closer the Hamming distance from the hard decision symbol, the higher the reliability of the symbol. The Hamming distance can be easily calculated using a binary XOR operation between symbols.

If EXI (extrinsic information) operation is performed from the i-th CN neighboring the j-th VN and the operation value σ _i,j is a1, will be voted on in the next iteration, = It can be expressed as +1.

Referring to FIG. 5, unlike assigning reliability only to hard decision symbols and symbols with a Hamming distance of 1, in one embodiment, reliability values are assigned differentially to all symbols according to the Hamming distance, and multiplied by dv to determine the reliability value according to the Hamming distance. The reliability values (R) differ by the column weight dv. By multiplying dv, we can prevent the symbol with maximum confidence from changing in the next iteration in one vote.

The syndrome check is performed based on Equation 1, the syndrome check equation, using the transpose matrix of the parity check matrix (H). The calculated syndrome check equation is less than the selected value or is repeated a selected number of times.

The codeword can be decrypted by repeating check node updates and variable node updates through repeated message exchange between the check node and variable node.

Figure 6 is a diagram showing an algorithm for decoding according to another embodiment of the present invention.

jth confidence of received symbol is initialized based on the hard decision information from the channel output and the Hamming distance between the different Galois field elements.

As can be seen with reference to Figure 6, the algorithm for decoding is largely divided into 1. initialization step 2. syndrome check 3. check node update 4. variable node update.

Since the initialization step of the algorithm in FIG. 6 is similar to the initialization step in FIG. 4, detailed description is omitted.

Looking at the check node update, For the same reason that is used for initialization, the Hamming distance is used to determine the weight coefficients. Calculate .

The smaller the Since the reliability of is higher, the corresponding weighting coefficient θ also gets bigger.

Looking at the VN update step, in the soft decision decoding algorithm, channel information is used in each iteration of VN update. The hard decision symbols at the channel output are voted on and updated in each VN.

In the syndrome check step of repeated decoding, the syndrome s ^(k) is repeatedly calculated according to Equation 5 at the end of each VN update.

[Equation 5]

s ^(k) = z ^(k) H ^T

Here, when the syndrome s ^(k) is 0, decoding is terminated and z ^(k) is output as a codeword.

In the syndrome s ^(k) operation, z ^(k) H ^T is a matrix multiplication, and the output vector length of the matrix multiplication becomes M. Each element of the output vector is calculated by Equation 6.

[Equation 6]

Here, Equation 6 can be expressed as Equation 7.

[Equation 7]

In Equation 5, if the syndrome s ^(k) is 0, it becomes the same as the EXI of the ith channel node, as in [Equation 8].

[Equation 8]

Here, addition and multiplication operations are Galois field operations. Referring to equation 6, When is 0 go It can be seen that it is the same as this is, When is 0, it means that EXI operation can be skipped in CN update.

Each channel node checks the syndrome and then Stores 1-bit information indicating whether is 0.

A check node CN with a value of 0 is called CN _SAT , and other check nodes CN are called CN _UNSAT . In the case of CN _SAT , the EXI operation is skipped in the CN update step, and Set the weight coefficient by calculating only the Hamming distance between them. Therefore, the amount of EXI calculation can be reduced without affecting the error rate performance of the decoder.

Figure 7 is a flowchart explaining a method of decoding a non-binary low-density parity check code according to an embodiment of the present invention.

Decoding the non-binary low-density parity check code of FIG. 7 is performed by the decoder described based on FIGS. 1 to 6.

In step S100, the decoder receives a readout vector corresponding to the codeword from the channel.

In step S110, the read values included in the received read vector are assigned to variable nodes, and the reliability of the hard decision is calculated using the Hamming distance based on the assigned values to generate similar soft decision information. Hard decision information can be provided from the outside, and similar soft decision information is initialized by calculating the Hamming distance between the hard decision symbol and other symbols multiplied by the column weight. At initialization, the number of executions for one iteration consisting of check node update, variable node update, and syndrome check can be set.

In step S120, syndrome values are calculated for all test nodes.

If the calculated syndrome value is 0, the process proceeds to step S160, the decision value of the variable node is output as a codeword, and decoding is terminated.

Proceeding to step S130, if the calculated syndrome value is not 0, it is checked whether the number of repetitions is a preset number of executions. If not, the check node update and variable node update are performed in step S140.

The check node update performs EXI (Extrinsic information sum) operation every time, and when updating the similar soft decision information of the symbol obtained as a result of the EXI operation, the weight coefficient calculated based on the Hamming distance can be used.

In one embodiment, the check node update performs an EXI operation every time, and if the result value of the ith syndrome check is 0, the EXI operation is not performed and similar soft decision information is provided for the hard decision symbol received from the variable node. can be updated.

If the number of repetitions is the same as the preset number of executions in step S130, the process proceeds to step S170, where it is determined that decoding of the hard decision data has failed and a fail is output.

The number of repetitions is increased by 1 in S150, and the decoding operation of step S150 is repeated in step S120.

One iteration consisting of check node update, variable node update, and syndrome check is performed multiple times.

Figure 8 is a configuration diagram showing the schematic configuration of a semiconductor memory system according to an embodiment of the present invention.

The semiconductor memory system may include a semiconductor memory 100, a decoder 200, and a channel 300.

The semiconductor memory 100 stores codewords, which are encoded data. The semiconductor memory 100 may be NAND flash memory.

The decoder 200 decodes the codeword stored in the semiconductor memory 100 using a parity check matrix to generate decoded data. Since the decoder 200 includes the functions of the decoder 200 described with reference to FIGS. 1 to 6, detailed description will be omitted.

The channel 300 connects the semiconductor memory 100 and the decoder 200.

In one embodiment, the channel 300 may obtain a hard decision value based on a codeword read from the semiconductor memory 100.

Channel 300 provides the hard decision value to decoder 200.

As described above, the decoder according to an embodiment of the present invention can perform decoding at a high processing speed while maintaining good error rate performance, so it can be applied to NAND flash memory where the memory space allowed for parity bits is relatively small. .

So far, the present invention has been examined focusing on its preferred embodiments. A person skilled in the art to which the present invention pertains will understand that the present invention may be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the equivalent scope should be construed as being included in the present invention.

Claims (15)

A method for decoding a non-binary low-density parity check code, comprising:
Receiving codewords consisting of N hard decision symbols from a semiconductor memory;
Generating pseudo-soft decision information that becomes larger as the Hamming distance decreases for each hard decision symbol and the remaining symbols in the Galois field excluding each hard decision symbol, based on the hard decision symbols constituting the received codeword; and
determining an error correction codeword based on the similar soft decision information;
Including,
The step of generating the similar soft decision information is,
Similar soft decision information is generated by multiplying the value considering the Hamming distance between each hard decision symbol and the remaining symbols in the Galois field, excluding each hard decision symbol, by the column weight corresponding to the NB-LDPC (nonbinary low-density parity-check) code. A non-binary low-density parity check code decoding method characterized by generating.
delete According to paragraph 1,
The step of determining the error correction codeword is,
Decrypt the codeword by repetitive message exchange between the N variable nodes and M check nodes having a connection relationship with the N variable nodes, which is determined by the parity check matrix (H) of the low-density parity check code. A non-binary low-density parity check code decoding method, characterized in that.
According to paragraph 1,
The non-binary low-density parity check code decoding method, characterized in that the non-binary low-density parity check code is a code defined for a Galois field GF(q) of order q.
According to paragraph 4,
The step of determining the codeword (corrected codeword) is
A non-binary low-density parity check code decoding method comprising one set of syndrome check, check node update, and variable node update, and the set is repeatedly executed a preset number of times.
According to clause 5,
The check node update performs EXI (Extrinsic information sum) operation every time, and updates the similar soft decision information based on the EXI operation result,
A non-binary low-density parity check code decoding method, characterized in that the EXI operation is calculated based on Equation 2 below.
[Equation 2]

Here, the EXI passed from the ith channel node to the jth variable node is It is expressed as means the parity check matrix (H), Ni connected to the ith channel node means a set of variable nodes, is a subset of Ni, meaning the set excluding the j-th variable node (0≤i<M, 0≤j<N) from Ni, refers to the hard decision value correspondingly generated in the kth iteration.
According to clause 6,
The check node update is non-binary low-density, characterized in that, if the result value of the ith syndrome check is 0 every time, the EXI operation is not performed and pseudo-soft decision information is updated for the hard decision symbol received from the variable node. How to decode parity check code.
Codewords consisting of N hard decision symbols are received from the semiconductor memory, and based on the hard decision symbols constituting the received codewords, the remaining symbols excluding each hard decision symbol within each hard decision symbol and Galois field are received. An initialization module that generates similar soft decision information that becomes larger as the Hamming distance decreases; and
a node processor that determines an error correction codeword based on the pseudo soft decision information;
Including,
The initialization module is,
In order to generate the pseudo soft decision information, a value corresponding to a nonbinary low-density parity-check (NB-LDPC) code is calculated based on the Hamming distance between each hard decision symbol and the remaining symbols in the Galois field, excluding each hard decision symbol. A non-binary low-density parity check code decoder characterized by generating pseudo soft decision information by multiplying column weights.
According to clause 8,
The initialization module is,
Similar soft decision information is generated by multiplying the value considering the Hamming distance between each hard decision symbol and the remaining symbols in the Galois field, excluding each hard decision symbol, by the column weight corresponding to the NB-LDPC (nonbinary low-density parity-check) code. A non-binary low-density parity check code decoder characterized by generating.
According to clause 8,
The node processor is,
The received codeword is determined by the parity check matrix (H) of the low-density parity check code by repetitive message exchange between the M check nodes having a connection relationship with the N variable nodes and the N variable nodes. A non-binary low-density parity check code decoder, characterized in that decoding.
According to clause 8,
The node processor is,
A non-binary low-density parity check code decoder comprising a syndrome check, check node update, and variable node update as one set, and the set is repeatedly executed a preset number of times.
According to clause 11,
The check node update performs EXI (Extrinsic information sum) operation every time, and updates the similar soft decision information based on the EXI operation result,
A non-binary low-density parity check code decoder, characterized in that the EXI operation is calculated based on Equation 2 below.
[Equation 2]

Here, the EXI passed from the ith channel node to the jth variable node is It is expressed as means the parity check matrix (H), Ni connected to the ith channel node means a set of variable nodes, is a subset of Ni, meaning the set excluding the j-th variable node (0≤i<M, 0≤j<N) from Ni, refers to the hard decision value correspondingly generated in the kth iteration.
According to clause 12,
The check node update is non-binary low-density, characterized in that, if the result value of the ith syndrome check is 0 every time, the EXI operation is not performed and pseudo-soft decision information is updated for the hard decision symbol received from the variable node. Parity check code decoder.
A semiconductor memory that stores codewords, which are encoded data;
a decoder that generates decoded data by decoding the codeword stored in the semiconductor memory through a parity check matrix composed of submatrices; and
A channel that connects the semiconductor memory and the decoder and provides the codeword of the semiconductor memory to the decoder
Including,
The decoder is
Codewords consisting of N hard decision symbols are received from a semiconductor memory, and the remaining symbols excluding each hard decision symbol within each hard decision symbol and Galois field are based on the hard decision symbols constituting the received codeword. An initialization module that generates similar soft decision information that becomes larger as the Hamming distance decreases; and
a node processor that determines an error correction codeword based on the pseudo soft decision information;
Including,
The initialization module is,
In order to generate the pseudo soft decision information, a value corresponding to a nonbinary low-density parity-check (NB-LDPC) code is calculated based on the Hamming distance between each hard decision symbol and the remaining symbols in the Galois field, excluding each hard decision symbol. A semiconductor memory system characterized by generating similar soft decision information by multiplying column weights.
15. The semiconductor memory system of claim 14, wherein the semiconductor memory is a NAND flash memory.