KR102610925B1 - Display device having a dummy pad disposed side by side a signal pad - Google Patents

Abstract

The present invention relates to a display device including a dummy pad positioned in parallel with a signal pad. The signal pad may be connected to the driver IC through a signal supply wire. The dummy pad may be insulated from the signal supply wire. The dummy pad may be connected to the common voltage supply line through a dummy connection line. Accordingly, malfunctions due to static electricity can be minimized in the display device according to the technical idea of the present invention. Therefore, reliability can be improved in the display device according to the technical idea of the present invention.

Description

Display device having a dummy pad disposed side by side a signal pad}

The present invention relates to a display device in which a signal pad and a dummy pad are positioned side by side on a non-display area of an array substrate.

In general, electronic devices such as monitors, TVs, laptops, digital cameras, etc. include display devices to display images. For example, the display device may include a liquid crystal display device and/or an organic light emitting display device.

The display device may include a display area and a non-display area. The display area can implement a specific image according to the user's request. The non-display area may be located outside the display area. The non-display area may generate/provide signals for implementing an image. For example, a driver IC may be located in the non-display area.

A pad area for receiving signals from the outside may be located within the non-display area. For example, the driver IC may be located between the display area and the pad area. At least one signal pad connected to the driver IC through a signal supply wire may be located within the pad area. The pad area may include a dummy pad positioned parallel to the signal pad. The dummy pad can prevent damage to some signal pads due to differences in density during the manufacturing process.

The dummy pad may be insulated from the signal supply wire. For example, the dummy pad may be in a floating state. However, charges generated by static electricity may accumulate in the floating dummy pad. Accordingly, in the display device, charges accumulated in the dummy pad may be transferred to the driver IC through adjacent signal pads and/or signal supply lines.

The problem to be solved by the present invention is to provide a display device that can minimize malfunction due to static electricity.

Another problem to be solved by the present invention is to provide a display device that can prevent charges charged by static electricity from accumulating in a dummy pad.

The problems to be solved by the present invention are not limited to the problems mentioned above. Problems not mentioned herein will become clear to those skilled in the art from the description below.

A display device according to the technical idea of the present invention to achieve the above-mentioned problem includes an array substrate. The array substrate includes a display area and a non-display area. The non-display area is located outside the display area. A driver IC, a signal pad, and a dummy pad are located on the non-display area of the array substrate. The driver IC is electrically connected to the display area. The signal pad is connected to the driver IC by a signal supply wire. The dummy pad is insulated from the signal supply wiring. The dummy pad is connected to the common voltage supply wire by a dummy connection wire.

The signal pad and dummy pad may be located between the driver IC and the common voltage supply line.

A test thin film transistor may be located between the signal pad and the common voltage supply line.

A driving thin film transistor may be located on the display area of the array substrate. The test thin film transistor may have the same structure as the driving thin film transistor.

The test thin film transistor may include a gate electrode, a gate insulating film, a semiconductor pattern, a source electrode, and a drain electrode. The dummy connection wire may include the same material as the drain electrode of the test thin film transistor.

A dummy pattern may be positioned between the array substrate and the dummy pad. The dummy pattern may include the same material as the semiconductor pattern of the test thin film transistor.

The gate electrode of the test thin film transistor may extend between the array substrate and the dummy pad.

The common voltage supply wiring may extend parallel to the gate electrode of the test thin film transistor.

A touch pad may be located on the non-display area of the array substrate. The touch pad may be connected to the driver IC through a touch supply wire. A dummy pad may be located between the signal pad and the touch pad. The touch supply wiring can be isolated from the dummy pad.

The touch supply wiring may include the same material as the signal supply wiring.

A planarization film may be positioned on the display area of the array substrate. A lower protective film may be positioned on the planarization film. An upper protective film may be located on the lower protective film. A pixel electrode may be located between the planarization film and the lower protective film. A common electrode may be located on the upper protective film. The common electrode may include at least one slit that overlaps the pixel electrode. A touch electrode may be located between the lower protective film and the upper protective film. The touch electrode may be located outside the pixel electrode. The signal supply wiring may include the same material as the touch electrode.

The planarization film may include a trench. The trench of the planarization film may be located on a non-display area of the array substrate. Signal pads, dummy pads, and touch pads may be located within the trenches of the planarization film.

In a display device according to the technical idea of the present invention, a dummy pad located in parallel with a signal pad on a non-display area of an array substrate is insulated from the signal supply wire connecting the signal pad to the driving IC, and the common electrode is formed by the dummy connection wire. Can be connected to supply wiring. Accordingly, in the display device according to the technical idea of the present invention, charges charged by static electricity may not be accumulated in the dummy pad. Therefore, in the display device according to the technical idea of the present invention, malfunction due to static electricity can be minimized and reliability can be improved.

1 is a diagram schematically showing a display device according to an embodiment of the present invention.
Figure 2a is an enlarged view of area P in Figure 1.
Figure 2b is an enlarged view of area R in Figure 1.
FIG. 3A is a diagram showing a cross section taken along line II' of FIG. 2A.
FIG. 3b is a diagram showing a cross section taken along line II-II' of FIG. 2b.
FIG. 3C is a cross-sectional view taken along line III-III' of FIG. 2B.
Figure 4 is a diagram schematically showing a display device according to another embodiment of the present invention.
5A to 11A, 5B to 11B, and 5C to 11C are diagrams sequentially showing the manufacturing process of a display device according to an embodiment of the present invention.

Details regarding the above-mentioned purpose, technical configuration, and effects thereof of the present invention will be more clearly understood through the following detailed description with reference to the drawings showing embodiments of the present invention. Here, since the embodiments of the present invention are provided so that the technical idea of the present invention can be sufficiently conveyed to those skilled in the art, the present invention may be embodied in other forms so as not to be limited to the embodiments described below.

In addition, parts indicated with the same reference numerals throughout the specification refer to the same components, and the length and thickness of a layer or region in the drawings may be exaggerated for convenience. Additionally, when a first component is described as being “on” a second component, it does not only mean that the first component is located above and in direct contact with the second component, but also that the first component and the It also includes cases where a third component is located between second components.

Here, the terms first, second, etc. are used to describe various components and are used for the purpose of distinguishing one component from other components. However, without departing from the technical spirit of the present invention, the first component and the second component may be arbitrarily named according to the convenience of those skilled in the art.

The terms used in the specification of the present invention are only used to describe specific embodiments and are not intended to limit the present invention. For example, an element expressed in the singular includes plural elements unless the context clearly indicates only the singular. In addition, in the specification of the present invention, terms such as "comprise" or "have" are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are intended to indicate the presence of one or It should be understood that this does not preclude the existence or addition of other features, numbers, steps, operations, components, parts, or combinations thereof.

Additionally, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless clearly defined in the specification of the present invention, they should not be taken in an idealistic or excessively formal sense. It is not interpreted.

(Example)

1 is a diagram schematically showing a display device according to an embodiment of the present invention. Figure 2a is an enlarged view of area P in Figure 1. Figure 2b is an enlarged view of area R in Figure 1. FIG. 3A is a diagram showing a cross section taken along line II' of FIG. 2A. FIG. 3b is a diagram showing a cross section taken along line II-II' of FIG. 2b. FIG. 3C is a cross-sectional view taken along line III-III' of FIG. 2B.

Referring to FIGS. 1, 2a, 2b, and 3a to 3c, a display device according to an embodiment of the present invention may include an array substrate 110. The array substrate 110 may include an insulating material. The array substrate 110 may include a transparent material. For example, the array substrate 110 may include plastic or glass.

The array substrate 110 may include a display area (AA) and a non-display area (NA). The display area (AA) can implement an image according to the user's request. For example, the display area AA may include a plurality of pixel areas. Each pixel area may be defined by a gate line (GL) and a data line (DL). For example, the data line DL may intersect the gate line GL.

A driving thin film transistor 200 may be located within each pixel area. The driving thin film transistor 200 may be driven by a gate signal applied through the gate line GL and a data signal applied through the data line DL. For example, the driving thin film transistor 200 may include a driving gate electrode 210, a driving gate insulating film 220, a driving semiconductor pattern 230, a driving source electrode 240, and a driving drain electrode 250. there is.

The driving gate electrode 210 may be located close to the array substrate 110. For example, the driving gate electrode 210 may directly contact the array substrate 110. The driving gate electrode 210 may include a conductive material. For example, the driving gate electrode 210 may include metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

The driving gate electrode 210 may be electrically connected to the gate line GL. The gate line GL may include the same material as the driving gate electrode 210. For example, the driving gate electrode 210 may have a shape that protrudes from the gate line GL extending in the first direction in a second direction perpendicular to the first direction.

The driving gate insulating layer 220 may be located on the driving gate electrode 210 . The driving gate insulating layer 220 may extend outward from the driving gate electrode 210 . For example, the side of the driving gate electrode 210 may be covered by the driving gate insulating film 220.

The driving gate insulating layer 220 may include an insulating material. For example, the driving gate insulating layer 220 may include silicon oxide and/or silicon nitride. The driving gate insulating layer 220 may include a high-K material. For example, the driving gate insulating layer 220 may include hafnium oxide (HfO) or titanium oxide (TiO).

The driving semiconductor pattern 230 may be located on the driving gate insulating layer 220 . The driving semiconductor pattern 230 may include a region that overlaps the driving gate electrode 210 . For example, the driving semiconductor pattern 230 may be insulated from the driving gate electrode 210 by the driving gate insulating film 220.

The driving semiconductor pattern 230 may include a semiconductor material. For example, the driving semiconductor pattern 230 may include amorphous silicon or polycrystalline silicon. The driving semiconductor pattern 230 may be an oxide semiconductor. For example, the driving semiconductor pattern 230 may include IGZO.

The driving semiconductor pattern 230 may include a source region, a drain region, and a channel region. The channel region may be located between the source region and the drain region. The driving gate electrode 210 may overlap the channel region of the driving semiconductor pattern 230 . The channel region may have lower conductivity than the source region and the drain region. For example, the source region and the drain region may include conductive impurities.

The driving source electrode 240 may be electrically connected to the source region of the semiconductor pattern 230. For example, the driving source electrode 240 may directly contact the source region of the semiconductor pattern 230.

The driving source electrode 240 may include a conductive material. For example, the driving source electrode 240 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), or tungsten (W). The driving source electrode 240 may include a material different from that of the driving gate electrode 210.

The driving source electrode 240 may be electrically connected to the data line DL. The data line DL may include the same material as the driving source electrode 240. For example, the driving source electrode 240 may have a shape that protrudes in the first direction from the data line DL extending in the second direction.

The driving drain electrode 250 may be electrically connected to the drain region of the semiconductor pattern 230. For example, the driving drain electrode 250 may directly contact the drain region of the semiconductor pattern 230. The driving drain electrode 250 may be spaced apart from the driving source electrode 240. For example, the driving source electrode 240 and the driving drain electrode 250 may expose the channel region of the driving semiconductor pattern 230.

A display device according to an embodiment of the present invention is described in which a partial area of the driving semiconductor pattern 230 is exposed by the driving source electrode 240 and the driving drain electrode 250. However, a display device according to another embodiment of the present invention may include an etch stopper located on the driving semiconductor pattern 230. The etch stopper can prevent damage to the driving semiconductor pattern 230 due to the manufacturing process. For example, in a display device according to another embodiment of the present invention, a partial area of the etch stopper may be exposed by the driving source electrode 240 and the driving drain electrode 250.

The driving drain electrode 250 may include a conductive material. For example, the driving drain electrode 250 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), or tungsten (W). The driving drain electrode 250 may include a material different from that of the driving gate electrode 210. For example, the driving drain electrode 250 may include the same material as the driving source electrode 240.

A planarization film 120 may be positioned on the driving thin film transistor 200. The planarization film 120 can remove steps caused by the driving thin film transistor 200. For example, the upper surface of the planarization film 120 facing the array substrate 110 may be a flat plane.

The planarization film 120 may include an insulating material. For example, the planarization film 120 may include an organic insulating material.

A pixel electrode 300 may be positioned on the planarization film 120. The pixel electrode 300 may be electrically connected to the driving thin film transistor 200. For example, the planarization film 120 may include a pixel contact hole that partially exposes the driving drain electrode 250 of the driving thin film transistor 200. The pixel electrode 300 may directly contact the driving drain electrode 250 within the pixel contact hole. The pixel electrode 300 may include a region that does not overlap the driving thin film transistor 200. For example, the pixel electrode 300 may extend outward from the driving thin film transistor 200.

The pixel electrode 300 may include a conductive material. The pixel electrode 300 may include a transparent material. For example, the pixel electrode 300 may include ITO or IZO.

A common electrode 400 may be located on the pixel electrode 300. The common electrode 400 may form a horizontal electric field with the pixel electrode 300. The common electrode 400 may include at least one slit SP that overlaps the pixel electrode 300. For example, a display device according to an embodiment of the present invention has the array substrate 110 on which the driving thin film transistor 200, the pixel electrode 300, and the common electrode 400 are formed between a backlight unit and a liquid crystal layer. It may be an IPS type liquid crystal display device disposed in.

The common electrode 400 may include a conductive material. The common electrode 400 may include a transparent material. For example, the common electrode 400 may include ITO or IZO.

A lower protective film 130 may be positioned between the pixel electrode 300 and the common electrode 400. The common electrode 400 may be insulated from the pixel electrode 300 by the lower protective film 130. The lower protective film 130 may extend outward from the pixel electrode 300 . For example, the lower protective layer 130 may contact the planarization layer 120 on the outside of the pixel electrode 300.

The lower protective film 130 may include an insulating material. The lower protective layer 130 may include a material different from that of the planarization layer 120. For example, the lower protective layer 130 may include silicon oxide or silicon nitride.

A touch electrode 500 and an upper protective film 140 may be positioned between the lower protective film 130 and the common electrode 400. For example, a display device according to an embodiment of the present invention may be an advanced in-cell touch (AIT) display device.

The touch electrode 500 may be located between the lower protective film 130 and the upper protective film 140. For example, the touch electrode 500 may directly contact the lower protective film 130. The touch electrode 500 may be insulated from the pixel electrode 300 by the lower protective film 130. The touch electrode 500 may not overlap the pixel electrode 300. For example, the touch electrode 500 may overlap the data line DL. The touch electrode 500 may extend in the second direction along the data line DL.

The touch electrode 500 may include a conductive material. The touch electrode 500 may include a transparent material. For example, the touch electrode 500 may include ITO or IZO.

The upper protective film 140 may cover the touch electrode 500. The common electrode 400 may be insulated from the touch electrode 500 by the upper protective film 140. The upper protective film 140 may extend between the lower protective film 130 and the common electrode 400. Accordingly, in the display device according to an embodiment of the present invention, the detection signal transmitted through the touch electrode 500 may not affect the electric field formed between the pixel electrode 300 and the common electrode 400. .

The upper protective film 140 may include an insulating material. For example, the upper protective layer 140 may include silicon oxide or silicon nitride. The upper protective film 140 may include the same material as the lower protective film 130.

The non-display area (NA) of the array substrate 110 may be located outside the display area (AA) of the array substrate 110 . The non-display area (NA) of the array substrate 110 may generate/supply signals for implementing an image. For example, a driver IC (DIC) may be located on the non-display area (NA) of the array substrate 110. The driving IC (DIC) may be electrically connected to the display area (AA). For example, the driving IC (DIC) includes signal transmission lines (SL) that transmit signals for the gate signal or the data signal and touch transmission lines (TL) that are electrically connected to the touch electrode 500. may include.

A pad area (PA) may be located on the non-display area (NA) of the array substrate 110 . A display device according to an embodiment of the present invention can receive signals from the outside through the pad area (PA). The pad area (PA) may be spaced apart from the driving IC (DIC). For example, the driving IC (DIC) may be located between the display area (AA) and the pad area (PA).

The pad area PA may include a signal pad area PA1, a touch pad area PA2, and a dummy pad area PA3.

At least one signal pad 610 may be located on the signal pad area PA1. The signal pad 610 may be connected to the driving IC (DIC) through a signal supply line 710. The driving IC (DIC) may be supplied with signals for generating the gate signal and the data signal from the outside through the signal pad 610.

At least one touch pad 620 may be located on the touch pad area PA2. The touch pad 620 may be connected to the driving IC (DIC) through a touch supply wire 720. The touch signal detected by the touch electrode 500 may be transmitted to the outside through the touch pad 620.

The dummy pad area PA3 may be located between the signal pad area PA1 and the touch pad area PA2. At least one dummy pad 630 may be located on the dummy pad area PA3. The dummy pad 630 can prevent damage to the signal pad 610 and the touch pad 620 due to differences in density during the manufacturing process. For example, the dummy pad 630 may be positioned parallel to the signal pad 610 and the touch pad 620.

The dummy pad 630 may be insulated from the signal supply wire 710 and the touch supply wire 720. The dummy pad 630 may not be electrically connected to the driving IC (DIC). For example, a wire containing a conductive material may not be located between the dummy pad 630 and the driving IC (DIC). Accordingly, in the display device according to an embodiment of the present invention, distortion of signals transmitted through the signal supply wire 710 and the touch supply wire 720 can be minimized.

The pad area PA may include test thin film transistors 801 and 802. The test thin film transistors 801 and 802 may be used to test the operation of the display area AA. For example, the test thin film transistors 801 and 802 are connected to the signal test thin film transistor 801 located between the signal pad 610 and the common voltage supply line (Vcom) and the touch pad 620 and the common voltage supply line (Vcom). It may include a touch test thin film transistor 802 located between the voltage supply lines (Vcom).

The touch test thin film transistor 802 may have the same structure as the signal test thin film transistor 801. The signal test thin film transistor 801 may have the same structure as the driving thin film transistor 200. For example, the signal test thin film transistor 801 may include a test gate electrode 810, a test gate insulating film 820, a test semiconductor pattern 830, a test source electrode 840, and a test drain electrode 850. You can.

The test gate electrode 810 may be located close to the array substrate 110. The test gate electrode 810 may include a conductive material. For example, the test gate electrode 810 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The test gate electrode 810 may include the same material as the driving gate electrode 210.

The test gate insulating film 820 may be located on the test gate electrode 810. The test gate insulating layer 820 may include an insulating material. For example, the test gate insulating layer 820 may include the same material as the driving gate insulating layer 220. The test gate insulating layer 820 may be connected to the driving gate insulating layer 220.

The test semiconductor pattern 830 may be located on the test gate insulating layer 820. The channel region of the test semiconductor pattern 830 may overlap the test gate electrode 810. The test semiconductor pattern 830 may include a semiconductor material. For example, the test semiconductor pattern 830 may include the same material as the driving semiconductor pattern 230.

The test source electrode 840 may be electrically connected to the source region of the test semiconductor pattern 830. The test source electrode 840 may include a conductive material. For example, the test source electrode 840 may include the same material as the driving source electrode 240.

The test source electrode 840 may be electrically connected to the common voltage supply line (Vcom). The common voltage supply line (Vcom) may include the same material as the test source electrode 840. For example, the test source electrode 840 may have a shape that protrudes from the common voltage supply line (Vcom).

The test drain electrode 850 may be electrically connected to the drain region of the test semiconductor pattern 830. The test drain electrode 850 may be spaced apart from the test source electrode 840. For example, the test source electrode 840 and the test drain electrode 850 may expose the channel region of the test semiconductor pattern 830. The test drain electrode 850 may include a conductive material. For example, the test drain electrode 850 may include the same material as the drive drain electrode 250.

A display device according to an embodiment of the present invention is described in which a partial area of the test semiconductor pattern 830 is exposed by the test source electrode 840 and the test drain electrode 850. However, a display device according to another embodiment of the present invention may further include an etch stopper located on the test semiconductor pattern 830. The etch stopper can prevent damage to the test semiconductor pattern 830 due to the manufacturing process. For example, in a display device according to another embodiment of the present invention, a partial area of the etch stopper may be exposed by the test source electrode 840 and the test drain electrode 850.

The test thin film transistors 801 and 802 may be controlled by a signal applied through a test pad (AP). For example, the test gate electrode 810 of each test thin film transistor 801 and 802 may be electrically connected to the test pad AP. The test pad (AP) may be located on the non-display area (NA) of the array substrate 110. The test gate electrode 810 of each test thin film transistor 801 and 802 may be connected to the test gate electrode 810 of the adjacent test thin film transistor 801 and 802. For example, the test thin film transistors 801 and 802 may include a test gate electrode 810 crossing the signal pad area PA1, the touch pad area PA2, and the dummy pad area PA3. You can.

The common voltage supply line (Vcom) may be a line for supplying a common voltage to the display area (AA) of the array substrate 110. For example, the common electrode 400 may be electrically connected to the common voltage supply line (Vcom). The common voltage supply line (Vcom) may cross the pad area (PA). For example, the common voltage supply line (Vcom) may extend parallel to the test gate electrode 810.

The planarization film 120 may extend onto the non-display area (NA) of the array substrate 110 . For example, steps caused by the test thin film transistors 801 and 802 can be removed by the planarization film 120. The planarization film 120 may include a trench 120t overlapping the pad area PA. For example, the signal pad 610, the touch pad 620, and the dummy pad 630 may be located within the trench 120t of the planarization film 120. Accordingly, in the display device according to an embodiment of the present invention, a flexible printed circuit board (FPCB) for supplying an external signal to the driving IC (DIC) is connected to each pad 610 of the pad area PA. , 620, 630).

The lower protective film 130 and the upper protective film 140 may extend onto the non-display area (NA) of the array substrate 110 . The signal pad 610, the touch pad 620, and the dummy pad 630 may be located on the upper protective layer 140. The signal pad 610, the touch pad 620, and the dummy pad 630 may include a conductive material. The signal pad 610, the touch pad 620, and the dummy pad 630 may include a material with relatively high corrosion resistance. For example, the signal pad 610, the touch pad 620, and the dummy pad 630 may include ITO or IZO. The signal pad 610, the touch pad 620, and the dummy pad 630 may include the same material as the common electrode 400.

The signal supply wire 710 may be located on a different layer from the signal pad 610, the touch pad 620, and the dummy pad 630. For example, the signal supply line 710 may be located between the lower protective layer 130 and the upper protective layer 140. The signal supply wiring 710 may include a conductive material. For example, the signal supply wire 710 may include the same material as the touch electrode 500.

The touch supply wire 720 may be located on the same layer as the signal supply wire 710. For example, the touch supply wire 720 may be located between the lower protective layer 130 and the upper protective layer 140. The touch supply wire 720 may include the same material as the signal supply wire 710.

The dummy pad 630 may be connected to the common voltage supply line (Vcom) by a dummy connection line 900. Accordingly, in the display device according to an embodiment of the present invention, charges charged by static electricity may not be accumulated in the dummy pad 630. That is, in the display device according to an embodiment of the present invention, the charge flowing into the dummy pad 630 may be discharged to the common voltage supply line (Vcom) through the dummy connection line 900. Therefore, malfunctions due to static electricity can be minimized in the display device according to an embodiment of the present invention.

The dummy connection wire 900 may include a conductive material. The dummy connection wire 900 may have a lower resistance than the dummy pad 630 . For example, the dummy connection wire 900 may include metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). Accordingly, in the display device according to an embodiment of the present invention, the charge flowing into the dummy pad 630 can be effectively discharged.

The dummy connection wire 900 may be located on a different layer from the dummy pad 630. For example, the dummy connection wire 900 may be located between the array substrate 110 and the dummy pad 630. The dummy connection wire 900 may extend between the array substrate 110 and the planarization film 120. For example, the dummy connection wire 900 may extend between the test gate insulating layer 820 and the planarization layer 120. The dummy connection wire 900 may directly contact the common voltage supply wire (Vcom). For example, the dummy connection wire 900 may include the same material as the test drain electrode 850. The dummy connection wire 900 may have a shape that protrudes from the common voltage supply wire (Vcom) in parallel with the test drain electrode 850. The dummy connection wire 900 may intersect a test gate electrode 810 crossing the signal pad area PA1, the touch pad area PA2, and the dummy pad area PA3. For example, the test gate electrode 810 may extend between the array substrate 110 and the dummy connection wire 900. Accordingly, in the display device according to an embodiment of the present invention, the step of the dummy connection wire 900 can be reduced.

As a result, the display device according to an embodiment of the present invention is equipped with a dummy pad 630 to prevent damage to the signal pad 610 and the touch pad 620 due to differences in density during the manufacturing process. ), when the charge charged by static electricity flows into the dummy pad 630, it can be discharged to the common voltage supply line (Vcom) through the dummy connection line 900. Accordingly, malfunctions due to static electricity can be prevented in the display device according to an embodiment of the present invention. Therefore, reliability can be improved in the display device according to an embodiment of the present invention.

A dummy gate 811 is provided between the array substrate 110 and the signal pad 610, between the array substrate 110 and the touch pad 620, and between the array substrate 110 and the dummy pad 630. 813) may be located. The dummy gates 811 and 813 may be located on the same layer as the test gate electrode 810. For example, the dummy gates 811 and 813 may be positioned between the array substrate 110 and the test gate insulating layer 820 to overlap the corresponding pads 610, 620, and 630. One end of the test drain electrode 850 may extend between the dummy gate 811 and the signal pad 610. The dummy connection wire 900 may include an end that overlaps the dummy gate 813 and the dummy pad 630. For example, the dummy gates 811 and 813 may include the same material as the test gate electrode 810. Accordingly, in the display device according to an embodiment of the present invention, the step difference between the pads 610, 620, and 630 located within the pad area PA can be reduced.

A dummy semiconductor pattern 831 may be positioned between the test gate electrode 810 and the dummy connection wire 900. The dummy semiconductor pattern 831 may be located on the same layer as the test semiconductor pattern 830. For example, the dummy semiconductor pattern 831 may be positioned between the test gate insulating layer 820 and the dummy connection wire 900 to overlap the test gate electrode 810. The dummy semiconductor pattern 831 may include a semiconductor material. For example, the dummy semiconductor pattern 831 may include the same material as the test semiconductor pattern 830. Accordingly, in the display device according to an embodiment of the present invention, the step of the dummy connection wire 900 can be reduced.

A display device according to an embodiment of the present invention is described in which the dummy pad area PA3 is located between the signal pad area PA1 and the touch pad area PA2. However, in a display device according to another embodiment of the present invention, the pad area PA may not include the touch pad area PA2. For example, as shown in FIG. 4, in a display device according to another embodiment of the present invention, a plurality of pad areas (PA) are located on the non-display area (NA) of the array substrate, and each pad area (PA) ) may include a signal pad area (PA1) located between two dummy pad areas (PA3).

5A to 11A, 5B to 11B, and 5C to 11C are diagrams sequentially showing the manufacturing process of a display device according to an embodiment of the present invention.

A method of manufacturing a display device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3C, 5A to 11A, 5B to 11B, and 5C to 11C. First, as shown in FIGS. 5A to 5C, the method of manufacturing a display device according to an embodiment of the present invention includes forming a driving gate electrode 210, a test gate electrode 810, and a dummy gate 811 on an array substrate 110. , 813).

Forming the driving gate electrode 210, the test gate electrode 810, and the dummy gates 811 and 813 includes forming a gate material layer on the array substrate 110 and forming the gate material layer. It may include a patterning step.

The gate material layer may be formed of a conductive material. For example, the gate material layer may be formed of metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

As shown in FIGS. 6A to 6C, the method of manufacturing a display device according to an embodiment of the present invention includes forming the driving gate electrode 210, the test gate electrode 810, and the dummy gate on the array substrate 110. forming gate insulating films 220 and 820 covering the gate insulating films 220 and 820, and forming a driving semiconductor pattern 230, a test semiconductor pattern 830 and a dummy semiconductor pattern 831 on the gate insulating films 220 and 820. It may include a forming step.

The step of forming the gate insulating films 220 and 820 includes depositing a gate insulating material on the array substrate 110 on which the driving gate electrode 210, the test gate electrode 810, and the dummy gate 811 are formed. It may include steps. The gate insulating layers 220 and 820 may include a driving gate insulating layer 220 covering the driving gate electrode 210 and a test gate insulating layer 820 covering the test gate electrode 810. Accordingly, in the method of manufacturing a display device according to an embodiment of the present invention, the test gate insulating layer 820 may be formed simultaneously with the driving gate insulating layer 220.

Forming the driving semiconductor pattern 230, the test semiconductor pattern 830, and the dummy semiconductor pattern 831 includes forming a semiconductor material layer on the gate insulating films 220 and 820 and the semiconductor material layer. It may include a step of patterning. The semiconductor material layer may be formed of a semiconductor material. For example, the semiconductor material layer may be formed of amorphous silicon or polycrystalline silicon.

As shown in FIGS. 7A to 7C, the method of manufacturing a display device according to an embodiment of the present invention includes forming a driving thin film transistor 200 and a test thin film transistor 801 on the array substrate 110, and It may include forming a dummy connection wire 900 on the array substrate 110 .

Forming the driving thin film transistor 200 and the test thin film transistor 801 includes forming a driving source electrode 240 on the array substrate 110 on which the driving semiconductor pattern 230 and the test semiconductor pattern 830 are formed. ), forming a driving drain electrode 250, a test source electrode 840, and a test drain electrode 850.

Forming the driving source electrode 240, the driving drain electrode 250, the test source electrode 840, and the test drain electrode 850 includes forming the driving semiconductor pattern 230 and the test semiconductor pattern 830. ) may include forming a conductive material layer on the array substrate 110 and patterning the conductive material layer.

The conductive material layer may be formed of a conductive material. For example, the conductive material layer may be formed of metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

The step of forming the dummy connection wire 900 may be performed simultaneously with the step of forming the driving thin film transistor 200 and the test thin film transistor 801. For example, the dummy connection wire 900 may be formed simultaneously with the driving source electrode 240, the driving drain electrode 250, the test source electrode 840, and the test drain electrode 850. The dummy connection wire 900 may include the same material as the driving source electrode 240, the driving drain electrode 250, the test source electrode 840, and the test drain electrode 850. For example, the dummy connection wire 900 may be formed through a patterning process of the conductive material layer. Accordingly, in the display device according to an embodiment of the present invention, an additional process for forming the dummy connection wire 900 may not be performed.

As shown in FIGS. 8A to 8C, the method of manufacturing a display device according to an embodiment of the present invention includes the array in which the driving thin film transistor 200, the test thin film transistor 801, and the dummy connection wire 900 are formed. It may include forming a planarization film 120 on the substrate 110 and forming a trench 120t and a pixel contact hole in the planarization film 120.

The trench 120t of the planarization film 120 may be formed on a non-display area of the array substrate 110. For example, the dummy gate 811 may overlap the trench 120t of the planarization film 120. The driving thin film transistor 200 and the test thin film transistor 800 may be covered by the planarization film 120 .

As shown in FIGS. 9A to 9C, the method of manufacturing a display device according to an embodiment of the present invention includes a pixel electrode connected to the driving drain electrode 250 through the pixel contact hole on the planarization film 120. 300) may include the step of forming.

Forming the pixel electrode 300 may include forming a transparent conductive material layer on the planarization film 120 and patterning the transparent conductive material layer. The transparent conductive material may be formed of ITO or IZO.

10A to 10C, the method of manufacturing a display device according to an embodiment of the present invention includes forming a lower protective film 130 on the array substrate 110 on which the pixel electrode 300 is formed, and It may include forming a touch electrode 500, a signal supply wire 710, and a touch supply wire 720 on the lower protective film 130.

11A to 11C, the method of manufacturing a display device according to an embodiment of the present invention includes an upper protective film covering the touch electrode 500, the signal supply wire 710, and the touch supply wire 720. It may include forming 140) and forming pad contact holes exposing a portion of the signal supply line 710.

As shown in FIGS. 3A to 3C, the method of manufacturing a display device according to an embodiment of the present invention includes forming a common electrode 400, a signal pad 610, a touch pad 620, and a dummy pad on the upper protective film 140. It may include forming (630).

As a result, the method of manufacturing a display device according to an embodiment of the present invention forms a dummy connection wire 900 using a process for forming the driving thin film transistor 200 and the test thin film transistor 800, thereby forming the dummy connection wire 900. Additional processing for the formation of (900) may not be necessary. Accordingly, in the method of manufacturing a display device according to an embodiment of the present invention, malfunctions due to static electricity can be minimized without additional processes. Therefore, the method of manufacturing a display device according to an embodiment of the present invention can improve reliability without reducing process efficiency.

110: array substrate 120: planarization film
130: lower shield 140: upper shield
200: Driving thin film transistor 300: Pixel electrode
400: common electrode 500: touch electrode
610: signal pad 620: touch pad
630: Dummy pad 710: Signal supply wiring
720: Touch supply wiring 801: Signal test thin film transistor
802: Touch test thin film transistor 900: Dummy connection wiring

Claims (12)

An array substrate including a display area and a non-display area located outside the display area;
a driving IC located on the non-display area of the array substrate and electrically connected to the display area;
a signal pad located on the non-display area of the array substrate and connected to the driver IC through a signal supply wire;
a touch pad located on the non-display area of the array substrate and connected to the driver IC through a touch supply wire; and
A dummy pad positioned side by side between the signal pad and the touch pad on the array substrate and insulated from the signal supply wire and the touch supply wire,
A display device in which the dummy pad is connected to a common voltage supply wire by a dummy connection wire. According to claim 1,
The signal pad and the dummy pad are located between the driver IC and the common voltage supply line. According to claim 1,
A display device further comprising a test thin film transistor located between the signal pad and the common voltage supply line. According to claim 3,
Further comprising a driving thin film transistor located on the display area of the array substrate,
A display device wherein the test thin film transistor has the same structure as the driving thin film transistor. According to claim 3,
The test thin film transistor includes a gate electrode, a gate insulating film, a semiconductor pattern, a source electrode, and a drain electrode,
The display device wherein the dummy connection wire includes the same material as the drain electrode of the test thin film transistor. According to claim 5,
Further comprising a dummy semiconductor pattern located between the array substrate and the dummy connection wire,
A display device wherein the dummy semiconductor pattern includes the same material as the semiconductor pattern of the test thin film transistor. According to claim 5,
A display device wherein the gate electrode of the test thin film transistor extends between the array substrate and the dummy connection wire. According to claim 7,
A display device wherein the common voltage supply line extends parallel to the gate electrode of the test thin film transistor. delete According to claim 1,
The display device wherein the touch supply wiring includes the same material as the signal supply wiring. According to claim 1,
a planarization film located on the display area of the array substrate;
a lower protective film positioned on the planarization film;
an upper protective film located on the lower protective film;
a pixel electrode positioned between the planarization film and the lower protective film;
a common electrode located on the upper protective film and including at least one slit overlapping the pixel electrode; and
A touch electrode located between the lower protective film and the upper protective film and spaced apart from the pixel electrode,
The display device wherein the signal supply wiring includes the same material as the touch electrode. According to claim 11,
The planarization film includes a trench located on the non-display area of the array substrate,
The signal pad, the dummy pad, and the touch pad are located within the trench of the planarization film.

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