KR102609586B1 - Thin film transistor - Google Patents

Abstract

A thin film transistor according to an embodiment of the present invention includes a first source/drain electrode on a substrate, a second source/drain electrode disposed on a top surface of the first source/drain electrode, a top surface of the first source/drain electrode, and the top surface of the first source/drain electrode. an insulating pattern disposed between the lower surface of the second source/drain electrode, an active pattern extending from the upper surface of the first source/drain electrode to the upper surface of the second source/drain electrode, and disposed on the active pattern, It may include a gate electrode partially overlapping the pattern.

Description

Thin film transistor {THIN FILM TRANSISTOR}

The present invention relates to thin film transistors, and more particularly to thin film transistors with increased channel length.

A thin film transistor, like a field effect transistor, is a device with three terminals: a gate electrode, a drain electrode, and a source electrode. The main function of a thin film transistor is switching operation. A thin film transistor can turn the channel between the source electrode and the drain electrode into an on or off state depending on the voltage applied to the gate electrode. Thin film transistors can be used as backplane elements in display devices. Recently, as display devices with ultra-high resolution have been proposed, there is a demand for high integration of thin film transistors in backplane elements. Accordingly, research on vertical channel transistors is in progress.

The problem to be solved by the present invention is to provide a vertical channel type thin film transistor with reduced leakage current and improved switching performance.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

The problem to be solved by the present invention is to provide a vertical channel type thin film transistor with reduced leakage current and improved switching performance.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present invention, a transistor with improved integration can be provided. Additionally, as the gate electrode has sides that are offset from the sides of the active pattern, leakage current between the gate electrode and the active pattern can be reduced. Additionally, as the gate electrode and the active pattern do not completely overlap, parasitic capacitance may be reduced.

1 is a plan view for explaining a thin film transistor according to embodiments of the present invention.
FIGS. 2A and 2B are cross-sectional views taken along lines A-A' and B-B' of FIG. 1, respectively.
Figure 3 is a plan view for explaining a thin film transistor according to embodiments of the present invention.
Figure 4A is a plan view for explaining a display device according to embodiments of the present invention.
FIG. 4B is a cross-sectional view taken along line A-A' of FIG. 4A.
Figure 5A is a plan view for explaining a display device according to embodiments of the present invention.
FIG. 5B is a cross-sectional view taken along line A-A' of FIG. 5A.
Figure 6A is a plan view for explaining a display device according to embodiments of the present invention.
FIG. 6B is a cross-sectional view taken along line A-A' of FIG. 6A.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be explained with reference to plan and cross-sectional views, which are ideal schematic diagrams of the present invention. Accordingly, the form of the illustration may be modified depending on manufacturing technology and/or tolerance. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in form produced according to the manufacturing process. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate a specific shape of the region of the device and are not intended to limit the scope of the invention.

Embodiments of the present invention will be described below with reference to the drawings.

1 is a plan view for explaining a thin film transistor according to embodiments of the present invention. Figures 2a and 2b are cross-sectional views taken along lines A-A' and B-B' of Figure 1, respectively. Figure 3 is an enlarged cross-sectional view corresponding to portion AA of Figure 2.

1, 2A, and 2B, thin film transistors according to embodiments of the present invention include a substrate 100, first and second source/drain electrodes 130 and 140, an active pattern 150, and a gate. It may include an electrode 160. First and second source/drain electrodes 130 and 140 may be stacked on the substrate 100 . The first source/drain electrode 130 and the second source/drain electrode 140 may be arranged to be vertically spaced apart from each other. The active pattern 150 may extend from the top surface of the first source/drain electrode 130 to the top surface of the second source/drain electrode 140. Accordingly, the active pattern 150 may have a vertically extending portion. The gate electrode 160 may be disposed on the active pattern 150 and partially overlap the active pattern 150.

The gate electrode 160 may have side surfaces 160s that are offset from the side surfaces 150s of the active pattern 150. In other words, the side surfaces 160s of the gate electrode 160 may not be aligned with the side surfaces 150s of the active pattern 150. Accordingly, leakage current between the gate electrode 160 and the active pattern 150 can be reduced.

In detail, first source/drain electrodes 130 may be disposed on the substrate 100. The substrate 100 may be an insulating substrate. The substrate 100 may include, for example, glass, plastic, or silicon. The first source/drain electrode 130 may include metal. The first source/drain electrode 130 may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti).

An insulating pattern 114 may be disposed on the substrate 100 and the first source/drain electrodes 130. The insulating pattern 114 may be disposed between the first source/drain electrode 130 and the second source/drain electrode 140 to electrically separate them. By adjusting the thickness of the insulating pattern 114, the gap between the first source/drain electrode 130 and the second source/drain electrode 140 can be increased. As a result, the length of the active pattern 150, which will be described later, can be increased. The insulating pattern 114 may cover a portion of the upper surface of the first source/drain electrode 130 and expose the other portion.

The second source/drain electrode 140 may be disposed on the insulating pattern 114 . The second source/drain electrodes 140 may be disposed on the upper surface of the insulating pattern 114 and vertically spaced apart from the first source/drain electrodes 130. Additionally, the second source/drain electrode 140 may have a side surface aligned with the side surface of the insulating pattern 114 . From a plan view, the second source/drain electrodes 140 may extend in the first direction D1 parallel to the top surface of the substrate 100. The second source/drain electrode 140 may at least partially overlap the first source/drain electrode 130. The second source/drain electrode 140 may include the same material as the first source/drain electrode 130.

The active pattern 150 may extend from the top surface of the first source/drain electrode 130 to the top surface of the second source/drain electrode 140. Additionally, the active pattern 150 may cover the side surface of the insulating pattern 114 and the side surface of the second source/drain electrode 140. The active pattern 150 may include a channel region forming a conductive channel between the first source/drain electrodes 130 and the second source/drain electrodes 140 depending on whether a voltage is applied to the gate electrode 160. The active pattern 150 may include an oxide semiconductor. Active pattern 150 includes, for example, zinc oxide (ZnO), indium oxide (InO), indium-gallium-zinc oxide (In-Ga-Zn-O), and zinc-tin oxide (Zn-Sn-O). can do. Additionally, the oxide semiconductor may include an oxide containing at least two elements selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and aluminum (Al).

A gate insulating layer 162 may be disposed on the active pattern 150 . The gate insulating layer 162 may completely cover the top surface of the active pattern 150. The gate insulating film 162 may be disposed between the active pattern 150 and the gate electrode 160, which will be described later, to electrically insulate them. The gate insulating film 162 may be formed entirely on the substrate 100 . In other words, the gate insulating film 162 includes the top surface of the substrate 100, the top surface of the first source/drain electrode 130, the top surface of the active pattern 150, the top surface of the second source/drain electrode 140, and the insulating pattern. It can cover the upper surface of (114). In the manufacturing process of a thin film transistor, the gate insulating film 162 may not be patterned together with the active pattern 150. That is, the gate insulating layer 162 may be formed after the active pattern 150 is patterned. As a result, the sides of the gate insulating layer 162 and the active pattern 150 may not be aligned, and leakage current between the active pattern 150 and the gate electrode 160 may be reduced.

A gate electrode 160 may be disposed on the active pattern 150 . The gate electrode 160 may partially overlap the active pattern 150. That is, the gate electrode 160 may not completely overlap the active pattern 150. The gate electrode 160 may extend in a second direction D2 perpendicular to the first direction D1 when viewed from a plan view. The gate electrode 160 may intersect the active pattern 150 when viewed from a plan view. The gate electrode 160 may cover a portion of the top surface of the first insulating layer 112 and a portion of the top surface of the second insulating layer. The gate electrode 160 may be formed by a patterning process different from the active pattern 150 to have side surfaces offset from the side surfaces of the active pattern 150. Side surfaces of the gate electrode 160 may not be aligned with side surfaces of the active pattern 150 . The gate electrode 160 may include the same material as the first source/drain electrode 130. According to embodiments, as shown in FIG. 1, the width of the gate electrode 160 in the first direction D1 may be smaller than the width of the active pattern 150 in the first direction D1. The width of the gate electrode 160 in the second direction D2 may be greater than the width of the active pattern 150 in the second direction D2.

An interlayer insulating film 122 may be formed on the entire surface of the substrate 100 . The interlayer insulating film 122 may cover the gate insulating film 162 and the gate electrode 160. The interlayer insulating film 122 may have a substantially flat top surface.

Figure 3 is a top view of a thin film transistor according to embodiments of the present invention. For simplicity of explanation, differences from the thin film transistor described above will be mainly explained, and detailed descriptions of overlapping configurations will be omitted.

Referring to FIG. 3, the active pattern 150 may completely overlap the gate electrode 160. At this time, the active pattern 150 may have side surfaces offset from the side surfaces of the gate electrode 160. The width of the active pattern 150 in the first direction D1 may be smaller than the width of the gate electrode 160 in the first direction D1. The width of the active pattern 150 in the second direction D2 may be smaller than the width of the gate electrode 160 in the second direction D2.

Figure 4A is a plan view for explaining a display device according to embodiments of the present invention. Figure 4b is a cross-sectional view taken along line A-A' in Figure 4a.

4A and 4B, the display device according to embodiments of the present invention includes data lines DL, gate lines GL, source/drain patterns 240, active patterns 250, and It may include pixel electrodes (PE).

The data lines DL extend in the second direction D2 and may be arranged in the first direction D1. The gate lines GL extend in the first direction D1 and may be arranged in the second direction D2. Data lines DL and gate lines GL may cross each other while being insulated from each other. The active pattern 250 and the source/drain pattern 240 may be disposed adjacent to the gate line GL and the data line DL. The active pattern 250 and the source/drain pattern 240 may be formed to at least partially overlap the intersection of the data lines DL and the gate lines GL. The pixel electrode PE may be disposed between the data lines DL and the gate lines GL. The side surfaces GLs of the gate line GL may be offset from the side surfaces 250s of the active patterns 250 .

In detail, a data line DL may be provided on the substrate 200. The data line DL may transmit a data voltage to the pixel electrode PE according to the gate signal applied to the gate line GL. The data line DL may function as a source or drain electrode and form a transistor together with the source/drain pattern 240 and the gate line GL. The data line DL may include a metal with low resistivity to reduce signal delay or voltage drop. The data line (DL) is, for example, magnesium (Mg), aluminum (Al), chromium (Cr), cobalt (Co), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), and platinum. It may include at least one of metallic materials such as (Pt), molybdenum (Mo), titanium (Ti), and their compounds.

The insulating pattern 214 and the source/drain pattern 240 may be sequentially stacked on the substrate 200 . The insulating pattern 214 may cover the top surface of the substrate 200 and the data line DL. The source/drain pattern 240 is disposed on the top surface of the insulating pattern 214 and may have the shape of an island. One side of the source/drain pattern 240 may be aligned with a side of the insulating pattern 214 . The source/drain pattern 240 may include a metal with low resistivity.

The active pattern 250 may extend from the top surface of the data line DL to the top surface of the source/drain pattern 240 . From a plan view, the active pattern 250 may be arranged to overlap the intersection of the data line DL and the gate line GL. The width of the active pattern 250 in the first direction D1 may be smaller than the width of the data line DL in the first direction D1. The width of the active pattern 250 in the second direction D2 may be smaller than the width of the gate line GL in the second direction D2. As shown in FIG. 4A, the side surfaces 250s of the active pattern 250 may be offset from the side surfaces GLs of the gate line GL and the side surfaces DLs of the data line DL. In other words, the side surfaces 250s of the active pattern 250 may not be aligned with the side surfaces GLs of the gate lines GL or the side surfaces DLs of the data line DL.

The gate insulating layer 262 and the gate line GL may be sequentially formed on the active pattern 250 . The gate insulating film 162 may be disposed between the active pattern 150 and the gate line GL to electrically insulate them. The gate insulating film 162 may be formed entirely on the substrate 200 . The gate insulating layer 162 may cover the data line DL, the top surface of the source/drain pattern 240, and the top surface of the insulating pattern 214. The gate insulating layer 262 may be formed to completely cover exposed surfaces of the active pattern 250 after the active pattern 250 is patterned. As a result, leakage current between the active pattern 250 and the gate line GL can be reduced.

An interlayer insulating film 222 may be formed on the entire surface of the substrate 200 . The interlayer insulating film 222 may cover the gate line GL and the gate insulating film 162. The interlayer insulating film 222 may have a substantially flat top surface.

The pixel electrode PE may be disposed on the interlayer insulating film 222 . The pixel electrode (PE) may be connected to the source/drain pattern 240 through a contact hole (CH) penetrating the interlayer insulating film 222. From a plan view, the pixel electrode PE may be disposed between the data lines DL and the gate lines GL, but is not limited thereto. The pixel electrode PE may be disposed to overlap the data lines DL or the gate lines GL. The pixel electrode PE may receive a data voltage from the data line DL and form an electric field with a common electrode (not shown) disposed on the pixel electrode PE. The pixel electrode (PE) is, for example, magnesium (Mg), aluminum (Al), chromium (Cr), cobalt (Co), nickel (Ni), palladium (Pd), silver (Ag), gold (Au), and platinum. It may include at least one of metallic materials such as (Pt), molybdenum (Mo), titanium (Ti), and their compounds.

Figure 5A is a plan view for explaining a display device according to embodiments of the present invention. Figure 5b is a cross-sectional view taken along line A-A' of Figure 5a. Figure 6A is a plan view for explaining a display device according to embodiments of the present invention. Figure 6b is a cross-sectional view taken along line A-A' of Figure 6a. For simplicity of explanation, the description will focus on differences from the previously described display device, and detailed descriptions of overlapping configurations will be omitted.

Referring to FIGS. 5A to 6B , the active pattern 250 may not completely overlap the gate lines GL and data lines DL. At this time, the side surfaces 250s of the active pattern 250 may be offset from the side surfaces GLs of the gate line GL and the side surfaces DLs of the data line DL. In other words, the side surfaces 250s of the active pattern 250 may not be aligned with the side surfaces GLs of the gate lines GL or the side surfaces DLs of the data line DL.

According to embodiments, as shown in FIGS. 5A and 5B, the width of the active pattern 250 in the first direction D1 may be greater than the width of the data line DL in the first direction D1. . The width of the active pattern 250 in the second direction D2 may be greater than the width of the gate line GL in the second direction D2.

According to embodiments, as shown in FIGS. 6A and 6B, the width of the active pattern 250 in the first direction D1 may be greater than the width of the data line DL in the first direction D1. . The width of the active pattern 250 in the second direction D2 may be smaller than the width of the gate line GL in the second direction D2.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims (10)

first source/drain electrodes disposed on the substrate and extending in a first direction;
second source/drain electrodes spaced apart from the first source/drain electrodes;
an insulating pattern disposed between the first source/drain electrode and the second source/drain electrode;
an active pattern connecting the first source/drain electrode to the second source/drain electrode along a side of the insulating pattern; and
A gate electrode disposed on the active pattern, extending in a second direction intersecting the first direction, and partially overlapping the active pattern,
The active pattern is a thin film transistor having a sidewall exposed outside of at least one of both sidewalls of the gate electrode in the first direction. According to claim 1,
The active pattern is a thin film transistor having a vertically extending portion. According to claim 1,
A thin film transistor wherein the active pattern covers a side surface of the insulating pattern. According to claim 1,
The active pattern covers a side of the second source/drain electrode. According to claim 1,
The width of the active pattern in the first direction is smaller than the width of the gate electrode in the first direction,
A thin film transistor wherein a width of the active pattern in a second direction crossing the first direction is greater than a width of the gate electrode in the second direction. According to claim 1,
The second source/drain electrode is a thin film transistor having a side surface aligned with a side surface of the insulating pattern. According to claim 1,
A thin film transistor further comprising a gate insulating film between the active pattern and the gate electrode. According to claim 1,
A thin film transistor wherein the active pattern completely overlaps the first source/drain electrode. According to claim 1,
A thin film transistor wherein the active pattern completely overlaps the gate electrode. According to claim 1,
The active pattern extends in a second direction perpendicular to the first direction and intersects the gate electrode.