KR102605294B1 - Display device - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a substrate, a display portion disposed on the substrate and including a plurality of subpixels, a non-display portion including a remaining area in addition to the display portion, and a pad portion disposed below the display portion in the non-display portion. , a gate driver disposed between the display unit and the pad unit, a gate connection line connected from the gate driver to a plurality of subpixels of the display unit, and a data connection line connected from the pad unit to a plurality of subpixels of the display unit. You can.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, to a display device that can reduce the bezel and diversify the panel shape.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device field has been rapidly changing toward thin, light, large-area flat panel displays (FPDs) replacing bulky cathode ray tubes (CRTs). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

Among these, organic light emitting display devices are self-emitting devices that emit light on their own and have the advantages of fast response speed, high luminous efficiency, brightness, and viewing angle. In particular, organic light emitting display devices can not only be formed on flexible substrates, but can also be driven at lower voltages than plasma display panels or inorganic electroluminescent (EL) displays and have relatively low power consumption. It has the advantage of being small and having excellent color.

The organic light emitting display device includes a display unit that implements an image by arranging a plurality of subpixels, a GIP driver unit that applies a gate driving signal to the display unit, and a pad unit that receives signals from the outside and transmits them to the display unit. Among these, the GIP driving unit is placed on the left and/or right side of the display unit and acts as a bezel on which images are not displayed. Therefore, there is a problem that the bezel of the GIP driving unit becomes larger.

The inventors of the present invention recognized the need for technology that can reduce the bezel of a display device. Accordingly, the inventors of the present invention invented a display device with a new structure that can reduce the bezel.

A display device according to an embodiment of the present invention includes a substrate, a display portion disposed on the substrate and including a plurality of subpixels, a non-display portion including a remaining area in addition to the display portion, and a pad portion disposed below the display portion in the non-display portion. , a gate driver disposed between the display unit and the pad unit, a gate connection line connected from the gate driver to a plurality of subpixels of the display unit, and a data connection line connected from the pad unit to a plurality of subpixels of the display unit. You can.

The plurality of subpixels may include at least one switching transistor, and the at least one switching transistor may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

The gate connection line may be connected to a gate line connected to the gate electrode of the at least one switching transistor.

The gate driver includes at least one transistor, and the gate connection line may be connected to the at least one transistor through a first contact hole formed in the gate driver.

The at least one transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and the gate connection line may be connected to any one of the source electrode and the drain electrode.

The gate connection line and the gate line may be formed as one body.

The gate connection line may be connected to the gate line through a second contact hole formed in the display unit.

The data connection line may be connected to a data line connected to the source electrode or the drain electrode of the at least one switching transistor.

The data connection line and the data line may be formed as one body.

The data connection line may be connected to the data line through a third contact hole formed in the display unit.

The data connection line may be connected to the data line through a fourth contact hole formed in the non-display portion.

It further includes an overcoat layer covering the gate driver and the at least one switching transistor, wherein the data connection line is disposed on the overcoat layer and connects the third contact hole or the fourth contact hole provided in the overcoat layer. It can be connected to the data line through.

The non-display unit in which the fourth contact hole is formed may be disposed between the gate driver and the display unit.

The display device according to an embodiment of the present invention has the advantage of reducing the bezel on the top and left and right sides of the display unit by providing a gate driver below the display unit.

Additionally, the display device according to an embodiment of the present invention has the advantage of being applicable to display devices having various shapes by providing both a gate driver and a pad portion on one side of the display portion.

1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a plan view showing a liquid crystal display panel according to an embodiment of the present invention.
Figure 3 is a plan view showing a touch element provided in a liquid crystal display panel in one embodiment of the present invention.
Figure 4 is a plan view showing a subpixel according to an embodiment of the present invention.
Figure 5 is a cross-sectional view taken along line A-A' of Figure 4.
Figure 6 is a plan view showing a subpixel according to the first embodiment of the present invention.
Figure 7 is a cross-sectional view taken along line B-B' of Figure 6.
Figure 8 is a cross-sectional view taken along the cutting line C-C' of Figure 6.
Figure 9 is a plan view showing a subpixel according to a second embodiment of the present invention.
Figure 10 is a cross-sectional view taken along the cutting line D-D' of Figure 9.
Figure 11 is a cross-sectional view taken along the cutting line E-E' of Figure 9.
12 is a diagram showing display devices of various shapes.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and that common knowledge in the technical field to which this specification pertains is provided. It is provided to fully inform those who have the scope of the specification, and this specification is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative and are not limited to the matters shown in the specification. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

First, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical idea of the present specification.

Each feature of the various embodiments of the present specification can be partially or fully combined or combined with each other, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, an electroluminescence display device according to an embodiment of the present specification will be described with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the gist of the present specification, the detailed description will be omitted or explained briefly.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to Figure 1, the display device according to the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode. It can be implemented as a flat panel display device such as an Organic Light Emitting Display (OLED) display device or an electrophoresis display device (EPD). In the following embodiments, the display device will be described focusing on the liquid crystal display device, but it should be noted that the display device of the present invention is not limited to liquid crystal display devices.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of data lines 15 and gate lines 16.

A pixel array is formed on the lower substrate of the liquid crystal display panel 10. The pixel array includes liquid crystal cells (Clc, pixels) formed at the intersection of the data lines 15 and gate lines 16, thin film transistors (TFTs, TFTs) connected to the pixel electrodes 1 of the pixels, and pixels. It includes a common electrode (2) opposite the electrode (1) and a storage capacitor (Cst). Each of the liquid crystal cells (Clc) is connected to a switching transistor (TFT) and driven by an electric field between the pixel electrode (1) and the common electrode (2). A black matrix, red (R), green (G), blue (B) color filters, etc. are formed on the upper substrate of the liquid crystal display panel 10. A polarizing plate is attached to each of the upper and lower substrates of the liquid crystal display panel 10, and an alignment film is formed to set the pre-tilt angle of the liquid crystal. The common electrode 2 is formed on the lower substrate together with the pixel electrode 1 in a horizontal electric field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode.

The liquid crystal display panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as IPS mode and FFS mode. The liquid crystal display device of the present invention can be implemented in any form, such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device. Transmissive and transflective liquid crystal displays require a backlight unit. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The display device of the present invention includes a driving unit 17 that drives the liquid crystal display panel 10. The driving unit 17 changes driving modes depending on whether the image data (RGB) input from an external system is a moving image or a still image. For example, when the image data (RGB) is a moving image, the driver 17 is driven in a high-speed driving mode with a high driving frequency, and when the image data (RGB) is a still image, the driver 17 is driven with a high driving frequency. It is driven in a low-frequency, low-speed drive mode. For this purpose, the driver 17 includes a host system 14, a timing controller 11, a source driver 12, and a data driver 13.

The host system 14 receives image data (RGB) from an external system, generates a driving mode signal (MS) corresponding to the image data (RGB), and outputs it to the timing controller 11. Specifically, when the image data (RGB) is a moving image, the host system 14 generates a driving mode signal (MS) corresponding to the moving image, and when the image data (RGB) is a still image, the host system 14 generates a driving mode signal (MS) corresponding to the still image. Generates a mode signal (MS). The driving mode signal (MS) is a signal that operates in high-speed mode when the image data (RGB) corresponds to a moving image. On the other hand, when the image data (RGB) corresponds to a still image, it operates in a low-speed mode to reduce power consumption. It is a signal that operates.

The timing controller 11 receives digital video data (RGB) of the input image from the host system 14 through the LVDS (Low Voltage Differential Signaling) interface method, and converts the digital video data (RGB) of this input image into mini-LVDS. It is supplied to the source driver 12 through an interface method. Additionally, the timing controller 11 receives a driving mode signal (MS) from the host system 14. The timing controller 11 aligns digital video data (RGB) input from the host system 14 according to the arrangement of the pixel array and then supplies it to the source driver 12.

The timing controller 11 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK) from the host system 14 and operates as a source. Control signals are generated to control the operation timing of the driver 12 and the gate driver 13. The control signals include a gate timing control signal for controlling the operation timing of the gate driver 13 and a source timing control signal for controlling the operation timing of the source driver 12.

Gate timing control signals include gate start pulse (Gate Start Pulse, GSP), gate shift clock (GSC), gate output enable signal (Gate Output Enable, GOE), etc. The gate start pulse (GSP) is applied to the gate drive IC (integrated circuit) that generates the first gate pulse and controls the gate drive IC to generate the first gate pulse. The gate shift clock (GSC) is a clock signal commonly input to gate drive ICs and is a clock signal for shifting the gate start pulse (GSP). The gate output enable signal (GOE) controls the output of gate drive ICs.

The source timing control signal includes the source start pulse (Source Start Pulse, SSP), source sampling clock (SSC), polarity control signal (POL), and source output enable signal (Source Output Enable, SOE). Includes. The source start pulse (SSP) controls the data sampling start timing of the source driver 12. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data in the source driver 12 based on the rising or falling edge. The polarity control signal (POL) controls the polarity of data voltages sequentially output from each of the source drive ICs. The source output enable signal (SOE) controls the output timing of the source driver 12.

The timing controller 11 implements interlace driving by time-dividing one frame into n sub-frames (n is a positive integer of 2 or more) and driving the gate lines 16 in a distributed manner through each sub-frame. The timing controller 11 groups the gate lines 16 into n gate groups, and corresponds each of the n gate groups to each of the n subframes in accordance with its driving order.

In each sub-frame, the timing controller 11 controls the operation of the gate driver 13 to complete a sequential scan of the gate lines 16 included in the gate group during the 1/n period of 1 sub-frame period. , a buffer operation control signal (LITEST) is generated and the driving power (high potential driving) is applied to the buffer units of the source driver 12 during the (n-1)/n period excluding the 1/n period among the 1 sub-frame period. voltage, base voltage). That is, the driving of the source driver 12 is controlled to stop during the skip period, and the driving power applied to the source driver 12 is cut off to remove the static current flowing in the buffer units of the source driver 12. (12) Dramatically reduces power consumption.

The source driver 12 includes a shift register, a latch array, a digital-to-analog converter, and an output circuit. The source driver 12 latches digital video data (RGB) according to the source timing control signal, then converts the latched data into analog positive/negative gamma compensation voltages to generate a plurality of data voltages whose polarity is inverted at a predetermined period. It is supplied to the data lines 15 through output channels. The output circuit includes multiple buffer units. The buffer units are connected to output channels, and each of the output channels is connected one-to-one to the data lines 15. The source driver 12 controls the polarity of data voltages output to output channels using a column inversion method to reduce power consumption. Based on the column inversion method, the polarity of the data voltage output from the same output channel is inverted on a sub-frame basis. Additionally, the polarities of data voltages output from neighboring output channels are opposite to each other.

The gate driver 13 uses a shift register and a level shifter to supply gate pulses to the gate lines 16 according to gate timing control signals in the interlace driving method described above. The source driver 12 and gate driver 13 may be mounted using a chip on glass (COG) or chip on film (COF) method. Additionally, the gate driver 13 may be formed directly on the lower substrate according to the GIP (Gate-driver In Panel) method. In the present invention, it will be explained as an example that the gate driver 13 is formed on the lower substrate using the GIP method.

Figure 2 is a plan view showing a liquid crystal display panel according to an embodiment of the present invention, and Figure 3 is a plan view showing a touch element provided in the liquid crystal display panel according to an embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display panel includes a display portion 60 and a non-display portion 61 on a lower substrate 20. The non-display portion 61 includes a gate driver 13 disposed below the lower substrate 20 and a pad portion 62 disposed below the lower substrate 20 . The display unit 60 has a plurality of subpixels 64 arranged to emit R, G, B or R, G, B, W to implement full color. A gate driver 13 is disposed below the display unit 60 to apply a gate driving signal to the display unit 60. The pad portion 62 is disposed on one side, for example, the lower side of the display portion 60, and chip-on films 66 are attached to the pad portion 62. The display unit 60 receives data signals and power supplied through the chip-on-film 66.

The above-mentioned liquid crystal display panel may be a touch element-integrated liquid crystal display with a touch element formed therein.

Referring to FIG. 3, the liquid crystal display panel includes a plurality of subpixels 64 provided with a pixel electrode and a common electrode on a lower substrate 20. The common electrode of the plurality of subpixels 64 is block and divided into touch driving units 51 to 54 and touch sensing units 58. The touch driving units 51 to 54 receive a driving signal from the Tx signal line 70, and the touch sensing unit 58 performs touch sensing through the Rx signal line 72. Here, the touch sensing unit 58 has a sensing line 74 extending from the Rx signal line 72 arranged vertically to connect the touch sensing unit 58, and the touch drivers 51 to 54 connect the Tx signal line 70. ) is connected to the Tx connection wire 76 that extends from the bottom of the touch sensing unit 58. Tx connection wires 76 are connected to the touch drivers 51 to 54 through contact holes 78, respectively.

In the following, a detailed description will be made with reference to the plane and cross section of each subpixel of the above-described liquid crystal display panel.

Figure 4 is a plan view showing a subpixel according to an embodiment of the present invention, and Figure 5 is a cross-sectional view taken along line A-A' of Figure 4.

Referring to FIG. 4, the subpixels are divided by the intersection of the gate line 16 and the data line 15. The subpixel includes a gate electrode 23 branched from the gate line 16, a source electrode 26a branched from the data line 15, and a drain electrode 26b spaced apart from the source electrode 26a, and disposed between them. A switching transistor (TFT) composed of a semiconductor layer 25 is disposed, respectively. Additionally, a pixel electrode 1 connected to the drain electrode 26b of the switching transistor (TFT) is disposed in the subpixel, and a common electrode (not shown) opposing the pixel electrode 1 is disposed.

In more detail, referring to FIG. 5, a switching transistor (TFT) is configured including a substrate 20, a semiconductor layer 25, a gate electrode 23, a source electrode 26a, and a drain electrode 26b. First, the gate electrode 23 is located on the substrate 20.

The gate electrode 23 is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed from either one or an alloy thereof. In addition, the gate electrode 23 is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or an alloy thereof. For example, the gate electrode 23 may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

A gate insulating film 30 is positioned on the gate electrode 23. The gate insulating film 30 may be made of a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a double layer thereof.

The semiconductor layer 25 is located on the gate insulating film 30. The semiconductor layer 25 may be made of a metal oxide, for example, zinc oxide (ZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), or zinc tin oxide (ZnSnO). The metal oxide semiconductor layer 25 has an off current (Ioff) of 10 ^-13 , which is about 100 times better than that of amorphous silicon (a-si), which has ^{10 -11} , so the semiconductor layer 25 has the advantage of excellent off characteristics. . In the present invention, by using the semiconductor layer 25 made of metal oxide, it is possible to reduce the flicker caused by the luminance deviation that occurs as the voltage leaks from the storage capacitor in the section where the data voltage should be maintained in the storage capacitor. Helps reduce device power consumption.

An etch stopper 28 is located on the semiconductor layer 25. The etch stopper 28 can prevent the lower semiconductor layer 25 from being damaged during the etching process of the source electrode 26a and the drain electrode 26b. The etch stopper 28 may be positioned corresponding to the channel region of the semiconductor layer 25. The etch stopper 28 may be made of a silicon oxide film (SiOx) or a silicon nitride film (SiNx).

Meanwhile, the source electrode 26a and the drain electrode 26b are located on the semiconductor layer 25 and the etch stopper 28. The source electrode 26a contacts one side of the semiconductor layer 25 and the drain electrode 26b contacts the other side of the semiconductor layer 25. The source electrode 26a and the drain electrode 26b may be made of a single layer or multiple layers. If the source electrode 26a and the drain electrode 26b are a single layer, molybdenum (Mo), aluminum (Al), chromium ( It may be made of any one selected from the group consisting of Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. In addition, when the source electrode 26a and the drain electrode 26b are multilayers, they are a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, or a triple layer of molybdenum/aluminum-neodymium/molybdenum. It can be done. Accordingly, a switching transistor (TFT) is constructed including the semiconductor layer 25, the gate electrode 23, the drain electrode 26b, and the source electrode 26a.

An overcoat layer 36 is located on the switching transistor (TFT). The overcoat layer 36 is a flattening film that alleviates the level difference in the lower structure and is made of organic materials such as polyimide, polyacryl, photoacryl, polyamide, and benzocyclobutane (BCB). You can.

The pixel electrode 1 is located on the overcoat layer 36. The pixel electrode 1 is connected to the drain electrode 26b of the switching transistor (TFT) through the via hole 38 formed in the overcoat layer 36. The pixel electrode 1 is a transparent material that can transmit light, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), and IGZO (Indium Gallium Zinc Oxide). It is made of conductive materials. The pixel electrode 1 serves to apply an electric field to the liquid crystal layer according to a signal from a switching transistor (TFT).

A passivation film 40 is positioned on the pixel electrode 1. The passivation film 40 insulates the pixel electrode 1 and may be made of silicon nitride (SiNx), silicon oxide (SiOx), or a stacked structure thereof.

A common electrode 2 is located on the passivation film 40. The common electrode 2 serves as a common electrode that applies an electric field to the liquid crystal layer from a subpixel perspective. The common electrode 2 is connected through a common line and receives a driving signal. When the common electrode 2 is divided into several blocks, the blocks can be connected to each other through a common line, thereby reducing the size and deviation between the storage capacitors of each subpixel. The common electrode 2, like the pixel electrode 1, may be made of a transparent conductive material that allows light to pass through, such as ITO, IZO, ITZO, ZnO, or IGZO.

A lower alignment layer 44a is located on the common electrode 2. The lower alignment layer 44a serves to initially align the liquid crystals of the upper liquid crystal layer 46 and may be made of polyimide.

An upper substrate 49 facing the lower substrate 20 is located on the lower substrate 20. The upper substrate 49 includes a black matrix 47, a color filter 48, and an upper alignment layer 44b. The black matrix 47 improves the contrast ratio by dividing each subpixel and preventing colors from mixing. A color filter 48 is located in the subpixels partitioned by the black matrix 47. The color filter 48 converts white light into red (R), green (G), and blue (B) to implement full color. An upper alignment layer 44b is located below the black matrix 47 and the color filter 48. Since the upper photo-alignment layer 44b is formed in the same manner as the lower alignment layer 44a described above, its description is omitted.

A liquid crystal layer 46 containing liquid crystal is located between the lower substrate 20 and the upper substrate 49. Liquid crystals are shaped like rice grains and have long and short axes with different dielectric constants. Here, if the dielectric constant of the major axis is greater than the dielectric constant of the minor axis, it is called positive liquid crystal, and if the dielectric constant of the long axis is smaller than the dielectric constant of the minor axis, it is called negative liquid crystal. The present invention can use positive or negative liquid crystal.

Meanwhile, as shown in FIG. 2, the present invention discloses that a GIP type gate driver is located below the display unit. In the following, a configuration for placing the gate driver on the lower side of the display will be described.

<First Example>

FIG. 6 is a plan view showing a subpixel according to the first embodiment of the present invention, FIG. 7 is a cross-sectional view taken along the cutting line B-B' of FIG. 6, and FIG. 8 is a cross-sectional view taken along the cutting line C-C' of FIG. 6. This is a cut cross-sectional view.

FIG. 6 is a plan view showing area P in FIG. 2 in detail. Referring to FIG. 6, the gate line 16 provided in the display portion 60 is connected from the gate driver 13 provided in the non-display portion 61 according to the first embodiment of the present invention, and the non-display portion 61 The data line 15 provided in the display unit 60 is connected from the pad unit 62 provided in .

In more detail, subpixels are divided by the intersection of the gate line 16 and the data line 15. The subpixel includes a gate electrode 23 branched from the gate line 16, a source electrode 26a branched from the data line 15, and a drain electrode 26b spaced apart from the source electrode 26a, and disposed between them. A switching transistor (TFT) composed of a semiconductor layer 25 is disposed, respectively. Additionally, a pixel electrode 1 connected to the drain electrode 26b of the switching transistor (TFT) is disposed in the subpixel, and a common electrode (not shown) opposing the pixel electrode 1 is disposed.

The gate line 16 is connected to the gate driver 13 through a gate connection line 82 extending from the gate driver 13. The gate connection line 82 is connected to the gate driver 13 through the first contact hole 84 in the gate driver 13, and may be integrated with the gate line 16. The data line 15 extends from the pad portion 62 to the subpixel and is connected to the source electrode 26a of the switching transistor (TFT) through the second contact hole 86. The first contact hole 84 is disposed in the non-display portion 61, and the second contact hole 86 is disposed in the display portion 60.

Specifically, the connection structure of the gate driver 13 and the gate line 16 will be examined with reference to FIG. 7. Referring to FIG. 7, a display portion 60 and a non-display portion 61 are divided on the lower substrate 20, and a gate driver 13 is disposed in the non-display portion 61.

The display unit 60 is composed of a switching transistor (TFT) including a semiconductor layer 25, a gate electrode 23, a source electrode 26a, and a drain electrode 26b on a lower substrate 20. A gate electrode 23 is located on the lower substrate 20, and a gate insulating film 30 is located on the gate electrode 23. A semiconductor layer 25 is located on the gate insulating film 30, and an etch stopper 28 is located on the semiconductor layer 25. The etch stopper 28 may be positioned corresponding to the channel region of the semiconductor layer 25.

A source electrode 26a and a drain electrode 26b are located on the semiconductor layer 25 and the etch stopper 28, so that the semiconductor layer 25, the gate electrode 23, the drain electrode 26b, and the source electrode 26a ) is configured to include a switching transistor (TFT).

An overcoat layer 36 is located on the switching transistor (TFT). The pixel electrode 1 is located on the overcoat layer 36. The pixel electrode 1 is connected to the drain electrode 26b of the switching transistor (TFT) through the via hole 38 formed in the overcoat layer 36. A passivation film 40 is positioned on the pixel electrode 1, and a common electrode 2 is positioned on the passivation film 40. A lower alignment layer 44a is located on the common electrode 2.

An upper substrate 49 facing the lower substrate 20 is located on the lower substrate 20. The upper substrate 49 includes a black matrix 47, a color filter 48, and an upper alignment layer 44b. The black matrix 47 partitions each subpixel, and a color filter 48 is located in the subpixels partitioned by the black matrix 47. The color filter 48 converts white light into red (R), green (G), and blue (B) to implement full color. An upper alignment layer 44b is located below the black matrix 47 and the color filter 48. A liquid crystal layer 46 containing liquid crystal is located between the lower substrate 20 and the upper substrate 49.

At least one driving transistor 90 is located in the gate driver 13 disposed in the non-display portion 61 on the lower substrate 20. This driving transistor 90 includes a pull-up transistor and a pull-down transistor of a shift register, and includes a plurality of transistors that apply a clock signal.

The driving transistor 90 includes a gate electrode 91, a semiconductor layer 92, an etch stopper 94, a source electrode 96a, and a drain electrode 96b. Specifically, the gate electrode 91 is located on the lower substrate 20, and the gate insulating film 30 is located on the gate electrode 91. A semiconductor layer 92 is located on the gate insulating film 30, and an etch stopper 94 is located on the semiconductor layer 92. The etch stopper 94 may be positioned corresponding to the channel region of the semiconductor layer 92. A source electrode 96a and a drain electrode 926b are positioned on the semiconductor layer 92 and the etch stopper 94 to form the driving transistor 90. An overcoat layer 36 extending from the display unit 60 is located on the driving transistor 90.

In the gate driver 13 of the present invention, the gate connection line 82 is connected to the drain electrode 96b of the driving transistor 90, and a gate driving signal is applied to the gate line 16 of the subpixel of the display unit 60. can do. To this end, the gate driver 13 is provided with a first contact hole 84 in the gate insulating film 30 so that the drain electrode 96b of the driving transistor 90 is connected to the gate connection line 82. The gate connection line 82 is formed as one body with the gate line 16 of the subpixel and can transmit a driving signal from the gate driver 13 to the gate electrode 23.

Meanwhile, the structure in which the data line extends from the pad portion will be described with reference to FIG. 8. In the following, descriptions overlapping with the above-described FIG. 7 will be briefly described.

Referring to FIG. 8, a display portion 60 and a non-display portion 61 are divided on the lower substrate 20, and the non-display portion 61 includes a pad portion 62 and a gate driver 13.

The display unit 60 is composed of a switching transistor (TFT) including a semiconductor layer 25, a gate electrode 23, a source electrode 26a, and a drain electrode 26b on a lower substrate 20. An overcoat layer 36 is located on the switching transistor (TFT), and the pixel electrode 1 is located on the overcoat layer 36. The pixel electrode 1 is connected to the drain electrode 26b of the switching transistor (TFT) through the via hole 38 formed in the overcoat layer 36. A passivation film 40 is positioned on the pixel electrode 1, and a common electrode 2 is positioned on the passivation film 40. A lower alignment layer 44a is located on the common electrode 2.

An upper substrate 49 facing the lower substrate 20 is located on the lower substrate 20. The upper substrate 49 includes a black matrix 47, a color filter 48, and an upper alignment layer 44b. The black matrix 47 partitions each subpixel, and a color filter 48 is located in the subpixels partitioned by the black matrix 47. The color filter 48 converts white light into red (R), green (G), and blue (B) to implement full color. An upper alignment layer 44b is located below the black matrix 47 and the color filter 48. A liquid crystal layer 46 containing liquid crystal is located between the lower substrate 20 and the upper substrate 49.

At least one driving transistor 90 is located in the gate driver 13 disposed in the non-display portion 61 on the lower substrate 20. This driving transistor 90 includes a gate electrode 91, a semiconductor layer 92, an etch stopper 94, a source electrode 96a, and a drain electrode 96b. The upper portion of the driving transistor 90 is formed by an overcoat layer 36 extending from the display unit 60 .

A data line 15 is extended and disposed on the pad portion 62 disposed in the non-display portion 61 on the lower substrate 20. The data line 15 extending from the pad portion 62 extends to the display portion 60 along the upper surface of the overcoat layer 36 disposed on the driving transistor 90. The data line 15 is insulated from the driving transistor 90 through the overcoat layer 36, so that it can extend to the display unit 60.

The data line 15 extending to the display unit 60 is connected to the source electrode 26a through the second contact hole 84 in the area corresponding to the source electrode 26a of the switching transistor (TFT). The second contact hole 84 is a hole exposing the source electrode 26a in the overcoat layer 36. As the data line 15 is connected to the thin film transistor (TFT) of the subpixel, a driving signal is applied to the pixel electrode 1 of the subpixel.

The data line 15 is disposed on the overcoat layer 36 in the same way as the pixel electrode 1, but the pixel electrode 1 has high resistance to be used as a wiring. Therefore, in the present invention, the Tx connection line 76 of the touch element described in FIG. 2 is formed of the same material. The data line 15 is made of a low-resistance metal material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), etc. to act as a wiring. It is formed of any one selected from the group consisting of neodymium (Nd) and copper (Cu) or an alloy thereof. In addition, the data line 15 is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or an alloy thereof. For example, data line 15 may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum or molybdenum/titanium.

In the first embodiment of the present invention, the data line 15 extending from the pad portion 62 to the display portion 60 is formed as one body, but is formed along the overcoat layer 36 on the gate driver 13. By doing so, interference with the gate driver 13 can be avoided. Therefore, there is an advantage in that the gate driver 13 can be formed below the display unit 60.

<Second Embodiment>

FIG. 9 is a plan view showing a subpixel according to a second embodiment of the present invention, FIG. 10 is a cross-sectional view taken along the cutting line D-D' of FIG. 9, and FIG. 11 is a cross-sectional view taken along the cutting line E-E' of FIG. 9. This is a cut cross-sectional view.

Referring to FIG. 9, the gate line 16 provided in the display portion 60 is connected from the gate driver 13 provided in the non-display portion 61 according to the first embodiment of the present invention, and the non-display portion 61 The data line 15 provided in the display unit 60 is connected from the pad unit 62 provided in .

In more detail, subpixels are divided by the intersection of the gate line 16 and the data line 15. The subpixel includes a gate electrode 23 branched from the gate line 16, a source electrode 26a branched from the data line 15, and a drain electrode 26b spaced apart from the source electrode 26a, and disposed between them. A switching transistor (TFT) composed of a semiconductor layer 25 is disposed, respectively. Additionally, a pixel electrode 1 connected to the drain electrode 26b of the switching transistor (TFT) is disposed in the subpixel, and a common electrode (not shown) opposing the pixel electrode 1 is disposed.

The gate line 16 is connected to the gate driver 13 through a gate connection line 82 extending from the gate driver 13. The gate connection line 82 is connected to the gate driver 13 and to the gate line 16 through the first contact hole 84 formed in the display unit 60. The data line 15 is connected to the pad portion 61 through a data connection line 88 extending from the pad portion 62. The data connection line 88 is connected to the data line 15 through the second contact hole 86 formed in the non-display portion 61. Accordingly, the data line 15 extends to the subpixel and is connected to the source electrode 26a of the switching transistor (TFT).

In the above-described first embodiment, the gate connection line 82 and the gate line 16 were connected through the first contact hole 84 formed in the non-display portion 61. In the second embodiment, there is a difference in that the first contact hole 84 is disposed in the display unit 60. In addition, in the above-described first embodiment, the data line 15 extends from the pad portion 62 to the display portion 60 and connects the switching transistor (TFT) through the second contact hole 86 formed in the display portion 60. It was connected to the source electrode (26a). In the second embodiment, a data connection line 88 is added from the pad portion 62 and extends to overlap the gate driver 13, and the second contact hole 88 formed in the non-display portion 61 is connected to the data connection line ( There is a difference in that 88) is connected to the data line 15.

Specifically, the connection structure of the gate driver 13 and the gate line 16 will be examined with reference to FIG. 10. Referring to FIG. 10, a display portion 60 and a non-display portion 61 are divided on the lower substrate 20, and a gate driver 13 is disposed in the non-display portion 61.

The display unit 60 is composed of a switching transistor (TFT) including a semiconductor layer 25, a gate electrode 23, a source electrode 26a, and a drain electrode 26b on a lower substrate 20. A gate electrode 23 is located on the lower substrate 20, and a gate insulating film 30 is located on the gate electrode 23. A semiconductor layer 25 is located on the gate insulating film 30, and an etch stopper 28 is located on the semiconductor layer 25. The etch stopper 28 may be positioned corresponding to the channel region of the semiconductor layer 25. A source electrode 26a and a drain electrode 26b are located on the semiconductor layer 25 and the etch stopper 28, so that the semiconductor layer 25, the gate electrode 23, the drain electrode 26b, and the source electrode 26a ) is configured to include a switching transistor (TFT).

An overcoat layer 36 is located on the switching transistor (TFT). The pixel electrode 1 is located on the overcoat layer 36. The pixel electrode 1 is connected to the drain electrode 26b of the switching transistor (TFT) through the via hole 38 formed in the overcoat layer 36. A passivation film 40 is positioned on the pixel electrode 1, and a common electrode 2 is positioned on the passivation film 40. A lower alignment layer 44a is located on the common electrode 2.

An upper substrate 49 facing the lower substrate 20 is located on the lower substrate 20. The upper substrate 49 includes a black matrix 47, a color filter 48, and an upper alignment layer 44b. The black matrix 47 partitions each subpixel, and a color filter 48 is located in the subpixels partitioned by the black matrix 47. The color filter 48 converts white light into red (R), green (G), and blue (B) to implement full color. An upper alignment layer 44b is located below the black matrix 47 and the color filter 48. A liquid crystal layer 46 containing liquid crystal is located between the lower substrate 20 and the upper substrate 49.

At least one driving transistor 90 is located in the gate driver 13 disposed in the non-display portion 61 on the lower substrate 20. The driving transistor 90 includes a gate electrode 91, a semiconductor layer 92, an etch stopper 94, a source electrode 96a, and a drain electrode 96b. Specifically, the gate electrode 91 is located on the lower substrate 20, and the gate insulating film 30 is located on the gate electrode 91. A semiconductor layer 92 is located on the gate insulating film 30, and an etch stopper 94 is located on the semiconductor layer 92. The etch stopper 94 may be positioned corresponding to the channel region of the semiconductor layer 92. A source electrode 96a and a drain electrode 926b are positioned on the semiconductor layer 92 and the etch stopper 94 to form the driving transistor 90. An overcoat layer 36 extending from the display unit 60 is located on the driving transistor 90.

In the gate driver 13 of the present invention, the gate connection line 82 is connected to the drain electrode 96b of the driving transistor 90, and a gate driving signal is applied to the gate line 16 of the subpixel of the display unit 60. can do. The drain electrode 96b of the driving transistor 90 may be formed as one body with the gate connection line 82. In the display unit 60, a first contact hole 84 is provided in the gate insulating film 30, and a gate connection line 82 integrated with the drain electrode 96b of the driving transistor 90 is connected to the gate line of the subpixel ( 16) Connect to. Therefore, a driving signal can be transmitted to the gate line 16 through the gate connection line 82 connected from the gate driver 13.

Meanwhile, the structure in which the data line extends from the pad portion will be described with reference to FIG. 11. Referring to FIG. 11, a display portion 60 and a non-display portion 61 are divided on the lower substrate 20, and the non-display portion 61 includes a pad portion 62 and a gate driver 13.

A data connection line 88 is disposed on the pad portion 62 disposed in the non-display portion 61 on the lower substrate 20. The data connection line 88 extending from the pad portion 62 extends along the upper surface of the overcoat layer 36 disposed on the driving transistor 90. The data connection line 88 is connected to the data line 15 of the subpixel through the second contact hole 84 formed in the non-display portion 61. The second contact hole 84 is a hole exposing the data line 15 in the overcoat layer 36. Accordingly, the data connection line 88 extending from the pad portion 62 is connected to the data line 15 of the subpixel through the second contact hole 84, thereby providing a driving signal to the switching transistor (TFT) of the subpixel. It can be delivered.

The data connection line 88 is disposed on the overcoat layer 36 in the same way as the pixel electrode 1. In the present invention, the data connection line 88 is formed of the same material as the Tx connection line 76 of the touch element described in FIG. 2. Additionally, the data line 15 disposed on the display unit 60 is made of the same material as the source electrode 26a of the switching transistor (TFT).

In the second embodiment of the present invention, interference with the gate driver 13 can be avoided by forming the data connection line 88 extending from the pad portion 62 along the overcoat layer 36 on the upper part of the gate driver 13. there is. Therefore, there is an advantage in that the gate driver 13 can be formed below the display unit 60.

As described above, the display device according to an embodiment of the present invention can implement the gate driver on the lower side of the display portion by providing a gate driver on the lower side of the display portion and disclosing the configurations for implementing the same. Accordingly, the display device according to an embodiment of the present invention has the advantage of reducing the bezels on the top, left, and right sides of the display unit by providing a gate driver below the display unit.

Figure 12 is a diagram showing display devices of various shapes.

Referring to FIG. 12, the display device according to embodiments of the present invention may be provided with a gate driver below the display unit, and thus has a structure in which both a gate signal and a data signal are applied from the bottom of the display unit. Therefore, as shown in (a) of FIG. 12, the shape of the display unit 60 can be applied to various shapes such as a triangle or a semicircle.

Additionally, as shown in (b) of FIG. 12, the display device according to embodiments of the present invention has a gate driver provided on one side of the display, for example, on the lower side, thereby reducing the bezel on the other side of the display. Therefore, when applied to a tile-type display device in which a plurality of display panels are configured in a tile type, display quality can be improved by reducing the visibility of boundaries between display panels.

As described above, the display device according to an embodiment of the present invention has the advantage of reducing the bezel on the top and left and right sides of the display unit by providing a gate driver below the display unit. Additionally, the display device according to an embodiment of the present invention has the advantage of being applicable to display devices having various shapes by providing both a gate driver and a pad portion on one side of the display portion.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present specification. Therefore, the technical scope of the present specification is not limited to the content described in the detailed description of the specification, but should be determined by the scope of the patent claims. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

13: gate driver 15: data line
16: gate line 60: display unit
61: Non-display area 82: Gate connection line
86: data connection line

Claims (14)

Board;
a display unit disposed on the substrate and including a plurality of subpixels;
a non-display portion including an area remaining in addition to the display portion;
a pad portion disposed below the display portion in the non-display portion;
a gate driver disposed between the display unit and the pad unit;
a gate connection line connected from the gate driver to a plurality of subpixels of the display unit;
Comprising a data connection line connected from the pad portion to a plurality of subpixels of the display portion,
The plurality of subpixels include at least one switching transistor,
The at least one switching transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode,
The gate connection line is connected to a gate line connected to the gate electrode of the at least one switching transistor,
The gate driver includes at least one driving transistor,
The gate connection line is connected to the at least one driving transistor through a first contact hole formed in the gate driver,
The at least one driving transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode,
The gate connection line is connected to one of the source electrode and the drain electrode,
The gate connection line and the gate line are formed as one body.
Display device. delete delete delete delete delete Board;
a display unit disposed on the substrate and including a plurality of subpixels;
a non-display portion including an area remaining in addition to the display portion;
a pad portion disposed below the display portion in the non-display portion;
a gate driver disposed between the display unit and the pad unit;
a gate connection line connected from the gate driver to a plurality of subpixels of the display unit;
Comprising a data connection line connected from the pad portion to a plurality of subpixels of the display portion,
The plurality of subpixels include at least one switching transistor,
The at least one switching transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode,
The gate connection line is connected to a gate line connected to the gate electrode of the at least one switching transistor,
The gate driver includes at least one driving transistor,
The gate connection line is connected to the at least one driving transistor through a first contact hole formed in the gate driver,
The at least one driving transistor includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode,
The gate connection line is connected to one of the source electrode and the drain electrode,
A display device wherein the gate connection line is connected to the gate line through a second contact hole formed in the display unit. According to claim 1,
The data connection line is connected to a data line connected to the source electrode or the drain electrode of the at least one switching transistor. According to clause 8,
A display device in which the data connection line and the data line are integrated into one body. According to clause 8,
A display device wherein the data connection line is connected to the data line through a third contact hole formed in the display unit. According to clause 7,
The data connection line is connected to a data line connected to the source electrode or the drain electrode of the at least one switching transistor,
A display device wherein the data connection line is connected to the data line through a fourth contact hole formed in the non-display portion. According to claim 10,
Further comprising an overcoat layer covering the gate driver and the at least one switching transistor,
The data connection line is disposed on the overcoat layer and connected to the data line through the third contact hole provided in the overcoat layer. According to claim 11,
The non-display unit in which the fourth contact hole is formed is disposed between the gate driver and the display unit. According to claim 11,
Further comprising an overcoat layer covering the gate driver and the at least one switching transistor,
The data connection line is disposed on the overcoat layer and connected to the data line through the fourth contact hole provided in the overcoat layer.

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