KR102599801B1 - Layout design system and semiconductor device fabricated by using the system - Google Patents

Abstract

A layout design system and a semiconductor device manufactured using the same are provided. The semiconductor device includes: a pillar cell including a first insulating structure and a second insulating structure formed in a first direction, the area of which is defined by a first cell boundary; and a third insulating structure formed in the first direction, including an adjacent cell disposed adjacent to the pillar cell in the first direction, the area of which is defined by a second cell boundary, and the first insulating structure. The structure and the second insulating structure are arranged to be spaced apart from each other in a second direction perpendicular to the first direction.

Description

Layout design system and semiconductor device manufactured using the same {LAYOUT DESIGN SYSTEM AND SEMICONDUCTOR DEVICE FABRICATED BY USING THE SYSTEM}

The present invention relates to a layout design system and a semiconductor device manufactured using the same.

As semiconductor device manufacturing processes become increasingly finer, demand for miniaturized semiconductor devices is increasing day by day. In order to manufacture such miniaturized semiconductor devices, a layout design that ensures the reliability of the finished device is required. In particular, a layout design that ensures insulation between adjacent transistors while preventing changes in the characteristics of the transistors is required.

The technical problem to be solved by the present invention is to provide a layout design system that can generate a layout design that ensures product reliability.

Another technical problem to be solved by the present invention is to provide a semiconductor device with improved reliability manufactured using the layout design system.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor device according to an embodiment of the present invention for achieving the above technical problem includes a first insulating structure and a second insulating structure formed in a first direction, and a pillar cell whose area is defined by the first cell boundary. ; and a third insulating structure formed in the first direction, including an adjacent cell disposed adjacent to the pillar cell in the first direction, the area of which is defined by a second cell boundary, and the first insulating structure. The structure and the second insulating structure are arranged to be spaced apart from each other in a second direction perpendicular to the first direction.

A semiconductor device according to another embodiment of the present invention for achieving the above technical problem includes a first insulating structure and a second insulating structure formed in a first direction, and a first insulating structure whose area is defined by a first cell boundary. cell; and a second cell disposed adjacent to the first cell in a second direction perpendicular to the first direction, wherein the first insulating structure and the second insulating structure are disposed in a second direction perpendicular to the first direction. are placed and spaced apart.

A layout design system according to an embodiment of the present invention for achieving the above technical problem includes a processor; A storage unit storing a plurality of standard cell designs; and a placement module that uses the processor to place the plurality of standard cell designs according to defined requirements, wherein the placement module places the plurality of standard cell designs in a first direction. A filler design including a first insulating structure and a second insulating structure formed in the first direction is disposed adjacent thereto, wherein the filler design has an area defined by a first cell boundary, The first insulating structure and the second insulating structure are arranged to be spaced apart from each other in the second direction.

A layout design system according to another embodiment of the present invention for achieving the above technical problem includes a processor; a storage unit where intermediate designs are stored; and a generation module that uses the processor to generate a design element in the intermediate design, wherein the intermediate design includes a standard cell design and a pillar design disposed adjacent to the standard cell design in a first direction. Includes, wherein the filler design has an area defined by a first cell boundary, and the generation module generates a first insulating structure and a second insulating structure within the filler design in the first direction, wherein the first insulating structure is The insulating structure and the second insulating structure are arranged to be spaced apart from each other in the second direction.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of a layout design system according to an embodiment of the present invention.
Figure 2 is a layout diagram of a semiconductor device according to an embodiment of the present invention.
3 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
FIG. 4 is a diagram for explaining the pillar cell shown in FIG. 3.
5 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
FIG. 6 is a diagram for explaining the pillar cell shown in FIG. 5.
Figure 7 is a block diagram of a layout design system according to another embodiment of the present invention.
Figure 8 is a block diagram of a layout design system according to another embodiment of the present invention.
9 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
10 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
11 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
12 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
13 is a layout diagram of a semiconductor device according to another embodiment of the present invention.
14 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

1 is a block diagram of a layout design system according to an embodiment of the present invention.

As used hereinafter, the term 'unit' or 'module' refers to software or hardware components such as FPGA or ASIC, and the 'unit' or 'module' performs certain roles. However, 'part' or 'module' is not limited to software or hardware. A 'unit' or 'module' may be configured to reside on an addressable storage medium and may be configured to run on one or more processors. Therefore, as an example, 'part' or 'module' refers to components such as software components, object-oriented software components, class components and task components, processes, functions, properties, May include procedures, subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functionality provided within components and 'parts' or 'modules' can be combined into smaller numbers of components and 'parts' or 'modules' or into additional components and 'parts' or 'modules'. Could be further separated.

Referring to FIG. 1, the layout design system 1 includes a storage unit 10, a placement module 20, a creation module 30, and a processor 50.

A standard cell design 12 may be stored in the storage unit 10 . Here, a standard cell may be a unit that constitutes the minimum unit in block, device, or chip design. For example, if the device is a Static Random Access Memory (SRAM) device or a logic device, the standard cell constituting the device may be an inverter cell.

Meanwhile, the standard cell design 12 may include a layout capable of manufacturing such a standard cell. For example, the standard cell design 12 may include an active region and a gate region disposed on the active region.

Although FIG. 1 shows one standard cell design 12 stored in the storage unit 10, the present invention is not limited thereto. In some embodiments of the present invention, a plurality of standard cell designs 12 constituting one block, device, or chip may be stored in the storage unit 10. That is, a plurality of standard cell designs 12 may be stored in the storage unit 10 in the form of a library.

Meanwhile, the intermediate design 14 output by the placement module 20 may be stored in the storage unit 10. In this embodiment, the intermediate design 14 may include a standard cell design 12 and a filler design disposed adjacent to the standard design 12 and including a plurality of insulating structures therein. there is. A more detailed explanation of this will be provided later.

In this embodiment, the standard cell design 12 may be used as an input to the placement module 12 as shown, and the intermediate design 14 may be used as an input to the creation module 30.

In some embodiments of the present invention, this storage unit 10 may be configured as, for example, a non-volatile memory device. Examples of such non-volatile memory devices include NAND flash, NOR flash, MRAM, PRAM, and RRAM, but the present invention is not limited thereto. Meanwhile, in some other embodiments of the present invention, the storage unit 10 may be composed of a hard disk drive, a magnetic storage device, etc.

The placement module 20 may generate an intermediate design 14 by placing a plurality of standard cell designs 12 according to defined chip design requirements 19 using the processor 50 . The intermediate design 14 created in this way may be stored in the storage unit 10, but the present invention is not limited thereto.

Meanwhile, the chip design requirement 19 provided to the placement module 20 may be input by a user, etc., but, unlike shown, may be pre-stored in the storage unit 10.

In some embodiments of the present invention, this deployment module 20 may be implemented in software form, but the present invention is not limited thereto.

The creation module 30 may generate design elements within the intermediate design 14 using the processor 50 . In this embodiment, design elements generated by the generation module 30 include, for example, an active area and a dummy gate area, but the present invention is not limited thereto.

In particular, in this embodiment, the creation module 30 may generate a plurality of insulating structures arranged to be spaced apart from each other within a pillar design disposed adjacent to the standard cell design 12 included in the intermediate design 14. A detailed explanation of this will be provided later.

In some embodiments of the present invention, this generation module 30 may also be implemented in software form, but the present invention is not limited thereto.

Meanwhile, in some embodiments of the present invention, when both the batch module 20 and the generation module 30 are implemented in software form, the batch module 20 and the generation module 30 store a code (code) in the storage unit 10. It may be stored in the form of a code, or it may be stored in the form of a code in another storage unit (not shown) separate from the storage unit 10.

The processor 50 may be used by the batch module 20 and the generation module 30 to perform operations. Although only one processor 50 is shown in Figure 1, the present invention is not limited thereto. In some embodiments of the present invention, a plurality of processors 50 may be disposed. In other words, the illustrated layout design system 1 can be modified to run in a multi-core environment. In this way, when the layout design system 1 runs in a multi-core environment, computational efficiency can be improved.

Meanwhile, although not shown in detail in the drawing, the processor 50 may additionally include cache memories such as L1 and L2 to improve computing power.

Although, in FIG. 1, the layout design system 1 is shown to generate the chip design 40 by placing the standard cell design 12 according to the chip design requirements 19, the present invention is not shown. It is not limited to this and can be modified in many different ways. For example, in some embodiments of the present invention, the layout design system 1 transforms the standard cell design 12 to create a block design (not shown) according to block design requirements (not shown). It could be.

Figure 2 is a layout diagram of a semiconductor device according to an embodiment of the present invention. For example, the layout diagram of FIG. 2 may be a layout diagram of the intermediate design 14 shown in FIG. 1 .

Referring back to FIG. 1, the placement module 20 may place a plurality of standard cell designs 12 according to chip design requirements 19. Additionally, the placement module 20 may generate an intermediate design 14 by placing a filler design between a plurality of standard cell designs 12 .

Figure 2 shows an example in which a plurality of standard cell designs (120a to 120f, 122a to 122e) and pillar designs (130a to 130c) are arranged according to chip design requirements 19.

Referring to FIG. 2, standard cell designs 120a to 120f and standard cell designs 122a to 122e are disposed above and below the middle design 14. And the pillar designs (130a to 130c) are disposed between the standard cell designs (120a to 120f) and the standard cell designs (122a to 122e).

In this embodiment, for convenience of explanation, the standard cell designs 120a to 120f are arranged adjacent to the pillar designs 130a to 130c in the first direction (Y), and the standard cell designs 122a to 122e are also positioned as pillars. Although it is shown to be arranged adjacent to the designs 130a to 130c in the first direction (Y), the scope of the present invention is not limited thereto. That is, the standard cell designs 120a to 120f or the standard cell designs 122a to 122e may be arranged adjacent to the pillar designs 130a to 130c in the second direction (X).

Here, the area of the pillar designs 130a to 130c is defined by a first cell boundary that demarcates the boundary. For example, the area of the pillar design 130b is defined by the first cell boundary (A). Likewise, the areas of the standard cell designs 120a to 120f and 122a to 122e are defined by a second cell boundary that demarcates the boundaries. For example, the area of the standard cell design 120f is defined by the second cell boundary B.

An insulating structure is formed between the standard cell designs 120a to 120f and between the standard cell designs 122a to 122e. For example, an insulating structure 150a is formed in the first direction (Y) at the boundary between the standard cell design 120a and the standard cell design 120b, and the insulating structure 150a is formed at the boundary between the standard cell design 120e and the standard cell design 120f. An insulating structure 150d may be formed at the boundary in the first direction (Y). Likewise, an insulating structure 150c is formed in the first direction (Y) at the boundary between the standard cell design 122a and the standard cell design 122b, and at the boundary between the standard cell design 122d and the standard cell design 122e. The insulating structure 150f may be formed in the first direction (Y).

Meanwhile, an insulating structure is also formed between the pillar designs 130a to 130c. For example, the insulating structure 150b may be formed at the boundary between the filler designs 130a and 130b, and the insulating structure 150e may be formed at the boundary between the filler designs 130b and 130c. there is.

These insulating structures are intended to provide electrical isolation between the designs that define each cell. However, as in the present embodiment, the insulating structures 150a, 150b, 150c or the insulating structures 150d, 150e, 150f extending continuously in the first direction (Y) are connected to the transistors formed in the cell area around them. The characteristics of the same devices can be changed.

Specifically, the insulating structures 150a, 150b, and 150c or the insulating structures 150d, 150e, and 150f are formed by forming a trench in a semiconductor substrate or an active region formed in a semiconductor substrate, and then burying an insulating material in the formed trench. The insulating structures 150a, 150b, 150c or the insulating structures 150d, 150e, 150f formed in this way may apply stress to the transistor formed in the cell region. In particular, the lines of the plurality of insulating structures 150a, 150b, and 150c or the lines of the plurality of insulating structures 150d, 150e, and 150f continuously extending in the first direction (Y) are transistors formed in the cell region. It can further increase the stress on the body.

Accordingly, if stress increases excessively, not only will the operating characteristics of the transistor formed in the cell area change, but it may also become difficult to predict the characteristics.

3 is a layout diagram of a semiconductor device according to another embodiment of the present invention. For example, the layout diagram of FIG. 3 may be a layout diagram of the intermediate design 14 shown in FIG. 1 . And FIG. 4 is a diagram for explaining the pillar design shown in FIG. 3.

Referring to FIG. 3, the difference from the embodiment of FIG. 2 is that the intermediate design 14 is between the standard cell designs 120a to 120f and the standard cell designs 122a to 122e in the second direction (X). It includes pillar designs 132a to 132c including a plurality of insulating structures spaced apart from each other.

Referring to FIG. 4 together, the pillar design 132b includes a first insulating structure 152b and a second insulating structure 154b formed in the first direction (Y). The area of the pillar design 132b is defined by the first cell boundary C1.

In this embodiment, at least one of the first insulating structure 152b and the second insulating structure 154b may be arranged to be spaced apart from the first cell boundary C1 in the second direction (X). For example, the first insulating structure 152b and the second insulating structure 154b may be arranged to be spaced apart by a distance S1 in the second direction (X).

Meanwhile, in this embodiment, the first insulating structure 152b is arranged to be spaced apart from one side of the first cell boundary C1 by a first distance D1 in the second direction (X), and the second insulating structure ( 154b) may be arranged to be spaced apart from one side of the first cell boundary C1 by a second distance D2 that is different from the first distance D1 in the second direction (X).

Furthermore, in this embodiment, the first insulating structure 152b and the second insulating structure 154b may not overlap each other in the second direction (X). In other words, the first insulating structure 152b and the second insulating structure 154b may be arranged to be spaced apart from each other at a distance S2 in the first direction Y.

Referring again to FIG. 3, the standard cell designs 120c and 120d include a third insulating structure 150g formed in the first direction (Y) and adjacent to the pillar design 132b in the first direction (Y). It is placed. Here, the areas of the standard cell designs 120c and 120d may be defined by the second cell boundary, respectively.

In such a pillar design 132b, for example, the first insulating structure 152b may be connected to the third insulating structure 150g, but the second insulating structure 154b may not be connected to the third insulating structure 150g. there is.

Accordingly, it is possible to prevent the formation of a plurality of lines of insulating structures continuously extending in the first direction (Y), thereby avoiding excessive increase in stress applied to the transistor formed in the cell region. .

Meanwhile, in this embodiment, cells adjacent to the pillar design 132b in the first direction (Y) are described as standard cell designs (120c, 120d, etc.), but the scope of the present invention is not limited thereto. That is, the cell designs 120c, 120d, etc. adjacent to the pillar design 132b in the first direction (Y) may be pillar designs.

5 is a layout diagram of a semiconductor device according to another embodiment of the present invention. For example, the layout diagram of FIG. 5 may be a layout diagram of the intermediate design 14 shown in FIG. 1 . And FIG. 6 is a diagram for explaining the pillar design shown in FIG. 5.

Referring to FIGS. 5 and 6 together, the difference from the embodiment of FIGS. 3 and 4 is that the pillar design 134b includes a first insulating structure 156b and a second insulating structure (156b) formed in the first direction (Y). 158b), and further includes a fourth insulating structure 157b and a fifth insulating structure 158b formed in the first direction (Y). The area of the pillar design 134b is defined by the first cell boundary C2.

In this embodiment, at least one of the first insulating structure 156b and the second insulating structure 158b may be arranged to be spaced apart from the first cell boundary C2 in the second direction (X). For example, the first insulating structure 156b and the second insulating structure 158b may be arranged to be spaced apart from each other by a distance S11 in the second direction (X).

Likewise, at least one of the fourth insulating structure 157b and the fifth insulating structure 159b may be arranged to be spaced apart from the first cell boundary C2 in the second direction (X). For example, the fourth insulating structure 157b and the fifth insulating structure 159b may be arranged to be spaced apart from each other by a distance S12 in the second direction (X).

In this embodiment, the spacing S11 and S12 may be the same, but the scope of the present invention is not limited thereto. That is, in some other embodiments of the present invention, the interval S11 and the interval S12 may be set differently.

Meanwhile, in this embodiment, the first insulating structure 156b is arranged to be spaced apart from one side of the first cell boundary C1 by a first distance D1 in the second direction (X), and the second insulating structure ( 158b) may be arranged to be spaced apart from one side of the first cell boundary C2 by a second distance D2 that is different from the first distance D1 in the second direction (X). And the fourth insulating structure 157b is disposed to be spaced apart from one side of the first cell boundary C1 by a third distance D3 in the second direction, and the fifth insulating structure 159b is disposed at a distance D3 from one side of the first cell boundary C1. ) may be arranged to be spaced apart from one side in the second direction (X) by a fourth distance (D4) that is different from the third distance (D3).

Furthermore, in this embodiment, the first insulating structure 156b and the second insulating structure 158b may not overlap each other in the second direction (X). In other words, the first insulating structure 156b and the second insulating structure 158b may be arranged to be spaced apart from each other at a distance S2 in the first direction Y. Likewise, the fourth insulating structure 157b and the fifth insulating structure 158b may not overlap each other in the second direction (X). In other words, the fourth insulating structure 157b and the fifth insulating structure 158b may be arranged to be spaced apart from each other at a distance S2 in the first direction (Y).

Referring again to FIG. 5, the standard cell designs 120d and 120e include a third insulating structure 150h formed in the first direction (Y) and adjacent to the pillar design 134b in the first direction (Y). It is placed. Here, the areas of the standard cell designs 120d and 120e may be defined by the second cell boundary, respectively.

In such a pillar design 134b, for example, the fourth insulating structure 157b may be connected to the third insulating structure 150h, but the second insulating structure 159b may not be connected to the third insulating structure 150h. there is.

Accordingly, it is possible to prevent the formation of a plurality of lines of insulating structures continuously extending in the first direction (Y), thereby avoiding excessive increase in stress applied to the transistor formed in the cell region. .

Figure 7 is a block diagram of a layout design system according to another embodiment of the present invention.

Referring to FIG. 7, a plurality of candidate filler designs 16 may be further stored in the storage unit 10 of the layout design system 2.

Specifically, a candidate pillar design including a plurality of insulating structures as described above with reference to FIGS. 3 to 6 may be stored in the storage unit 10 .

Meanwhile, in this embodiment, the generation module 32 may exchange the filler design included in the intermediate design 14 with one of the plurality of candidate filler designs 16 stored in the storage unit 10. That is, the generation module 32 according to the present embodiment does not newly generate a plurality of insulating structures as in the previously described embodiment, but generates a candidate including a plurality of insulating structures as previously described in FIGS. 3 to 6. By selecting the filler design (16), the intermediate design (14) can be created.

Meanwhile, in FIG. 7, the generation module 32 is shown to select one of a plurality of candidate filler designs 16, but the present invention is not limited thereto. In some embodiments of the invention, deployment module 20 may select one of a plurality of candidate pillar designs 16 that include different insulating structures. For example, in the step of the placement module 20 placing the pillar design, among the plurality of candidate pillar designs 16, a pillar design including an insulation structure of the form shown in FIG. 4 or an insulation structure of the form shown in FIG. 6 The embodiment may be practiced with modifications to select a pillar design that includes the structure.

Figure 8 is a block diagram of a layout design system according to another embodiment of the present invention.

Referring to FIG. 8, in the layout design system 3, the placement module 22 and the creation module 34 may be implemented as one integrated integrated module 60. Accordingly, the intermediate design 14 output by the placement module 22 is not stored in the storage unit 10, but can be directly provided to the creation module 34.

8 also shows the generation module 34 selecting one of a plurality of candidate filler designs 16, but the present invention is not limited thereto, and as described above, the placement module 22 selects one of a plurality of candidate filler designs 16. The embodiment may be modified by selecting one of the candidate filler designs 16.

9 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 9 , the semiconductor device 21a includes a first cell (F1) and a second cell (P1). In some embodiments of the present invention, the semiconductor device 21a may be a power gating cell.

The first cell F1 includes a first insulating structure IS11 and a second insulating structure IS12 formed in the first direction Y, and its area may be defined by the first cell boundary F1. .

The first cell F1 may correspond to a fill area of the power gating cell. One or more patterns PT and a plurality of insulating structures IS11 to IS16 may be formed in the fill area. Here, the pattern PT may form a dummy active pattern, a dummy polysilicon pattern, a dummy decoupling capacitor, etc.

The second cell P1 may be placed adjacent to the first cell F1 in the second direction (X).

The second cell P1 may be an active area of a power gating cell including one or more patterns PT. Here, the pattern PT may form an active pattern, a polysilicon pattern, a decoupling capacitor, etc. In some embodiments of the invention, the active area may be, for example, the PMOS switch area of a power gating cell.

The first insulating structure IS11 and the second insulating structure IS12 may be arranged to be spaced apart in the second direction (X).

In this embodiment, at least one of the first insulating structure IS11 and the second insulating structure IS12 may be arranged to be spaced apart from the first cell boundary F1 in the second direction (X).

Meanwhile, in this embodiment, the first insulating structure IS11 and the second insulating structure IS12 are one part of the first insulating structure IS11 and the second insulating structure IS12 and the first cell boundary F1. Each distance from the side may be arranged to be different from each other.

Furthermore, the first insulating structure IS11 and the second insulating structure IS12 may not overlap each other in the second direction (X). In other words, the first insulating structure IS11 and the second insulating structure IS12 may be arranged to be spaced apart from each other in the first direction (Y).

The semiconductor device 21a may further include a third cell F2.

The third cell F2 includes a third insulating structure IS21 and a fourth insulating structure IS22 formed in the first direction Y, and its area may be defined by the third cell boundary F2. .

Like the first cell F1, the third cell F2 may also correspond to a fill area of the power gating cell. One or more patterns PT and a plurality of insulating structures IS21 to IS26 may be formed in the fill area.

The third insulating structure IS21 and the fourth insulating structure IS22 may be arranged to be spaced apart in the second direction (X).

In this embodiment, at least one of the third insulating structure IS21 and the fourth insulating structure IS22 may be arranged to be spaced apart from the third cell boundary F2 in the second direction (X).

Meanwhile, in this embodiment, the third insulating structure IS21 and the fourth insulating structure IS22 are one part of the third insulating structure IS21 and the fourth insulating structure IS22 and the third cell boundary F2. Each distance from the side may be arranged to be different from each other.

Furthermore, the third insulating structure IS21 and the fourth insulating structure IS22 may not overlap each other in the second direction (X). In other words, the third insulating structure IS21 and the fourth insulating structure IS22 may be arranged to be spaced apart from each other in the first direction (Y).

10 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 10, the semiconductor device 21b is different from the semiconductor device 21a of FIG. 9 in that the first insulating structure IS11 and the second insulating structure IS12 are spaced apart from each other in the first direction (Y). The point is that it is placed without . Additionally, the third insulating structure IS21 and the fourth insulating structure IS22 may also be disposed in the first direction (Y) without space from each other.

11 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 11 , the semiconductor device 22a includes a first cell F3 and a second cell P2. Additionally, the semiconductor device 22a further includes a third cell (F4), a fourth cell (P3), and a fifth cell (F5). In some embodiments of the present invention, semiconductor device 22a may be a power gating cell.

The first cell F3 includes a first insulating structure IS31 and a second insulating structure IS32 formed in the first direction Y, and its area may be defined by the first cell boundary F3. . Meanwhile, the third cell F4 includes a third insulating structure IS41 and a fourth insulating structure IS42 formed in the first direction Y, and its area is defined by the third cell boundary F4. You can. The fifth cell F5 includes a fifth insulating structure IS45 and a sixth insulating structure IS46 formed in the first direction Y, and its area may be defined by the fifth cell boundary F5. .

The first cell (F3), the third cell (F4), and the fifth cell (F5) may correspond to a fill area of the power gating cell.

The second cell P1 may be arranged adjacent to the first cell F3, third cell F4, and fifth cell F5 in the second direction (X). Meanwhile, the fourth cell P3 may be arranged adjacent to the third cell F4 and the fifth cell F5 in the first direction (Y).

The second cell P1 and the fourth cell P3 may be active areas of a power gating cell including one or more patterns PT. In some embodiments of the present invention, the second cell P1 may be, for example, a PMOS switch area of a power gating cell, and the fourth cell P3 may be, for example, a buffer area of a power gating cell.

The first insulating structure IS31 and the second insulating structure IS32 may be arranged to be spaced apart in the second direction (X).

In this embodiment, at least one of the first insulating structure IS31 and the second insulating structure IS32 may be arranged to be spaced apart from the first cell boundary F3 in the second direction (X).

Meanwhile, in this embodiment, the first insulating structure IS31 and the second insulating structure IS32 are one part of the first insulating structure IS31 and the second insulating structure IS32 and the first cell boundary F3. Each distance from the side may be arranged to be different from each other.

Furthermore, the first insulating structure IS31 and the second insulating structure IS32 may not overlap each other in the second direction (X). In other words, the first insulating structure IS31 and the second insulating structure IS32 may be arranged to be spaced apart from each other in the first direction (Y).

The third insulating structure (IS41) and the fourth insulating structure (IS42), the fifth insulating structure (IS45) and the sixth insulating structure (IS46), the first insulating structure (IS31) and the second insulating structure (IS32) It can be arranged similarly.

12 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 12, the semiconductor device 22b is different from the semiconductor device 22a of FIG. 11 in that the first insulating structure IS31 and the second insulating structure IS32 are spaced apart from each other in the first direction (Y). The point is that it is placed without . In addition, the third insulating structure IS41 and fourth insulating structure IS42, and the fifth insulating structure IS45 and sixth insulating structure IS46 may be arranged without space from each other in the first direction (Y). You can.

13 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 13 , the semiconductor device 23a includes a first cell F6 and a second cell P4. In some embodiments of the present invention, the semiconductor device 23a may be an endcap cell.

The first cell F6 includes a first insulating structure IS51, a second insulating structure IS52, a third insulating structure IS53, a fourth insulating structure IS54, and a fifth insulating structure formed in the first direction (Y). It may include a structure (IS55) and a sixth insulating structure (IS56). The area of the first cell F6 may be defined by the first cell boundary F6.

The first cell F6 may correspond to the fill area of the end cap cell.

The first insulation structure (IS51), the second insulation structure (IS52), the third insulation structure (IS53), the fourth insulation structure (IS54), the fifth insulation structure (IS55), and the sixth insulation structure (IS56) are the second insulation structure (IS56). It can be arranged spaced apart in the direction (X).

In this embodiment, the first insulation structure (IS51), the second insulation structure (IS52), the third insulation structure (IS53), the fourth insulation structure (IS54), the fifth insulation structure (IS55), and the sixth insulation structure ( At least one of IS56) may be arranged to be spaced apart from the first cell boundary (F3) in the second direction (X).

Meanwhile, in this embodiment, the first insulation structure (IS51), the second insulation structure (IS52), the third insulation structure (IS53), the fourth insulation structure (IS54), the fifth insulation structure (IS55), and the sixth insulation structure The structure IS56 includes a first insulating structure IS51, a second insulating structure IS52, a third insulating structure IS53, a fourth insulating structure IS54, a fifth insulating structure IS55, and a sixth insulating structure. (IS56) may be arranged so that the respective distances between one side of the first cell boundary (F6) are different from each other.

Furthermore, the first insulating structure IS51 and the second insulating structure IS52, the third insulating structure IS53 and the fourth insulating structure IS54, and the fifth insulating structure IS55 and the sixth insulating structure IS56. may not overlap each other in the second direction (X). In other words, the first insulation structure (IS51) and the second insulation structure (IS52), the third insulation structure (IS53) and the fourth insulation structure (IS54), and the fifth insulation structure (IS55) and the sixth insulation structure (IS56). may be arranged to be spaced apart from each other in the first direction (Y).

14 is a layout diagram of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 12, the semiconductor device 23b is different from the semiconductor device 23a of FIG. 13 in that the first insulating structure IS51, the second insulating structure IS52, the third insulating structure IS53, and the The fourth insulating structure IS54, the fifth insulating structure IS55, and the sixth insulating structure IS56 are each disposed in the first direction (Y) without space from each other.

According to the various embodiments of the present invention described so far, it is possible to prevent the formation of lines of a plurality of insulating structures extending continuously in one direction, thereby excessively increasing the stress applied to the transistor formed in the cell region. This can be avoided while providing insulation to the semiconductor device.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: storage unit 20: batch module
30: Generation module 50: Processor

Claims (10)

a pillar cell including a first insulating structure and a second insulating structure extending in a first direction and defined by a first cell boundary; and
It includes a third insulating structure extending in the first direction, and a standard cell disposed adjacent to the pillar cell in the first direction and defined by a second cell boundary,
The first insulating structure and the second insulating structure are spaced apart from each other in a second direction perpendicular to the first direction,
The first insulating structure is connected to the third insulating structure,
A semiconductor device wherein the second insulating structure is not connected to the third insulating structure. According to paragraph 1,
At least one of the first insulating structure and the second insulating structure is spaced apart from the first cell boundary in the second direction. According to paragraph 1,
The first insulating structure is spaced apart from the first cell boundary by a first distance in the second direction on one side of the pillar cell,
The second insulating structure is spaced apart from the first cell boundary on the one side of the pillar cell in the second direction by a second distance different from the first distance. According to paragraph 1,
A semiconductor device wherein the first insulating structure and the second insulating structure do not overlap each other in the second direction. According to paragraph 1,
The pillar cell further includes a fourth insulating structure and a fifth insulating structure extending in the first direction,
The first insulating structure and the second insulating structure are spaced apart from each other at a first distance in the second direction,
The fourth insulating structure and the fifth insulating structure are spaced apart from each other by the first distance in the second direction. According to paragraph 1,
The standard cell includes an active region having at least one of a switch region of a power gating cell or a buffer region of the power gating cell. a first pillar cell including a first insulating structure and a second insulating structure extending in a first direction and defined by a first cell boundary; and
It includes a third insulating structure extending in the first direction, and includes a first standard cell disposed adjacent to the first pillar cell in the first direction and defined by a second cell boundary,
The first insulating structure and the second insulating structure are spaced apart in a second direction perpendicular to the first direction,
The first insulating structure is connected to the third insulating structure,
The second insulating structure is not connected to the third insulating structure,
A semiconductor device wherein the first insulating structure and the second insulating structure do not overlap each other in the second direction. In clause 7,
The first insulating structure and the second insulating structure extend to the first pillar cell. In clause 7,
The first pillar cell includes a fourth insulating structure and a fifth insulating structure extending in the first direction,
The first insulating structure and the second insulating structure include a first gap in the second direction between the first insulating structure and the second insulating structure,
The fourth insulating structure and the fifth insulating structure include the first gap in the second direction between the fourth insulating structure and the fifth insulating structure. For a layout of a semiconductor device, execute machine readable instructions on a processor to create at least one filler cell for placement between a first standard cell and a second standard cell, according to the layout. Including manufacturing the semiconductor device,
The at least one pillar cell includes a first insulating structure and a second insulating structure extending in a first direction,
The first insulating structure forms a line with the third insulating structure in the first standard cell,
The second insulating structure does not form a line with the insulating structure in the second standard cell,
The first insulating structure and the second insulating structure are spaced apart from each other in a second direction perpendicular to the first direction.

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