KR102543038B1 - Organic Light Emitting Display Device and Method of Manufacturing the same - Google Patents

Abstract

The present invention improves the threshold voltage characteristics and HCS reliability of a driving transistor by improving the channel hydrogenation rate and strengthening the film quality, preparing the capacitance of a capacitor suitable for realizing high resolution and high definition, and improving the reliability and initial performance of the device. is to do In the present invention, at least one of the first interlayer insulating layer and the second interlayer insulating layer is configured as a multi-layer in order to improve the channel hydrogenation rate and strengthen the film quality.

Description

Organic light emitting display device and method of manufacturing the same {Organic Light Emitting Display Device and Method of Manufacturing the same}

The present invention relates to an organic light emitting display device and a manufacturing method thereof.

An organic light emitting device used in an organic light emitting display device is a self light emitting device in which a light emitting layer is formed between two electrodes. In the organic light emitting device, electrons and holes are injected into the light emitting layer from an electron injection electrode (cathode) and a hole injection electrode (anode), respectively, and excitons, in which the injected electrons and holes are combined, enter an excited state. It is an element that emits light when it falls from the ground state.

An organic light emitting display device forms a display panel using an organic light emitting element. The display panel may be implemented in a top-emission type, a bottom-emission type, and a dual-emission type according to the direction in which light is emitted, and a passive matrix type ( It can be implemented in passive matrix) and active matrix type.

Organic light emitting display devices have high luminance and high color gamut and are used in various sizes and devices. In addition, recently, research is being conducted to implement the organic light emitting display device in various forms such as imparting ductility to have a curved surface or artificially or mechanically bending the organic light emitting display device.

When the organic light emitting display device aims to realize high resolution and high definition, design margins of subpixels must be considered, and a layout must be designed in consideration of the space occupied by the compensation circuit added inside the subpixels.

However, when a display panel is manufactured according to a manufacturing method proposed in the related art, there is a problem in that the reliability of the device is lowered and the threshold voltage is shifted according to the structural characteristics of the thin film, making it difficult to realize high resolution and high definition.

In order to solve the problems of the background art described above, the present invention improves the threshold voltage characteristics and HCS reliability of the driving transistor by improving the channel hydrogenation rate and strengthening the film quality, and preparing the capacitance of the capacitor suitable for high resolution and high definition implementation. and to improve the reliability and initial performance of the device.

As a means for solving the above problems, the present invention provides an organic light emitting display device including a semiconductor layer, a gate insulating layer, a gate metal layer, a first interlayer insulating layer, an intermediate metal layer, a second interlayer insulating layer, and a source-drain metal layer. A semiconductor layer is located on the first substrate. A gate insulating layer is located on the semiconductor layer. A gate metal layer is located on the gate insulating layer. A first interlayer insulating layer is located on the gate metal layer. An intermediate metal layer is located on the first interlayer insulating layer. The second interlayer insulating layer is located on the intermediate metal layer. The source-drain metal layer is located on the second interlayer insulating layer. At least one of the first interlayer insulating layer and the second interlayer insulating layer is composed of a multi layer.

The first and second interlayer insulating layers may include a silicon oxide layer (SiO2) or a silicon nitride layer (SiNx).

The second interlayer insulating layer is composed of at least a double layer, and an upper layer and a lower layer of the double layer may be composed of different materials.

A lower layer of the second interlayer insulating layer may be selected as a silicon oxide film (SiO2), and an upper layer of the second interlayer insulating layer may be selected as a silicon nitride film (SiNx).

The first interlayer insulating layer is composed of at least a double layer, and an upper layer and a lower layer of the double layer may be composed of different materials.

A lower layer of the first interlayer insulating layer may be selected as a silicon oxide film (SiO2), and an upper layer of the first interlayer insulating layer may be selected as a silicon nitride film (SiNx).

A thickness ratio of the lower layer and the upper layer of the first interlayer insulating layer may be 30%:70% to 50%:50%.

A portion of the gate metal layer, a portion of the intermediate metal layer, and a portion of the source-drain metal layer may form a multilayer capacitor.

It further includes a passivation layer positioned on the source-drain metal layer, a planarization layer positioned on the passivation layer, a lower electrode positioned on the planarization layer, an organic emission layer positioned on the lower electrode, and an upper electrode positioned on the organic emission layer. And, the lower electrode may be electrically connected to a portion of the source-drain metal layer on the multi-layer capacitor including a portion of the gate metal layer, a portion of the middle metal layer, and a portion of the source-drain metal layer.

The present invention has an effect of improving product reliability by improving threshold voltage characteristics and HCS (Hot Carrier Stress) reliability of a driving transistor by improving a channel hydrogenation rate and strengthening a film quality. In addition, the present invention has an effect of improving reliability and initial performance of a device when implementing high resolution and high definition. In addition, the present invention has an effect of providing a sub-pixel design method capable of converging a sub-pixel design margin and a space occupied by a compensation circuit when high resolution and high-definition implementation are aimed at. In addition, the present invention has the effect of preparing the capacitance of the capacitor in a form suitable for high resolution and high definition implementation.

1 is a schematic block diagram of an organic light emitting display device;
2 is a schematic circuit configuration diagram of a sub-pixel.
3 is an exemplary circuit configuration diagram of a sub-pixel embodying the compensation circuit of FIG. 2;
4 is an exemplary view of a driving waveform of a sub-pixel of FIG. 3;
5 is a cross-sectional view of a conventionally proposed sub-pixel.
6 is a cross-sectional view of a sub-pixel according to a first embodiment of the present invention.
7 is a cross-sectional view of a sub-pixel according to a second embodiment of the present invention.

Hereinafter, specific details for the implementation of the present invention will be described with reference to the accompanying drawings.

1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a schematic circuit configuration diagram of a subpixel, and FIG. 3 is an exemplary circuit configuration diagram of a subpixel embodying the compensation circuit of FIG. 2. FIG. 4 is an exemplary view of driving waveforms of the sub-pixels of FIG. 3 .

As shown in FIG. 1 , the organic light emitting display device includes an image processor 110 , a timing controller 120 , a data driver 130 , a gate driver 140 and a display panel 150 .

The image processor 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processor 110 may output one or more of a vertical sync signal, a horizontal sync signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description. The image processing unit 110 is formed in the form of an integrated circuit (IC) on a system circuit board.

The timing controller 120 receives a data signal DATA along with a data enable signal DE or driving signals including a vertical synchronization signal, a horizontal synchronization signal, and a clock signal from the image processing unit 110 .

The timing controller 120 generates a gate timing control signal (GDC) for controlling the operation timing of the gate driver 140 and a data timing control signal (DDC) for controlling the operation timing of the data driver 130 based on the driving signal. outputs The timing controller 120 is formed in the form of an IC on a control circuit board.

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120, converts it into a gamma reference voltage, and outputs the result. . The data driver 130 outputs the data signal DATA through the data lines DL1 to DLn. The data driver 130 is formed in the form of an IC on a data circuit board.

The gate driver 140 outputs a gate signal while shifting the level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120 . The gate driver 140 outputs a gate signal through the gate lines GL1 to GLm. The gate driver 140 is formed in the form of an IC on a gate circuit board or formed in a gate-in-panel method on the display panel 150 . A part formed in the gate-in-panel method in the gate driver 140 is a shift register or the like.

The display panel 150 displays an image in response to the data signal DATA and the gate signal supplied from the data driver 130 and the gate driver 140 . The display panel 150 includes subpixels SP that display an image.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel, or include a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The sub-pixels SP may have different areas of one or more light emitting regions (regions where light is emitted) or circuit regions (regions where transistors, etc. are formed) according to light emitting characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The switching transistor SW performs a switching operation to store the data signal supplied through the first data line DL1 as a data voltage in the capacitor Cst in response to the gate signal supplied through the first gate line GL1. The driving transistor DR operates to allow a driving current to flow between the high potential power line EVDD and the low potential power line EVSS according to the data voltage stored in the capacitor Cst. The compensation circuit CC is a circuit for compensating for the threshold voltage of the driving transistor DR.

The compensation circuit (CC) is composed of one or more thin film transistors and capacitors. The configuration of the compensation circuit (CC) is very diverse according to the compensation method. The transistor may be implemented based on low-temperature polysilicon (LTPS), amorphous silicon (a-Si), oxide, or organic.

As shown in FIG. 3 , when the compensation circuit CC is included, the sub-pixel includes a compensation capacitor C, a sensing transistor ST, a 1b gate line GL1b controlling the sensing transistor ST, and a sensing transistor. An initialization line (VINI) that senses the node B (B) through ST, or supplies an initialization voltage (Vini), an emission control transistor (ET), and a 1c gate line (GL1c) that controls the emission control transistor (ET). This is included. In FIG. 3, "cold" means a parasitic capacitor of an organic light emitting diode.

The switching transistor SW, the driving transistor DR, the sensing transistor ST, and the emission control transistor ET included in the sub-pixel are based on N-type transistors (NMOS TFTs). However, the transistors included in the sub-pixel are not limited thereto and may be implemented as P-type transistors (PMOS TFTs).

3 and 4, when the compensation circuit (CC) is included, the sub-pixel operates in the order of an initialization period (ti), a sampling period (ts), a programming period (tw), and a light emission period (tem). do. A brief description of the period for driving the sub-pixels is as follows.

During the initialization period ti, a predetermined reference voltage Vref is supplied to the first data line DL1. During the initialization period ti, the voltage of the A-th node A is initialized to the reference voltage Vref, and the voltage of the B-th node B is initialized to a predetermined initialization voltage Vini.

During the sampling period ts, the voltage Vgs between the gate and source of the driving transistor DR is sampled as the threshold voltage Vth of the driving transistor DR according to the source-follower method, and the sampled threshold voltage ( Vth) is stored in the capacitor (Cst). During the sampling period ts, the voltage of the A-th node A becomes the reference voltage Vref, and the voltage of the B-th node B becomes Vref-Vth.

During the programming period tw, the data voltage Vdata is supplied through the first data line DL1, and the threshold voltage is compensated for the data voltage Vdata-Vref + Vth-C' *(Vdata-Vref )) is programmed. Here, C' is the voltage charged in the compensation capacitor (C) and has a value defined as Cst/(Cst+C). When the potential of the A-th node (A) changes according to the data voltage (Vdata) during the programming period (tw), the capacitors (Cst, C) divide the voltage and reflect the change to the B-th node (B).

During the light emission period tem, the organic light emitting diode OLED emits light in response to a driving current generated based on the data voltage stored in the capacitor Cst. Meanwhile, although the initialization period ti, the sampling period ts, and the programming period tw are made within one horizontal time period (1H) as an example, the present invention is not limited thereto.

Hereinafter, problems that may occur when manufacturing a high-resolution and high-definition organic light emitting display based on a sub-pixel to which a compensation circuit of a 4T (transistor) 2C (capacitor) structure is added will be considered. Meanwhile, hereinafter, the driving transistor, the capacitor, and the organic light emitting diode will be described based on cross-sections, and the remaining circuits will be omitted. In addition, the transistor based on low-temperature polysilicon (LTPS) will be described as an example.

<Conventional structure>

5 is a cross-sectional view of a conventionally proposed sub-pixel.

As shown in FIG. 5 , a buffer layer BUF is formed on the first substrate SUB. A semiconductor layer ACT having an impurity region LDD (or lightly doped drain; LDD) is formed on the buffer layer BUF. A gate insulating layer GI is formed on the semiconductor layer ACT. Gate metal layers GAT1a and GAT1b are formed on the gate insulating layer GI.

An interlayer insulating layer ILD is formed on the gate metal layers GAT1a and GAT1b. Source-drain metal layers SDa to SDc are formed on the interlayer insulating layer ILD. A passivation layer PAS is formed on the source-drain metal layers SDa to SDc. A planarization layer OC is formed on the passivation layer PAS.

A lower electrode E1 is formed on the planarization layer OC. A bank layer BNK having an open area is formed on the lower electrode E1. A spacer SPC is formed on the non-opening region of the bank layer BNK. An organic emission layer OL is formed on the opening area of the bank layer BNK. An upper electrode E2 is formed on the organic emission layer OL.

The driving transistor DR includes a semiconductor layer ACT disposed on the first substrate SUB, an A-th gate metal layer GAT1a, and A-th and B-th source-drain metal layers SDa and SDb. The capacitor Cst includes a B-th gate metal layer GAT1b and a C-th source-drain metal layer SDc. The organic light emitting diode (OLED) includes a lower electrode E1, an organic light emitting layer OL, and an upper electrode E2.

Organic light emitting display devices have high luminance and high color gamut and are used in various sizes and devices. In addition, recently, research is being conducted to implement the organic light emitting display device in various forms such as imparting ductility to have a curved surface or artificially or mechanically bending the organic light emitting display device.

When the organic light emitting display device aims to realize high resolution and high definition, design margins of subpixels must be considered, and a layout must be designed in consideration of the space occupied by the compensation circuit added inside the subpixels.

More specifically, when high-resolution and high-definition implementation is aimed at, the designable area of sub-pixels decreases, but the complexity of electrodes or signal lines constituting the circuit increases due to the addition of a compensation circuit. However, the manufacturing method proposed in the prior art still uses a thin film laminated structure, which is difficult to achieve.

For example, when manufacturing a display panel according to a manufacturing method proposed in the related art, capacitance of the capacitor Cst cannot be provided in a form suitable for realizing high resolution and high definition within a limited area. The reason is that it is defined as C=ε*A/d (C: capacitor capacitance, ε: permittivity, A: area, d: distance). In addition, it is difficult to implement high resolution and high definition when following the conventionally proposed manufacturing method.

Hereinafter, the present invention derives embodiments capable of developing a high-resolution and high-definition display panel in addition to solving the problems of the conventionally proposed manufacturing method, which will be described as follows.

<First Embodiment>

6 is a cross-sectional view of a sub-pixel according to a first embodiment of the present invention.

As shown in FIG. 6 , an adhesive layer ADH is formed on the first substrate SUB. A multi-buffer layer MBUF is formed on the adhesive layer ADH. A buffer layer BUF is formed on the multi-buffer layer MBUF. A semiconductor layer ACT having an impurity region LDD (or lightly doped drain; LDD) is formed on the buffer layer BUF.

A gate insulating layer GI is formed on the semiconductor layer ACT. Gate metal layers GAT1a and GAT1b are formed on the gate insulating layer GI. The gate metal layers GAT1a and GAT1b are made of molybdenum (Mo), aluminum (Al), indium tin oxide (ITO), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one or an alloy thereof selected from the group consisting of, and may be made of a single layer or multiple layers.

A first interlayer insulating layer ILD1 is formed on the gate metal layers GAT1a and GAT1b. The first interlayer insulating layer ILD1 may be formed of a single layer or a multi layer. Intermediate metal layers TM2a and TM2b are formed on the first interlayer insulating layer ILD1. The intermediate metal layers TM2a and TM2b are made of molybdenum (Mo), aluminum (Al), indium tin oxide (ITO), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one or an alloy thereof selected from the group consisting of, and may be made of a single layer or multiple layers.

A second interlayer insulating layer ILD2 is positioned on the intermediate metal layers TM2a and TM2b, and the second interlayer insulating layer ILD2 may be formed of a single layer or a multi layer. In the first embodiment, the second interlayer insulating layer ILD2 is formed as a double layer including a second lower interlayer insulating layer ILD2a and a second upper interlayer insulating layer ILD2b. Source-drain metal layers SDa to SDc are formed on the second lower and second upper interlayer insulating layers ILD2a and ILD2b. A passivation layer PAS is formed on the source-drain metal layers SDa to SDc. A planarization layer OC is formed on the passivation layer PAS.

A lower electrode E1 is formed on the planarization layer OC. The lower electrode E1 is electrically connected to the Ath source-drain metal layer SDa. A bank layer BNK having an open area is formed on the lower electrode E1. A spacer SPC is formed on the non-opening region of the bank layer BNK. An organic emission layer OL is formed on the opening area of the bank layer BNK. An upper electrode E2 is formed on the organic emission layer OL.

The driving transistor DR includes a semiconductor layer ACT, a 1A gate metal layer GAT1a, and A and B source-drain metal layers SDa and SDb disposed on the first substrate SUB. The capacitor Cst includes a B-th gate metal layer GAT1b, a B-th intermediate metal layer TM2b, and an A-th source-drain metal layer SDa. The organic light emitting diode (OLED) includes a lower electrode E1, an organic light emitting layer OL, and an upper electrode E2.

In the first embodiment, intermediate metal layers TM2a and TM2b are further added on the first interlayer insulating layer ILD1. The intermediate metal layers TM2a and TM2b are formed of the same material as the gate metal layer or the source-drain metal layer. The intermediate metal layers TM2a and TM2b provide an advantage of increasing the capacitance of the capacitor Cst within a limited area, and double (or double gate electrodes) the gate electrode of the driving transistor to improve driving characteristics (current driving ability). improvement) has the advantage of being able to improve.

In the first embodiment, a silicon oxide film (SiO2) is used as the gate insulating layer (GI), a silicon oxide film (SiO2) is used as the first interlayer insulating layer (ILD1), and the second lower and second upper interlayer insulating layers ( For ILD2a and ILD2b), a silicon oxide film (SiO2) and a silicon nitride film (SiNx) are used.

As a result of evaluating the first embodiment, with the addition of the intermediate metal layers TM2a and TM2b, the capacitance of the capacitor Cst and the compensation capacitor C is prepared in a form suitable for high resolution and high definition implementation, and at the time of subpixel layout It was found that the problem of increasing complexity can be solved.

More specifically, in the first embodiment, the capacitor Cst is formed by further using an intermediate metal layer or a source-drain metal layer positioned on the gate metal layer. That is, since the first embodiment uses a thin film stack structure that is higher than that of the conventional structure, the design margin rate of the subpixel is increased. In addition, in the first embodiment, a dry etching process is performed on a minimum number of electrodes or lines in order to prevent a short circuit that may be caused by a structural problem between the gate metal layer and the intermediate metal layer in the manufacturing process.

<Second Embodiment>

7 is a cross-sectional view of a sub-pixel according to a second embodiment of the present invention.

As shown in FIG. 7 , an adhesive layer ADH is formed on the first substrate SUB. A multi-buffer layer MBUF is formed on the adhesive layer ADH. A buffer layer BUF is formed on the multi-buffer layer MBUF. A semiconductor layer ACT having an impurity region LDD (or lightly doped drain; LDD) is formed on the buffer layer BUF.

A gate insulating layer GI is formed on the semiconductor layer ACT. Gate metal layers GAT1a and GAT1b are formed on the gate insulating layer GI. The gate metal layers GAT1a and GAT1b are made of molybdenum (Mo), aluminum (Al), indium tin oxide (ITO), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one or an alloy thereof selected from the group consisting of, and may be made of a single layer or multiple layers.

The first interlayer insulating layer ILD1 on the gate metal layers GAT1a and GAT1b may be formed as a single layer or a multi-layer. In the second embodiment, the first interlayer insulating layer ILD1 is formed as a double layer including a first lower interlayer insulating layer ILD1a and a first upper interlayer insulating layer ILD1b. Intermediate metal layers TM2a and TM2b are formed on the first upper interlayer insulating layer ILD1b. The intermediate metal layers TM2a and TM2b are made of molybdenum (Mo), aluminum (Al), indium tin oxide (ITO), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu). It may be one or an alloy thereof selected from the group consisting of, and may be made of a single layer or multiple layers.

A second interlayer insulating layer ILD2 is positioned on the intermediate metal layers TM2a and TM2b, and the second interlayer insulating layer ILD2 may be formed of a single layer or a multi layer. In the second embodiment, the second interlayer insulating layer ILD2 is formed as a double layer including a second lower interlayer insulating layer ILD2a and a second upper interlayer insulating layer ILD2b. Source-drain metal layers SDa to SDc are formed on the second upper interlayer insulating layer ILD2b. A passivation layer PAS is formed on the source-drain metal layers SDa to SDc. A planarization layer OC is formed on the passivation layer PAS.

A lower electrode E1 is formed on the planarization layer OC. The lower electrode E1 is electrically connected to the Ath source-drain metal layer SDa. The lower electrode E1 is electrically connected to the Ath source-drain metal layer SDa in the region where the capacitor Cst is located.

A bank layer BNK having an open area is formed on the lower electrode E1. A spacer SPC is formed on the non-opening region of the bank layer BNK. An organic emission layer OL is formed on the opening area of the bank layer BNK. An upper electrode E2 is formed on the organic emission layer OL.

The driving transistor DR includes a semiconductor layer ACT, a 1A gate metal layer GAT1a, and A and B source-drain metal layers SDa and SDb disposed on the first substrate SUB. The capacitor Cst includes a B-th gate metal layer GAT1b, a B-th intermediate metal layer TM2b, and an A-th source-drain metal layer SDa. The organic light emitting diode (OLED) includes a lower electrode E1, an organic light emitting layer OL, and an upper electrode E2.

In the second embodiment, intermediate metal layers TM2a and TM2b are further added on the first lower interlayer insulating layer ILD1b. The intermediate metal layers TM2a and TM2b are formed of the same material as the gate metal layer or the source-drain metal layer.

The intermediate metal layers TM2a and TM2b provide an advantage of increasing the capacitance of the capacitor Cst within a limited area (increase in capacitance and decrease in area due to the multi-layer capacitor structure), and double the gate electrode of the driving transistor ( or 2 gate electrodes), there is an advantage in that driving characteristics (improvement of current driving ability) can be improved.

Meanwhile, in the first embodiment, a silicon oxide film (SiO2) is used as the gate insulating layer (GI), a silicon oxide film (SiNx) is used as the first interlayer insulating layer (ILD1), and the second lower and second upper interlayer insulating layers are used. A silicon oxide film (SiO2) and a silicon nitride film (SiNx) are used as the layer (ILD2).

Unlike this, in the second embodiment, the first interlayer insulating layer ILD1 uses a double layer of silicon nitride film (SiNx) (upper layer)/silicon oxide film (SiO2) (lower layer) rather than a single layer of silicon nitride film (SiNx).

By this structure, in the second embodiment, hydrogen is smoothly supplied from the silicon nitride film (SiNx) constituting the first interlayer insulating layer (ILD1), and the moving distance of hydrogen is increased due to the intermediate metal layers (TM2a, TM2b). appeared to be resolved. As a result, in the second embodiment, the hydrogen supply was strengthened with the double-layered first interlayer insulating layer structure, and through this, the reliability of the device could be further improved.

In addition, as the second embodiment uses a double-layered first interlayer insulating layer structure, compared to the first embodiment, the gate insulating layer (GI) by dry etch plasma and silane gas (Gas) could alleviate the damage problem.

As a result, compared to the first embodiment, the second embodiment can further improve the reliability of the device when manufacturing a display panel capable of realizing high resolution and high definition (relieve the problem of lowering current mobility after a stress application test). appear. In addition, the second embodiment was found to be able to more reliably prevent the problem of the threshold voltage of the driving transistor moving in comparison to the first embodiment (prevention of the problem of the threshold voltage moving in the negative direction after the high-temperature reliability test).

Meanwhile, in the first and second embodiments of the present invention, as an example, a silicon nitride film (SiNx) and a silicon oxide film (SiO2) are selected as materials for an interlayer insulating layer. However, this is just one example and the interlayer insulating layer may be selected from a material containing silicon such as silicon carbide (SiC).

Table 1 shows the materials used for the main structural layers of the first and second embodiments in a table. Experimental conditions for obtaining the evaluation results of the examples are shown in Table 1 below. In Table 1 below, the unit of thickness is Å (Angstrom).

Example 1 Example 2 2nd Interlayer Insulation Layer
(thickness) SiNx/SiO2
(2300/2700Å) SiNx/SiO2
(4000/2000Å) middle metal layer
(thickness) Mo
(2500Å) Mo
(2000Å) First interlayer insulating layer
(thickness) SiNx
(1300Å) SiNx/SiO2
(750/500Å) gate metal layer
(thickness) Mo
(2500Å) Mo
(2500Å) gate insulation layer
(thickness) SiO2
(1100Å) SiO2
(1300Å)

As a result of various evaluations based on the second embodiment of the present invention, the thicknesses of the silicon oxide (SiO2) and silicon nitride (SiNx) used in the first lower and first upper interlayer insulating layers (ILD1a, ILD1b) are traded. It was found that there is a trade off relationship.

For example, as the thickness of the silicon nitride film (SiNx) increases, the reliability of the device improves and the threshold voltage of the driving transistor shifts in a positive direction (Vth + Shift) (threshold voltage characteristic improvement). However, on the contrary, as the thickness of the silicon nitride film (SiNx) increases, the BTS (Bias Temperature Stress) characteristic that influences high-temperature reliability deteriorates.

In contrast, as the thickness of the silicon oxide film (SiO2) increases, the initial performance of the device improves, but the reliability of the device and the threshold voltage characteristic (the threshold voltage moves in a negative direction) of the driving transistor deteriorate.

When the thickness of the silicon oxide film (SiO2) constituting the first lower interlayer insulating layer (ILD1a) is formed within a range of 10% to 90%, the reliability of the device is improved compared to the first embodiment. However, as described above, the thicknesses of the silicon oxide film (SiO2) and the silicon nitride film (SiNx) used in the first lower and first upper interlayer insulating layers ILD1a and ILD1b have a trade-off relationship, and the range for converging them all is It is shown in Table 2 below.

Between the first upper floors
Insulation layer (SiNx) Between the first lower floors
Insulation layer (SiO2) Reliability and initial performance evaluation results 70% 30% good 60% 40% very good 50% 50% good Related to reliability improvement Relationship with Initial Performance Improvement

As can be seen from Table 2, the thickness ratio of the first lower interlayer insulating layer (SiO2) and the first upper interlayer insulating layer (SiNx) is preferably set to 30%: 70% to 50%: 50%. In addition, when the thickness ratio of the first lower interlayer insulating layer (SiO2) and the first upper interlayer insulating layer (SiNx) is out of the above range, reliability and initial performance evaluation results are poor.

Table 2 shows results obtained by repeating experiments to optimize the thicknesses of the silicon oxide film (SiO2) and the silicon nitride film (SiNx) used in the first lower and first upper interlayer insulating layers ILD1a and ILD1b. That is, the second embodiment obtained a result of improving the reliability and initial performance of the device as well as improving the channel hydrogenation rate and film quality by using a total of four layers of interlayer insulating layer structure.

Table 2 shows experimental results of a display panel to which a compensation circuit of a 4T2C structure based on a low-temperature polysilicon (LTPS) transistor is added. In the second embodiment, the above evaluation result was obtained based on a low-temperature polysilicon (LTPS) transistor, but this result is not an indication based on an amorphous silicon (a-Si), oxide, or organic transistor. It could also be applied to panels.

On the other hand, the structure as in the second embodiment has conditions for improving the reliability and initial performance of the device, so that when forming the gate electrode of the transistor, the single gate electrode structure (the gate electrode is divided into two parts on the gate insulating layer) It is expected to be able to take a structure consisting of one rather than a structure). According to this effect, the area occupied by the transistor can be minimized even when implementing high resolution and high definition.

As described above, the present invention has an effect of improving product reliability by improving threshold voltage characteristics and HCS (Hot Carrier Stress) reliability of a driving transistor by improving a channel hydrogenation rate and strengthening a film quality. In addition, the present invention has an effect of improving reliability and initial performance of a device when implementing high resolution and high definition. In addition, the present invention has an effect of providing a sub-pixel design method capable of converging a sub-pixel design margin and a space occupied by a compensation circuit when high resolution and high-definition implementation are aimed at. In addition, the present invention has the effect of preparing the capacitance of the capacitor in a form suitable for high resolution and high definition implementation.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the above-described technical configuration of the present invention can be changed into other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that it can be implemented. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driver 140: gate driver
150: display panel GI: gate insulating layer
ILD1: first interlayer insulating layer ILD2: second interlayer insulating layer
GAT1a, GAT1b: Gate metal layer TM2a, TM2b: Intermediate metal layer
SDa to SDc: source drain metal layer

Claims (9)

a switching transistor having a gate electrode connected to a first gate line, a first electrode connected to a first data line, and a second electrode connected to the gate electrode of the driving transistor;
a sensing transistor having a gate electrode connected to a 1b gate line, a first electrode connected to an initialization line, and a second electrode connected to the second electrode of the driving transistor;
a light emission control transistor having a gate electrode connected to a 1c gate line, a first electrode connected to a high potential power supply line, and a second electrode connected to the first electrode of the driving transistor;
a capacitor having a first electrode connected to the gate electrode of the driving transistor and a second electrode connected to the second electrode of the driving transistor;
a compensation capacitor having a first electrode connected to the high potential power line and a second electrode connected to the second electrode of the driving transistor; and
An organic light emitting diode having an anode electrode connected to the second electrode of the driving transistor and a cathode electrode connected to a low potential power line;
The driving transistor is
A semiconductor layer positioned on the first substrate;
A gate insulating layer positioned on the semiconductor layer;
A gate metal layer positioned on the gate insulating layer;
A first interlayer insulating layer positioned on the gate metal layer;
An intermediate metal layer positioned on the first interlayer insulating layer;
A second interlayer insulating layer positioned on the intermediate metal layer;
A source-drain metal layer positioned on the second interlayer insulating layer;
At least one of the first interlayer insulating layer and the second interlayer insulating layer is composed of multiple layers,
The organic light emitting display device wherein the thickness ratio of the lower layer and the upper layer of the first interlayer insulating layer is 30%: 70% to 50%: 50%. According to claim 1,
The first and second interlayer insulating layers are
An organic light emitting display device comprising a silicon oxide layer (SiO2) or a silicon nitride layer (SiNx). According to claim 1,
The second interlayer insulating layer is composed of at least a double layer,
An organic light emitting display device wherein the upper and lower layers of the double layer are composed of different materials. According to claim 3,
The lower layer of the second interlayer insulating layer is selected as a silicon oxide film (SiO2),
The organic light emitting display device of claim 1 , wherein an upper layer of the second interlayer insulating layer is selected from silicon nitride (SiNx). According to claim 1,
The first interlayer insulating layer is composed of at least a double layer,
An organic light emitting display device wherein the upper and lower layers of the double layer are composed of different materials. According to claim 5,
The lower layer of the first interlayer insulating layer is selected as a silicon oxide film (SiO2),
The organic light emitting display device of claim 1 , wherein an upper layer of the first interlayer insulating layer is selected from silicon nitride (SiNx). delete According to claim 1,
A portion of the gate metal layer, a portion of the intermediate metal layer, and a portion of the source-drain metal layer form a multilayer capacitor. According to claim 1,
A passivation layer positioned on the source-drain metal layer;
A planarization layer positioned on the protective film;
a lower electrode positioned on the planarization layer;
an organic light emitting layer positioned on the lower electrode;
Further comprising an upper electrode positioned on the organic light emitting layer,
The lower electrode is electrically connected to a portion of the source-drain metal layer on a multi-layer capacitor including a portion of the gate metal layer, a portion of the intermediate metal layer, and a portion of the source-drain metal layer.

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