KR102542998B1 - Three Dimensional Stacked Semiconductor Memory Device - Google Patents

Abstract

A semiconductor memory device and a neuromorphic device having variable resistance layers are described. The semiconductor memory device or the neuromorphic device may include row lines extending in parallel in a first horizontal direction; column line stacks extending in parallel in a second horizontal direction orthogonal to the first horizontal direction, the column line stacks including a plurality of column lines extending in parallel in a vertical direction; and cell pillars vertically penetrating the column lines of the column line stacks. First ends of the cell pillars may be electrically connected to the row lines. Second ends of the cell pillars may be floating.

Description

Three Dimensional Stacked Semiconductor Memory Device

The present invention relates to a semiconductor memory device, and more particularly to a three-dimensional stacked semiconductor memory device.

As next-generation semiconductor memory technology, three-dimensional stacked semiconductor memory technology and cross-point type variable resistive memory technology are attracting attention. In addition, neuromorphic technology that mimics the human brain is also attracting attention so that it can be used in artificial intelligence technology and the like. A neuromorphic device according to the neuromorphic technology includes a plurality of pre-synaptic neurons, a plurality of post-synaptic neurons, and a plurality of synapses. The neuromorphic device may have various resistance levels according to learned states, and may output various voltages or currents according to the resistance levels.

An object to be solved by the present invention is to provide a semiconductor memory device and a neuromorphic device capable of implementing multiple resistance levels by having multiple variable resistance layers.

An object to be solved by the present invention is to provide a cross-point type semiconductor memory device and a neuromorphic device.

An object to be solved by the present invention is to provide a three-dimensionally stacked semiconductor memory device and a neuromorphic device.

An object to be solved by the present invention is to provide a cross-point type three-dimensionally stacked semiconductor memory device and a neuromorphic device having multiple variable resistance layers.

Various problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor memory device or neuromorphic device according to an embodiment of the present invention includes row lines extending in parallel in a first horizontal direction; column line stacks extending in parallel in a second horizontal direction orthogonal to the first horizontal direction, the column line stacks including a plurality of column lines extending in parallel in a vertical direction; and cell pillars vertically penetrating the column lines of the column line stacks. First ends of the cell pillars may be electrically connected to the row lines. Second ends of the cell pillars may be floating.

The second ends of the cell pillars may protrude from the lowermost column lines of the column line stacks.

Each of the cell pillars includes a central core; and a memory layer surrounding the core.

The core may include one or more of a metal, a metal compound, a metal silicide, or combinations thereof.

The core may include a metal such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al); metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The row lines and the core may be directly connected.

The memory layer may include at least three variable resistance layers. The three-layer variable resistance layers may have different band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, phase change threshold voltages, or atomic migration threshold voltages.

The at least three variable resistance layers may each include one of various metal oxides including oxygen vacancy or high dielectric constant oxides such as hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide. can

The column lines may be made of a metal such as tungsten (W), ruthenium (Ru), or iridium (Ir); other metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The row lines may be buried in the substrate.

A semiconductor memory device or neuromorphic device according to an embodiment of the present invention includes a word line extending in a first horizontal direction; a bit line stack extending in a second horizontal direction orthogonal to the first horizontal direction; and a cell pillar extending from the word line to vertically pass through the bit line stack. A first end of the cell pillar may be electrically connected to the word line. The second end of the cell pillar may be floating.

The bit line stack may include a plurality of bit lines stacked in a vertical direction and extending in parallel to the second horizontal direction.

The bit lines may be made of a metal such as tungsten (W), ruthenium (Ru), or iridium (Ir); other metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The second ends may protrude from lowermost ends of the column line stacks.

The cell pillar may include a central core and memory layers surrounding the core.

The memory layers include at least three layers of variable resistance layers, and the three layers of variable resistance layers include band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, phase change threshold voltages, or atomic movement thresholds. One or more of the voltages may be different.

The at least three variable resistance layers may each include one of various metal oxides including oxygen vacancy or high dielectric constant oxides such as hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide. can

The word line may include a metal such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al); metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

A semiconductor memory device according to an embodiment of the present invention includes a substrate; a lower insulating layer formed on the substrate; bit lines and interlayer insulating layers alternately stacked on the lower insulating layer, the bit lines extending in parallel in a first horizontal direction; an upper insulating layer on the bit lines; a word line extending in a second horizontal direction perpendicular to the first horizontal direction on the upper insulating layer; and a vertical pillar vertically penetrating the upper insulating layer, the interlayer insulating layers, and the bit lines from the word line. The vertical pillar may include a conductive core and at least three variable resistance layers surrounding the core. An upper end of the vertical pillar may be directly connected to the word line. A lower end of the vertical pillar may protrude into the lower insulating layer so as not to contact the substrate.

The at least three variable resistance layers are different from each other at least one of band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, magnetization threshold voltages, phase change threshold voltages, or atomic movement threshold voltages. , hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide.

Details of other embodiments are included in the detailed description and drawings.

A semiconductor memory device and a neuromorphic device according to the technical concept of the present invention may have a high degree of integration.

A semiconductor memory device and a neuromorphic device according to the technical concept of the present invention may have high operating speed and low power consumption.

Other effects by various embodiments of the present invention that are not mentioned will be mentioned within the text.

1 is a block diagram conceptually illustrating a cell array of a semiconductor memory device according to an exemplary embodiment of the present invention.
2 is a three-dimensional perspective view schematically showing a cell array of the semiconductor memory device according to an exemplary embodiment of the present invention.
FIG. 3A is a schematic longitudinal sectional view of the semiconductor memory device taken along line II' of FIG. 2 and FIG. 3B is a schematic longitudinal sectional view of the semiconductor memory device taken along line II-II' of FIG. 2 .
FIG. 4A is an enlarged view of area 'A' of FIG. 3, and FIG. 4B is a cross-sectional view taken along line III-III'.
5A and 5B are diagrams explaining a programming operation principle of the semiconductor memory device.
6 is a three-dimensional perspective view schematically showing a cell array of the semiconductor memory device according to an exemplary embodiment of the present invention.
FIG. 7A is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line IV-IV' of FIG. 6, and FIG. 7B is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line VV' of FIG.
FIG. 8A is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line IV-IV' of FIG. 6, and FIG. 8B is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line VV' of FIG.
9 is a block diagram conceptually illustrating a cell array of a semiconductor memory device according to an exemplary embodiment of the present invention.
10A and 10B are three-dimensional perspective views schematically showing cell arrays of semiconductor memory devices according to example embodiments.
11 is a conceptual longitudinal cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.
12 is a diagram conceptually illustrating a pattern recognition system according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms, but only the present embodiments make the disclosure of the present invention complete, and the common knowledge in the art to which the present invention belongs It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

Like reference numbers designate like elements throughout the specification. Accordingly, the same reference numerals or similar reference numerals may be described with reference to other drawings, even if not mentioned or described in the drawings. Also, even if reference numerals are not indicated, description may be made with reference to other drawings.

1 is a block diagram conceptually illustrating a cell array 100 of a semiconductor memory device according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 , the cell array 100A of the semiconductor memory device includes a row driver RD, a column driver CD, and a plurality of row lines R1 extending in parallel in a row direction from the row driver RD. -Rn), a plurality of column lines (C1-Cm) extending in parallel in a column direction from the column driver (CD), and between the row lines (R1-Rn) and the column lines (C1-Cm). It may include a plurality of memory cells MC disposed in crossing areas of . The plurality of row lines R1 to Rn may correspond to word lines, and the plurality of column lines C1 to Cm may correspond to bit lines. The plurality of memory cells MC may include variable resistance layers. First electrodes of the plurality of memory cells MC may be electrically connected to the plurality of row lines R1-Rn, respectively, and second electrodes of the plurality of memory cells MC may be electrically connected to the plurality of column lines. It may be electrically connected to the lines C1-Cm, respectively.

The cell array 100 may have a cross-point type connection structure. The semiconductor memory device may be a variable resistive memory device such as a resistive random access memory (ReRAM), a phase changeable random access memory (PCRAM), or a conductive bridge random access memory (CBRAM). . In the technical concept of the present invention, the row lines R1 to Rn may correspond to word lines, and the column lines C1 to Cm may correspond to bit lines.

In another embodiment, the cell array 100 of the semiconductor memory device may be a synaptic array of a neuromorphic device. For example, the row driver RD may correspond to a pre-synaptic neuron of the neuromorphic device, and the column driver RD may correspond to a post-synaptic neuron of the neuromorphic device; The row lines R1-Rn may correspond to pre-synaptic lines of the neuromorphic device, and the column lines C1-Cm may correspond to post-synaptic lines of the neuromorphic device. and the memory cells MC may correspond to synapses of a neuromorphic device.

2 is a three-dimensional perspective view schematically showing a cell array 100A of the semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the cell array 100A of the semiconductor memory device may include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. . The word lines 30 may extend parallel to each other in the first direction D1. The first direction D1 may be a horizontal row direction. The bit lines 40 may include a plurality of bit line stacks 40S extending in the second direction D2. That is, each of the bit line stacks 40S may have a plurality of bit lines 40 . The second direction D2 may be a horizontal column direction. The plurality of cell pillars P may extend in the third direction D3 to pass through the bit lines 40 . The third direction D3 may be a vertical direction. That is, the plurality of cell pillars P may have circular pillar shapes extending in a vertical direction from the word lines 30 . The plurality of cell pillars P may be electrically and directly connected to the word lines 30 . Since the cell pillars P vertically pass through the bit line stacks 40S, the one bit line stack 40S may be electrically connected to a plurality of cell pillars P.

The word lines 30 may be disposed on the bit line stacks 40S and the cell pillars P. Upper ends of the plurality of cell pillars P may be electrically connected to the word lines 30, respectively, and lower ends of the plurality of cell pillars P may be lowermost portions of the bit line stacks 40S. may protrude downward from the bit line 40 of and may float from the word lines 30 and the bit lines 40 . That is, lower ends of the plurality of cell pillars P may not be connected to other conductive components.

FIG. 3A is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along line II' of FIG. 2 and FIG. 3B is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along line II-II' of FIG. 2 .

Referring to FIGS. 3A and 3B , a cell array 100A of a semiconductor memory device according to an embodiment of the present invention has a lower insulating layer 20 formed on a substrate 10 and stacked on the lower insulating layer 20 . may include bit line stacks 40S, cell pillars P, and word lines 30. The bit line stacks 40S may include a plurality of bit lines 40 extending in parallel in a horizontal direction. A plurality of interlayer insulating layers 25 may be interposed between the plurality of stacked bit lines 40 . Thus, the bit lines 40 and the interlayer insulating layers 25 may be alternately stacked on the substrate 10 and the lower insulating layer 20 . An upper interlayer insulating layer 26 may be formed between the bit line stacks 40S and the word lines 30 .

The substrate 10 may include a bulk semiconductor wafer such as single crystal silicon or a semiconductor layer such as epitaxially grown single crystal silicon.

The lower insulating layer 20 may include silicon oxide, silicon nitride, or a combination thereof. The lower insulating layer 20 may electrically insulate the substrate 10 from the bit lines 40 and the substrate 10 from the cell pillars P.

The cell pillars P may extend in a vertical direction to vertically pass through the bit lines 40 . Upper ends of the cell pillars P may be directly electrically connected to the word lines 30, respectively, and lower ends of the cell pillars P may be floating. That is, lower ends of the cell pillars P may not be electrically and physically connected to the substrate 10 or other conductive elements. The cell pillars P may pass through the upper interlayer insulating layer 26 and the interlayer insulating layers 25 and partially protrude into the lower interlayer insulating layer 20 . Lower ends of the plurality of cell pillars P may protrude downward from the lowermost bit line 40 of the bit line stacks 40S.

The word lines 30 may be disposed on the cell pillars P so as to be electrically connected to the cell pillars P. The word lines 30 may extend in a horizontal direction orthogonal to the bit lines 40 . For example, the word lines 30 may extend in a first horizontal direction, and the bit lines 40 may extend in a second horizontal direction orthogonal to the first horizontal direction. The word lines 30 may include a conductor. For example, the word lines 30 may include a metal such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al); metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The bit lines 40 may include a conductor. For example, the bit lines 40 may include a metal such as tungsten (W), ruthenium (Ru), or iridium (Ir); other metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The plurality of interlayer insulating layers 25 may include an insulating material such as silicon oxide or silicon nitride to electrically insulate the bit lines 40 . The upper interlayer insulating layer 26 may include an insulating material such as silicon oxide or silicon nitride to electrically insulate the bit line stacks 40S and the word lines 30 .

FIG. 4A is an enlarged view of area 'A' of FIG. 3, and FIG. 4B is a cross-sectional view taken along line III-III'. Referring to FIGS. 4A and 4B , the cell pillar P may include a central core 35 and a peripheral memory layer 60 . A portion of the core 35 and a portion of the memory layer 60 may each form one memory cell MC. For example, the cell pillar P may include the plurality of stacked memory cells MC, and the memory cells MC include a central core 35 and a memory surrounding the core 35, respectively. Layer 60 may be included.

The core 35 may be directly electrically connected to the word line 30 . The core 35 may include a conductor. For example, the core 35 may include a metal such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al); metal compounds such as tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), and ruthenium oxide (RuO ₂ ); metal silicides such as tungsten silicide (WSi), titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi); or doped silicon.

The memory layer 60 may include at least three layers of first to third variable resistance layers 61 , 62 , and 63 . The first to third variable resistance layers 61, 62, and 63 are configured to measure energy band gaps, chemical potentials, ion mobility, filament generation threshold voltages, phase change threshold voltages, or At least one of the atomic movement threshold voltages may be different from each other. For example, the first variable resistance layer 61 has the largest energy band gap, chemical potential, filament generation threshold voltage, phase change threshold voltage, or atom migration threshold voltage, and the third variable resistance layer 63 It may have the smallest energy band gap, chemical potential, filament formation threshold voltage, phase change threshold voltage, or atomic migration threshold voltage. Alternatively, the first variable resistance layer 61 may have the lowest ion mobility, and the third variable resistance layer 63 may have the highest ion mobility. The electrical resistance of the first variable resistance layer 61 is most difficult to change, and the electrical resistance of the third variable resistance layer 63 is most easily changeable. When the semiconductor memory device is a resistive RAM or a conductive bridge RAM, a conductive filament can be formed most difficult in the first variable resistance layer 61, and a conductive filament can be formed most easily in the third variable resistance layer 63 It can be. In other words, the first variable resistance layer 61 may have a relatively high filament generation threshold voltage, and the third variable resistance layer 63 may have a relatively low filament generation threshold voltage.

The first to third variable resistance layers 61, 62, and 63 may include hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), and tantalum oxide (Ta ₂ O ₅ ). ), silicon oxide (SiO ₂ ), or various metal oxides including oxygen vacancy such as titanium oxide (TiO ₂ ), a high dielectric constant oxide, or a combination thereof.

5A and 5B are diagrams explaining a programming operation principle of the semiconductor memory device. As an example, three memory cells MC1 to MC3 and three bit lines 40_1 to 40_3 are described.

5A and 5B , in the programming operation of the semiconductor memory device, in order to program the memory cells MC1 to MC3 to have different data values, for example, different resistance levels, the semiconductor memory device may have different resistance levels. The word line program voltage Vwp is applied to the word line 30, that is, the core 35, the first bit line program voltage Vbp1 is applied to the first bit line 40_1, and the second bit line ( The second bit line program voltage Vbp2 may be applied to 40_2 , and the third bit line program voltage Vbp3 may be applied to the third bit line 40_3 .

A difference between the word line program voltage Vwp and the first bit line program voltage Vbp1 is the largest, and a difference between the word line program voltage Vwp and the third bit line program voltage Vbp3 is the smallest. It is assumed, and described. That is, |Vwp - Vbp1| > |Vwp - Vbp2| > |Vwp - Vbp3| can be For example, when all of the program voltages Vwp, Vbpp1, Vbp2, and Vbp3 have positive (+) values, the first bit line program voltage Vbp1 is the smallest, and the third bit line program voltage ( Vbp3) may be the highest.

The largest first filament F1 can be formed in the first memory cell MC1 to which the largest voltage difference is applied, and the smallest third filament F1 can be formed in the third memory cell MC3 to which the smallest voltage difference is applied. A filament F3 may be applied. A second filament F2 having an intermediate size may be formed in the second memory cell MC2 to which the intermediate voltage difference is applied. It is assumed and described that the memory cells MC1 - MC3 are memory cells of a resistive memory RAM or a conductive bridge RAM. When the memory cells MC1 to MC3 are memory cells of a phase change RAM, the filaments F1 to F3 may be phase changed regions.

As mentioned above, the first variable resistance layer 61 has the highest band gap, chemical potential, ion mobility, filament generation threshold voltage, phase change threshold voltage, or atomic migration threshold voltage, and the third variable resistance layer ( 63) has the lowest band gap, chemical potential, ion mobility, filament generation threshold voltage, phase change threshold voltage, or atom migration threshold voltage, the first to third variable resistance layers 61 to 63 have the same It is possible to form conductive filaments of different sizes, respectively, at the voltage. Specifically, the filament formed in the first variable resistance layer 61 having the highest threshold voltage may be the smallest, and the filament formed in the third variable resistance layer 63 having the lowest threshold voltage may be the smallest. can be big Therefore, in the read operation of the semiconductor memory device, the resistance value of the first memory cell MC1 may be the lowest and the resistance value of the third memory cell MC3 may be the highest.

Referring to FIG. 5B , in the first memory cell MC1 to which the largest voltage difference is applied, the first filament F1 includes the filaments formed in the first to third variable resistance layers 61 to 63 . In the second memory cell MC2 to which the medium voltage difference is applied, the second filament F2 may include filaments formed in the second and third variable resistance layers 62 and 63. and in the third memory cell MC3 to which the smallest voltage difference is applied, the third filament F3 may include a filament formed only in the third variable resistance layer 63 . The first variable resistance layer 61 of the second memory cell MC2 where the filament is not formed, and the first variable resistance layer 61 and the second variable resistance layer 61 of the third memory cell MC3 In the layer 62, electron tunneling may occur according to voltage differences between read voltages applied to the core 35 (ie, the word line 30) and the bit lines 40_1, 40_2, and 40_3. . Therefore, in the read operation of the semiconductor memory device, the first memory cell MC1 may have the lowest resistance value and the third memory cell MC3 may have the highest resistance value.

According to the technical concept of the present invention, the memory cells MC1 to MC3 may have various resistance levels according to a voltage difference between the word line program voltage Vwp and the bit line program voltages Vbp1 to Vbp3. For example, in the case of a neuromorphic device, the memory cells MC1 to MC3 may have various learning levels according to a voltage difference between the word line program voltage Vwp and the bit line program voltages Vbp1 to Vbp3. can

In the spirit of the present invention, the memory layer 60 has been described as including three layers of variable resistance layers 61 to 63, but the memory layer 60 may include four or more layers of variable resistance layers. there is. That is, it can have more resistance levels.

6 is a three-dimensional perspective view schematically showing the cell array 100B of the semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 6 , the cell array 100B of the semiconductor memory device may include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. . Compared to the cell array 100A of the semiconductor memory device shown in FIG. 2 , the plurality of word lines 30 are the plurality of bit lines 40 and the plurality of cell pillars P. can be placed at the bottom. That is, lower ends of the plurality of cell pillars P may be electrically connected to the word lines 30, respectively, and upper ends of the plurality of cell pillars P may be floating.

7A is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line IV-IV' of FIG. 6, and FIG. 7B is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line V-V' of FIG.

Referring to FIGS. 7A and 7B , a cell array 100B of a semiconductor memory device according to an embodiment of the present invention has a lower insulating layer 20 formed on a substrate 10 and disposed on the lower insulating layer 20 . word lines 30, cell pillars P and bit line stacks 40S disposed on the weed lines 20. Compared to the cell array 100A of the semiconductor memory device shown in FIGS. 3A and 3B , the word lines 30 are disposed below the cell pillars P and the bit line stacks 40S. It can be. The word lines 30 may be insulated from the substrate 10 by the lower interlayer insulating layer 20 . That is, lower ends of the cell pillars P may be electrically connected to the word lines 30 , and upper ends of the cell pillars P may be floating.

8A is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line IV-IV' of FIG. 6, and FIG. 8B is a schematic longitudinal cross-sectional view of the semiconductor memory device taken along the line V-V' of FIG.

Referring to FIGS. 8A and 8B , a cell array 100C of a semiconductor memory device according to an embodiment of the present invention includes word lines 30 buried in a substrate 10, and a lower portion formed on the substrate 10. It may include an insulating layer 20 , cell pillars P disposed on the weed lines 20 , bit line stacks 40S, and a plurality of interlayer insulating layers 25 and 26 . Compared to the cell array 100A of the semiconductor memory device shown in FIGS. 3A and 3B , the word lines 30 are disposed below the cell pillars P and the bit line stacks 40S. It can be. The word lines 30 may be buried inside the substrate 10 . The word lines 30 may be doped regions formed in the substrate 10 or may be metal lines buried in the substrate 10 . The word lines 30 may be electrically insulated from the bulk region of the substrate 10 by an insulating region 12 formed in the substrate 10 . The insulating region 12 may include an insulating material including silicon oxide or silicon nitride. In another embodiment, the insulating region 12 may be an N-type or P-type doped region for forming a depletion region with either the word line 30 or the substrate 10 .

9 is a block diagram conceptually illustrating a cell array 200 of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 9 , the cell array 200 of the semiconductor memory device includes a row driver RD, a plurality of column drivers CD-1 to CD-m, and a plurality of column drivers CD-1 to CD-m in parallel in a row direction from the row driver RD. A column including a plurality of row lines (R1-Rn) extending, and a plurality of column lines (C11-CmM) extending in parallel in a column direction from the plurality of column drivers (CD-1 to CD-m). A plurality of memories arranged in line sets (CS-1, CS-2, ..., CD-m) and crossing areas between the row lines (R1-Rn) and the column lines (C11-CmM) Cells MC may be included. One of the plurality of column drivers CD-1, CD-2, ..., CD-m is connected to one of the column line sets CS-1, CS-2, ..., CD-m, respectively. Memory blocks B1, B2, ..., Bm may be formed.

10A and 10B are three-dimensional perspective views schematically illustrating cell arrays 200A and 200B of a semiconductor memory device according to example embodiments.

10A and 10B, the cell arrays 200A and 200B of the semiconductor memory device include a plurality of word lines 30, a plurality of bit lines 40, and a plurality of cell pillars P. can include The word lines 30 may extend parallel to each other in the first direction D1. The first direction D1 may be a horizontal row direction. The bit lines 40 may include a plurality of bit line stacks 40S extending in the second direction D2. That is, each of the bit line stacks 40S may have a plurality of bit lines 40 . The second direction D2 may be a horizontal column direction. Each of the plurality of bit line stacks 40S may form a memory cell block B. The plurality of cell pillars P may extend in the third direction D3 to pass through the bit lines 40 . The third direction D3 may be a vertical direction.

Referring to FIG. 10A , the word lines 30 may be disposed above the bit line stacks 40S and the cell pillars P. Referring to FIG. 10B , the word lines 30 may be disposed under the bit line stacks 40S and the cell pillars P. A more detailed description of the cell arrays 200A and 200B shown in FIGS. 10A and 10B will be understood with reference to FIGS. 3A and 3B and FIGS. 4A and 4B .

9, 10A, and 10B, one of the word lines 30 and a plurality of bit lines 40 may be electrically connected through one of the cell pillars P. Further referring to FIGS. 4A and 4B , each of the cell pillars P may include a plurality of memory cells MC in an area where the word line 30 and the bit lines 40 intersect. Accordingly, a plurality of memory cells MC may output a plurality of data through a plurality of bit lines 40 through one word line 30 . The one word line 30 may be electrically connected to a plurality of blocks (B). When the plurality of blocks B are driven at different voltage levels, the cell arrays 200A and 200B may operate using only one block B or selected plurality of blocks B. Accordingly, driving efficiency and speed of the semiconductor memory device may be improved, and multi-data leveling may be implemented.

11 is a conceptual longitudinal cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 11 , the semiconductor memory device according to an embodiment of the present invention includes a circuit unit 15 formed on a substrate 10, a lower insulating layer 20, and bits stacked on the lower insulating layer 20. Lines 40 and interlayer insulating layers 25, cell pillars P vertically penetrating the bit lines 40 and the interlayer insulating layers 25, the cell pillars P It may include word lines 30 and via plugs 45 for electrically connecting the bit lines 40 and the circuit unit 15 .

The circuit unit 15 may include a plurality of transistors. For example, the circuit unit 15 may include a logic circuit, a pre-synaptic circuit, and/or a post-synaptic circuit. The via plugs 45 may include a conductor. For example, the via plugs 45 may include metal such as tungsten (W), ruthenium (Ru), copper (Cu), or aluminum (Al). In other embodiments of the present invention, the via plugs 45 are formed of tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds such as ruthenium oxide (RuO ₂ ), tungsten silicide (WSi) ), a metal silicide such as titanium silicide (TiSi), nickel silicide (NiSi), or cobalt silicide (CoSi), or doped silicon.

Active regions for electrically connecting the transistors and the via plugs 45 may be formed in the substrate 10 . For example, doped regions may be formed.

Since the word lines 30 , the bit line stacks 40 , and the cell pillars P are formed on the circuit part 15 , the degree of integration can be increased. In addition, since the vertically arranged circuit unit 15 and the cell array reduce electrical signal paths, the operating speed can be increased.

12 is a diagram conceptually illustrating a pattern recognition system 900 according to an embodiment of the present invention. For example, the pattern recognition system 900 may be a speech recognition system, an imaging recognition system, a code recognition system, a signal recognition system, or other It can be one of the systems for recognizing various patterns.

Referring to FIG. 12 , the pattern recognition system 900 according to an embodiment of the present invention includes a central processing unit 910, a memory unit 920, a communication control unit 930, a network 940, and an output unit 950. ), an input unit 960, an analog-to-digital converter 970, a neuromorphic unit 980, and/or a bus 990. The central processing unit 910 generates and transmits various signals for learning of the neuromorphic unit 980, and various signals for recognizing patterns such as voice and video according to output from the neuromorphic unit 980. processing and functions.

The central processing unit 910 may be connected to a memory unit 920, a communication control unit 930, an output unit 950, an analog-to-digital converter 970, and a neuromorphic unit 980 through a bus 990. can

The memory unit 920 may store various information required to be stored in the pattern recognition system 900 . The memory unit 920 includes a volatile memory device such as DRAM or SRAM, a non-volatile memory device such as PRAM, MRAM, ReRAM, or NAND flash memory. It may include at least one of a memory or various storage units such as a hard disk drive (HDD) or solid state drive (SSD).

The communication control unit 930 may transmit and/or receive recognized data such as voice and video to a communication control unit of another system through the network 940 .

The output unit 950 may output data such as recognized voice and video in various ways. For example, the output unit 950 may include a speaker, printer, monitor, display panel, beam projector, hologrammer, or other various output devices.

The input unit 960 may include at least one of a microphone, camera, scanner, touch pad, keyboard, mouse, mouse pen, or various sensors.

The analog-to-digital converter 970 may convert analog data input from the input device 960 into digital data.

The neuromorphic unit 980 may perform learning, recognition, etc. using the data output from the analog-to-digital converter 970, and may output data corresponding to the recognized pattern. . The neuromorphic unit 980 may include at least one of neuromorphic elements according to various embodiments of the inventive concept.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art can implement the present invention in other specific forms without changing the technical spirit or essential features. You will understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

RD: low driver, pre-synaptic neuron
CD: column driver, post-synaptic neuron
R: low line
C: column line
MC: memory cell
10: substrate
12: Insulation area
15: circuit part
20: lower insulating layer
30: word line
35: core
40: bit line
45 Via plug
40S: bit line stack
P: cell pillar
60: memory layer
61: first variable resistance layer
62: second variable resistance layer
63: third variable resistance layer

Claims (20)

Board;
a plurality of row lines buried in the substrate and extending in parallel in a first horizontal direction;
a plurality of column line stacks extending in parallel in a second horizontal direction orthogonal to the first horizontal direction, the column line stacks including a plurality of column lines stacked in a vertical direction;
cell pillars vertically penetrating the column lines of the column line stacks; and
an upper insulating layer covering the column line stacks and the cell pillars;
Lower ends of the cell pillars are electrically connected to the row lines, and
Upper ends of the cell pillars are floating semiconductor memory devices.
◈Claim 2 was abandoned when the registration fee was paid.◈ According to claim 1,
The upper ends of the cell pillars protrude upward from an uppermost column line among the column lines of the column line stacks and are positioned within the upper insulating layer.
◈Claim 3 was abandoned when the registration fee was paid.◈ According to claim 1,
Each of the cell pillars,
central core; and
A semiconductor memory device comprising a memory layer surrounding the core.
◈Claim 4 was abandoned when the registration fee was paid.◈ According to claim 3,
The semiconductor memory device of claim 1 , wherein the core includes at least one of a metal, a metal compound, a metal silicide, or combinations thereof.
◈Claim 5 was abandoned when the registration fee was paid.◈ According to claim 4,
The core may be a metal such as tungsten, ruthenium, copper, or aluminum; metal compounds such as tungsten nitride, titanium nitride, tantalum nitride, and ruthenium oxide; metal silicides such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide; or doped silicon.
◈Claim 6 was abandoned when the registration fee was paid.◈ According to claim 3,
The row lines and the core are directly connected to each other.
◈Claim 7 was abandoned when the registration fee was paid.◈ According to claim 3,
The memory layer includes at least three layers of variable resistance layers, and the three layers of variable resistance layers include band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, phase change threshold voltages, or atomic movement thresholds. a semiconductor memory element having at least one voltage different from each other;
◈Claim 8 was abandoned when the registration fee was paid.◈ According to claim 7,
The at least three variable resistance layers each include one of various metal oxides including oxygen vacancy or high dielectric constant oxides such as hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide. semiconductor memory device.
◈Claim 9 was abandoned when the registration fee was paid.◈ According to claim 1,
The column lines may be made of a metal such as tungsten, ruthenium, or iridium; other metal compounds such as tungsten nitride, titanium nitride, tantalum nitride, ruthenium oxide; metal silicides such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide; or doped silicon.
delete Board;
a lower insulating layer on the substrate;
a word line extending in a first horizontal direction;
a bit line stack extending in a second horizontal direction orthogonal to the first horizontal direction, the bit line stack including a plurality of bit lines stacked in a vertical direction; and
a cell pillar extending downwardly from the word line to vertically penetrate the bit line stack;
An upper end of the cell pillar is electrically connected to the word line, and
The lower end of the cell pillar is floated so as not to be electrically connected to any conductive component,
The lower end of the cell pillar protrudes downward from the bit line positioned at the lowermost part of the bit line stack and is positioned within the lower insulating layer.
delete ◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 11,
The bit lines may be made of a metal such as tungsten, ruthenium, or iridium; other metal compounds such as tungsten nitride, titanium nitride, tantalum nitride, ruthenium oxide; metal silicides such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide; or doped silicon.
delete ◈Claim 15 was abandoned when the registration fee was paid.◈ According to claim 11,
The semiconductor memory device of claim 1 , wherein the cell pillar includes a central core and memory layers surrounding the core.
◈Claim 16 was abandoned when the registration fee was paid.◈ According to claim 15,
The memory layers include at least three layers of variable resistance layers, and the three layers of variable resistance layers include band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, phase change threshold voltages, or atomic movement thresholds. A semiconductor memory device in which at least one of the voltages is different from each other.
◈Claim 17 was abandoned when the registration fee was paid.◈ According to claim 16,
The at least three variable resistance layers each include one of various metal oxides including oxygen vacancy or high dielectric constant oxides such as hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide. semiconductor memory device.
◈Claim 18 was abandoned when the registration fee was paid.◈ According to claim 11,
The word line may be made of a metal such as tungsten, ruthenium, copper, or aluminum; metal compounds such as tungsten nitride, titanium nitride, tantalum nitride, and ruthenium oxide; metal silicides such as tungsten silicide, titanium silicide, nickel silicide, or cobalt silicide; or doped silicon.
Board;
a lower insulating layer formed on the substrate;
bit lines and interlayer insulating layers alternately stacked on the lower insulating layer, the bit lines extending in parallel in a first horizontal direction;
an upper insulating layer on the bit lines;
a word line extending in a second horizontal direction perpendicular to the first horizontal direction on the upper insulating layer; and
a vertical pillar vertically penetrating the upper insulating layer, the interlayer insulating layers, and the bit lines from the word line;
The vertical pillar includes a conductive core and at least three variable resistance layers surrounding the core,
An upper end of the vertical pillar is directly connected to the word line, and
A lower end of the vertical pillar protrudes into the lower insulating layer so as not to contact the substrate.
◈Claim 20 was abandoned when the registration fee was paid.◈ According to claim 19,
The at least three variable resistance layers are different from each other at least one of band gaps, chemical potentials, ion mobilities, filament generation threshold voltages, magnetization threshold voltages, phase change threshold voltages, or atomic movement threshold voltages. , hafnium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, silicon oxide, or titanium oxide.

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