KR102518092B1 - Display Driver IC Reliability Test Method - Google Patents

Abstract

The present invention proposes a reliability test method of a display driver IC. In the test method of the present invention, non-defective IC chips arranged on an adhesive tape (UV tape) are mounted on a tray. Then, a reliability test is conducted in a high-temperature environment for the tray itself provided with the non-defective IC chip. After the reliability test is completed, air cleaning is performed to remove contaminants on the non-defective IC chip, after which the non-defective IC chip is again aligned on the adhesive tape, the final test is performed, and the test result is provided. is done in the order Accordingly, it is possible to simplify the test process instead of the conventional method, thereby reducing costs and improving reliability.

Description

Reliability test method of display driver IC {Display Driver IC Reliability Test Method}

The present invention relates to a method for testing the reliability of a semiconductor device, and more particularly, to a method for testing the reliability of a display driver IC using a dedicated tray capable of withstanding a high temperature.

Unlike a flat panel display, a flexible display is a display device capable of transforming its shape, such as folding or bending. In addition, a display driver IC is provided to drive the flexible display, and the display driver IC is designed to transmit signals to the flexible display through a plurality of electrically connected input/output pads.

Such a display driver IC must pass a high-temperature environment test capable of withstanding a relatively high temperature in order to satisfy the reliability of the device. This is because, in general, reliability cannot be sufficiently confirmed only by tests that identify whether a display driver IC is good or bad.

1 is a process flow chart for performing a reliability test of a display driver IC according to a conventional method.

According to FIGS. 1(a) and (b), only non-defective IC chips are selected for a reliability test among display driver ICs mounted on a wafer 1 of a predetermined standard, and the selected non-defective IC chips are aligned on a UV tape 20. (Align). In practice, this process is called 'Reconstruction process' (sometimes called 'Recon process' for short). In FIG. 1(a), reference numeral 10 indicates a good IC chip and 12 indicates a defective IC chip. The surface of the defective IC chip 12 is marked with ink, etc. Thus, the non-defective IC chips are sorted and sorted. In the subsequent process, only non-defective IC chips are used for reliability testing.

Referring to FIG. 1(c), a non-defective IC chip 10 is bonded on a standard chip on film 30 having a predetermined length, and then the chip on film is cut. In a subsequent process, it is cut into a size that can be mounted on a carrier of a predetermined size. One non-defective IC chip 10 is bonded to one cut chip-on film.

Referring to FIG. 1(d), each cut chip-on film 32 is mounted on a carrier 40. The carrier 40 is configured to test the reliability of the non-defective IC chip 10 in a high-temperature environment. The chip-on film 32 is mounted in the carrier 40 and the chip-on film 32 is installed using a bracket 42. It is a structure that can be assembled so as not to be separated from the carrier 40.

Referring to FIGS. 1(e) and (f), the carrier 40 is put into the socket 50 and a pre-test is performed. In the drawing, the socket 50 is composed of a base 52 and a cover 54, and the carrier 40 is put into the base 52 and the cover 54 is coupled thereon. The purpose of the pre-test is to determine good IC chips and defective IC chips after the reliability test.

Referring to FIG. 1(g), when the pre-test is completed, the carrier 40 is separated from the socket 50. And, in FIG. 1 (h), a reliability test is performed only for the carrier 40 in a high-temperature environment.

After the reliability test is performed, referring to FIG. 1(i), the chip-on film 32 is separated from the carrier 40, and then a cleaning process is performed to remove contaminants or foreign substances from the film. Referring to FIG. 1(j), the chip-on film 32 is reassembled to the carrier 40, and the carrier 40 is assembled to the socket 50 as shown in FIG. 1(k), and then a final test is performed. Reliability test results are provided after the final test.

However, such a conventional reliability test method has the following problems.

First, since the non-defective IC chip 10 is bonded to the chip-on film 30, costs for manufacturing the dedicated chip-on film 30 are incurred.

In addition, a carrier 40 for mounting the cut chip-on film 32 is required. Therefore, manufacturing costs for the carrier 40 are incurred, and a process of mounting the cut chip-on film 32 on the carrier 40 is required. In addition, since the cut chip-on film 32 is mounted on the carrier in a manual manner, there is a possibility of defects due to human error.

In addition, due to the nature of the high temperature test, contaminants may remain on the film due to environmental factors, and furthermore, since the electrical test is conducted through the pins of a good IC chip at high temperatures, the pins themselves are also contaminated. Since subsequent tests are difficult if these contaminants are not removed, a laser cleaning or chemical cleaning process must be performed to remove them. In the case of severe contamination during the cleaning process, repeated cleaning processes are required, and tests may not be possible if the contamination is not removed.

Also, in the related art, the number of testable pins in the non-defective IC chip 10 was limited according to the sizes of the carrier 40 and the socket 50 . That is, in the prior art, as shown in FIG. 2, only about 436 pins of non-defective IC chips could be tested. Considering that the number of pins of the display driver IC is approximately 2000 to 3000, it is impossible to test the remaining pins. As much as that, there is a limit to the verification of characteristics after reliability.

Also, during the reliability test, since the carrier 40 is arranged in a plane, it is necessary to secure a space for the reliability test.

The present invention is to solve the above problems, and to provide a reliability test method of a display driver IC capable of improving a reliability test process and reducing various costs required for a reliability test.

Another object of the present invention is to provide a dedicated tray for reliability testing of display driver ICs.

A method for testing the reliability of a display driver IC according to the present invention to achieve the above object includes performing a pre-test on non-defective IC chips aligned on an adhesive tape; mounting the non-defective IC chip on a tray; performing a reliability test on the tray on which the non-defective IC is mounted; performing cleaning after completion of the reliability test; aligning the non-defective IC chip on the adhesive tape again; and performing a final test on the non-defective IC chip and providing a test result.

The method may further include selecting good ICs from among tested IC chips in the wafer.

The pre-test may be a probe test in which all pins of a non-defective IC chip are tested.

The cleaning is performed by supplying air at a predetermined wind speed and volume in a state where a cover for preventing scattering of non-defective IC chips is assembled on the upper surface of the tray.

The tray (tray), a base formed with a plurality of seating grooves on the upper surface; a cover covering an upper surface of the base; and a locking clip coupling the base and the cover, and the cover may have a mesh structure through which air can penetrate from the outside to the upper surface of the base by driving a fan.

The tray is made of an amorphous thermoplastic resin.

The tray is made of MPPO (Modified Polyphenylene Oxide, Noryl) material.

According to the present invention, since the high-temperature reliability test of the display driver IC is performed using a dedicated tray, conventional processes such as cutting and assembling, mounting the cut tape on the carrier, and cleaning can be omitted. It can be expected to improve work efficiency due to process simplification.

In addition, there is no need to manufacture a dedicated chip-on film, and test costs can be reduced because a carrier for socket test is not required, and human defect factors that can occur in manual work such as carrier assembly can be fundamentally excluded, improving test reliability. can make it

In addition, the test space can be minimized, and the characteristics of all pins provided on the IC chip can be verified.

1 is a flowchart of a reliability test process of a conventional display driver IC.
2 is a diagram showing the number of possible pins of a display driver IC during a conventional reliability test process.
3 is a flowchart of a reliability test process of a display driver IC according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a reconstruction process of FIG. 3 .
5 is an exploded perspective view of a tray for a reliability test of the present invention.
6 and 7 are views showing states before and after locking of the base and the cover.
8 and 9 are diagrams illustrating a work space according to a conventional reliability test process and a test process according to the present invention.

Since the present invention can apply various transformations and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail. However, it should be understood that this is not intended to limit the specific embodiments of the present invention, and includes all conversions, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the present invention, if it is determined that a detailed description of related known technologies may obscure the gist of the present invention, the detailed description will be omitted.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another.

Terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Spatially relative terms, such as below, beneath, lower, above, upper, etc., facilitate the correlation between one element or component and another element or component, as shown in the drawing. can be used to describe Spatially relative terms should be understood as encompassing different orientations of elements in use or operation in addition to the orientations shown in the figures. For example, when an element shown in the drawing is turned over, an element described as below or beneath another element may be placed above or above the other element. Accordingly, the exemplary term below may include both directions of down and above. Elements may also be oriented in other orientations, and thus spatially relative terms may be interpreted according to orientation.

As used in the present invention, an expression indicating a part such as “part” or “part” refers to a device in which a corresponding component may include a specific function, software which may include a specific function, or a device which may include a specific function. and software, but cannot necessarily be limited to the expressed functions, which are provided only to help a more general understanding of the present invention, and those with ordinary knowledge in the field to which the present invention belongs If so, various modifications and variations are possible from these descriptions.

In addition, it should be noted that all electrical signals used in the present invention, as an example, can be reversed in signs of all electrical signals to be described below when an inverter or the like is additionally provided in the circuit of the present invention. Therefore, the scope of the present invention is not limited to the direction of the signal.

Therefore, the spirit of the present invention should not be limited to the described embodiments, and it will be said that not only the claims to be described later, but also all modifications equivalent or equivalent to these claims fall within the scope of the spirit of the present invention. .

Hereinafter, the present invention will be described in more detail based on the embodiments shown in the drawings.

3 is a flowchart of a reliability test process of a display driver IC according to an embodiment of the present invention.

Referring to FIG. 3(a) , in a state in which the display driver IC is mounted on a wafer 100 of a predetermined standard, the defective IC chip is determined according to the test result of checking the non-defective IC chip 110 and the defective IC chip 120 of the display driver IC. 120 shows a state marked with ink or the like.

Referring to FIG. 3(b), a reconstruction process of sorting only good IC chips 110 and arranging them on a UV tape 130 is performed, excluding defective IC chips 120 marked for reliability testing. For this process, 'Die Transfer Machine' equipment, which is a die transfer equipment, is used. In the embodiment, the reconstruction process may align good quality IC chips on a 12-inch wafer to the UV tape 130 . And the reconstruction process is for matching the IC chips before and after the test in order in the reliability test process, and is not necessarily a necessary process in the reliability test process. Reconstruction process can be omitted if necessary.

Here, an example of the reconstruction process using the 'Die Transfer Machine' equipment is shown in FIG. Referring to FIG. 4 , (a) is a state in which good IC chips 110 and marked bad IC chips 120 are aligned on a 12-inch wafer 100 . In this state, using the 'Die Transfer Machine' equipment, as shown in (b), only the good IC chips 110 are moved and rearranged (PnP; Pick & Replace) on the UV tape 130 of a predetermined standard. .

Referring to FIG. 3(c), a probe test is performed on the non-defective IC chips 110 aligned on the UV tape 130. Since the probe test targets the IC chip itself, it is possible to test all pins of the non-defective IC chip 110 . Compared to the prior art, it is possible to solve the problem of verifying characteristics due to the limitation of the number of pins.

Referring to FIG. 3(d), a non-defective IC chip is supplied to the seating groove 212 provided in the dedicated tray 200 at high temperature, and a high-temperature environment test is performed in the step of FIG. 3(e). The configuration of the dedicated tray 200 will be examined in detail below. Reliability tests in high-temperature environments include uHAST (Unbiased HAST) and thermal cycle test (T/C) methods. That is, in the present invention, a reliability test is performed on the tray 200 in a state in which non-defective IC chips 110 are mounted in the tray 200 . Typically, about 15 non-defective IC chips 110 are seated in the tray 200 to perform a reliability test, but the number of supplied IC chips may vary depending on the size of the tray 200 and the like. Here, the pick and replace (PnP; Pick & replace) method is used to transfer the non-defective IC chip to the dedicated tray.

When the reliability test is completed, a cleaning process is performed to remove contaminants from the surface of the non-defective IC chip 110 or the like. As shown in FIG. 3(f), the cleaning process is performed with the good IC chip 110 in the tray 200, and air having a predetermined air volume and speed is used. As such, since the present invention is tested with the good IC chip 110 mounted inside the tray 200, a laser cleaning or chemical cleaning process is performed to remove contaminants such as tapes, films, and pins, as in the prior art. No need to. This is because only contaminants that may exist on the surface of the non-defective IC chip 110 need be removed.

The cleaning process using air may be configured to supply air at a predetermined air volume and speed to the inside of the tray 200 . For example, a fan installed on one side of the tray 200 may be used. In addition, a cover 220 is required on the upper side of the tray 200 to prevent the non-defective IC chips 110 placed in the seating grooves 212 of the tray 200 from scattering during the cleaning process. In the present invention, since the non-defective IC chip 110 is not bonded to the upper surface of the tray 200 but is simply raised, it is necessary to prevent the non-defective IC chip 110 from being blown away by air.

Referring to FIG. 3( g ), when the reliability test using the tray 200 is completed, the non-defective IC chips 110 in the tray 200 are aligned on the UV tape 130 again. Then, as shown in FIG. 3(h), a final test using a probe is performed, and a final result is provided.

As such, the present invention proceeds using the dedicated tray 200, so the process can be simplified compared to the prior art, equipment such as carriers and sockets do not need to be used, and the possibility of contamination can be significantly eliminated.

5 is an exploded perspective view of a tray for a reliability test of the present invention, and FIGS. 6 and 7 are views showing states before and after locking of a base and a cover.

According to FIG. 5 , the tray 200 includes a base 210 having a predetermined size and a cover 220 covering the upper surface of the base 210 . The base 210 is provided with a plurality of seating grooves 212 in which display driver ICs (that is, non-defective IC chips) are placed, and the seating grooves 212 correspond to the exterior of the non-defective IC chip 110 . In the embodiment, one tray 200 is provided with 15 seating grooves 212 to mount 15 non-defective IC chips, but the number may be changed. And the corner side of the base 210 is formed with a locking slit (214).

6 and 7, in a state where the cover 220 is covered on the base 210, the upper end of the locking clip 230 is in contact with the upper surface of the cover 220 and the lower end is inserted into the locking slit 214 It is fastened to couple the base 210 and the cover 220.

The cover 220 is to prevent the non-defective IC chip placed in the seating groove 212 of the base 210 from being blown away during a cleaning process using air. In addition, the cover 220 should have a structure in which air is supplied to the upper surfaces of the non-defective IC chips to remove contaminants. For example, it may be formed in a mesh structure. However, the structure of the cover 220 does not need to be limited to a specific structure as long as air is sufficiently supplied and contaminants can be removed from the non-defective IC chip.

The reliability test of the present invention is made at high temperature. Therefore, the tray 200 must be made of a material that can withstand a high temperature of about 150°C. The embodiment is manufactured using MPPO (Modified Polyphenylene Oxide, Noryl) material, which is an amorphous thermoplastic resin. These material properties include low mechanical properties and molding shrinkage, excellent heat resistance, and low physical property degradation at low temperatures. In addition, it has very low water absorption rate and excellent water resistance, so it is strong against heat or steam, has excellent creep characteristics, and has excellent electrical characteristics due to its low water absorption rate.

The tray 200 may be made of other materials. ABS resin (ABS resin, acrylonitrile butadiene styrene copolymer), PPO (Polyphehylene Oxide), PSU (Polyarylsulfones), PES (Polyether sulfone), PEEK (Polyetheretherketone), etc. can be used. It can be used by mixing with the amorphous thermoplastic resin MPPO shown in the above examples.

8 and 9 are diagrams illustrating a work space according to a conventional reliability test process and a test process according to the present invention.

Referring to FIG. 8, it is a diagram showing a required area when a reliability test is performed using the uHAST (Unbiased HAST) method. If 45 non-defective IC chips are tested, conventionally, 45 carriers must be arranged in a plane. This is because only one good IC chip is supplied to each carrier. So, if the size of one carrier is 63 * 63 mm2, an area of about 178,605 mm2 (63 * 63 * 45 pieces) is required on a flat surface basis.

On the other hand, referring to FIG. 9, the present invention requires only three trays 200. Since 15 non-defective IC chips can be accommodated in one tray, reliability testing of a total of 45 non-defective IC chips is possible with 3 trays. If the size of one tray 200 is 51 * 51 mm2, only about 7,803 mm2 (51 * 51 * 3) of area is required on a plane basis, so it is possible to save space by about 20 times compared to the required area in the conventional reliability test. there is.

Although the above has been described with reference to the illustrated embodiments of the present invention, these are only examples, and those skilled in the art to which the present invention belongs can variously It will be apparent that other embodiments that are variations, modifications and equivalents are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: wafer
110: good IC chip
120: bad IC chip
130: UV tape
200: tray
210: base
212: seating groove
214: locking slit
220: cover
230: locking clip

Claims (7)

performing a pre-test on the non-defective IC chips aligned on the adhesive tape;
mounting the non-defective IC chip on a tray;
performing a reliability test on the tray on which the non-defective IC chip is mounted;
performing cleaning after completion of the reliability test;
aligning the non-defective IC chip on the adhesive tape again; and
A reliability test method of a display driver IC, comprising the steps of performing a final test on the non-defective IC chip and providing a test result. According to claim 1,
Before performing the pre-test,
The reliability test method of the display driver IC further comprising the step of selecting good ICs from the tested IC chips on the wafer and arranging them on the adhesive tape. According to claim 1,
The pre-test,
Reliability test method of display driver IC, which is a probe test that tests all pins of non-defective IC chips. According to claim 1,
The cleaning (cleaning),
A reliability test method of a display driver IC performed by supplying air with a predetermined wind speed and air volume in a state in which a cover for preventing scattering of non-defective IC chips is assembled on the upper surface of the tray. According to claim 1,
The tray,
A base having a plurality of seating grooves formed on the upper surface;
a cover covering an upper surface of the base; and
Including a locking clip coupling the base and the cover,
The reliability test method of the display driver IC in which the cover is formed in a structure in which air can penetrate from the outside to the upper surface of the base by driving a fan. According to claim 5,
the tray,
Reliability test method of display driver IC made of amorphous thermoplastic resin. According to claim 5,
the tray,
Reliability test method of display driver IC made of MPPO (Modified Polyphenylene Oxide, Noryl) material.

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