KR102485999B1 - Cache coherent system including master-side filter and data processing system having the same - Google Patents

Abstract

An application processor is published. The application processor includes a cache coherent interconnect, a first master device coupled to the cache coherent interconnect, a second master device, and a master-side filter coupled between the cache coherent interconnect and the second master device. . The master-side filter receives the snoop request transmitted from the first master device through the cache coherent interconnect, and the second security attribute of the second master device and the first master device included in the snoop request. The first security attribute is compared, and based on the comparison result, it is determined whether to transmit the address included in the snoop request to the second master device.

Description

Cache coherent system including master-side filter and data processing system including the same

An embodiment according to the concept of the present invention relates to a cache coherent system, and more particularly, to a cache coherent system including a master-side filter performing a security check and a data processing system including the same.

In computer science, cache coherence refers to coherence between local caches included in each of clients (or processors) in a shared memory system. When each of the clients includes its own local cache and the clients share memory, cache coherency problems may occur when a cache of one of the clients is updated.

When the cache coherency problem occurs, since the shared memory system performs operations for cache coherency, latency of a write operation when the shared memory system writes data to the shared memory may increase.

In a conventional system comprising a cache coherent interface, a CPU coupled to the cache coherent interface, and a GPU coupled to the cache coherent interface, the CPU operating in a non-secure mode outputs a snoop request to the GPU; When a cache hit occurs in the cache of the GPU, a cache line (ie, line data) stored in the cache is written back to an external memory device connected to the system. After the write-back is completed, the CPU transmits a command for reading a cache line written-back to the external memory device to a controller that controls the external memory device. Accordingly, write-back traffic related to the write-back and memory read request traffic related to reading the cache line stored in the external memory device increase.

A technical problem to be achieved by the present invention is to eliminate additional write-back traffic and memory read request traffic generated for security check when a snoop request is performed between masters connected to a cache coherent interconnect in order to increase cache efficiency. To provide a cache coherent system including a master-side filter that replaces a conventional slave-side filter for the snoop request and performs the security check, and a data processing system including the same.

An application processor according to an embodiment of the present invention is connected between a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and between the cache coherent interconnect and the second master device. , Receiving a snoop request transmitted from the first master device through the cache coherent interconnect, and determining a second security attribute of the second master device and a first security attribute of the first master device included in the snoop request. and a master-side filter that compares and determines whether to transmit the first address included in the snoop request to the second master device according to the comparison result.

The master-side filter transmits a first cache miss through the cache coherent interconnect without transmitting the first address to the second master device when the first security attribute and the second security attribute are different from each other. transmitted to the first master device. The master-side filter transmits the first address to the second master device when the first security attribute and the second security attribute are equal to each other, and each of the first security attribute and the second security attribute is Includes secure mode and non-secure mode.

The second master device includes a cache for storing a second address and data corresponding to the second address, and a cache controller for controlling an operation of the cache, wherein the cache controller includes the second address and the master-side The first addresses transmitted from the filter are compared with each other, and when the first address and the second address match, the data stored in the cache is transmitted to the master-side filter and the first address and the second address are matched. transmits a second cache miss to the master-side filter when is different, and the cache coherent interconnect transmits the first cache miss, the data, or the second cache miss output from the master-side filter to the first transmit to the master device.

The application processor further includes a security attribute controller for determining the second security attribute based on a control signal transmitted from the first master device, and a transmission line for transmitting the second security attribute to the master-side filter. .

According to embodiments, the master-side filter includes a memory device for storing a second address and an attribute of a memory area corresponding to the second address, connected to the memory device, and the first security attribute and the second security attribute. and a decision logic circuit for determining whether attributes match and whether the first address and the second address match, and determining whether to transmit the first address to the second master device according to a result of the determination.

The decision logic circuit transmits the first address to the second master device when the first security attribute matches the second security attribute and the first address matches the second address; When the first security attribute and the second security attribute do not match or the first address and the second address do not match, a cache miss is transmitted to the cache coherent interconnect, and the cache coherent interconnect detects the cache miss. transmitted to the first master device.

According to embodiments, the master-side filter includes a memory device for storing a second address and an attribute of a memory area corresponding to the second address, connected to the memory device, and the first security attribute and the second security attribute. A decision logic circuit for determining whether the attributes match and whether the attributes of the first address and the attributes of the second address match, and determining whether to transmit the first address to the second master device according to a result of the determination do.

The decision logic circuit transmits the first address to the second master device when the first security attribute and the second security attribute match and the attribute of the first address and the attribute of the second address match. and when the first security attribute and the second security attribute do not match or the attribute of the first address and the attribute of the second address do not match, transmit a cache miss to the cache coherent interconnect; A coherent interconnect forwards the cache miss to the first master device.

Software running on the first master device and controlling the operation of the second master device, when the second master device enters a secure mode from a non-secure mode, all data stored in a cache included in the second master device delete data, and when the second master device exits from the secure mode to the non-secure mode, all data stored in the cache while the second master device operates in the secure mode is deleted.

The application processor further includes a slave-side filter coupled to the cache coherent interconnect and processing a memory access request of the first master device to a main memory device, wherein the master-side filter performs a snoop operation; , the slave-side filter does not perform the snoop operation.

The first master device is a CPU, and the second master device is a graphics processing unit (GPU), a general-purpose computing on graphics processing unit (GPGPU), or a digital signal processor (DSP).

A data processing system according to an embodiment of the present invention includes an application processor and an external memory device connected to the application processor. The application processor is coupled between a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and between the cache coherent interconnect and the second master device, wherein the first master device A master-side filter that performs a snoop operation in response to a snoop request transmitted from the external memory device, and is connected between the cache coherent interconnect and the external memory device, and responds to a memory access request output from the first master device to the external memory device. and a slave-side filter that performs memory access operations on the memory device.

The master-side filter receives the snoop request through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device included in the snoop request, and , It is determined whether to transmit the first address included in the snoop request to the second master device according to the comparison result.

The master-side filter transmits a first cache miss through the cache coherent interconnect without transmitting the first address to the second master device when the first security attribute and the second security attribute are different from each other. to a first master device, and the master-side filter transmits the first address to the second master device when the first security attribute and the second security attribute are equal to each other, and the first security attribute and each of the second security attributes includes a secure mode and a non-secure mode.

A cache coherent system according to an embodiment of the present invention includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and between the cache coherent interconnect and the second master device. a master-side filter that is connected and performs a snoop operation in response to a snoop request transmitted from the first master device, and a memory that is connected between the cache coherent interconnect and an external memory device and that is output from the first master device and a slave-side filter that performs a memory access operation on the external memory device in response to an access request.

The master-side filter receives the snoop request through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device included in the snoop request, and , When the first security attribute and the second security attribute are different from each other, transmit a cache miss to the cache coherent interconnect without transmitting the first address included in the snoop request to the second master device, and When the first security attribute and the second security attribute are equal to each other, the master-side filter transmits the first address to the second master device.

An application processor or cache coherent system including a master-side filter according to an embodiment of the present invention provides write-back traffic and memory for secure search during a snoop operation in a data processing system supporting a secure mode and a non-secure mode. This has the effect of removing lead request traffic. The master-side filter has an effect of managing full cache coherency.

When an application processor or a cache coherent system according to an embodiment of the present invention includes a master device including an internal cache in a cache coherent network, overhead of the application processor or the cache coherent system can be reduced or eliminated. There are possible effects.

An application processor or a cache coherent system including a master-side filter according to an embodiment of the present invention has an effect of not having to change hardware for cache-coherent interconnect.

An application processor or cache coherent system including a master-side filter according to an embodiment of the present invention has an effect of not having to change hardware for a master device having non-security awareness or non trustzone awareness. there is.

An application processor or cache coherent system including a master-side filter according to an embodiment of the present invention has an effect of removing timing overhead for a cache coherent network, compared to conventional solutions. there is.

Since an application processor or cache coherent system including a master-side filter according to an embodiment of the present invention may execute software for converting (or switching) between a secure mode and a non-secure mode, a security decision logic circuit for This has the effect of reducing or minimizing area overhead.

A detailed description of each drawing is provided in order to more fully understand the drawings cited in the detailed description of the present invention.
1 is a block diagram of a data processing system according to an embodiment of the present invention.
FIG. 2 is a block diagram of a master-side filter and a second master device according to the embodiment of the present invention shown in FIG. 1 .
FIG. 3 is a flow chart for explaining the operation of the master-side filter and the second master device shown in FIG. 1;
FIG. 4 is a first table for explaining the operation of the master-side filter and the second master device shown in FIG. 1 .
FIG. 5 is exemplary embodiments for explaining operations of a master-side filter according to a snoop request output from the first master of FIG. 1 .
FIG. 6 is a block diagram of a master-side filter and a second master device according to the embodiment of the present invention shown in FIG. 1 .
FIG. 7 is a flow chart for explaining the operation of the master-side filter and the second master device shown in FIG. 6 .
FIG. 8 is a second table for explaining the operation of the master-side filter and the second master device shown in FIG. 6 .
FIG. 9 is a third table for explaining operations of the master-side filter and the second master device shown in FIG. 6 .
FIG. 10 is an embodiment for explaining operations of a master-side filter according to a snoop request output from the first master device of FIG. 1 .
11 is a diagram conceptually illustrating operation modes of the second master device shown in FIG. 1 and software operations in each of the operation modes.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are only illustrated for the purpose of explaining the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention It can be embodied in various forms and is not limited to the embodiments described herein.

Embodiments according to the concept of the present invention can apply various changes and have various forms, so the embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosure forms, and includes all changes, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another, e.g. without departing from the scope of rights according to the concept of the present invention, a first component may be termed a second component and similarly a second component may be termed a second component. A component may also be referred to as a first component.

It is understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements may exist in the middle. It should be. On the other hand, when a component is referred to as “directly connected” or “directly connected” to another component, it should be understood that no other component exists in the middle. Other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", etc., should be interpreted similarly.

Terms used in this specification are used only to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in this specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this specification, it should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a data processing system according to an embodiment of the present invention. Referring to FIG. 1 , the data processing system 100 may include a controller 200 and a main memory device 300 .

The data processing system 100 may be implemented as a personal computer (PC) or a mobile device. The mobile device includes a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, and a portable MPP (PMP). multimedia player), personal navigation device or portable navigation device (PND), handheld game console, mobile internet device (MID), wearable computer, Internet of Things (IoT) device , Internet of Everything (IoE) devices, drones, or e-books. Further, the data processing system 100 may be used in a smart car or automotive system.

The controller 200 may control the operation of the main memory device 300 . The controller 200 may mean a cache coherent system, a cache coherent network, or a cache coherent controller. The controller 200 may refer to a device including heterogeneous core clusters. For example, the heterogeneous core clusters include a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose computing on graphics processing unit (GPGPU), and a digital signal processor (DSP) connected to the cache coherent interconnect 210 . It may include, but is not limited to.

In addition, the controller 200 may be an integrated circuit (IC), a system on chip (SoC), a processor, an application processor, a mobile application processor, a motherboard, a chipset, or a set of semiconductor chips. can mean For example, the controller 200 and the main memory device 300 may be implemented as a package-on-package.

The controller 200 includes a cache coherent interconnect 210, a first master device (or first master; 220), a second controller (or first security attribute controller; 230), a second master device (or second master; 240), a master-side filter 250, and a slave-side filter 280. According to embodiments, the controller 200 may further include a third controller (or second security attribute controller) 260 and a third master device (or third master; 270).

As the master-side filter 250 is connected between the cache coherent interconnect 210 and the second master device 240, and a security check is performed in the master-side filter 250, the snoop time ( This has the effect of reducing snoop time or snoop latency.

Components 220 , 230 , 250 , 260 , 270 , and 280 may send or receive signals through cache coherent interconnect 210 .

The first master device 220 transmits the first control signal CTR1 for setting the operation mode of the second master device 240 to a secure mode or a non-secure mode as a cache code. It can be transmitted to the second controller 230 through the runt interconnect 210 . The secure mode may mean a secure operation mode capable of processing data requiring security, and the non-secure mode may mean a non-secure operating mode capable of processing data not requiring security. It is not limited.

The first master device 220 may be implemented as a CPU. For example, the first master device 220 may be a master device having security awareness. The first master device 220 may generate a first snoop request SREQ1 including the first security attribute AT1 and the address ADD. The first security attribute AT1 means information (or data) indicating whether the operation mode of the first master device 220 is a secure mode or a non-secure mode, and the address ADD is the first master device 220 ) may indicate a memory area of the main memory device 300 to be accessed.

The first master device 220 may execute software 222 , and the software 222 may be used to control the operation of the other master devices 240 and/or 270 .

The second controller 230 may set the operation mode of the second master device 240 to a secure mode or a non-secure mode by using the first control signal CTR1 output from the first master device 220. there is. The first control signal CTR1 may be stored in a register 235 included in the second controller 230 .

For example, register 235 may be implemented as a special function register (SFR). The security attribute of the second master device 240, for example, the second security attribute AT2, may be determined according to the first control signal CTR1 stored in the SFR 235. The second security attribute AT2 may be provided to the master-side filter 250 through the transmission line TL. The transmission line TL may be a dedicated transmission line. The second security attribute AT2 may be information (or data) indicating whether the operation mode of the second master device 240 is a secure mode or a non-secure mode.

The second master device 240 may set the operation mode of the second master device 240 to a secure mode or a non-secure mode based on the second security attribute AT2 set in the SFR 235 . The second master device 240 may be implemented as a GPU, GPGPU, or DSP, but is not limited thereto, and may include all masters having a cache therein and capable of memory access. . For example, the second master device 240 may be a master device with non-security awareness or a master device without security awareness.

The master-side filter 250 may be connected between the cache coherent interconnect 210 and the first master device 220 . The master-side filter 250 or 250-1 according to embodiments of the present invention may perform a security search in a snoop operation or a cache snoop operation. Master-side filter 250 may be referred to as a master-side security filter.

Since the master-side filter 250 can perform a secure search during snoop operations, the data processing system 100 including the master-side filter 250 can perform a slave search for every snoop hit (or every cache hit). - can eliminate write-back traffic and memory read request traffic, compared to conventional data processing systems that rely on secure searches performed using side filters 280; There is an effect.

The master-side filter 250 receives the first snoop request (SREQ1) transmitted from the first master device 220 through the cache coherent interconnect 210, and receives the second security attribute of the second master device 240. (AT2) and the first security attribute (AT1) of the first master device 220 included in the first snoop request (SREQ1) are compared with each other, and the address included in the first snoop request (SREQ1) according to the comparison result. It is possible to determine whether to transmit (ADD) to the second master device 240.

For example, the master-side filter 250 transmits the address ADD included in the first snoop request SREQ1 to the second master device when the first security attribute AT1 and the second security attribute AT2 are different from each other. Instead of transmitting to 240 , the cache miss may be directly transmitted (or returned) to the first master device 220 through the cache coherent interconnect 210 .

However, when the first security attribute AT1 and the second security attribute AT2 are equal to each other, the master-side filter 250 converts the address ADD included in the first snoop request SREQ1 to the second master device ( 240).

The second master device 240 determines whether an address matching the address ADD transmitted from the master-side filter 250 exists in the internal cache of the second master device 240, and according to the result of the determination, a cache miss Alternatively, a cache hit may be determined and the determined result may be transmitted to the master-side filter 250 .

Master-side filter 250 performs a first-order security check in a snoop operation. However, the slave-side filter 280 may process a memory access request (eg, a data read request) for the main memory device 300 without performing the primary security search in the snoop operation. For example, the memory access request may be generated by the first master device 220 based on a result of a snoop operation transmitted from the master-side filter 250, for example, a cache miss.

Although the data processing system 100 shown in FIG. 1 includes a slave-side filter 280 and a main memory device 200 for a purpose other than system configuration, a cache for snoop operation considering security. Only coherent interconnect 210 and master-side filter 250 are required.

The third controller 260 may use the second control signal CTR2 output from the first master device 220 to set the operation mode of the third master device 270 to a secure mode or a non-secure mode. there is. The second control signal CTR2 may be stored in a register 265 included in the third controller 260 . Each of the control signals CTR1 and CTR2 may be a flag or a digital signal having at least one bit.

For example, register 265 may be implemented as an SFR. The third security attribute AT3 of the third master device 270 may be determined according to the second control signal CTR2 stored in the SFR 265 . The third security attribute AT3 may be information (or data) indicating whether the operation mode of the third master device 270 is a secure mode or a non-secure mode.

The third master device 270 may set the operation mode of the third master device 270 to a secure mode or a non-secure mode based on the third security attribute AT3 set in the SFR 265 . The third master device 270 may be implemented as a GPU, GPGPU, or DSP, but is not limited thereto. For example, the third master device 270 may be a master device with non-security considerations or a master device without security considerations. For example, the third master device 270 may generate a second snoop request SREQ2 including the third security attribute AT3 and the address.

The master-side filter 250 receives the second snoop request (SREQ2) transmitted from the third master device 270 through the cache coherent interconnect 210, and receives the second security attribute of the second master device 240. (AT2) and the third security attribute (AT3) of the third master device 270 included in the second snoop request (SREQ2) are compared with each other, and according to the comparison result, the security attribute (AT3) included in the second snoop request (SREQ2) is compared. It is possible to determine whether to transmit the address to the second master device 240 .

For example, the master-side filter 250 transfers the address included in the second snoop request SREQ2 to the second master device 240 when the first security attribute AT1 and the third security attribute AT3 are different from each other. A cache miss may be directly transmitted to the third master device 270 through the cache coherent interconnect 210 without transmission to . However, the master-side filter 250 transmits the address included in the second snoop request SREQ2 to the second master device 240 when the first security attribute AT1 and the third security attribute AT3 are equal to each other. can be sent to

The second master device 240 determines whether an address matching the address transmitted from the master-side filter 250 exists in the internal cache of the second master device 240 and, depending on the result of the determination, a cache miss or cache miss. A hit may be determined, and the determined result may be transmitted to the master-side filter 250 .

The main memory device 300 may store firmware and user data necessary for the operation of the controller 200 . For example, the main memory device 300 may be implemented with dynamic random access memory (DRAM).

2 is a block diagram of a master-side filter and a second master device according to an embodiment of the present invention shown in FIG. 1, and FIG. 3 explains the operation of the master-side filter and the second master device shown in FIG. 5 is a flowchart for explaining operations of a master-side filter according to a snoop request output from the first master device of FIG. 1 .

It is assumed that the second security attribute AT2 of the second master device 240 indicates a security mode, and the cache 244 included in the second master device 240 has respective addresses ADD1, ADD3, ADD4, and ADD5 Assume that data (DATA1, DATA3, DATA4, and DATA5) corresponding to are stored.

Referring to FIGS. 1, 2, 3, and 5, the first master device 220 sends a first snoop request (SREQ1) including a first security attribute (AT1) and a first address (ADD=ADD1). may be transmitted to the cache coherent interconnect 210 .

The master-side filter 250 may receive the first snoop request SREQ1 including the first security attribute AT1 and the first address ADD1 through the cache coherent interconnect 210 (S110).

The master-side filter 250 may compare the first security attribute (AT1) and the second security attribute (AT2) (S120). When the first security attribute (AT1) and the second security attribute (AT2) are different (NO in S120), the master-side filter 250 transfers the first address (ADD=ADD1) to the second master device 240. The snoop miss (MISS) may be transmitted to the cache coherent interconnect 210 without being transmitted (S130). A snoop miss (MISS) may mean a cache miss (MISS). Accordingly, the cache miss MISS may be transmitted to the first master device 220 through the cache coherent interconnect 210 .

For example, as shown in case 3 (CASE3) of FIG. 5, the first snoop request SREQ1 includes the third indication bit NSMB and the first address ADD=ADD1. The third indication bit NSMB indicates that the operation mode of the first master device 220 is a non-secure mode, and the third indication bit NSMB indicates the first security attribute AT1. That is, the first security attribute AT1 for the first master device 220 indicates a non-secure mode.

Since the first security attribute AT1 of the first master device 220 indicates a non-secure mode and the second security attribute AT2 of the second master device 240 indicates a secure mode, the master-side filter 250 ) may transmit a snoop miss (MISS) to the cache coherent interconnect 210 without transmitting the first address (ADD=ADD1) to the second master device 240 (S130).

When the first security attribute (AT1) and the second security attribute (AT2) are equal to each other (YES in S120), the master-side filter 250 assigns the first address (ADD=ADD1) to the second master device 240. to the cache controller 242. Accordingly, the cache controller 242 of the second master device 240 may perform a snoop operation for the internal cache line (S140).

For example, as shown in case 1 (CASE1) of FIG. 5, the first snoop request SREQ1 includes the first indication bit SMB and the first address ADD=ADD1. The first indication bit SMB indicates that the operation mode of the first master device 220 is a security mode, and the first indication bit SMB indicates the first security attribute AT1. That is, the first security attribute (AT1) of the first master device 220 indicates a security mode.

The cache controller 242 may determine whether an address matching the first address (ADD=ADD1) exists in the cache 244 . When the address ADD1 matching the first address ADD=ADD1 exists in the cache 244, that is, when a snoop hit (or cache hit) occurs (YES in S150), the cache controller 242 caches ( 244) and transmits the data DATA1 corresponding to the first address (ADD=ADD1) to the master-side filter 250 (S160). The master-side filter 250 transmits data DATA1 corresponding to the first address ADD=ADD1 to the cache coherent interconnect 210 . Data DATA1 transmitted from the master-side filter 250 may be transmitted to the first master device 220 through the cache coherent interconnect 210 .

For example, as shown in case 2 (CASE2) of FIG. 5, the first snoop request SREQ1 includes the second indication bit SMB and the first address ADD=ADD2. A first security attribute AT1 for the first master device 220 indicates a security mode.

The cache controller 242 may determine whether an address matching the first address (ADD=ADD2) exists in the cache 244 . When the address ADD2 matching the first address ADD=ADD2 does not exist in the cache 244, that is, when a cache miss (or snoop miss) occurs (NO in S150), the cache controller 242 may transmit a snoop miss (MISS) to the master-side filter 250 (S130). The master-side filter 250 forwards snoop misses (MISS) to the cache coherent interconnect 210 . The cache miss (MISS) transmitted from the master-side filter 250 may be transmitted to the first master device 220 through the cache coherent interconnect 210 .

When a snoop miss (MISS) occurs according to case 2 (CASE2) of FIG. 5, the first master device 220 generates a memory access request (eg, data read request) including the first address ADD2. The memory access request is sent to the slave-side filter 280 via the cache coherent interconnect 210. The slave-side filter 280 performs a security search on the memory access request, and then, in response to the memory access request including the first address ADD2, stores a memory area corresponding to the first address ADD2. Read the stored data. The read data is transmitted to the first master device 220 through the cache coherent interconnect 210 .

FIG. 4 is a first table for explaining the operation of the master-side filter and the second master device shown in FIG. 1 . 1 to 4, as shown in Table 1 (TABLE1), when the operation mode of the requester (eg, 220 or 270) and the operation mode of the handler (eg, 240) are the same, that is, the security attribute When are equal, the master-side filter 250 may transmit the address included in the snoop request (SREQ1 or SREQ2) transmitted from the requester (eg, 220 or 270) to the cache controller 242. A requester (eg, 220 or 270) may mean a sender, and a handler (eg, 240) may mean a receiver.

However, when the operation mode of the requestor (eg, 220 or 270) is different from that of the handler (eg, 240), that is, when the security attributes do not match, the master-side filter 250 determines whether the requestor (eg, 220 or 240) 270) to the requestor (e.g., 220 or 270) through the cache coherent interconnect 210 to send a snoop miss (MISS) to the cache controller 242 without sending the address included in the sent snoop request (SREQ1 or SREQ2) to the cache controller 242. can transmit

For example, when a first snoop request (SREQ1) is generated by the requestor 220, the two decisions may be performed in sequence. First, the master-side filter 250 performs a security check (or comparison of security attributes AT1 and AT2) on the first snoop request SREQ1 (S120). Second, as a result of the security check, if there is no security issue (or when the security attributes (AT1 and AT2) are the same; YES in S120), the cache controller 242 of the handler (eg 240) ) checks for a cache hit or cache miss (S150).

6 is a block diagram of a master-side filter and a second master device according to the embodiment of the present invention shown in FIG. 1, and FIG. 7 is a snoop request output from the master-side filter shown in FIG. 6 and the second master. These are embodiments for explaining the operations of the master-side filter according to.

Referring to FIGS. 1, 6, and 7 , the master-side filter 250-1 may include a decision logic circuit 252 and a memory device 254 that stores a security attribute look-up table. Although FIG. 6 shows an embodiment in which the master-side filter 250-1 includes the memory device 254, the memory device 254 may be implemented outside the master-side filter 250-1. there is. According to example embodiments, the memory device 254 may be implemented as static random access memory (SRAM). According to example embodiments, since the memory device 254 may be implemented anywhere inside the controller 200 , the memory device 254 may be included in the second master device 240 .

The memory device 254 may store security attributes (SM and NSM) of memory areas corresponding to the respective addresses ADD1 , ADD3 , ADD4 , and ADD5 . In this specification, the memory area may mean the whole of the main memory device 300, a part of the whole, and a line (or a line corresponding to a cache line).

As exemplarily illustrated in FIG. 6 , each memory area corresponding to the respective addresses ADD1 and ADD3 may represent a memory area (eg, a secure memory area) accessible in the secure mode (SM). Also, each memory area corresponding to the addresses ADD4 and ADD5 may represent a memory area (eg, a non-secure memory area) accessible in the non-secure mode (NSM).

The first master device 220 may transmit a first snoop request SREQ1 including a first security attribute AT1 and a first address (ADD=ADD1) to the cache coherent interconnect 210 .

The decision logic circuit 252 of the master-side filter 250-1 generates a first snoop request SREQ1 including the first security attribute AT1 and the first address ADD1 through the cache coherent interconnect 210. It can receive (S210).

The decision logic circuit 252 may compare the first security attribute AT1 and the second security attribute AT2 with each other and determine whether an address matching the first address ADD=ADD1 exists in the memory device 254. Yes (S220). The comparison and the determination may be performed sequentially or in parallel.

When the first security attribute (AT1) and the second security attribute (AT2) are identical to each other and an address matching the first address (ADD=ADD1) exists in the memory device 254 (YES in S220), the decision logic circuit ( 252) may transmit the first address (ADD=ADD1) included in the first snoop request SREQ1 to the second master device 240. The cache controller 242 of the second master device 240 may transmit data DATA1 stored in the cache 244 and corresponding to the first address ADD=ADD1 to the master-side filter 250-1. (S160). The decision logic circuit 252 of the master-side filter 250 - 1 may transmit data DATA1 to the cache coherent interconnect 210 . Data DATA1 transmitted from the master-side filter 250 may be transmitted to the first master device 220 through the cache coherent interconnect 210 .

To describe case 4 (CASE4) and case 5 (CASE5), it is assumed that the second security attribute AT2 of the second master device 240 indicates that the operation mode of the second master device 240 is a security mode.

For example, as shown in case 4 (CASE4) of FIG. 10 , the first snoop request SREQ1 includes the fourth indication bit SMB and the first address ADD=ADD1. The fourth indication bit (SMB) indicates that the operation mode of the first master device 220 is a security mode, and the fourth indication bit (SMB) indicates the first security attribute (AT1). Accordingly, the memory area corresponding to the first address (ADD=ADD1) is a secure memory area accessible in the secure mode (SM).

The first security attribute (AT1) of the first master device 220 indicates the security mode, and the second security attribute (AT2) of the second master device 240 indicates the security mode, and the first address (ADD=ADD1) Since the corresponding memory area is the secure memory area and the memory area corresponding to the address ADD1 stored in the memory device 254 is the secure memory area, the decision logic circuit 252 determines the first snoop request SREQ1 included in the first snoop request SREQ1. The address (ADD=ADD1) may be transmitted to the cache controller 242 of the second master device 240 (YES in S220). A cache hit or a snoop hit occurs according to the operation of the cache controller 242 (S240).

For example, as shown in case 5 (CASE5) of FIG. 10, the first snoop request SREQ1 includes the fifth indication bit SMB and the first address ADD=ADD4. The fifth indication bit (SMB) indicates that the operation mode of the first master device 220 is a security mode, and the fifth indication bit (SMB) indicates the first security attribute (AT1). Accordingly, the memory area corresponding to the first address (ADD=ADD4) is a non-secure memory area accessible in the non-secure operation mode.

A first security attribute (AT1) indicating a security mode and a second security attribute (AT2) indicating the security mode coincide with each other. Since the first security attribute AT1 of the first master device 220 indicates the security mode, the first master device 220 must output an address that can access the secure memory area. However, although the first security attribute (AT1) of the first master device 220 indicates the security mode, the first address (ADD=ADD4) to be accessed by the first master device 220 is a non-secure memory area. instruct

Therefore, the decision logic circuit 252 directly transmits the snoop miss to the cache coherent interconnect 210 without transmitting the first address (ADD=ADD1) to the cache controller 242 of the second master device 240 ( NO of S220 and S230).

To describe case 6 (CASE6) and case 7 (CASE7), it is assumed that the second security attribute AT2 of the second master device 240 indicates a non-secure mode.

For example, as shown in case 6 (CASE6) of FIG. 10 , the first snoop request SREQ1 includes the sixth indication bit NSMB and the first address ADD=ADD4. The sixth indication bit NSMB indicates that the operation mode of the first master device 220 is a non-secure mode, and the sixth indication bit NSMB indicates the first security attribute AT1.

A first security attribute (AT1) indicating the non-secure mode and a second security attribute (AT2) indicating the non-secure mode coincide with each other. In addition, the first address ADD=ADD4 included in the first snoop request SREQ1 indicates a non-secure memory area, and the address ADD4 stored in the memory device 254 indicates a non-secure memory area. . Accordingly, the attribute of the first address (ADD=ADD4) included in the first snoop request (SREQ1) and the attribute of the address (ADD4) stored in the memory device 254 coincide with each other.

The decision logic circuit 252 may transmit the first address ADD4 included in the first snoop request SREQ1 to the cache controller 242 of the second master device 240 . A cache hit or a snoop hit occurs according to the operation of the cache controller 242 .

For example, as shown in case 7 (CASE7) of FIG. 10 , the first snoop request SREQ1 includes the seventh indication bit NSMB and the first address ADD=ADD1. The seventh indication bit NSMB indicates that the operation mode of the first master device 220 is a non-secure mode, and the seventh indication bit NSMB indicates the first security attribute AT1.

The first security attribute AT1 indicating the non-secure mode and the second security attribute AT2 indicating the non-secure mode coincide with each other. However, the first security attribute (AT1) included in the first snoop request (SREQ1) indicates a non-secure mode, and the first address (ADD=ADD1) included in the first snoop request (SREQ1) indicates a non-secure memory area. address ADD1 stored in the memory device 254 indicates a secure memory area. Accordingly, the attribute of the first address (ADD=ADD1) included in the first snoop request SREQ1 and the attribute of the address ADD4 stored in the memory device 254 do not match each other. The decision logic circuit 252 does not transmit the first address (ADD=ADD4) included in the first snoop request SREQ1 to the cache controller 242 of the second master device 240 and transmits the snoop miss to the cache coherent interconnect. It is transmitted to (210) (NO of S220 and S230).

8 is an embodiment of a second table for explaining the operation of the master-side filter and the second master device shown in FIG. Referring to the embodiments shown in FIGS. 6 to 8 , the operation mode of the requester 220 and the operation mode of the handler 240 match each other and correspond to the address ADD included in the first snoop request SREQ1. When the address is present in the memory device 254, a snoop hit occurs. The snoop hit may mean that the cache controller 242 transmits data corresponding to the address ADD output from the decision logic circuit 252 to the decision logic circuit 252 .

For example, the operation mode of the requester 220 is the secure mode (SM), the first address ADD included in the first snoop request SREQ1 indicates a secure memory area, and the operation mode of the handler 240 is the secure mode. and a second address matching the first address ADD is stored in the memory device 254 and the second address indicates a secure memory area, a snoop hit occurs.

However, if the operation mode of the requester 220 is the secure mode (SM), the first address ADD included in the first snoop request SREQ1 indicates a secure memory area, and the operation mode of the handler 240 is the secure mode, When a third address matching the first address ADD is stored in the memory device 254 and the third address points to a non-secure memory area, a snoop miss occurs. When the snoop miss occurs, the decision logic circuit 252 may block transmission of the first address ADD included in the first snoop request SREQ1 to the second master device 240 . That is, the decision logic circuit 252 does not transmit the first address ADD included in the first snoop request SREQ1 to the second master device 240 .

According to embodiments, the decision logic circuit 252 not only determines whether the security attributes of the requester 220 and the security attributes of the handler 240 match, but also determines whether or not the security attributes of the requester 220 match the first snoop request SREQ1 transmitted from the requestor 220. It is determined whether a second address matching the included first address ADD exists in the memory device 254, and according to the determination result, the first address ADD is transmitted to the second master device 240 or the first address ADD is transmitted to the second master device 240. Transmission of the address ADD to the second master device 240 may be blocked.

In this case, the decision logic circuit 252 does not consider whether the attribute of the first address ADD matches the attribute of the second address. That is, the security attributes of the requester 220 and the security attributes of the handler 240 match each other and the second address matches the first address ADD included in the first snoop request SREQ1 transmitted from the requestor 220. When is present in the memory device 254 , the decision logic circuit 252 transmits the first address ADD to the second master device 240 .

According to embodiments, the decision logic circuit 252 not only determines whether the security attributes of the requester 220 and the security attributes of the handler 240 match, but also determines whether or not the security attributes of the requester 220 match the first snoop request SREQ1 transmitted from the requestor 220. It is determined whether the included attribute of the first address ADD matches the attribute of the second address stored in the memory device 254, and the first address ADD is transferred to the second master device 240 according to the result of the determination. Transmission or transmission of the first address ADD to the second master device 240 may be blocked. In this case, the decision logic circuit 252 considers whether the attribute of the first address ADD matches the attribute of the second address.

Here, the attribute of the address may be information (or data) indicating whether a memory area corresponding to the address is a secure memory area or a non-secure memory area.

FIG. 9 is an embodiment of a third table for explaining the operation of the master-side filter and the second master device shown in FIG. 6 . Referring to the embodiments shown in FIGS. 6, 7, and 9 , when the second security attribute AT2 indicates the security mode and the second address stored in the memory device 254 indicates the secure memory area, the first 1 If the first security attribute (AT1) included in the snoop request (SREQ1) indicates a security mode and the first address (ADD) included in the first snoop request (SREQ1) indicates a secure memory area, a snoop hit may occur. there is. At this time, it is assumed that the first address ADD1 and the second address are the same.

However, when the second security attribute AT2 indicates a security mode and the second address stored in the memory device 254 indicates a secure memory area, the first security attribute AT1 included in the first snoop request SREQ1 If the first address ADD, which indicates a secure mode and is included in the first snoop request SREQ1, indicates a non-secure memory area, a snoop miss may occur.

As another example, when the second security attribute AT2 indicates a non-secure mode and the second address stored in the memory device 254 indicates a non-secure memory area, the first snoop request SREQ1 includes the second address. 1 If the security attribute AT1 indicates a non-secure mode and the first address ADD included in the first snoop request SREQ1 indicates a non-secure memory area, a snoop hit may occur.

However, when the second security attribute AT2 indicates a non-secure mode and the second address stored in the memory device 254 indicates a non-secure memory area, the first security attribute included in the first snoop request SREQ1 When (AT1) indicates a non-secure mode and the first address (ADD) included in the first snoop request (SREQ1) indicates a secure memory area, a snoop miss may occur.

The embodiment shown in FIG. 8 shows a method of referring to the attributes of each of the requester 220 and handler 240 and the attribute of the address area (or address) together, and the embodiment shown in FIG. Attributes and addresses How to refer to the attributes of the field (or addresses) are shown.

11 is a diagram conceptually illustrating operation modes of the second master device shown in FIG. 1 and software operations in each of the operation modes. Referring to FIGS. 1 and 11 , the first master device 220 may execute software (or firmware; SW) capable of performing a security mode. Software (SW) executed by the first master device 220 may control the operation of the second master device (240).

The first master device 220 may transmit a first control signal CTR1 for setting the operation mode of the second master device 240 to the security mode to the second controller 230 . The second controller 230 may set the first control signal CTR1 to the SFR 235 . According to the first control signal CTR1 set in the SFR 235, the second security attribute AT2 indicates a security mode.

Software SW may control the cache controller 242 to delete all data stored in the cache 244 . When all data stored in the cache 244 is deleted (CACHE FLUSH1), the second master device 240 may operate in a secure mode under the control of the software (SW). Data may be stored in the cache 244 while the second master device 240 operates in the secure mode.

After that, the first master device 220 may transmit a first control signal CTR1 for setting the operation mode of the second master device 240 to a non-secure mode to the second controller 230 . The second controller 230 may set the first control signal CTR1 to the SFR 235 . According to the first control signal CTR1 set in the SFR 235, the second security attribute AT2 indicates a non-secure mode.

The software SW may control the cache controller 242 to delete all data stored in the cache 244 while the second master device 240 operates in the secure mode. When all data stored in the cache 244 is deleted (CACHE FLUSH2), the second master device 240 may operate in a non-secure mode under the control of the software (SW). Therefore, before (or immediately before) the second master device 240 starts operating in the non-secure mode, all data stored in the cache 244 while operating in the secure mode is deleted, so that the security of the controller 200 This has an enhancing effect.

That is, cache flush operations (CACHE FLUSH1 and CACHE FLUSH2) may be performed at the start (or entry) of the secure operation mode and the end (or exit) of the secure operation mode. Accordingly, all data stored in the cache 244 is deleted. For example, when an attribute is not supported for each address of the cache 244 or for each cache line of the cache 244 or when the attribute is not checked, all data stored in the cache 244 may be deleted as described above. . However, when an attribute is supported for each address of the cache 244 or each cache line of the cache 244 or when the attribute is checked, all data stored in the cache 244 may not be deleted.

As described with reference to FIGS. 1 to 11 , the master-side filter 250 is implemented in the controller 200 for snoop control, and the snoop operation (or the first security search in the snoop operation) is performed on the slave - access to the slave-side filter 280 is no longer required for the snoop operation (or the first security search in the snoop operation) as it is performed in the master-side filter 250 instead of the side filter 280 .

Snoop time or snoop latency may be determined only by signals exchanged between the first master device 220 and the second master device 240 . Accordingly, timing overhead for the snoop operation in the controller 200 including the master-side filter 250 can be eliminated.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached claims.

100: data processing system
200: controller
210: cache coherent interconnect
220: first master or first master device
230: security attribute controller
240: second master or second master device
242: cache controller
244: cache
250, 250-1: Master-side filter
252: decision logic circuit
254: memory device
280: slave-side filter
300: external memory device

Claims (20)

a first master device that has a first security attribute and transmits a snoop request including a first snoop address and a security attribute indicator indicating the first security attribute;
a second master device having a second security attribute; and
Including a master side filter,
The first master device, the second master device, and the master side filter are connected to each other by a cache coherent interconnect,
The master side filter executes a snoop operation by receiving the first snoop request from the first master device through the cache coherent interconnect, and the second security attribute and the first security attribute indicated by the snoop request , and if the first security attribute and the second security attribute are different from each other, it is determined not to transmit the first snoop address to the second master device, and the first security attribute and the second security attribute are An application processor that determines to transmit the first snoop address to the second master device when they are the same. According to claim 1,
the first security attribute indicates a secure mode or a non-secure mode for the first master device; and
The second security attribute indicates a secure mode or a non-secure mode for the second master device. According to claim 2,
When determining not to transmit the first snoop address to the second master device, the master side filter transmits a first cache miss to the cache co Application processor transmitting to the first master device through the runt interconnect. According to claim 3,
The second master device:
a cache for storing at least one address and data corresponding to each of the at least one address; and
comparing the at least one address with the first snoop address when the first snoop address is transmitted from the master side filter, and when identifying an address of the at least one address matching the first snoop address; Data corresponding to the matching address is transmitted to the master side filter, and when there is no address matching the first snoop address among the at least one address, a first snoop indicating a state in which there is no address matching the first snoop address. 2 cache miss to the master side filter. According to claim 4,
wherein the master side filter transmits any one of the first cache miss, the corresponding data, or the second cache miss to the first master device over the cache coherent interconnect. According to claim 2,
When the first master device exits the secure mode and enters the non-secure mode, the first master device deletes all secure data stored in the cache of the second master device while operating in the secure mode. Application processor for further controlling the operation of the second master device. According to claim 1,
Further comprising a controller determining the second security attribute in response to a control signal transmitted from the first master device and transmitting the second security attribute to the master side filter using a transmission line;
Wherein the transmission line is a dedicated transmission line between the controller and the master side filter. According to claim 1,
The master side filter is:
a memory device configured to store the at least one address and a memory area corresponding to each of the at least one address; and
and a decision logic circuit connected to the memory device and configured to compare the first security attribute with the second security attribute and to compare the first snoop address with each of the at least one address. According to claim 8,
When the first security attribute is equal to the second security attribute and the first snoop address is equal to a matching address of the at least one address, the decision logic circuit transmits the first snoop address to the second master device. doing, and
When the first security attribute is different from the second security attribute or the first snoop address and the at least one address are different from each other, the decision logic circuit determines that the first security attribute is different from the second security attribute. An application processor configured to transmit cache misses indicating different states or states in which the first snoop address and the at least one address are different from each other to the first master device through the cache coherent interconnect. According to claim 8,
the memory device further stores a corresponding security attribute for each memory area;
The decision logic circuit determines whether the first security attribute is equal to the second security attribute, and whether the first security attribute corresponding to the memory area indicated by the first snoop address matches one of the at least one address. An application that further determines whether the first security attribute is equal to a second security attribute corresponding to the appearing memory area, and transmits the first snoop address to the second master device only when the first security attribute is equal to the second security attribute. processor. According to claim 1,
A slave side filter connected to the cache coherent interconnect and accessing a main memory device in response to a memory access request received from the first master device;
The slave side filter cannot perform the snoop operation executed by the master side filter. According to claim 1,
Wherein the first master device is a CPU, and the second master device is a GPU, a general purpose computing on GPU (GPGPU), or a digital signal processor (DSP) application processor. It is connected to an external main memory device and includes a first master device having a first security attribute, a second master device having a second security attribute, a master side filter, and a slave side filter, wherein the first master device, the A second master device, the master side filter, and the slave side filter include a controller connected to each other by a cache coherent interconnect,
the first master device transmits a snoop request indicating a first snoop address and a security attribute indicator indicating the first security attribute;
The master side filter is coupled between the cache coherent interconnect and the second master device, and executes a snoop operation by receiving the first snoop request from the first master device through the cache coherent interconnect, and 2 Compare the security attribute with the first security attribute indicated by the snoop request, and determine not to transmit the first snoop address to the second master device when the first security attribute and the second security attribute are different from each other and when the first security attribute and the second security attribute are equal to each other, determine to transmit the first snoop address to the second master device, and
The slave side filter is coupled between the cache coherent interconnect and the main memory device, and controls a memory access operation for the main memory device in response to a memory access received from the first master device through the cache coherent interconnect. A data processing system that performs According to claim 13,
the first security attribute indicates a secure mode or a non-secure mode for the first master device;
the second security attribute indicates a secure mode or a non-secure mode for the second master device; and
When determining not to transmit the first snoop address to the second master device, the master side filter transmits a first cache miss to the cache co A data processing system for transmitting to the first master device through a runt interconnect. 15. The method of claim 14,
The second master device:
a cache for storing at least one address and data corresponding to each of the at least one address; and
comparing the at least one address with the first snoop address when the first snoop address is transmitted from the master side filter, and when identifying an address of the at least one address matching the first snoop address; Data corresponding to the matching address is transmitted to the master side filter, and when there is no address matching the first snoop address among the at least one address, an address matching the first snoop address among the at least one address and a cache controller to transmit a second cache miss indicating a state in which there is no error to the master side filter. According to claim 15,
wherein the master side filter transmits any one of the first cache miss, the corresponding data, or the second cache miss to the first master device over the cache coherent interconnect. 15. The method of claim 14,
When the first master device exits the secure mode and enters the non-secure mode, the first master device deletes all secure data stored in the cache of the second master device while operating in the secure mode. A data processing system for controlling the operation of the second master device. According to claim 13,
Further comprising a controller determining the second security attribute in response to a control signal transmitted from the first master device and transmitting the second security attribute to the master side filter using a transmission line;
The transmission line is a dedicated transmission line between the controller and the master side filter. According to claim 13,
The master side filter is:
a memory device configured to store at least one address and a memory area corresponding to each of the at least one address; and
and a decision logic circuit coupled to the memory device to compare the first security attribute and the second security attribute and to compare the first snoop address and each of the at least one address. A first master device having a first security attribute and transmitting a snoop request including a first snoop address and a security attribute indicator indicating the first security attribute, a second master device having a second security attribute, and a master side filter In the method of operating an application processor, wherein the first master device, the second master device, and the master side filter are connected to each other by a cache coherent interconnect,
sending a snoop request including a first snoop address and a security attribute indicator indicating the first security attribute from the first master device to the master side filter via the cache coherent interconnect; and
Executing a snoop operation in response to the snoop request using the master side filter;
The step of executing the snoop action is:
comparing the second security attribute with the first security attribute; and
When the first security attribute and the second security attribute are equal to each other, the first snoop address is transmitted to the second master device, and when the first security attribute and the second security attribute are different from each other, the first snoop address is transmitted to the second master device. and transmitting a first cache miss indicating a state in which an attribute and the second security attribute are different from each other to the first master device through the cache coherent interconnect.

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