KR102468858B1 - Substrate for display and display including the same - Google Patents

Abstract

The present invention relates to a substrate for a display device and a display device including the same. The substrate for a display device according to the present invention includes a first thin film transistor having an oxide semiconductor layer, a second thin film transistor having a polycrystalline semiconductor layer, and a second thin film transistor having a polycrystalline semiconductor layer. It includes first and second gate insulating patterns disposed between the gate electrode of the thin film transistor and the polycrystalline semiconductor layer, and the first and second gate insulating patterns are disposed between the polycrystalline semiconductor layer and the second gate electrode so as to overlap the second gate electrode. are sequentially stacked on, and the first gate insulating pattern has a higher hydrogen content than the second gate insulating pattern.

Description

Substrate for display device and display device including the same

The present invention relates to a substrate for a display device and a display device including the same, and more particularly, to a substrate for a display device capable of realizing low power consumption and a large area, and a display device including the same.

BACKGROUND OF THE INVENTION [0002] Video display devices, which implement various information on a screen, are a core technology in the information and communication era, and are developing toward a thinner, lighter, portable and high-performance direction. Accordingly, a flat panel display device capable of reducing the weight and volume, which are disadvantages of a cathode ray tube (CRT), is in the spotlight.

These flat panel displays include liquid crystal display devices (LCDs), plasma display panels (PDPs), organic light emitting display devices (OLEDs), and electrophoretic displays (electrophoretic displays). Display Device: ED), etc.

Such a flat panel display device includes a substrate for a display device on which thin film transistors are formed in pixels. In order to apply such display devices to portable devices, low power consumption is required. However, it is difficult to implement low power consumption with the technologies related to display devices developed to date.

The present invention is to solve the above problems, and the present invention provides a substrate for a display device capable of realizing low power consumption and a large area and a display device including the same.

In order to achieve the above object, a substrate for a display device according to the present invention is provided between a first thin film transistor having an oxide semiconductor layer, a second thin film transistor having a polycrystalline semiconductor layer, and a gate electrode of the second thin film transistor and the polycrystalline semiconductor layer. The first and second gate insulating patterns are sequentially stacked between the polycrystalline semiconductor layer and the second gate electrode so as to overlap the second gate electrode, and the first gate insulating pattern is positioned on the first gate insulating layer. The pattern has a higher hydrogen content than the second gate insulating pattern.

According to the present invention, low power consumption and low voltage can be obtained by applying a thin film transistor positioned in a display area to a thin film transistor having an oxide semiconductor layer. In addition, the present invention can reduce the number of driving integrated circuits and reduce the bezel area by applying a thin film transistor having a polycrystalline semiconductor layer to the gate driver and the multiplexer located in the non-display area. In addition, since the interlayer insulating film is located between the oxide semiconductor layer and each of the first source and first drain electrodes in the present invention, the capacitance value of the parasitic capacitor of the first thin film transistor is the parasitic capacitor of the back channel etch type TFT can be reduced from the capacity of In addition, since the interlayer insulating film is positioned on the oxide semiconductor layer according to the present invention, it is possible to prevent the oxide semiconductor layer from being damaged during patterning of the first source and first drain electrodes. In addition, in the present invention, the source and drain contact holes and the storage hole are formed through the same mask process. Accordingly, the organic light emitting diode display according to the present invention can reduce the total number of mask processes per mask process compared to the prior art, thereby improving productivity and reducing cost.

1 is a cross-sectional view illustrating a substrate for a display device according to a first embodiment of the present invention.
2 is a block diagram illustrating a display device according to the present invention.
FIG. 3 is a cross-sectional view illustrating a liquid crystal display device having the display substrate shown in FIG. 1 .
FIG. 4 is a cross-sectional view illustrating an organic light emitting diode display having the display substrate shown in FIG. 1 .
5A to 5L are cross-sectional views for explaining a manufacturing method of the organic light emitting diode display shown in FIG. 4 .

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a substrate for a display device according to the present invention.

The display device substrate shown in FIG. 1 includes first and second thin film transistors 100 and 150 .

The first thin film transistor 100 having a bottom gate structure includes a first gate electrode 106 , an oxide semiconductor layer 104 , a first source electrode 108 , and a first drain electrode 110 .

The first gate electrode 106 is formed on the substrate 101 and overlaps the oxide semiconductor layer 106 with the buffer layer 102 therebetween. The first gate electrode 106 is formed of the same material as the light blocking layer 152 on the same plane as the light blocking layer 152 positioned below the second thin film transistor 150 . Accordingly, since the first gate electrode 106 and the light blocking layer 152 can be formed through the same mask process, mask processes can be reduced.

The oxide semiconductor layer 104 is formed on the buffer layer 102 to overlap the first gate electrode 106 to form a channel between the first source and first drain electrodes 108 and 110 . The oxide semiconductor layer 104 is formed of an oxide containing at least one metal selected from among Zn, Cd, Ga, In, Sn, Hf, and Zr. Since the first thin film transistor 100 including the oxide semiconductor layer 104 has higher charge mobility and lower leakage current characteristics than the second thin film transistor 150 including the polycrystalline semiconductor layer 154, it is turned on. It is preferable to apply it to a switching thin film transistor that maintains a short on time and a long off time. The oxide semiconductor layer 104 is preferably located above the first gate electrode 106 so as to effectively secure the stability of the device.

The first source electrode 108 is connected to the exposed oxide semiconductor layer 104 through a first source contact hole 124S passing through the interlayer insulating layer 116 . The first drain electrode 110 is connected to the exposed oxide semiconductor layer 104 through a first drain contact hole 124D passing through the interlayer insulating layer 116 .

In this case, the interlayer insulating film 116 positioned between the first source and first drain electrodes 108 and 110 is formed to cover the oxide semiconductor layer 104 and serves as an etch stopper. Accordingly, the interlayer insulating film 116 positioned between the first source and first drain electrodes 108 and 110 prevents the oxide semiconductor layer 104 from being damaged when the first source and first drain electrodes 108 and 110 are etched.

In addition, an interlayer insulating film 116 is positioned between each of the first source and first drain electrodes 108 and 110 and the oxide semiconductor layer 104 . Accordingly, the distance between each of the first source and first drain electrodes 108 and 110 and the first gate electrode 106 is related to the back channel etch type TFT structure in which the source and drain electrodes are formed directly on the semiconductor layer. far compared to Accordingly, the capacitance value of the parasitic capacitor formed between each of the first source and first drain electrodes 108 and 110 and the first gate electrode 106 is higher than the capacitance value of the parasitic capacitor of the back channel etch type TFT. can be reduced

The first source and first drain electrodes 108 and 110 are formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be a single layer or multiple layers made of any one of neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

The second thin film transistor 150 having a top gate structure is disposed on the substrate 101 to be spaced apart from the first thin film transistor 100 . The second thin film transistor 150 includes a polycrystalline semiconductor layer 154 , a second gate electrode 156 , a second source electrode 158 , and a second drain electrode 160 .

A polycrystalline semiconductor layer 154 is formed on the buffer layer 102 covering the substrate 101 . The polycrystalline semiconductor layer 154 includes a channel region 154C, a lightly doped drain (LDD) 154L, a source region 154S, and a drain region 154D. The channel region 154C overlaps the second gate electrode 156 with the first gate insulating layer 112 interposed therebetween to form a channel between the second source and second drain electrodes 158 and 160 . The source region 154S is electrically connected to the second source electrode 158 through the second source contact hole 164S. The drain region 154D is electrically connected to the second drain electrode 160 through the second drain contact hole 164D. The LDD region 154L is positioned between each of the source region 154S and the drain region 154D and the channel region 154C, and does not overlap the second gate electrode 156 . Since the polycrystalline semiconductor layer 154 has high mobility, low energy consumption, and excellent reliability, it is suitable for applications in a gate driver driving a gate line and/or a multiplexer (MUX).

The second gate electrode 156 overlaps the channel region 154C of the polycrystalline semiconductor layer with the first and second gate insulating patterns 112 and 114 interposed therebetween. The second gate electrode 156 is made of the same material as the first gate electrode 106, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), or nickel. It may be a single layer or multiple layers made of any one of (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

The first and second gate insulating patterns 112 and 114 are sequentially stacked between the polycrystalline semiconductor layer 154 and the second gate electrode 156 to overlap the second gate electrode 156 .

The first gate insulating pattern 112 is positioned on the polycrystalline semiconductor layer 154 and is formed of an inorganic insulating layer having a higher hydrogen particle content than the second gate insulating pattern 114 , for example, silicon nitride (SiNx). During the hydrogenation process, hydrogen particles included in the first gate insulating pattern 112 diffuse into the polycrystalline semiconductor layer 154 to fill the gaps in the polycrystalline semiconductor layer with hydrogen. Accordingly, since the polycrystalline semiconductor layer 154 can be stabilized, degradation of the characteristics of the second thin film transistor 150 can be prevented.

The second gate insulating pattern 114 is formed on the first gate insulating pattern 112 with an inorganic insulating layer having a low hydrogen particle content, for example, silicon oxide (SiOx). The second gate insulating pattern 114 prevents hydrogen of the polycrystalline semiconductor layer 154 from diffusing into the oxide semiconductor layer 104 during a heat treatment process of the oxide semiconductor layer 104 .

The second source electrode 158 is formed of the same material on the same plane as the first source electrode 108, and the polycrystalline semiconductor layer 154 is formed through the second source contact hole 164S penetrating the interlayer insulating film 116. It is connected to the source region 154S of .

The second drain electrode 160 is formed of the same material on the same plane as the first drain electrode 110, and the polycrystalline semiconductor layer 154 is formed through the second drain contact hole 164D penetrating the interlayer insulating film 116. is connected to the drain region 154D of

After the process of activating and hydrogenating the polycrystalline semiconductor layer 154 of the second thin film transistor 150, the oxide semiconductor layer 104 of the first thin film transistor 100 is formed. Accordingly, since the oxide semiconductor layer 104 is not exposed to the high-temperature atmosphere of the activation and hydrogenation process of the polycrystalline semiconductor layer 154, damage to the oxide semiconductor layer 104 can be prevented and reliability is improved.

Such a substrate for a display device according to the present invention can be applied to a display device as shown in FIG. 2 .

The display device shown in FIG. 2 includes a display panel 180, a gate driver 182 driving the gate line GL of the display panel 180, and driving the data line DL of the display panel 180. A data driver 184 is provided.

The display panel 180 includes a display area AA and a non-display area NA surrounding the display area AA.

In the display area AA of the display panel 180, a plurality of pixels positioned at intersections of the gate line GL and the data line DL are arranged in a matrix form. Each of the plurality of pixels has at least one of the first and second thin film transistors 100 and 150 and a light control element.

A gate driver 182 is disposed in the non-display area NA. The gate driver 182 is configured using the second thin film transistor 150 having the polycrystalline semiconductor layer 154 . At this time, the second thin film transistor 150 of the gate driver 182 is simultaneously formed in the same process as the first and second thin film transistors 100 and 150 of the display area AA.

Meanwhile, a multiplexer 186 may be disposed between the data driver 184 and the data line DL. The multiplexer 186 divides the data voltage from the data driver 184 into a plurality of data lines DL in time division, thereby reducing the number of output channels of the data driver 184, thereby forming a data driving integrated circuit constituting the data driver. can reduce the number of This multiplexer 186 is constructed using the second thin film transistor 150 having the polycrystalline semiconductor layer 154 . At this time, the second thin film transistor 150 of the multiplexer 186 together with the second thin film transistor 150 of the gate driver 182 and the first and second thin film transistors 100 and 150 of the display area AA It can be formed directly on a substrate.

Such display devices include the liquid crystal display shown in FIG. 3 having a liquid crystal layer as a light control element for controlling light emitted to the outside, and the organic light emitting diode display shown in FIG. 4 having a light emitting element as a light control element. It can be applied to a display device requiring a thin film transistor.

The liquid crystal display shown in FIG. 3 includes first and second thin film transistors 100 and 150, a pixel electrode 172 connected to the first thin film transistor 100, and a common electrode forming an electric field with the pixel electrode 172 ( 174) and a storage capacitor 140.

The first thin film transistor 100 having the oxide semiconductor layer 104 is applied to the thin film transistor connected to the pixel electrode 172 positioned in the display area AA.

The second thin film transistor 150 having the polycrystalline semiconductor layer 154 is applied to a transistor of at least one driving circuit of a gate driver and a multiplexer located in the non-display area NA.

The storage capacitor 140 includes first and second storage capacitors. The first storage capacitor includes a storage lower electrode 142 and a storage intermediate electrode 144 overlapping with a buffer layer 102 interposed therebetween. The second storage capacitor includes a storage intermediate electrode 144 and a storage upper electrode 146 overlapping with a passivation layer 118 interposed therebetween.

The storage lower electrode 142 is formed of the same material on the same layer as the light blocking layer 152, the storage intermediate electrode 144 is formed of the same material on the same layer as the polycrystalline semiconductor layer 154, and the storage upper electrode 146 ) is formed of the same material as the pixel electrode 172 on the passivation layer 118 and is exposed through the storage contact hole 168 penetrating the planarization layer 128 to be electrically connected to the pixel electrode 172 .

Here, the storage intermediate electrode 144 is exposed through the storage hole 148 penetrating the interlayer insulating film 116 and overlaps the storage upper electrode 146 with the protective film 118 formed of SiNx interposed therebetween. Accordingly, the storage intermediate electrode 144 is overlapped with the storage upper electrode 146 with the passivation layer 118 formed of SiNx having a higher permittivity than the interlayer insulating film 116 formed of SiOx therebetween, so that the second dielectric constant is proportional to the dielectric constant. 2 The capacitance value of the storage capacitor increases.

In addition, since the storage intermediate electrode 144 made of the same material as the polycrystalline semiconductor layer 154 is formed on the same layer (buffer layer 102) as the oxide semiconductor layer 104, the protective film of the conventional multi-layer structure is composed of only a single layer. It is possible.

Specifically, since the conventional multi-layered passivation layer includes a first passivation layer for protecting an oxide semiconductor layer and a second passivation layer positioned between electrodes of a storage capacitor, material costs increase and structures and processes become complicated.

On the other hand, the oxide semiconductor layer 104 of the present invention is protected by the interlayer insulating film 116 formed of SiOx without hydrogen particles compared to SiNx containing hydrogen particles. In this case, since the oxide semiconductor layer 104 is not affected by hydrogen, it is possible to prevent the threshold voltage of the first thin film transistor 100 from fluctuating, thereby improving device stability. As described above, in the present invention, since the oxide semiconductor layer 104 is protected using the interlayer insulating film 116, a separate protective film for protecting the oxide semiconductor layer 104 is not required, so the structure and process are simplified compared to the prior art. .

The pixel electrode 172 is connected to the first drain electrode 110 of the first thin film transistor 100 through the pixel contact hole 120 . Accordingly, the data signal from the data line DL is supplied to the pixel electrode 172 through the first thin film transistor 100 .

The common electrode 174 is formed to have a plurality of slits on the second passivation layer 138 formed to cover the pixel electrode 172 . When a common voltage is supplied to the common electrode 174, the common electrode 174 forms a fringe electric field with the pixel electrode 172, and the liquid crystal molecules of the liquid crystal layer, which is the light control element, rotate due to dielectric anisotropy. will do In addition, the light transmittance passing through the pixel area is changed according to the degree of rotation of liquid crystal molecules, which are light control elements, so that gray levels are implemented.

The organic light emitting diode display shown in FIG. 4 includes first and second thin film transistors 100 and 150 , a light emitting element 130 connected to the first thin film transistor 100 , and a storage capacitor 140 .

The first thin film transistor 100 having the oxide semiconductor layer 104 includes a switching transistor for switching a data voltage written in each pixel located in the display area AA, and a driving transistor connected to each light emitting element 130. is applied as In addition, the first thin film transistor 100 having the oxide semiconductor layer 104 is applied to the switching transistor of each pixel located in the display area AA, and the second thin film transistor 150 having the polycrystalline semiconductor layer 154 It may also be applied to a driving transistor of each pixel positioned in the display area AA.

The second thin film transistor 150 having the polycrystalline semiconductor layer 154 is applied as a transistor of at least one driving circuit of a gate driver and a multiplexer located in the non-display area NA.

The storage capacitor 140 includes a first capacitor composed of the storage lower electrode 142 and the storage intermediate electrode 144, and a second storage capacitor composed of the storage intermediate electrode 144 and the storage upper electrode 146.

The storage upper electrode 146 is formed of the same material on the same layer as the auxiliary electrode 122 and is electrically connected to the anode electrode 122 .

Here, the storage upper electrode 146 is overlapped with the storage intermediate electrode 144 with the passivation layer 118 formed of SiNx having a higher dielectric constant than the interlayer insulating layer formed of SiOx, thereby forming a second storage capacitor proportional to the dielectric constant. The capacity value will increase.

In addition, the storage intermediate electrode 144 made of the same material as the polycrystalline semiconductor layer 154 and the oxide semiconductor layer 104 are formed on the same layer (buffer layer 102). Accordingly, the oxide semiconductor layer 104 is protected by the interlayer insulating film 116 formed of SiOx without hydrogen particles compared to SiNx containing hydrogen particles. In this case, since the oxide semiconductor layer 104 is not affected by hydrogen, it is possible to prevent the threshold voltage of the first thin film transistor 100 from fluctuating, thereby improving device stability. As described above, in the present invention, since the oxide semiconductor layer 104 is protected using the interlayer insulating film 116, a separate protective film for protecting the oxide semiconductor layer 104 is not required, so the structure and process are simplified compared to the prior art. .

The light emitting element 130 includes a first electrode 132 connected to the first drain electrode 110 of the first thin film transistor 100, an organic light emitting layer 134 formed on the first electrode 132, and an organic A second electrode 136 formed on the light emitting layer 134 is provided.

The first electrode 132 is connected to the exposed first drain electrode 110 through the pixel contact hole 120 penetrating the passivation layer 118 and the planarization layer 128 . In the case of a top emission type organic light emitting display device, the first electrode 132 is formed to include a metal material having high reflective efficiency. For example, the first electrode 132 is formed of a metal layer including aluminum (Al), silver (Ag), APC (Ag; Pb; Cu), or the like.

The organic light emitting layer 134 is formed on the first electrode 132 of the light emitting region provided by the bank 138 . The organic light-emitting layer 134 is formed by stacking a hole-related layer, a light-emitting layer, and an electron-related layer in the order or reverse order on the first electrode 132 .

The second electrode 136 is formed as a single body so as to cover the entire surface of the display area on the organic light emitting layer 134 . In the case of a top emission organic light emitting display device, the second electrode 136 is formed of a transparent conductive oxide (TCO). For example, the first electrode 132 is formed of a transparent conductive layer such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

As such, in the present invention, the first thin film transistor 100 having the oxide semiconductor layer 104 is applied to the switching element of each pixel. The first thin film transistor 100 having the oxide semiconductor layer 104 has a lower off current than the second thin film transistor 150 having the polycrystalline semiconductor layer 154 . Accordingly, the present invention can reduce power consumption by lowering the frame frequency in a still image or an image having a slow data update cycle. In addition, since the oxide semiconductor layer 104 of the first thin film transistor has excellent saturation characteristics, it is easy to lower the voltage.

In addition, in the present invention, the second thin film transistor 150 having the polycrystalline semiconductor layer 154 is applied to the driving element of each pixel and the driving element of the driving circuit. Such a polycrystalline semiconductor layer has higher mobility (more than 100 cm 2 /Vs), low energy consumption and excellent reliability compared to the oxide semiconductor layer, so it can be applied to a gate driver and/or a multiplexer (MUX).

5A to 5L are cross-sectional views illustrating a manufacturing method of the organic light emitting diode display shown in FIG. 4 .

Referring to FIG. 5A , a light blocking layer 152 , a first gate electrode 106 of a first thin film transistor, and a lower storage electrode 142 are formed on a substrate 101 .

Specifically, an opaque metal layer is formed on the substrate 101 through a deposition process. Then, the opaque metal layer is patterned through a photolithography process and an etching process to form the light blocking layer 152 , the first gate electrode 106 of the first thin film transistor, and the storage lower electrode 142 .

Referring to FIG. 5B , a buffer film 102 is formed on the substrate 101 on which the light blocking layer 152, the first gate electrode 106, and the storage lower electrode 142 are formed, and a polycrystalline semiconductor layer 154 is formed thereon. ) and the storage intermediate electrode 144 are formed.

Specifically, LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), etc. Through the method, the buffer film 102 and the amorphous silicon thin film are formed. Then, it is formed into a polycrystalline silicon thin film by crystallizing the amorphous silicon thin film. Further, the polycrystalline semiconductor layer 154 and the storage intermediate electrode 144 are formed in a pure polycrystalline silicon state by patterning the polycrystalline silicon thin film through a photolithography process and an etching process.

Then, a photoresist pattern is formed on each of the storage intermediate electrode 144 and the channel region 154C of the polycrystalline semiconductor layer to cover them. The LDD region 154L of the polycrystalline semiconductor layer 154 is formed by selectively implanting n-type or p-type impurities at a low concentration into the polycrystalline semiconductor layer using the photoresist pattern as a mask. Then, a photoresist pattern is formed on the polycrystalline semiconductor layer to cover the polycrystalline semiconductor layer. By selectively injecting n-type or p-type impurities into the storage intermediate electrode 144 using the photoresist pattern as a mask, the storage intermediate electrode 144 has conductivity characteristics.

Referring to FIG. 5C , first and second gate insulating patterns 112 and 114 and a second gate electrode 156 are formed on the substrate 101 on which the polycrystalline semiconductor layer 154 and the storage intermediate electrode 144 are formed. .

Specifically, first and second gate insulating films are sequentially formed on the substrate 101 on which the polycrystalline semiconductor layer 154 and the storage intermediate electrode 144 are formed, and a gate metal layer is formed thereon by a deposition method such as sputtering. . As the first gate insulating layer, an inorganic insulating layer containing a large amount of hydrogen particles, such as SiNx, is used, and as the second gate insulating layer, an inorganic insulating layer containing no hydrogen particles, such as SiOx, is used. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer or as a multilayer structure using these materials. Then, the gate metal layer and the first and second gate insulating films are simultaneously patterned through a photolithography process and an etching process, so that the second gate electrode 156 and the first and second gate insulating patterns 112 and 114 are formed in the same pattern. do. At this time, the line width of the second gate electrode 156 and the first and second gate insulating patterns 112 and 114 is larger than that of the channel region 154C of the polycrystalline semiconductor layer 154 .

Then, by implanting n-type or p-type impurities into the polycrystalline semiconductor layer 154 using the second gate electrode 106 as a mask, the source region 154S and the drain region 154D of the polycrystalline semiconductor layer 154 are formed. is formed Then, the polycrystalline semiconductor layer 154 is activated and hydrogenated by heat-treating the substrate on which the source region 154S and the drain region 154D of the polycrystalline semiconductor layer 154 are formed.

Referring to FIG. 5D , an oxide semiconductor layer 104 is formed on the substrate 101 on which the first and second gate insulating patterns 112 and 114 and the second gate electrode 156 are formed.

Specifically, an oxide semiconductor material is coated on the entire surface of the substrate 101 on which the first and second gate insulating patterns 112 and 114 and the second gate electrode 156 are formed. Then, the oxide semiconductor layer 104 is formed by patterning the oxide semiconductor material through a photolithography process and an etching process.

Referring to FIG. 5E , first source and first drain contact holes 124S and 124D and second source and second drain contact holes 154S and 154D are formed on the substrate 101 on which the oxide semiconductor layer 104 is formed. and an interlayer insulating film 116 having a storage hole 148 is formed.

Specifically, an interlayer insulating film 116 is formed on the substrate 101 on which the oxide semiconductor layer 104 is formed by a deposition method such as PECVD. Then, the interlayer insulating film 116 is patterned through a photolithography process and an etching process to form the first source and first drain contact holes 124S and 124D and the second source and second drain contact holes 154S and 154D. , a storage hole 148 is formed.

Referring to FIG. 5F , an interlayer insulating layer 116 having first source and first drain contact holes 124S and 124D, second source and second drain contact holes 154S and 154D, and a storage hole 148 First and second source electrodes 108 and 158 and first and second drain electrodes 110 and 160 are formed on the top.

Specifically, sputtering is performed on the interlayer insulating layer 116 having the first source and first drain contact holes 124S and 124D, the second source and second drain contact holes 154S and 154D, and the storage hole 148. The data metal layer is formed by a deposition method such as or the like. As the data metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer or as a multilayer structure using these materials. Then, first and second source electrodes 108 and 158 and first and second drain electrodes 110 and 160 are formed on the interlayer insulating layer 116 by patterning the data metal layer through a photolithography process and an etching process.

Referring to FIG. 5G , a protective layer 118 having an auxiliary contact hole 126 is formed on the interlayer insulating layer 116 on which the first and second source electrodes 108 and 158 and the first and second drain electrodes 110 and 160 are formed. do.

Specifically, a passivation layer 118 is formed on the interlayer insulating layer 116 on which the first and second source electrodes 108 and 158 and the first and second drain electrodes 110 and 160 are formed. An inorganic insulating material such as SiOx or SiNx is used as the passivation layer 118 . Then, the protective layer 118 is patterned through a photolithography process and an etching process, thereby forming an auxiliary contact hole 126 .

Referring to FIG. 5H , the auxiliary electrode 122 and the storage upper electrode 148 are formed on the passivation layer 118 having the auxiliary contact hole 126 .

An auxiliary metal layer is formed on the protective layer 118 having the auxiliary contact hole 126 . As the auxiliary metal layer, a highly conductive metal such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used. Then, the auxiliary electrode 122 and the storage upper electrode 148 are formed by patterning the auxiliary metal layer through a photolithography process and an etching process.

Referring to FIG. 5I , a planarization layer 128 having a pixel contact hole 120 is formed on the passivation layer 118 on which the auxiliary electrode 122 and the upper storage electrode 148 are formed.

Specifically, the planarization layer 128 is formed by coating an organic layer such as photoacrylic on the protective layer 118 on which the auxiliary electrode 122 and the upper storage electrode 148 are formed. Then, the pixel contact hole 120 is formed by patterning the planarization layer 128 through a photolithography process.

Referring to FIG. 5J , an anode electrode 132 is formed on the planarization layer 128 having the pixel contact hole 120 .

Specifically, a metal material such as ITO/Ag alloy/ITO is sequentially deposited on the planarization layer 128 having the pixel contact hole 120 by a deposition method such as sputtering. Then, the anode electrode 132 is formed by patterning the metal material through a photolithography process and an etching process.

Referring to FIG. 5K , a bank 138 is formed on the substrate 101 on which the anode electrode 132 is formed.

Specifically, an organic insulating material for a bank is applied on the substrate 101 on which the anode electrode 132 is formed. The organic insulating material for the bank is made of, for example, a polyimide-based resin or an acrylic-based resin. Then, when the organic insulating material is a photosensitive material, the organic insulating material is patterned through a photolithography process, or when the organic insulating material is a non-photosensitive material, the organic insulating material is patterned through a photolithography process and an etching process. A bank 138 is formed. Since the bank 138 is formed to cover the side surface of the anode electrode 132, corrosion of the anode electrode 132 can be prevented.

Referring to FIG. 5L , an organic emission layer 134 and a cathode electrode 136 are sequentially formed on the substrate 101 on which the bank 138 is formed.

Specifically, the organic light emitting layer 134 is formed on the anode electrode 132 exposed by the bank 138 . Then, a cathode electrode 136 is formed on the substrate 101 on which the organic light emitting layer 134 is formed.

As such, in the present invention, the source and drain contact holes 124S, 124D, 164S, and 164D and the storage hole 148 are formed through the same mask process. Accordingly, the organic light emitting diode display according to the present invention can reduce the total number of mask processes per mask process compared to the prior art, thereby improving productivity and reducing cost.

Meanwhile, in the present invention, although the auxiliary electrode 122 is connected to the anode electrode 132 as an example, an auxiliary electrode connected to the cathode electrode 136 may be further provided. A resistance component of the cathode electrode 136, which increases as the area of the organic light emitting diode display becomes larger, can be reduced by the auxiliary electrode.

The above description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed by the claims below, and all techniques within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100,150: thin film transistor 104,154: semiconductor layer
106,156: gate electrode 108,158: source electrode
110,160: drain electrode 112,114: gate insulating pattern
148: storage hall

Claims (9)

a light blocking layer disposed on the substrate;
a first thin film transistor having a first gate electrode positioned on the same plane as the light blocking layer and an oxide semiconductor layer;
a second thin film transistor having a polycrystalline semiconductor layer positioned on the same plane as the oxide semiconductor layer and a second gate electrode positioned on the polycrystalline semiconductor layer;
First and second gate insulating patterns sequentially stacked between the polycrystalline semiconductor layer and the second gate electrode so as to overlap the second gate electrode,
The first gate insulating pattern has a higher hydrogen content than the second gate insulating pattern. According to claim 1,
an interlayer insulating film disposed to cover the second gate electrode, the oxide semiconductor layer, and the polycrystalline semiconductor layer;
The first thin film transistor
The first gate electrode positioned below the oxide semiconductor layer, and first source and first drain electrodes connected to the oxide semiconductor layer through first source and first drain contact holes penetrating the interlayer insulating film, ,
The second thin film transistor
a second gate electrode and second source and second drain electrodes connected to the polycrystalline semiconductor layer through second source and second drain contact holes penetrating the interlayer insulating film;
The first source and first drain electrodes and the second source and second drain electrodes are disposed on the same plane as the display device substrate. According to claim 2,
a storage lower electrode made of the same material on the same plane as the light blocking layer;
a storage intermediate electrode overlapping the storage lower electrode with a buffer layer interposed therebetween, made of the same material as the polycrystalline semiconductor layer, and positioned on the same plane as the oxide semiconductor layer;
Further comprising a storage upper electrode overlapping the storage intermediate electrode with a protective layer interposed therebetween;
The interlayer insulating film has a storage hole exposing the storage intermediate electrode. According to claim 3,
The protective film is made of a material having a higher dielectric constant than the interlayer insulating film,
The interlayer insulating film is a substrate for a display device made of a material having a lower hydrogen content than the protective film. According to claim 4,
The material of the first gate insulating pattern and the protective layer is SiNx,
The material of the second gate insulating pattern and the interlayer insulating layer is SiOx. a display device substrate according to any one of claims 1 to 5;
A display device comprising a light control element connected to one of the first and second thin film transistors and controlling light emitted to the outside. According to claim 6,
The first thin film transistor is located in a display area where a plurality of pixels are disposed,
The second thin film transistor is positioned in a non-display area surrounding the display area. According to claim 7,
a gate driver located in the non-display area and driving a gate line of the display area;
a data driver driving data lines of the display area;
a multiplexer for distributing the data voltage from the data driver to the data line;
The second thin film transistor is included in at least one of the multiplexer and the gate driver. According to claim 7,
The light control element is any one of a light emitting element and a liquid crystal layer located in the display area.

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