KR102459067B1 - Enhancement-mode semiconductor device - Google Patents

Abstract

The present invention relates to an E-mode semiconductor device capable of improving operating characteristics as a switching device by facilitating adjustment of threshold voltage and on-resistance,
An E-mode semiconductor device according to an embodiment of the present invention,
Board; a buffer layer formed on the substrate and doped with a first concentration; a body layer formed on the buffer layer and doped with a second concentration greater than the first concentration; and a channel layer formed on the body layer, doped with a third concentration greater than the second concentration, and including a recess in which a gate electrode is formed.

Description

E-mode semiconductor device {Enhancement-mode semiconductor device}

The present invention relates to an E-mode semiconductor device capable of improving operating characteristics as a switching device by facilitating adjustment of a threshold voltage and an on-resistance.

β-Ga ₂ O ₃ is a material property with a large energy bandgap of 4.9 eV, and is very popular as a next-generation semiconductor material for power devices with “high withstand voltage, low loss, and low on-resistance” characteristics. Considering the breakdown voltage characteristics, it has a very high characteristic of 8 MV/cm, so it is expected to be used in industrial fields with high rated voltage.

Due to the characteristics of oxide semiconductors, the electron mobility is about 300 cm ² /(V s), which is relatively low compared to other semiconductors. It has about 4 to 5 times more properties than GaN and SiC, so it is a material that is in the spotlight as a next-generation power semiconductor.

In order to use a semiconductor device using an existing β-Ga ₂ O ₃ material as a power switching device, a normally-off (E-mode) operation is required. However, β-Ga ₂ O ₃ is difficult to implement E-mode (enhancement-mode) having an inversion channel because P-type doping or ion implantation is still technically difficult, and most of the D-mode (depletion-mode) ) is reported as a FET technology in operation.

A semiconductor device having a D-mode (hereinafter, a D-mode semiconductor device) will be described with reference to FIGS. 1 and 2 . FIG. 1 is a cross-sectional view illustrating a semiconductor device having a D-mode, and FIG. 2 is a graph showing output current-voltage characteristics of the semiconductor device shown in FIG. 1 .

1 , a conventional D-mode semiconductor device includes a substrate 10a, a buffer layer 20a formed on the substrate, a channel layer 30a formed on the buffer layer, and a channel layer 30a formed on the substrate 10a. It includes an insulating layer 40a, source (S) and drain electrodes (D), and a gate electrode (G) formed on the insulating layer. An ohmic contact layer 60a is formed between the channel layer 30a and the source (S) and drain electrodes (D). A passivation layer 50a for protecting a device is formed on the insulating layer 40a, the source S, the drain electrode D, and the gate electrode G.

In such a D-mode semiconductor device, the buffer layer 20a and the channel layer 30a include β-Ga ₂ O ₃ and are N-type doped. When a bias is applied to the gate electrode G and the drain electrode D, electrons move in the channel layer 30a to generate a drain current.

Referring to FIG. 2 , the D-mode semiconductor device of FIG. 1 exhibits normally-on operation characteristics because current flows when the gate voltage Vg is 0V. In order to turn off the drain current, it is necessary to apply a gate voltage (Vg) of about -7 to -8V. Such a D-mode semiconductor device is not suitable as a switching device because it requires a circuit for generating a negative voltage in order to be used as a switching device and has a problem of stability in which current can flow when a gate voltage is not applied.

A semiconductor device having an E-mode according to the related art will be described with reference to FIG. 3 . 3 is a cross-sectional view illustrating a semiconductor device having an E-mode according to the related art.

3, the E-mode semiconductor device according to the related art includes a substrate 10b, a buffer layer 20b formed on the substrate, a channel layer 30b formed on the buffer layer, and a channel layer 30b. It includes an insulating layer 40b formed thereon, source (S) and drain electrodes (D), and a gate electrode (G) formed on the insulating layer. An ohmic contact layer 60b is formed between the channel layer 30b and the source (S) and drain electrodes (D). A passivation layer 50b for protecting the device is formed on the insulating layer 40b, the source S, the drain electrode D, and the gate electrode G.

The channel layer 30b has a recess R formed by etching to a predetermined depth, and a gate electrode G is formed in the recess R.

As such, in the conventional E-mode semiconductor device, a recess R is formed in the channel layer 30b to narrow the channel layer 30b under the gate electrode G so that the narrow channel layer is formed in a state where the gate voltage is 0V. It shows a normally-off operation characteristic of blocking current by causing all to be depleted.

In this state, when a positive gate voltage is applied, electrons move through the channel layer 30b under the gate electrode G in which the recess R is formed. It can be used as a small.

However, such a conventional E-mode semiconductor device has a disadvantage in that a gate applied voltage for switching is very small (about 1V) and a large current cannot flow because a channel layer is narrow.

Korean Patent Publication No. 10-2012-0048244

An object of the present invention is to provide an E-mode semiconductor device capable of improving operating characteristics as a switching device by facilitating adjustment of a threshold voltage and an on-resistance.

An E-mode semiconductor device according to an embodiment of the present invention,

Board; a buffer layer formed on the substrate and doped with a first concentration; a body layer formed on the buffer layer and doped with a second concentration greater than the first concentration; and a channel layer formed on the body layer, doped with a third concentration greater than the second concentration, and including a recess in which a gate electrode is formed.

In the E-mode semiconductor device according to the embodiment of the present invention, it is preferable that the buffer layer, the body layer, and the channel layer are a gallium oxide-based semiconductor.

In the E-mode semiconductor device according to the embodiment of the present invention, the gallium oxide-based semiconductor is preferably doped with an N-type impurity.

In the E-mode semiconductor device according to an embodiment of the present invention, the gallium oxide-based semiconductor may be β-Ga ₂ O ₃ .

In the E-mode semiconductor device according to an embodiment of the present invention, it is preferable that the third concentration is 10 times or more of the second concentration, and the second concentration is 10 times or more of the first concentration.

In the E-mode semiconductor device according to the embodiment of the present invention, the second concentration is 5×10 ¹⁴ (cm ^-3 ) to 5×10 ¹⁶ (cm ^-3 ), and the third concentration is 1×10 ¹⁶ (cm ^-3 ) to 2×10 ¹⁸ (cm ^-3 ).

In the E-mode semiconductor device according to an embodiment of the present invention, the thickness of the body layer may be 50 nm to 500 nm, and the thickness of the channel layer may be 10 nm to 1000 nm.

In the E-mode semiconductor device according to the embodiment of the present invention, the recess may be formed through the channel layer.

In the E-mode semiconductor device according to an embodiment of the present invention, the recess may be formed by etching at least a portion of the channel layer and the body layer.

In the E-mode semiconductor device according to an embodiment of the present invention, the recess may be formed in a range of 50 nm or less from an upper end of the body layer.

In the E-mode semiconductor device according to an embodiment of the present invention, an insulating layer having a thickness of 5 nm to 100 nm or less may be formed between the body layer and the recess.

Other details of implementations according to various aspects of the invention are included in the detailed description below.

According to the embodiment of the present invention, it is possible to improve the operating characteristics as a switching element by facilitating adjustment of the threshold voltage and the on-resistance.

1 is a cross-sectional view illustrating a semiconductor device having a D-mode.
FIG. 2 is a graph showing output current-voltage characteristics of the semiconductor device shown in FIG. 1 .
3 is a cross-sectional view illustrating a semiconductor device having an E-mode according to the related art.
4 and 5 are cross-sectional views illustrating a semiconductor device having an E-mode according to an embodiment of the present invention.
6 is a view showing a simulation of an operation process of a semiconductor device having an E-mode according to an embodiment of the present invention.
7 is a graph showing an output current-voltage characteristic of a semiconductor device having an E-mode according to an embodiment of the present invention.
8 and 9 are graphs illustrating changes in output current-voltage characteristics due to negative interfacial charges in a semiconductor device having an E-mode according to an embodiment of the present invention.
10 and 11 are graphs showing a threshold voltage change characteristic according to a change in the thickness of an insulating layer and a doping concentration of a body layer in a semiconductor device having an E-mode according to an embodiment of the present invention.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

The terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present invention, terms such as 'comprise' or 'have' are intended to designate that the features, numbers, steps, operations, components, parts, or combinations thereof described in the specification exist, and one or more other features It is to be understood that this does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof. Hereinafter, an E-mode semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

4 and 5 are cross-sectional views illustrating a semiconductor device having an E-mode according to an embodiment of the present invention.

As shown in FIG. 4 , a semiconductor device having an E-mode (hereinafter, an “E-mode semiconductor device”) according to an embodiment of the present invention includes a substrate 110 , a buffer layer 120 , and a body layer 170 . ), a channel layer 130 , an insulating layer 140 , source (S) and drain electrodes (D), and a gate electrode (G).

The substrate 110 may be a growth substrate such as a sapphire substrate, an AlN substrate, a GaN substrate, a SiC substrate, or a Si substrate, and is not particularly limited as long as it is a substrate capable of growing a semiconductor.

The buffer layer 120 , the body layer 170 , and the channel layer 130 may be formed of a gallium oxide-based semiconductor. The buffer layer 120 , the body layer 170 , and the channel layer 130 may be formed in the gallium oxide-based semiconductor by varying the doping concentration of the N-type impurity according to the height from the substrate 110 . The doping concentration of the buffer layer 120 is the smallest, and the doping concentration increases toward the body layer 170 and the channel layer 130 . The gallium oxide-based semiconductor may be β-Ga ₂ O ₃ . Of course, the present invention is not limited thereto, and any semiconductor grown as an N-type is possible.

The buffer layer 120 is formed on the substrate 110 and is a first resistive layer in which electrons are difficult to move, and may be doped with an N-type impurity to a first concentration. For example, the first concentration may be 5×10 ¹⁴ (cm ⁻³ ) or less. The thickness of the buffer layer 120 may be, for example, 500 nm or more. When the doping of the buffer layer 120 is high, since a current can flow along the buffer layer 120, the lower the doping concentration, the better 5×10 ¹⁴ (cm ^-3 ) It is suitable to set it as below. In the case of thickness, a thickness for growing a good quality epitaxial layer from a substrate is required, and at least 500 nm or more is suitable.

The body layer 170 is formed on the buffer layer 120 and is a second resistive layer in which electrons are relatively easier to move than that of the buffer layer 120 , and the N-type impurity is doped with a first concentration and a second concentration greater than that of the second resistance layer. can The second concentration may be at least 10 times greater than the first concentration. For example, the second concentration may be in a range of 5×10 ¹⁴ (cm ⁻³ ) to 5×10 ¹⁶ (cm ⁻³ ). Since the buffer layer 120 under the body layer 170 functions as an insulating layer, the concentration of the body layer 170 does not have to be less than that of the insulating layer. When the doping concentration of the body layer 170 exceeds 5×10 ¹⁶ (cm ⁻³ ), a normally-on operation characteristic in which a current is always conducted through the body layer 170 may be exhibited. That is, the doping concentration difference with the channel layer 130 is relatively small, so that both the body layer 170 and the channel layer 130 can function as one layer capable of electron movement, so that the second concentration is 5 It is preferably in the range of ×10 ¹⁴ (cm ^-3 ) to 5×10 ¹⁶ (cm ^-3 ). The thickness of the body layer 170 may be, for example, 50 nm to 500 nm. If the body layer 170 is too thin, the energy band may not be flat due to the doping concentration of the buffer layer 120, and a thickness of 500 nm or more is possible. .

The channel layer 130 is formed on the body layer 170 and is a third resistive layer in which electrons are relatively easier to move than the body layer 170 , and the N-type impurity has a second concentration and a higher third concentration. may be doped. The third concentration may be at least ten times greater than the second concentration. For example, the third concentration may be in the range of 1×10 ¹⁶ (cm ⁻³ ) to 2×10 ¹⁸ (cm ⁻³ ). If the doping concentration of the channel layer 130 is less than 1×10 ¹⁶ (cm ^-3 ), there is a large problem in the resistance of the channel layer, and when it exceeds 1×10 ¹⁸ (cm ^-3 ), there is a problem that the breakdown voltage is too low. have. The thickness of the channel layer 130 may be, for example, 10 nm to 1000 nm. If the channel layer is 10 nm or less, there is a big problem in channel resistance, and if it is 1000 nm or more, the disadvantage of a long growth time and the time consuming and depth control of the gate region etching process may not be easy.

The doping concentration and thickness of the body layer 170 determine the threshold voltage, and the doping concentration and thickness of the channel layer 130 and the length of the channel layer 130 determine the on-resistance and the magnitude of the breakdown voltage. That is, as the thickness of the channel layer 130 increases, the on-resistance decreases, the breakdown voltage decreases, and the drain current increases. Also, as the doping concentration of the body layer 170 increases, the threshold voltage decreases, and as the doping concentration decreases, the threshold voltage increases. Accordingly, if the thickness of the channel layer 130 and the doping concentration and thickness of the body layer 170 are appropriately adjusted, an E-mode semiconductor device having desired operating characteristics (threshold voltage) may be realized. In the above, the threshold voltage means a gate applied voltage for ON/OFF switching.

The channel layer 130 has a recess R. The recess R is formed through the channel layer 130 . Alternatively, the recess R may be formed by etching at least a portion of the body layer 170 by over-etching the channel layer 130 as shown in FIG. 5 . At this time, as the depth of the recess (R) in the body layer 170 increases, the effective channel length increases and the drain current decreases. Accordingly, the depth of the recess (R) in the body layer 170 is preferably formed in a range of 50 nm or less from the top of the body layer 170 .

An ohmic contact layer 160 is formed on both sides of the channel layer 130 . The ohmic contact layer 160 is a layer for improving the ohmic junction between the source electrode S and the drain electrode D, and is formed by doping an N-type impurity at a concentration of 1Х10 ¹⁸ (cm ^-3 ) or more.

A source electrode S and a drain electrode D are respectively formed on both sides of the ohmic contact layer 160 . The source electrode S and the drain electrode D may include Ti, Au, Al, Ni, Ti/Al, Ti/Au, and Ni/Au.

The insulating layer 140 is formed on the channel layer 130 , the recess R, and the ohmic contact layer 160 . The insulating layer 140 may be formed using various insulating materials such as Al ₂ O ₃ , SiO ₂ , HfO ₂ , and SiN _x . The thickness of the insulating layer 140 is preferably 5 nm to 100 nm or less. When the thickness of the insulating layer 140 is less than 5 nm, there is a problem in that leakage current occurs, and when it exceeds 100 nm, there is a problem in that the rate of change of current due to the gate voltage is reduced, thereby deteriorating the operating characteristics of the device.

The threshold voltage varies according to the thickness of the insulating layer 140 and the doping concentration of the body layer 170 . Accordingly, if the thickness of the insulating layer 140 and the doping concentration of the body layer 170 are formed within an appropriate range, an E-mode semiconductor device having desired operating characteristics (threshold voltage) may be realized. This will be described later with reference to FIGS. 10 to 12 .

The gate electrode G is formed on the insulating layer 140 while filling the recess R. The gate electrode G may include Au, Ag, Ni, Pt, Ti, Ni/Au, or Pt/Ti/Au. A passivation layer 150 is formed on the insulating layer 140 , the source electrode S, the drain electrode D, and the gate electrode G to protect the device.

An operation process of the E-mode semiconductor device according to an embodiment of the present invention configured as described above will be described with reference to FIGS. 6 and 7 . 6 is a view showing a simulation of an operation process of a semiconductor device having an E-mode according to an embodiment of the present invention, and FIG. 7 is an output current of a semiconductor device having an E-mode according to an embodiment of the present invention. It is a graph showing voltage characteristics.

Referring to FIG. 6 , (a) of FIG. 6 is a case in which the drain voltage V is biased and the gate voltage Vgs is 0V, and FIG. 6(b) is a state in which the drain voltage V is biased. In the case where the gate voltage (Vgs) is 8V.

As shown in (a) of FIG. 6 , when the gate voltage Vgs is 0V, the depletion region DA is formed in the body layer 170 under the gate electrode G, so that electrons cannot move, so the drain current converges to zero. is in an off state.

As shown in (b) of FIG. 6 , when the gate voltage Vgs is equal to or greater than the threshold voltage, the depletion region is removed and electrons move through the body layer 170 (shown by an arrow in FIG. 4 ) to generate a drain current. becomes the hot state.

7 shows output current-voltage characteristics when the gate voltage Vgs is 0 to 8V and the drain voltage is 0 to 30V.

Referring to FIG. 7 , when the gate voltage (Vgs) is 0 to 1V, even when the drain voltage is applied, the drain current converges to 0, and when the gate voltage (Vgs) is 2V or more, the drain current is generated, so ON/OFF switching is performed. It can be seen that

Accordingly, the E-mode semiconductor device according to an embodiment of the present invention exhibits an off operation characteristic in which the current is cut off when the gate voltage is 0 to 1V, and when the gate voltage is 2V or more, a current is generated and turned on Because the /OFF switching operation is performed, the gate applied voltage (threshold voltage) for switching rises, so that it can be used as a switching device exhibiting stable operation characteristics.

Meanwhile, the above-described FIGS. 6 and 7 are results that do not take into account the effect of negative interface charges formed at the interface of the body layer 170 in contact with the insulating layer 140 . Accordingly, changes in operating characteristics due to negative interfacial charges will be described with reference to FIGS. 8 and 9 . 8 and 9 are graphs showing changes in output current-voltage characteristics due to negative interfacial charges. 9A is a simulation of an E-mode semiconductor device having no negative interfacial charge, and FIGS. 9B to 9D are simulations of an E-mode semiconductor device in which a negative interfacial charge is gradually increased. did it

A negative interface charge is formed at the interface of the body layer 170 in contact with the insulating layer 140 . For example, when the insulating layer 140 is Al ₂ O ₃ and the body layer 170 is β-Ga ₂ O ₃ , a negative interfacial charge having a range of 1x10 ¹² to 2x10 ¹³ (cm ^-2 ) is formed. do.

Referring to FIGS. 8 and 9 , it can be seen that the gate applied voltage (threshold voltage) for switching increases and the drain current decreases as the negative interfacial charge increases. Since it has a negative interfacial charge, it has a high threshold voltage, which makes it possible to reliably maintain an off state in an environment in which a signal applied to the gate changes according to an environment in which the high voltage switching device is used.

Next, a threshold voltage change characteristic according to a change in the thickness of the insulating layer 140 and the doping concentration of the body layer 170 will be described with reference to FIGS. 10 and 11 .

10 and 11 are graphs illustrating a threshold voltage change characteristic according to a change in the thickness of an insulating layer and a doping concentration of a body layer in a semiconductor device having an E-mode according to an embodiment of the present invention. 10 shows a case where the thickness of the insulating layer 140 is 20 nm, and FIG. 11 shows a case where the thickness of the insulating layer 140 is 50 nm. 10 and 11 , it was simulated that a negative interfacial charge of 1× ^{10 12} (cm ⁻² ) exists at the interface between the insulating layer 140 and the body layer 170 .

10 and 11 , the doping concentration of the body layer 170 was changed within the range of 1x10 ¹³ (cm ^-3 ) to 1x10 ¹⁷ (cm ^-3 ), the drain voltage was fixed to 5V, and the gate voltage was 0 The drain current value was simulated by changing it to ~8V. The doping concentration of the channel layer 130 is 3x10 ¹⁷ (cm ^-3 ).

10 and 11, (a) is a graph showing a gate voltage versus a drain current value, and (b) is a graph obtained by converting (a) to a logarithmic scale.

Referring to Figure 10 (b), 1x10 ¹⁶ (cm ^-3 _, Purple line) and 1x10 ¹⁷ (cm ^-3 , green line) show a relatively large drain current value (0.01 ~ 10 ^-3 (A/mm)) when the gate voltage is 1V, so the current always conducts normally. - You can see that it is on.

On the other hand, 1x10 ¹³ (cm ^-3 , black line), 1x10 ¹⁴ (cm ^-3 , red line), and 1x10 ¹⁵ (cm ^-3 , blue line) are less than 10 ^-5 (A/mm) when the gate voltage is 1V. It can be seen that it is in a normally-off state because it shows a very small amount of drain current.

Referring to (b) of FIG. 11 , 1x10 ¹⁶ (cm ^-3 , purple line) and 1x10 ¹⁷ (cm ^-3 , green line) have relatively large drain current values (0.01 to 10 ^{- 4} (A/mm)), so it can be seen that the current is always in a normally-on state.

On the other hand, 1x10 ¹³ (cm ^-3 , black line), 1x10 ¹⁴ (cm ^-3 , red line), and 1x10 ¹⁵ (cm ^-3 , blue line) are less than 10 ^-5 (A/mm) when the gate voltage is 1V. It can be seen that it is in a normally-off state because it shows a very small amount of drain current.

Accordingly, it can be seen that when the doping concentration of the body layer 170 is 1/100 to 1/10 compared to the doping concentration of the channel layer 130 , it shows stable operating characteristics as a switching device.

Above, an embodiment of the present invention has been described, but those of ordinary skill in the art can add, change, delete or add components within the scope that does not depart from the spirit of the present invention described in the claims. The present invention may be variously modified and changed by such as, and it will be said that it is also included within the scope of the present invention.

110: substrate 120: buffer layer
130: channel layer 140: insulating layer
150: passivation layer 160: ohmic contact layer
170: body layer R: recess
S: source electrode D: drain electrode
G: gate electrode

Claims (11)

Board;
a buffer layer formed on the substrate and doped with a first concentration;
a body layer formed on the buffer layer and doped with a second concentration greater than the first concentration to facilitate electron movement than the buffer layer;
a channel layer formed on the body layer, including a recess in which a gate electrode is formed, and doped with a third concentration greater than the second concentration to facilitate electron movement than the body layer;
An E-mode semiconductor device comprising a.
The method according to claim 1,
The buffer layer, the body layer, and the channel layer are gallium oxide-based semiconductors, E-mode semiconductor device.
3. The method according to claim 2,
The gallium oxide-based semiconductor is doped with an N-type impurity, an E-mode semiconductor device.
3. The method according to claim 2,
The gallium oxide-based semiconductor is β-Ga ₂ O ₃ , E-mode semiconductor device.
The method according to claim 1,
The third concentration is 10 times or more of the second concentration, and the second concentration is 10 times or more of the first concentration.
The method according to claim 1,
The second concentration is 5×10 ¹⁴ (cm ^-3 ) to 5×10 ¹⁶ (cm ^-3 ), and the third concentration is 1×10 ¹⁶ (cm ^-3 ) to 2×10 ¹⁸ (cm ^-3 ) Phosphorus, E-mode semiconductor device.
The method according to claim 1,
The thickness of the body layer is 50nm ~ 500nm, the thickness of the channel layer is 10nm ~ 1000nm, E-mode semiconductor device.
The method according to claim 1,
The recess is formed through the channel layer, E-mode semiconductor device.
The method according to claim 1,
and the recess is formed by etching at least a portion of the channel layer and the body layer.
10. The method of claim 9,
The recess is formed in a range of 50 nm or less from the top of the body layer, E-mode semiconductor device.
The method according to claim 1,
An insulating layer having a thickness of 5 nm to 100 nm or less is formed between the body layer and the recess, an E-mode semiconductor device.

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