KR102432678B1 - Mother substrate for display substrate and method of manufacturing the same - Google Patents

Abstract

A mother substrate for a display substrate includes an active pattern disposed in an array region of a base substrate, a first gate insulating layer disposed on the active pattern, disposed in the array region, overlapping the active pattern, and a first distance from the active pattern a first gate electrode spaced apart from each other, a second gate insulating layer disposed on the first gate electrode, a second second gate insulating layer disposed on the first gate electrode, disposed in the array region, overlapping the active pattern, and greater than the first distance from the active pattern and a display cell including a second gate electrode spaced apart by a distance and an insulating layer disposed on the second gate electrode, and an alignment mark disposed in an outer region outside the array region. The alignment marks may include an active alignment pattern disposed in the same layer as the active pattern, a first gate alignment pattern disposed in the same layer as the first gate electrode, and a second gate alignment pattern disposed in the same layer as the second gate electrode. and a contact hole alignment pattern formed through the first gate insulating layer, the second gate insulating layer, and the insulating layer.

Description

Motherboard for display substrate and manufacturing method thereof

The present invention relates to a mother substrate for a display substrate and a method of manufacturing the mother substrate for a display substrate, and more particularly, to a mother substrate for a display substrate capable of reducing defects and a method of manufacturing the mother substrate for a display substrate.

In recent years, with the development of the information society, various types of demands for display devices have increased, so that a liquid crystal display device (LCD), a plasma display panel (PDP), and a field emission device (Field Emission Display) have increased. Device; FED), an electrophoretic display device (EPD), an organic electroluminescence emitting device (OLED), such as a display device research is being actively conducted.

In general, in a lithography process for manufacturing a semiconductor device or a liquid crystal display device, an exposure apparatus for transferring a pattern formed on a mask or a reticle onto a substrate coated with a resist, ie, a wafer, is used.

When a precise semiconductor pattern is to be formed on the wafer through such a lithography process, the position of the reticle must be in a designated position, and the wafer corresponding to the reticle must also be accurately aligned.

Accordingly, the wafer forms alignment marks at various positions while going through a plurality of processes, and performs alignment by detecting these alignment marks. For example, the overlay of the alignment marks on the wafer may be measured after performing wafer alignment, and the overlay between the alignment marks formed in the previous step and the photoresist marks formed in the current step after the exposure and development process.

However, the overlay measurement using the alignment mark can measure the overlay between one layer and the other layer, and there is a problem in that it is difficult to measure each overlay between three or more layers at the same time.

Accordingly, it is an object of the present invention to provide a mother substrate for a display substrate capable of simultaneously monitoring the overlay of three or more layers.

Another object of the present invention is to provide a method of manufacturing the mother substrate for the display substrate.

A mother substrate for a display substrate according to an embodiment of the present invention includes an active pattern disposed in an array region of a base substrate, a first gate insulating layer disposed on the active pattern, and disposed in the array region, and , a first gate electrode overlapping the active pattern and spaced apart from the active pattern by a first distance, a second gate insulating layer disposed on the first gate electrode, disposed in the array region, the active pattern and A display cell overlapping and including a second gate electrode spaced apart from the active pattern by a second distance greater than the first distance and an insulating layer disposed on the second gate electrode, and an outer region outside the array region and an alignment mark placed on The alignment marks may include an active alignment pattern disposed on the same layer as the active pattern, a first gate alignment pattern disposed on the same layer as the first gate electrode, and a second gate alignment pattern disposed on the same layer as the second gate electrode. and a contact hole alignment pattern formed through the first gate insulating layer, the second gate insulating layer, and the insulating layer.

In an exemplary embodiment, the active alignment pattern has a rectangular shape, the first gate alignment pattern has a frame shape surrounding the active alignment pattern, and the second gate alignment pattern includes the first gate alignment pattern. It may have a frame shape surrounding the pattern, the contact hole alignment pattern may be formed outside the second gate alignment pattern, and may have a band shape parallel to sides of the second gate alignment pattern.

In one embodiment of the present invention, the active alignment pattern has a rectangular shape, the contact hole alignment pattern is formed outside the active alignment pattern, has a band shape parallel to sides of the active alignment pattern, the The second gate alignment pattern may have a frame shape surrounding the contact hole alignment pattern, and the first gate alignment pattern may have a frame shape surrounding the second gate alignment pattern.

In an embodiment of the present invention, the first gate electrode may not overlap the second gate electrode.

In an embodiment of the present invention, the first gate electrode has a first width, the second gate electrode has a second width, and the first gate electrode and the second gate electrode have the first width and It may be spaced apart by a third distance smaller than the second width.

In an embodiment of the present invention, the active pattern includes a first impurity region, a second impurity region, a third impurity region, a first channel region, and a second channel region, and the first channel region includes the first The impurity region may be disposed between the impurity region and the second impurity region, and the second channel region may be disposed between the second impurity region and the third impurity region.

In an embodiment of the present invention, the mother substrate for the display substrate includes a source electrode passing through the first gate insulating layer and the second gate insulating layer, and electrically contacting the first impurity region of the active pattern, and the second gate insulating layer. A drain electrode passing through the first gate insulating layer and the second gate insulating layer may further include a drain electrode in electrical contact with the third impurity region of the active pattern.

In an embodiment of the present invention, the source electrode may be disposed adjacent to the first gate electrode, and the drain electrode may be disposed adjacent to the second gate electrode.

In an embodiment of the present invention, the mother substrate for the display substrate may further include a first gate line electrically connected to the first gate electrode and a second gate line electrically connected to the second gate electrode. have.

In an embodiment of the present invention, the first gate line and the second gate line may overlap, and the first gate line and the second gate line may be electrically insulated by the first gate insulating layer.

A method of manufacturing a mother substrate for a display substrate according to an embodiment of the present invention for realizing another object of the present invention includes forming an active pattern and an active alignment pattern on a base substrate, and covering the active pattern and the active alignment pattern. forming a first gate insulating layer, forming a first gate electrode and a first gate alignment pattern on the first gate insulating layer, and forming the first gate electrode and the first gate alignment pattern on the first gate insulating layer forming a second gate insulating layer covering and forming a contact hole alignment pattern to be formed.

In an exemplary embodiment, the active alignment pattern has a rectangular shape, the first gate alignment pattern has a frame shape surrounding the active alignment pattern, and the second gate alignment pattern includes the first gate alignment pattern. It may have a frame shape surrounding the pattern, the contact hole alignment pattern may be formed outside the second gate alignment pattern, and may have a band shape parallel to sides of the second gate alignment pattern.

In one embodiment of the present invention, the active alignment pattern has a rectangular shape, the contact hole alignment pattern is formed outside the active alignment pattern, has a band shape parallel to sides of the active alignment pattern, the The second gate alignment pattern may have a frame shape surrounding the contact hole alignment pattern, and the first gate alignment pattern may have a frame shape surrounding the second gate alignment pattern.

In an embodiment of the present invention, the first gate electrode may not overlap the second gate electrode.

In an embodiment of the present invention, the first gate electrode has a first width, the second gate electrode has a second width, and the first gate electrode and the second gate electrode have the first width and It may be spaced apart by a third distance smaller than the second width.

In an embodiment of the present invention, the active pattern includes a first impurity region, a second impurity region, a third impurity region, a first channel region, and a second channel region, and the first channel region includes the first The impurity region may be disposed between the impurity region and the second impurity region, and the second channel region may be disposed between the second impurity region and the third impurity region.

In an embodiment of the present invention, the mother substrate for the display substrate includes a source electrode passing through the first gate insulating layer and the second gate insulating layer, and electrically contacting the first impurity region of the active pattern, and the second gate insulating layer. A drain electrode passing through the first gate insulating layer and the second gate insulating layer may further include a drain electrode in electrical contact with the third impurity region of the active pattern.

In an embodiment of the present invention, the source electrode may be disposed adjacent to the first gate electrode, and the drain electrode may be disposed adjacent to the second gate electrode.

In an embodiment of the present invention, the mother substrate for the display substrate may further include a first gate line electrically connected to the first gate electrode and a second gate line electrically connected to the second gate electrode. have.

In an embodiment of the present invention, the first gate line and the second gate line may overlap, and the first gate line and the second gate line may be electrically insulated by the first gate insulating layer.

According to embodiments of the present invention, a mother substrate for a display substrate includes an alignment mark formed in an outer region. The alignment marks include an active alignment pattern disposed on the same layer as the active pattern, a first gate alignment pattern disposed on the same layer as the first gate electrode, a second gate alignment pattern disposed on the same layer as the second gate electrode, and a first and a gate insulating layer, a second gate insulating layer, and a contact hole alignment pattern formed through the insulating layer. Accordingly, it is possible to monitor the overlay of three or more layers at once. Accordingly, defects of the display substrate may be reduced and yield may be improved.

1 is a plan view illustrating a mother substrate for a display substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a plan view illustrating a gate line and a thin film transistor of an array region of FIG. 1 .
FIG. 3 is an enlarged plan view of alignment marks formed on the mother substrate of FIG. 1 .
4 is a cross-sectional view taken along line II' of FIG. 2 and line II-II' of FIG. 3 .
5 to 9 are cross-sectional views illustrating a method of manufacturing a mother substrate for a display substrate of FIG. 4 .
FIG. 10 is an enlarged plan view of alignment marks formed on the mother substrate of FIG. 1 .
11 is a cross-sectional view taken along line I-I' of FIG. 2 and line III-III' of FIG. 10 .
12 to 16 are cross-sectional views illustrating a method of manufacturing the mother substrate for a display substrate of FIG. 11 .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a plan view illustrating a mother substrate for a display substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , the base mother substrate 210 of the mother substrate 200 for a display substrate includes a plurality of array areas AA on which an array layer is formed and an outer area SA between the adjacent array areas AA. includes Each array area AA includes a display area DA displaying an image and a peripheral area PA surrounding the display area DA. The array layer includes a gate line (not shown) formed in the display area DA, a data line crossing the gate line to define a pixel area, and test signal lines and driving signal lines formed in the peripheral area PA. include

Through a cutting process of cutting the base mother substrate 210 in units of each array area AA, each of the array areas AA of the base mother substrate 210 is formed as one display substrate DP. A cutting line extending in one direction of the base mother substrate 210 is defined as a first cutting line CL1 , and a cutting line extending in a direction perpendicular to the one direction is defined as a second cutting line CL2 . . The first and second cutting lines CL1 and CL2 correspond to virtual lines capable of cutting the mother substrate 200 for display substrates in the cutting process.

An alignment mark AM is formed in the outer area SA of the base mother substrate 210 . The alignment mark AM may be used to monitor the overlay of respective layers of the display substrate DP. In FIG. 1 , the alignment marks AM are shown to be formed one per cell in the outer area SA of the base mother substrate 210 , but the present invention is not limited thereto, and the number of alignment marks AM is not limited thereto. may be appropriately changed according to the size of the base mother substrate 210 and the size and number of cells to be formed.

FIG. 2 is a plan view illustrating a gate line and a thin film transistor of an array region of FIG. 1 . FIG. 3 is an enlarged plan view of alignment marks formed on the mother substrate of FIG. 1 . 4 is a cross-sectional view taken along line I-I' of FIG. 2 and line II-II' of FIG. 3 . For convenience of description, some components (eg, data lines, driving voltage lines, capacitors?) of the marking board are omitted from FIG. 2 .

2 to 4 , the display substrate according to example embodiments includes a scan circuit unit 10 , a plurality of gate lines 135 and 155 , and gate lines disposed on a base substrate 100 . 135, 155) electrically connected to the thin film transistor. In addition, the thin film transistor includes an active pattern 110 , a first gate insulating layer 120 , a first gate electrode 130 , a second gate insulating layer 140 , a second gate electrode 150 , an insulating layer 160 , and a source. It includes an electrode 170 and a drain electrode 180 .

The base substrate 100 may include a transparent insulating material. For example, the base substrate 100 may include a glass substrate, a transparent plastic substrate, a transparent ceramic substrate, or the like. In other exemplary embodiments, the base substrate 100 may be formed of a flexible substrate.

The scan circuit unit 10 may transmit a gate signal to the thin film transistor through the plurality of gate lines 135 and 155 .

The active pattern 110 is disposed on the base substrate 100 . For example, the active pattern 110 may have a shape extending along the first direction D1 as shown in FIG. 2 .

In an exemplary embodiment, the active pattern 110 may include amorphous silicon, polysilicon obtained by crystallizing apolar silicon, partially crystallized silicon, silicon including microcrystals, and the like. In other exemplary embodiments, the active pattern 110 may be formed of indium (In), zinc (Zn), gallium (Ga), tin (Sn), or hafnium (Hf). Oxides may be included. For example, the active pattern 110 includes indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or hafnium indium zinc oxide (HIZO). You may.

In example embodiments, the active pattern 110 may have a first impurity region 111 , a second impurity region 113 , a third impurity region 115 , and a first channel region 112 depending on the concentration of impurities. and a second channel region 114 . In this case, the first to third impurity regions 111 , 113 , and 115 may have higher impurity concentrations than the first and second channel regions 112 and 114 . For example, when the active pattern 110 includes amorphous silicon or polysilicon, the first to third impurity regions 111 , 113 , and 115 may include an n-type impurity or a p-type impurity. On the other hand, when the active pattern 110 includes a metal oxide semiconductor, the first to third impurity regions 111 , 113 , and 115 may include impurities such as hydrogen or fluorine. Accordingly, the first to third impurity regions 111 , 113 , and 115 may have higher conductivity than the first and second channel regions 112 and 114 .

The first to third impurity regions 111 , 113 , and 115 may be disposed to be spaced apart from each other, and the first and second channel regions 112 and 114 may be disposed between them. For example, the first channel region 112 may be disposed between the first impurity region 111 and the second impurity region 113 , and the second channel region 114 may be disposed between the second impurity region 113 and the second impurity region 113 . It may be disposed between the third impurity regions 115 . In example embodiments, the first channel region 112 may have a first width W1 , and the second channel region 114 may have a second width W2 .

In an exemplary embodiment, the first impurity region 111 may serve as a source region of the thin film transistor, and the third impurity region 115 may serve as a drain region of the thin film transistor. Also, the second impurity region 113 electrically connects the first channel region 112 and the second channel region 114 .

The first gate insulating layer 120 is disposed on the base substrate 100 and may cover the active pattern 110 . Accordingly, the active pattern 110 may be electrically insulated. In example embodiments, the first gate insulating layer 120 may include silicon oxide or silicon nitride. Alternatively, the first gate insulating layer 120 may include an insulating material having a high dielectric constant, such as hafnium oxide, zirconium oxide, or titanium oxide. The first gate insulating layer 120 may have a thickness of about 1000 Å to about 2000 Å. Preferably, the first gate insulating layer 120 may have a thickness of about 1400 Å.

The first gate electrode 130 and the first gate line 135 may be disposed on the first gate insulating layer 120 .

The first gate line 135 may extend in the first direction D1 as shown in FIG. 2 , and one end may be electrically connected to the scan circuit unit 10 . Meanwhile, the first gate electrode 130 may be electrically connected to the first gate line 135 . For example, the first gate electrode 130 may protrude from the first gate line 135 in the second direction D2 .

The first gate electrode 130 and the first gate line 135 may include the same material and have the same thickness. For example, the first gate electrode 130 and the first gate line 135 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of layers. It may have a multilayer structure including a metal layer and a conductive oxide layer.

On the other hand, the first gate electrode 130 and the first gate line 135 are about 2000? to about 3000? It can have a thickness in between. Preferably, the first gate electrode 130 and the first gate line 135 may have a thickness of about 2500°.

Also, the first gate electrode 130 may be disposed to overlap the active pattern 110 . Specifically, the first gate electrode 130 may be disposed to overlap the first channel region 112 of the active pattern 110 . In example embodiments, the first gate electrode 130 has a first width W1 in the first direction D1 , and the first width W1 of the first gate electrode 130 is the first channel. It may be substantially equal to the width of region 112 . For example, the first width W1 may have a length of about 2 μm to about 4 μm.

Meanwhile, the first gate electrode 130 may be disposed to be spaced apart from the active pattern 110 by a first distance D1 that is the thickness of the first gate insulating layer 120 .

The second gate insulating layer 140 is disposed on the first gate insulating layer 120 and may cover the first gate electrode 130 and the first gate line 135 . In example embodiments, the second gate insulating layer 140 may include a material substantially the same as or similar to that of the first gate insulating layer 120 . The second gate insulating layer 140 may have a thickness of about 1000 Å to about 2000 Å. Preferably, the second gate insulating layer 140 may have a thickness of about 1200 Å which is smaller than that of the first gate insulating layer 120 .

The second gate electrode 150 and the second gate line 155 may be disposed on the second gate insulating layer 140 .

The second gate line 155 may extend in the first direction D1 as shown in FIG. 2 , and one end may be electrically connected to the scan circuit unit 10 . Meanwhile, the second gate electrode 150 may be electrically connected to the second gate line 155 . For example, the second gate electrode 150 may protrude from the second gate line 155 in the second direction D2 .

The second gate electrode 150 and the second gate line 155 may include the same material and have the same thickness. In example embodiments, the second gate electrode 150 and the second gate line 155 may have substantially the same material and the same thickness as the first gate electrode 130 and the first gate line 135 . have.

Also, the second gate line 155 may be disposed to overlap the first gate line 135 . That is, the second gate line 155 may entirely or partially overlap the first gate line 135 . However, since the first gate insulating layer 120 is disposed between the second gate line 155 and the first gate line 135 , they may be electrically insulated. Accordingly, different electrical signals may be applied to the first gate line 135 and the second gate line 155 in the process of operating the thin film transistor.

Meanwhile, the second gate electrode 150 may be disposed to overlap the active pattern 110 . Specifically, the second gate electrode 150 may be disposed to overlap the second channel region 114 of the active pattern 110 , and may not overlap the first gate electrode 130 . In example embodiments, the second gate electrode 150 has a second width W2 in the first direction D1 , and the second width W2 of the second gate electrode 150 is the second channel. It may be substantially equal to the width of region 114 . For example, the second width W2 may have a length of about 2 μm to about 4 μm.

The first gate electrode 130 and the second gate electrode 150 may be disposed to be spaced apart from each other by a third distance D3 in the first direction D1 . The third distance D3 may be smaller than the first width W1 and the second width W2 . For example, the third distance D3 may have a length of about 0.7 μm to about 2 μm. Since the first gate electrode 130 and the second gate electrode 150 are disposed in different layers and formed through separate processes, the third distance D3 between them is set to the first width W1 and the second width W1. It may be arranged to be smaller than the width W2. As the third distance D3 decreases, an area occupied by the thin film transistor may be reduced.

Meanwhile, the second gate electrode 150 is spaced apart from the active pattern 110 by a second distance D2 that is the sum of the thickness of the first gate insulating layer 120 and the thickness of the second gate insulating layer 140 . That is, the second distance D2 between the second gate electrode 150 and the active pattern 110 is the first distance D1 between the first gate electrode 130 and the active pattern 110 and the active pattern 110 . ) is greater than As the distance from the active pattern 110 increases, the current blocking characteristic is improved. That is, the second gate electrode 150 additionally disposed on the first gate electrode 130 may improve the current blocking characteristic of the thin film transistor.

In an exemplary embodiment, the first gate electrode 130 is disposed adjacent to the source electrode 170 to be described later, and the second gate electrode 150 is disposed adjacent to the drain electrode 180 to be described later. can be As the second gate electrode 150 that is further away from the active pattern 110 is adjacent to the drain electrode 180 , the current blocking characteristic of the thin film transistor may be further improved.

The insulating layer 160 is disposed on the second gate insulating layer 140 and may cover the second gate electrode 150 and the second gate line 155 . In example embodiments, the insulating layer 160 may include a material substantially the same as or similar to that of the second gate insulating layer 150 . The insulating layer 160 may have a thickness of about 1000 Å to about 4000 Å.

The source electrode 170 may be disposed on the insulating layer 160 . The source electrode 170 is connected to the first impurity region 111 of the active pattern 110 through the first contact hole CH1 penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . ) can be electrically connected to. The source electrode 170 may include a metal or a transparent conductive oxide.

The drain electrode 180 may be disposed on the insulating layer 160 . The drain electrode 180 has the third impurity region 115 of the active pattern 110 through the second contact hole CH2 penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . ) can be electrically connected to. The drain electrode 180 may include a metal or a transparent conductive oxide.

In example embodiments, the thin film transistor of the display substrate may include an active pattern 110 , a first gate electrode 130 , and a second gate electrode 150 . The second distance D2 between the second gate electrode 150 and the active pattern 110 may be greater than the first distance D1 between the first gate electrode 130 and the active pattern 110 . Accordingly, the second gate electrode 150 may improve the current blocking characteristic of the thin film transistor. In addition, since the first gate electrode 130 and the second gate electrode 150 may be formed through separate processes, the distance between them may be reduced.

The alignment mark AM may include an active alignment pattern AMA disposed on the same layer as the active pattern 110 , a first gate alignment pattern AMG1 disposed on the same layer as the first gate electrode 130 , and A second gate alignment pattern AMG2 disposed on the same layer as the second gate electrode 150 and formed through the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . A contact hole alignment pattern (AMC) is included.

The active alignment pattern AMA may have a rectangular shape. The active alignment pattern AMA may be disposed on the same layer as the active pattern 110 . The active alignment pattern AMA may include the same material as the active pattern 110 .

For example, the active alignment pattern AMA may include amorphous silicon, polysilicon obtained by crystallizing amorphous silicon, partially crystallized silicon, silicon including microcrystals, or the like. In other example embodiments, the active alignment pattern AMA may include indium (In), zinc (Zn), gallium (Ga), tin (Sn), or hafnium (Hf). may contain oxides of For example, the active alignment pattern (AMA) includes indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or hafnium indium zinc oxide (HIZO). may include

The first gate alignment pattern AMG1 may have a frame shape surrounding the active alignment pattern AMA. The first gate alignment pattern AMG1 is disposed on the same layer as the first gate electrode 130 . The first gate alignment pattern AMG1 may include the same material as the first gate electrode 130 .

For example, the first gate alignment pattern AMG1 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of metal layers and conductive oxide layers. It may have a multi-layer structure comprising

The second gate alignment pattern AMG2 may have a frame shape surrounding the first gate alignment pattern AMG1 . The second gate alignment pattern AMG2 is disposed on the same layer as the second gate electrode 150 . The second gate alignment pattern AMG2 may include the same material as the second gate electrode 150 .

For example, the second gate alignment pattern AMG2 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of metal layers and conductive oxide layers. It may have a multi-layer structure comprising

The contact hole alignment pattern AMC is formed outside the second gate alignment pattern AMG2 , and may have a band shape parallel to sides of the second gate alignment pattern AMG2 . The active alignment pattern AMA, the first gate alignment pattern AMG1, and the second gate alignment pattern AMG2 may have an embossed shape, while the contact hole alignment pattern AMC may have an engraved shape. .

5 to 9 are cross-sectional views illustrating a method of manufacturing a mother substrate for a display substrate of FIG. 4 .

Referring to FIG. 5 , an active pattern 110 , an active alignment pattern AMA, and a first gate insulating layer 120 may be formed on the base substrate 100 .

The active pattern 110 and the active alignment pattern AMA may be formed by forming a semiconductor layer on the base substrate 100 and then patterning the semiconductor layer. In an exemplary embodiment, the semiconductor layer may be formed to include amorphous silicon through a chemical vapor deposition (CVD) process, a sputtering process, or the like. Thereafter, the amorphous silicon may be crystallized through a heat treatment process. In another exemplary embodiment, the semiconductor layer may be formed to include a metal oxide semiconductor through a sputtering process or the like.

Thereafter, the first gate insulating layer 120 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

Referring to FIG. 6 , the first gate electrode 130 , the first gate alignment pattern AMG1 , and the second gate insulating layer 140 may be formed on the first gate insulating layer 120 .

The first gate electrode 130 and the first gate alignment pattern AMG1 are formed by forming a first gate electrode layer and a first photoresist pattern on the first gate insulating layer 120 , and etching using the first photoresist pattern. It may be formed by partially removing the first gate electrode layer through a process. In an exemplary embodiment, the first gate electrode 130 may have a first width W1 in the first direction. The first width W1 may be the smallest width allowed in the patterning process. For example, the first width W1 may have a length of 2 μm to about 4 μm.

Meanwhile, in the process of forming the first gate electrode 130 , a first gate line electrically connected to the first gate electrode 130 may be formed together.

Thereafter, the second gate insulating layer 140 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

Referring to FIG. 7 , the second gate electrode 150 and the second gate alignment pattern AMG2 may be formed on the second gate insulating layer 140 .

The second gate electrode 150 and the second gate alignment pattern AMG2 are formed by forming a second gate electrode layer and a second photoresist pattern on the second gate insulating layer 140 , and etching using the second photoresist pattern. It may be formed by partially removing the second gate electrode layer through a process. In an exemplary embodiment, the second gate electrode 150 may have a second width W2 in the first direction. The second width W2 may be the smallest width allowed in the patterning process. For example, the second width W2 may have a length of 2 μm to about 4 μm.

Meanwhile, the first gate electrode 130 and the second gate electrode 150 may be disposed to be spaced apart from each other by a third distance D3 in the first direction D1 . The third distance D3 may be smaller than the first width W1 and the second width W2 . For example, the third distance D3 may have a length of about 0.7 μm to about 2 μm. Since the first gate electrode 130 and the second gate electrode 150 are disposed in different layers and formed through separate patterning processes, a third distance D3 smaller than the smallest width allowed in the patterning process is used. They may be spaced apart. Accordingly, an area occupied by the thin film transistor may be reduced.

In addition, the second gate electrode 150 is spaced apart from the active pattern 110 by a second distance D2 that is the sum of the thickness of the first gate insulating layer 120 and the thickness of the second gate insulating layer 140 . That is, the second gate electrode 150 additionally disposed on the first gate electrode 130 may improve the current blocking characteristic of the thin film transistor.

Meanwhile, while the second gate electrode 150 is formed, a second gate line electrically connected to the second gate electrode 150 may be formed together.

Referring to FIG. 8 , impurities may be implanted into the active pattern 110 to form a first impurity region 111 , a second impurity region 113 , and a third impurity region 115 .

The impurity implantation process may be performed using the first gate electrode 130 and the second gate electrode 150 as an ion implantation mask. Accordingly, impurities may not be implanted into portions of the active pattern 110 overlapping the first gate electrode 130 and the second gate electrode 150 .

Meanwhile, a portion between the first impurity region 111 and the second impurity region 113 may be defined as the first channel region 112 , and between the second impurity region 113 and the third impurity region 115 . A portion of may be defined as the second channel region 114 .

Referring to FIG. 9 , after the insulating layer 160 covering the second gate electrode 150 and the second gate alignment pattern AMG2 is formed, the source electrode 170 and the drain electrode 180 are formed on the insulating layer 160 . can form.

The insulating layer 160 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

In addition, the source electrode 170 and the drain electrode 180 are formed by partially removing the insulating layer 160 , the second gate insulating layer 140 , and the first gate insulating layer 120 to form the first impurity region 111 and the third impurity. After forming the contact holes exposing each of the regions 115 , an electrode layer filling the contact holes is deposited on the insulating layer 160 and patterned to form the electrode layer. In this case, a contact hole alignment pattern AMC penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 may be formed.

FIG. 10 is an enlarged plan view of alignment marks formed on the mother substrate of FIG. 1 . 11 is a cross-sectional view taken along line I-I' of FIG. 2 and line III-III' of FIG. 10 .

2 , 10 and 11 , the display substrate according to example embodiments includes a scan circuit unit 10 , a plurality of gate lines 135 and 155 , and a gate disposed on a base substrate 100 . and a thin film transistor electrically connected to lines 135 and 155 . In addition, the thin film transistor includes an active pattern 110 , a first gate insulating layer 120 , a first gate electrode 130 , a second gate insulating layer 140 , a second gate electrode 150 , an insulating layer 160 , and a source. It includes an electrode 170 and a drain electrode 180 .

The base substrate 100 may include a transparent insulating material. For example, the base substrate 100 may include a glass substrate, a transparent plastic substrate, a transparent ceramic substrate, or the like. In other exemplary embodiments, the base substrate 100 may be formed of a flexible substrate.

The scan circuit unit 10 may transmit a gate signal to the thin film transistor through the plurality of gate lines 135 and 155 .

The active pattern 110 is disposed on the base substrate 100 . For example, the active pattern 110 may have a shape extending along the first direction D1 as shown in FIG. 2 .

In an exemplary embodiment, the active pattern 110 may include amorphous silicon, polysilicon obtained by crystallizing apolar silicon, partially crystallized silicon, silicon including microcrystals, and the like. In other exemplary embodiments, the active pattern 110 may be formed of indium (In), zinc (Zn), gallium (Ga), tin (Sn), or hafnium (Hf). Oxides may be included. For example, the active pattern 110 includes indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or hafnium indium zinc oxide (HIZO). You may.

In example embodiments, the active pattern 110 may have a first impurity region 111 , a second impurity region 113 , a third impurity region 115 , and a first channel region 112 depending on the concentration of impurities. and a second channel region 114 . In this case, the first to third impurity regions 111 , 113 , and 115 may have higher impurity concentrations than the first and second channel regions 112 and 114 . For example, when the active pattern 110 includes amorphous silicon or polysilicon, the first to third impurity regions 111 , 113 , and 115 may include an n-type impurity or a p-type impurity. On the other hand, when the active pattern 110 includes a metal oxide semiconductor, the first to third impurity regions 111 , 113 , and 115 may include impurities such as hydrogen or fluorine. Accordingly, the first to third impurity regions 111 , 113 , and 115 may have higher conductivity than the first and second channel regions 112 and 114 .

The first to third impurity regions 111 , 113 , and 115 may be disposed to be spaced apart from each other, and the first and second channel regions 112 and 114 may be disposed between them. For example, the first channel region 112 may be disposed between the first impurity region 111 and the second impurity region 113 , and the second channel region 114 may be disposed between the second impurity region 113 and the second impurity region 113 . It may be disposed between the third impurity regions 115 . In example embodiments, the first channel region 112 may have a first width W1 , and the second channel region 114 may have a second width W2 .

In an exemplary embodiment, the first impurity region 111 may serve as a source region of the thin film transistor, and the third impurity region 115 may serve as a drain region of the thin film transistor. Also, the second impurity region 113 electrically connects the first channel region 112 and the second channel region 114 .

The first gate insulating layer 120 is disposed on the base substrate 100 and may cover the active pattern 110 . Accordingly, the active pattern 110 may be electrically insulated. In example embodiments, the first gate insulating layer 120 may include silicon oxide or silicon nitride. Alternatively, the first gate insulating layer 120 may include an insulating material having a high dielectric constant, such as hafnium oxide, zirconium oxide, or titanium oxide. The first gate insulating film 120 is about 1000 ? It may have a thickness of about 2000?. Preferably, the first gate insulating layer 120 may have a thickness of about 1400°.

The first gate electrode 130 and the first gate line 135 may be disposed on the first gate insulating layer 120 .

The first gate line 135 may extend in the first direction D1 as shown in FIG. 2 , and one end may be electrically connected to the scan circuit unit 10 . Meanwhile, the first gate electrode 130 may be electrically connected to the first gate line 135 . For example, the first gate electrode 130 may protrude from the first gate line 135 in the second direction D2 .

The first gate electrode 130 and the first gate line 135 may include the same material and have the same thickness. For example, the first gate electrode 130 and the first gate line 135 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of layers. It may have a multilayer structure including a metal layer and a conductive oxide layer.

On the other hand, the first gate electrode 130 and the first gate line 135 are about 2000? to about 3000? It can have a thickness in between. Preferably, the first gate electrode 130 and the first gate line 135 may have a thickness of about 2500°.

Also, the first gate electrode 130 may be disposed to overlap the active pattern 110 . Specifically, the first gate electrode 130 may be disposed to overlap the first channel region 112 of the active pattern 110 . In example embodiments, the first gate electrode 130 has a first width W1 in the first direction D1 , and the first width W1 of the first gate electrode 130 is the first channel. It may be substantially equal to the width of region 112 . For example, the first width W1 may have a length of about 2 μm to about 4 μm.

Meanwhile, the first gate electrode 130 may be disposed to be spaced apart from the active pattern 110 by a first distance D1 that is the thickness of the first gate insulating layer 120 .

The second gate insulating layer 140 is disposed on the first gate insulating layer 120 and may cover the first gate electrode 130 and the first gate line 135 . In example embodiments, the second gate insulating layer 140 may include a material substantially the same as or similar to that of the first gate insulating layer 120 . The second gate insulating layer 140 may have a thickness of about 1000 Å to about 2000 Å. Preferably, the second gate insulating layer 140 may have a thickness of about 1200 Å which is smaller than that of the first gate insulating layer 120 .

The second gate electrode 150 and the second gate line 155 may be disposed on the second gate insulating layer 140 .

The second gate line 155 may extend in the first direction D1 as shown in FIG. 2 , and one end may be electrically connected to the scan circuit unit 10 . Meanwhile, the second gate electrode 150 may be electrically connected to the second gate line 155 . For example, the second gate electrode 150 may protrude from the second gate line 155 in the second direction D2 .

The second gate electrode 150 and the second gate line 155 may include the same material and have the same thickness. In example embodiments, the second gate electrode 150 and the second gate line 155 may have substantially the same material and the same thickness as the first gate electrode 130 and the first gate line 135 . have.

Also, the second gate line 155 may be disposed to overlap the first gate line 135 . That is, the second gate line 155 may entirely or partially overlap the first gate line 135 . However, since the first gate insulating layer 120 is disposed between the second gate line 155 and the first gate line 135 , they may be electrically insulated. Accordingly, different electrical signals may be applied to the first gate line 135 and the second gate line 155 in the process of operating the thin film transistor.

Meanwhile, the second gate electrode 150 may be disposed to overlap the active pattern 110 . Specifically, the second gate electrode 150 may be disposed to overlap the second channel region 114 of the active pattern 110 , and may not overlap the first gate electrode 130 . In example embodiments, the second gate electrode 150 has a second width W2 in the first direction D1 , and the second width W2 of the second gate electrode 150 is the second channel. It may be substantially equal to the width of region 114 . For example, the second width W2 may have a length of about 2 μm to about 4 μm.

The first gate electrode 130 and the second gate electrode 150 may be disposed to be spaced apart from each other by a third distance D3 in the first direction D1 . The third distance D3 may be smaller than the first width W1 and the second width W2 . For example, the third distance D3 may have a length of about 0.7 μm to about 2 μm. Since the first gate electrode 130 and the second gate electrode 150 are disposed in different layers and formed through separate processes, the third distance D3 between them is set to the first width W1 and the second width W1. It may be arranged to be smaller than the width W2. As the third distance D3 decreases, an area occupied by the thin film transistor may be reduced.

Meanwhile, the second gate electrode 150 is spaced apart from the active pattern 110 by a second distance D2 that is the sum of the thickness of the first gate insulating layer 120 and the thickness of the second gate insulating layer 140 . That is, the second distance D2 between the second gate electrode 150 and the active pattern 110 is the first distance D1 between the first gate electrode 130 and the active pattern 110 and the active pattern 110 . ) is greater than As the distance from the active pattern 110 increases, the current blocking characteristic is improved. That is, the second gate electrode 150 additionally disposed on the first gate electrode 130 may improve the current blocking characteristic of the thin film transistor.

In an exemplary embodiment, the first gate electrode 130 is disposed adjacent to the source electrode 170 to be described later, and the second gate electrode 150 is disposed adjacent to the drain electrode 180 to be described later. can be As the second gate electrode 150 that is further away from the active pattern 110 is adjacent to the drain electrode 180 , the current blocking characteristic of the thin film transistor may be further improved.

The insulating layer 160 is disposed on the second gate insulating layer 140 and may cover the second gate electrode 150 and the second gate line 155 . In example embodiments, the insulating layer 160 may include a material substantially the same as or similar to that of the second gate insulating layer 150 . The insulating layer 160 may have a thickness of about 1000 Å to about 4000 Å.

The source electrode 170 may be disposed on the insulating layer 160 . The source electrode 170 is connected to the first impurity region 111 of the active pattern 110 through the first contact hole CH1 penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . ) can be electrically connected to. The source electrode 170 may include a metal or a transparent conductive oxide.

The drain electrode 180 may be disposed on the insulating layer 160 . The drain electrode 180 has the third impurity region 115 of the active pattern 110 through the second contact hole CH2 penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . ) can be electrically connected to. The drain electrode 180 may include a metal or a transparent conductive oxide.

In example embodiments, the thin film transistor of the display substrate may include an active pattern 110 , a first gate electrode 130 , and a second gate electrode 150 . The second distance D2 between the second gate electrode 150 and the active pattern 110 may be greater than the first distance D1 between the first gate electrode 130 and the active pattern 110 . Accordingly, the second gate electrode 150 may improve the current blocking characteristic of the thin film transistor. In addition, since the first gate electrode 130 and the second gate electrode 150 may be formed through separate processes, the distance between them may be reduced.

The alignment mark AM may include an active alignment pattern AMA disposed on the same layer as the active pattern 110 , a first gate alignment pattern AMG1 disposed on the same layer as the first gate electrode 130 , and A second gate alignment pattern AMG2 disposed on the same layer as the second gate electrode 150 and formed through the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 . A contact hole alignment pattern (AMC) is included.

The active alignment pattern AMA may have a rectangular shape. The active alignment pattern AMA may be disposed on the same layer as the active pattern 110 . The active alignment pattern AMA may include the same material as the active pattern 110 .

For example, the active alignment pattern AMA may include amorphous silicon, polysilicon obtained by crystallizing amorphous silicon, partially crystallized silicon, silicon including microcrystals, or the like. In other example embodiments, the active alignment pattern AMA may include indium (In), zinc (Zn), gallium (Ga), tin (Sn), or hafnium (Hf). may contain oxides of For example, the active alignment pattern (AMA) includes indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or hafnium indium zinc oxide (HIZO). may include

The contact hole alignment pattern AMC is formed outside the active alignment pattern AMA, and may have a band shape parallel to sides of the active alignment pattern AMA. The active alignment pattern AMA, the first gate alignment pattern AMG1, and the second gate alignment pattern AMG2 may have an embossed shape, while the contact hole alignment pattern AMC may have an engraved shape. .

The second gate alignment pattern AMG2 may have a frame shape surrounding the first contact hole alignment pattern AMC. The second gate alignment pattern AMG2 is disposed on the same layer as the second gate electrode 150 . The second gate alignment pattern AMG2 may include the same material as the second gate electrode 150 .

For example, the second gate alignment pattern AMG2 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of metal layers and conductive oxide layers. It may have a multi-layer structure comprising

The first gate alignment pattern AMG1 may have a frame shape surrounding the second gate alignment pattern AMG2 . The first gate alignment pattern AMG1 is disposed on the same layer as the first gate electrode 130 . The first gate alignment pattern AMG1 may include the same material as the first gate electrode 130 .

For example, the first gate alignment pattern AMG1 may include copper, silver, chromium, molybdenum, aluminum, titanium, manganese, aluminum, or an alloy thereof, and may have a single layer structure or a plurality of metal layers and conductive oxide layers. It may have a multi-layer structure comprising

12 to 16 are cross-sectional views illustrating a method of manufacturing the mother substrate for a display substrate of FIG. 11 .

Referring to FIG. 12 , the active pattern 110 , the active alignment pattern AMA, and the first gate insulating layer 120 may be formed on the base substrate 100 .

The active pattern 110 and the active alignment pattern AMA may be formed by forming a semiconductor layer on the base substrate 100 and then patterning the semiconductor layer. In an exemplary embodiment, the semiconductor layer may be formed to include amorphous silicon through a chemical vapor deposition (CVD) process, a sputtering process, or the like. Thereafter, the amorphous silicon may be crystallized through a heat treatment process. In another exemplary embodiment, the semiconductor layer may be formed to include a metal oxide semiconductor through a sputtering process or the like.

Thereafter, the first gate insulating layer 120 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

Referring to FIG. 13 , the first gate electrode 130 , the first gate alignment pattern AMG1 , and the second gate insulating layer 140 may be formed on the first gate insulating layer 120 .

The first gate electrode 130 and the first gate alignment pattern AMG1 are formed by forming a first gate electrode layer and a first photoresist pattern on the first gate insulating layer 120 , and etching using the first photoresist pattern. It may be formed by partially removing the first gate electrode layer through a process. In an exemplary embodiment, the first gate electrode 130 may have a first width W1 in the first direction. The first width W1 may be the smallest width allowed in the patterning process. For example, the first width W1 may have a length of 2 μm to about 4 μm.

Meanwhile, in the process of forming the first gate electrode 130 , a first gate line electrically connected to the first gate electrode 130 may be formed together.

Thereafter, the second gate insulating layer 140 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

Referring to FIG. 14 , the second gate electrode 150 and the second gate alignment pattern AMG2 may be formed on the second gate insulating layer 140 .

The second gate electrode 150 and the second gate alignment pattern AMG2 are formed by forming a second gate electrode layer and a second photoresist pattern on the second gate insulating layer 140 , and etching using the second photoresist pattern. It may be formed by partially removing the second gate electrode layer through a process. In an exemplary embodiment, the second gate electrode 150 may have a second width W2 in the first direction. The second width W2 may be the smallest width allowed in the patterning process. For example, the second width W2 may have a length of 2 μm to about 4 μm.

Meanwhile, the first gate electrode 130 and the second gate electrode 150 may be disposed to be spaced apart from each other by a third distance D3 in the first direction D1 . The third distance D3 may be smaller than the first width W1 and the second width W2 . For example, the third distance D3 may have a length of about 0.7 μm to about 2 μm. Since the first gate electrode 130 and the second gate electrode 150 are disposed in different layers and formed through separate patterning processes, a third distance D3 smaller than the smallest width allowed in the patterning process is used. They may be spaced apart. Accordingly, an area occupied by the thin film transistor may be reduced.

In addition, the second gate electrode 150 is spaced apart from the active pattern 110 by a second distance D2 that is the sum of the thickness of the first gate insulating layer 120 and the thickness of the second gate insulating layer 140 . That is, the second gate electrode 150 additionally disposed on the first gate electrode 130 may improve the current blocking characteristic of the thin film transistor.

Meanwhile, while the second gate electrode 150 is formed, a second gate line electrically connected to the second gate electrode 150 may be formed together.

Referring to FIG. 15 , impurities may be implanted into the active pattern 110 to form a first impurity region 111 , a second impurity region 113 , and a third impurity region 115 .

The impurity implantation process may be performed using the first gate electrode 130 and the second gate electrode 150 as an ion implantation mask. Accordingly, impurities may not be implanted into portions of the active pattern 110 overlapping the first gate electrode 130 and the second gate electrode 150 .

Meanwhile, a portion between the first impurity region 111 and the second impurity region 113 may be defined as the first channel region 112 , and between the second impurity region 113 and the third impurity region 115 . A portion of may be defined as the second channel region 114 .

Referring to FIG. 16 , after the insulating layer 160 covering the second gate electrode 150 and the second gate alignment pattern AMG2 is formed, the source electrode 170 and the drain electrode 180 are formed on the insulating layer 160 . can form.

The insulating layer 160 may be formed using silicon oxide or silicon nitride through a chemical vapor deposition process or the like.

In addition, the source electrode 170 and the drain electrode 180 are formed by partially removing the insulating layer 160 , the second gate insulating layer 140 , and the first gate insulating layer 120 to form the first impurity region 111 and the third impurity. After forming the contact holes exposing each of the regions 115 , an electrode layer filling the contact holes is deposited on the insulating layer 160 and patterned to form the electrode layer. In this case, a contact hole alignment pattern AMC penetrating the first gate insulating layer 120 , the second gate insulating layer 140 , and the insulating layer 160 may be formed.

According to embodiments of the present invention, a mother substrate for a display substrate includes an alignment mark formed in an outer region. The alignment marks include an active alignment pattern disposed on the same layer as the active pattern, a first gate alignment pattern disposed on the same layer as the first gate electrode, a second gate alignment pattern disposed on the same layer as the second gate electrode, and a first and a gate insulating layer, a second gate insulating layer, and a contact hole alignment pattern formed through the insulating layer. Therefore, it is possible to monitor the overlay of three or more layers at once. Accordingly, defects of the display substrate may be reduced and yield may be improved.

Although the above has been described with reference to the embodiments, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. You will understand that there is

100: base substrate 110: active pattern
111: first impurity region 112: first channel region
113: second impurity region 114: second channel region
115: third impurity region 120: first gate insulating layer
130: first gate electrode 140: second gate insulating layer
150: second gate electrode 160: insulating film
170: source electrode 180: drain electrode

Claims (20)

an active pattern disposed on an array region of the base substrate, a first gate insulating layer disposed on the active pattern, a first gate insulating layer disposed on the array region, overlapping the active pattern, and spaced apart from the active pattern by a first distance a first gate electrode, a second gate insulating layer disposed on the first gate electrode, disposed in the array region, overlapping the active pattern, and spaced apart from the active pattern by a second distance greater than the first distance a display cell including a second gate electrode and an insulating layer disposed on the second gate electrode; and
and an alignment mark disposed in an outer area outside the array area, wherein the alignment mark comprises:
an active alignment pattern disposed on the same layer as the active pattern;
a first gate alignment pattern disposed on the same layer as the first gate electrode;
a second gate alignment pattern disposed on the same layer as the second gate electrode; and
and a contact hole alignment pattern formed through the first gate insulating layer, the second gate insulating layer, and the insulating layer;
and the active alignment pattern, the first gate alignment pattern, the second gate alignment pattern, and the contact hole alignment pattern are adjacent to each other and constitute one alignment mark. According to claim 1,
The active alignment pattern has a rectangular shape,
The first gate alignment pattern has a frame shape surrounding the active alignment pattern,
The second gate alignment pattern has a frame shape surrounding the first gate alignment pattern,
The contact hole alignment pattern is formed outside the second gate alignment pattern, and has a strip shape parallel to sides of the second gate alignment pattern. According to claim 1,
The active alignment pattern has a rectangular shape,
The contact hole alignment pattern is formed outside the active alignment pattern, and has a band shape parallel to sides of the active alignment pattern;
The second gate alignment pattern has a frame shape surrounding the contact hole alignment pattern,
The mother substrate for a display substrate, wherein the first gate alignment pattern has a frame shape surrounding the second gate alignment pattern. The mother substrate of claim 1 , wherein the first gate electrode does not overlap the second gate electrode. The method of claim 1 , wherein the first gate electrode has a first width, the second gate electrode has a second width, and the first gate electrode and the second gate electrode have the first width and the second width. A mother substrate for a display substrate, characterized in that it is spaced apart by a third distance smaller than the width. 2 . The active pattern of claim 1 , wherein the active pattern includes a first impurity region, a second impurity region, a third impurity region, a first channel region, and a second channel region, wherein the first channel region is formed with the first impurity region and and wherein the second channel region is disposed between the second impurity region and the third impurity region. The method of claim 6 , further comprising: a source electrode passing through the first gate insulating layer and the second gate insulating layer and in electrical contact with the first impurity region of the active pattern;
and a drain electrode passing through the first gate insulating layer and the second gate insulating layer and electrically contacting the third impurity region of the active pattern. The mother substrate of claim 7 , wherein the source electrode is disposed adjacent to the first gate electrode, and the drain electrode is disposed adjacent to the second gate electrode. The apparatus of claim 1 , further comprising: a first gate line electrically connected to the first gate electrode; and
and a second gate line electrically connected to the second gate electrode. The display substrate of claim 9 , wherein the first gate line and the second gate line overlap, and the first gate line and the second gate line are electrically insulated by the second gate insulating layer. for mosquito nets. Forming an active pattern and an active alignment pattern on the base substrate
forming a first gate insulating layer covering the active pattern and the active alignment pattern;
forming a first gate electrode and a first gate alignment pattern on the first gate insulating layer;
forming a second gate insulating layer on the first gate insulating layer to cover the first gate electrode and the first gate alignment pattern;
forming a second gate electrode and a second gate alignment pattern on the second gate insulating layer;
forming an insulating layer on the second gate insulating layer to cover the second gate electrode and the second gate alignment pattern; and
forming a contact hole alignment pattern formed through the first gate insulating layer, the second gate insulating layer, and the insulating layer;
The method of claim 1, wherein the active alignment pattern, the first gate alignment pattern, the second gate alignment pattern, and the contact hole alignment pattern are adjacent to each other and constitute one alignment mark. 12. The method of claim 11,
The active alignment pattern has a rectangular shape,
The first gate alignment pattern has a frame shape surrounding the active alignment pattern,
The second gate alignment pattern has a frame shape surrounding the first gate alignment pattern,
The contact hole alignment pattern is formed outside the second gate alignment pattern, and has a strip shape parallel to sides of the second gate alignment pattern. 12. The method of claim 11,
The active alignment pattern has a rectangular shape,
The contact hole alignment pattern is formed outside the active alignment pattern, and has a band shape parallel to sides of the active alignment pattern;
The second gate alignment pattern has a frame shape surrounding the contact hole alignment pattern,
The method of claim 1 , wherein the first gate alignment pattern has a frame shape surrounding the second gate alignment pattern. The method of claim 11 , wherein the first gate electrode does not overlap the second gate electrode. The method of claim 11 , wherein the first gate electrode has a first width, the second gate electrode has a second width, and the first gate electrode and the second gate electrode have the first width and the second width. A method of manufacturing a mother substrate for a display substrate, characterized in that they are spaced apart by a third distance smaller than the width. The active pattern of claim 11 , wherein the active pattern includes a first impurity region, a second impurity region, a third impurity region, a first channel region, and a second channel region, wherein the first channel region is formed with the first impurity region and and wherein the second channel region is disposed between the second impurity region and the second impurity region and the third impurity region. 17 . The method of claim 16 , further comprising: a source electrode passing through the first gate insulating layer and the second gate insulating layer and in electrical contact with the first impurity region of the active pattern;
and a drain electrode passing through the first gate insulating layer and the second gate insulating layer and electrically contacting the third impurity region of the active pattern. The method of claim 17 , wherein the source electrode is disposed adjacent to the first gate electrode, and the drain electrode is disposed adjacent to the second gate electrode. The apparatus of claim 11 , further comprising: a first gate line electrically connected to the first gate electrode; and
and a second gate line electrically connected to the second gate electrode. The display substrate of claim 19 , wherein the first gate line and the second gate line overlap, and the first gate line and the second gate line are electrically insulated by the second gate insulating layer. A method of manufacturing a mother substrate for a dragon.

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