KR102421846B1 - Sub-pulsing during a state - Google Patents

Abstract

A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal having two states from a clock source and generating a pulsed signal from the clock signal. The pulsed signal has sub-states in one of the states. The sub-states alternate with respect to each other at a frequency higher than the frequency of the states. The method includes providing a pulsed signal to control the power of the RF signal generated by a radio frequency (RF) generator. Power is controlled to be synchronized with the pulsed signal.

Description

SUB-PULSING DURING A STATE

The present embodiments relate to generating sub-pulses during one state of a radio frequency (RF) generator.

Plasma chambers are used to perform various processes such as, for example, etching, deposition, and the like. For example, gas is supplied to the plasma chamber when power is supplied to the chamber. The plasma was struck when power was applied while the gas was in the plasma chamber. Plasma was used to etch the substrate or clean the plasma chamber. In addition, materials were deposited on the substrate by using a liquid flow or gas flow into the chamber.

However, controlling the processes is a difficult task. For example, materials on the substrate are etched too much or too little. As another example, the layers deposited on the substrate have a thickness greater than or less than a desired thickness.

In this context, the embodiments described in this disclosure occur.

Embodiments of the present disclosure provide apparatus, methods, and computer programs for sub-pulsing in one state. It will be understood that the present embodiments may be implemented in many ways, for example, in a process, apparatus, system, device, or method on a computer-readable medium. Some embodiments are described below.

In some embodiments, a method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states, and generating a pulsed signal from the clock signal. The pulsed signal has sub-states in one of the states. The sub-states alternate with respect to each other at a frequency higher than the frequency of the states. The method includes providing a pulsed signal to control power of an RF signal generated by a radio frequency (RF) generator. Power is controlled to be synchronized with the pulsed signal.

In various embodiments, an RF generator is described. The RF generator includes a processor. The processor receives a clock signal from a clock source. The clock signal has two states. The processor generates a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. Sub-states have a higher frequency than the frequency of the states. The processor provides the pulsed signal to control the power of the RF signal. Power is controlled to be synchronized with the pulsed signal. The RF generator includes an RF power supply coupled to the processor. The RF power supply generates an RF signal having power to provide the RF signal to the plasma chamber through an impedance matching circuit.

In various embodiments, a plasma system is described. A plasma system includes a processor that receives a clock signal from a clock source. The clock signal has two states. The processor generates a pulsed signal from the clock signal. The pulsed signal has sub-states in one of the states, the sub-states having a frequency greater than the frequency of the states. The processor provides the pulsed signal to control the power of the radio frequency (RF) signal. Power is controlled to be synchronized with the pulsed signal. The plasma system further includes an RF power supply for generating an RF signal having power. The plasma system also includes an RF cable coupled to the RF power supply. The plasma system includes an impedance matching circuit coupled to an RF power supply for receiving an RF signal via an RF cable. The impedance matching circuit matches an impedance of a load coupled to the impedance matching circuit with an impedance of a source coupled to the impedance matching circuit to generate a modified RF signal from the RF signal. The plasma system includes a plasma chamber coupled to an impedance matching circuit to receive a modified RF signal to change an impedance of the plasma.

Some advantages of the described embodiments include the use of sub-pulsing within a state to create sub-states within that state. When used by a low frequency RF generator, eg, a 2 MHz RF generator, etc., sub-pulsing is the processing of a wafer, eg, a substrate, a substrate having one or more layers of one or more materials deposited on the substrate, etc. gives rise to coarse control of For example, when an RF signal generated by a low frequency RF generator is sub-pulsed within a state, coarser control of the etching or deposition of materials on the substrate is reduced compared to when the RF signal is not sub-pulsed. is achieved In addition, when used by a high frequency RF generator, eg, a 60 MHz RF generator, etc., sub-pulsing results in superior control of wafer processing. For example, when an RF signal generated by a high frequency RF generator is sub-pulsed within a state, a more granular rate of etching or deposition of materials on the substrate compared to when the RF signal is not sub-pulsed. ) control is achieved. It should be noted that, in some embodiments, coarse control is to achieve a range of rates that are within the range of rates associated with coarse control.

Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

Embodiments may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
1 is a diagram to illustrate sub-pulsing in a state of an RF signal generated by a radio frequency (RF) generator, in accordance with some embodiments described in this disclosure.
2A is a diagram to illustrate sub-pulsing in a state for an x MHz (megahertz) RF generator, in accordance with some embodiments described in this disclosure.
2B is a graph to illustrate the use of sub-pulsing with an x MHz RF generator in conjunction with the use of pulsing with a y MHz RF generator, in accordance with some embodiments described in this disclosure.
2C is a graph to illustrate a signal having a non-zero logic level during sub-pulsing state S1b, in accordance with some embodiments described in this disclosure.
2D is a graph to illustrate a signal having a non-zero logic level during sub-pulsing state S1b with a pulsed signal generated by a y MHz RF generator, in accordance with some embodiments described in this disclosure.
2E is a diagram of a graph to illustrate a duty cycle different from a duty cycle of 50% during state S1, in accordance with some embodiments described in this disclosure.
3A is a diagram of a system for controlling the energy of ions during states S0, S1a, and S1b, in accordance with various embodiments described in this disclosure.
3B is a diagram of another system for controlling ion energy during states S0, S1a, and S1b when the x MHz RF generator is the master generator, in accordance with some embodiments described in this disclosure.
4A illustrates an x MHz RF generator operating in two states S1 and S0, and a y MHz RF generator operating in states S1, S0a, and S0b, in accordance with some embodiments described in this disclosure. It is a graph.
4B is a y MHz RF generator operating in state S1, state S0a, and state S0b, in accordance with various embodiments described in this disclosure; It is a graph.
4C is a graph to illustrate a y MHz RF generator operating in states S1, S0a, and S0b and a different level of state S0b than illustrated in FIG. 4A, in accordance with some embodiments described in this disclosure.
4D illustrates the use of different levels of a delivered power signal during states S0a and S0b compared to the levels of the delivered power signal shown in the graph of FIG. 4A , in accordance with some embodiments described in this disclosure; This is a graph for
4E is a graph to illustrate a duty cycle different from a duty cycle of 50% during state S0, in accordance with various embodiments described in this disclosure.
5A is a diagram of a system to illustrate generation by a y MHz RF generator of an RF signal having states S1, S0a, and S0b, in accordance with some embodiments described in this disclosure.
5B is a system for illustrating generation by a y MHz RF generator of an RF signal having states S1, S0a, and S0b when the x MHz RF generator is the master generator, in accordance with various embodiments described in this disclosure; is a drawing of
6A is a graph to illustrate sub-pulsing of an RF signal generated by an x MHz RF generator during two states S1 and S0, in accordance with some embodiments described in this disclosure.
6B illustrates the use of a y MHz RF generator in conjunction with the use of an x MHz RF generator to generate an RF signal having four sub-states S0a, S0b, S1a, and S1b, in accordance with various embodiments described in this disclosure. It is a graph to illustrate.
6C is a diagram of a graph to illustrate a different duty cycle during state S0 than during state S1, in accordance with some embodiments described in this disclosure.
7A is a diagram of a system to illustrate the use of four sub-states S0a, S0b, S1a, and S1b of an x MHz RF generator, in accordance with some embodiments described in this disclosure.
7B is to illustrate the use of four sub-states S0a, S0b, S1a, and S1b of an x MHz RF generator when the x MHz RF generator is the master generator, in accordance with various embodiments described in this disclosure; A drawing of the system.
8A is a graph to illustrate sub-pulsing of an RF signal generated by a y MHz RF generator during two states S1 and S0, in accordance with some embodiments described in this disclosure.
8B illustrates the use of an x MHz RF generator in conjunction with the use of a y MHz RF generator to generate an RF signal having four sub-states S0a, S0b, S1a, and S1b, in accordance with various embodiments described in this disclosure. It is a graph to illustrate.
8C is a diagram of a graph to illustrate the duty cycle during state S0 different than during state S1, in accordance with various embodiments described in this disclosure.
9A is a diagram of a system to illustrate the use of four sub-states S0a, S0b, S1a, and S1b in a y MHz RF generator, in accordance with some embodiments described in this disclosure.
9B is to illustrate the use of four sub-states S0a, S0b, S1a, and S1b of a y MHz RF generator when the x MHz RF generator is the master generator, in accordance with various embodiments described in this disclosure; A drawing of the system.
10A is a diagram of a graph to illustrate a plurality of sub-states of both an x MHz RF generator and a y MHz RF generator, in accordance with various embodiments described in this disclosure.
10B is a diagram of a graph to illustrate a plurality of sub-states of both an x MHz RF generator and a y MHz RF generator, in accordance with some embodiments described in this disclosure.
11A is a diagram of a system to illustrate the simultaneous use of sub-pulsing in both an x MHz RF generator and a y MHz RF generator, in accordance with some embodiments described in this disclosure.
11B is a system for illustrating the simultaneous use of sub-pulsing in both the x MHz RF generator and the y MHz RF generator when the x MHz RF generator functions as a master generator, in accordance with various embodiments described in this disclosure. It is a drawing.
12 illustrates the use of a switch to select one of four sub-states S1a, S1b, S0a, and S0b in an x MHz RF generator or a y MHz RF generator, in accordance with various embodiments described in this disclosure; It is a diagram of a system for
13A is a diagram of a digital signal processor (DSP) to illustrate the use of an internal clock source to generate a digitally pulsed signal, in accordance with some embodiments described in this disclosure.
13B is a diagram of a DSP to illustrate the use of a plurality of internal clock sources to generate a digitally pulsed signal, in accordance with various embodiments described in this disclosure.
14 is a diagram of a DSP using a modulating signal to determine whether to generate a sub-state Sna and a state Snb or to generate a state Sm, in accordance with some embodiments described in this disclosure.

The following embodiments describe systems and methods for sub-pulsing in one state. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

1 is a diagram of one embodiment of a radio frequency (RF) generator 100 to illustrate sub-pulsing in a state. The RF generator 100 receives, or generates a clock signal, a clock signal, eg, a transistor-transistor logic (TTL) signal, or the like. For example, RF generator 100 includes a clock source that receives or generates a clock signal from a clock source. Examples of a clock source include an oscillator, eg, a crystal oscillator, etc. or an oscillator coupled to a phase-locked loop (PLL). The clock signal has states Sm, where m is 1 or 0. For example, a clock signal has a high state and a low state that is lower than the high state. As another example, the clock signal has a logic level 1 and a logic level 0.

RF generator 100 generates a pulsed signal from a clock signal having states Sm. For example, RF generator 100 generates a pulsed signal that transitions from state Sm to state Sna and also transitions to state Snb, where n is 0 or 1. The pulsed signal generated by RF generator 100 has a higher frequency than the frequency of the clock signal with states Sm. For example, the pulsed signal has a higher frequency than the frequency of the clock signal during states S1 and S0 during state S1 or S0. As another example, the pulsed signal has a higher frequency than the frequency of the clock signal during states S1 and S0 during states S1 and S0.

In some embodiments, state S1 has a higher power level than the power level of state S0. For example, the power level of the RF signal with state S1 is 2000 W and the power level of the RF signal with state S0 is 0 W. As another example, the power level of the RF signal having state S1 is greater than 0 W and the power level of the RF signal having state S0 is 0 W. As yet another example, the power level of the RF signal having state S0 is greater than 0 W and the power level of the RF signal during state S1 is greater than the power level of the RF signal having state S0.

State Sna and state Snb are embedded in state S1 or state S0 of the clock signal. For example, state Sna and state Snb occupy one of states Sm. As another example, state S1a and state S1b occupy state S1 and do not occupy state S0. As yet another example, state S0a and state S0b occupy state S0 and do not occupy state S1.

As illustrated in graph 102, a pulsed signal having state Sna and state Snb transitions from state Sna to state Snb, and also transitions from state Snb to state Sna, and then from state Sna to state Snb, then Transition to state Sm.

2A is an embodiment of a graph 200 to illustrate sub-pulsing in one state for an x MHz RF generator, where x is two. In some embodiments, x is within a predetermined range of two. For example, x is 1 MHz out of 2. As another example, x is 2.5. As yet another example, x is 1.5.

In various embodiments, x is 27. In various embodiments, x is within a predetermined range of 27. For example, x is 2 MHz out of 27. As another example, x is 25.5. As yet another example, x is 29. As yet another example, x is 5 MHz out of 27.

Graph 200 plots the logic level of the pulsed signal 202 or the like versus time measured in seconds. The pulsed signal 202 is generated from a clock signal 204 , eg, a TTL1 signal, or the like. For example, the pulsed signal 202 is generated from the clock signal 204 by modulating the clock signal 204 using a modulating signal, eg, a TTL2 signal, etc. to arrive at the pulsed signal 202 . do. As another example, the pulsed signal 202 is multiplied by the amplitude of the signal whose amplitude, eg, the power level of the clock signal 204 , and the like, is the same as the pulsed signal 202 . Pulsed signal 202 is an example of a digitally pulsed signal TTL3.

During state SO of clock signal 204 , pulsed signal 202 includes one logic level, eg, logic level 0, logic level 0.5, logic level 0.2, and the like. During the state S1 of the clock signal 204, the pulsed signal 202 may have a plurality of logics, e.g., logic level 1 and logic level 0, logic level 0.5 and logic level 1, logic level 0.9 and logic level 0, etc. have levels. During state S1 of clock signal 204, pulsed signal 202 transitions, eg, alternating between states S1a and S1b. The transition frequency between states S1a and S1b of the pulsed signal 202 is higher than the transition frequency between the states S1 and S0 of the clock signal 204 . For example, the transition frequency between states S1b and S1a is four times higher than the transition frequency between states S0 and S1. As another example, the transition frequency between states S1b and S1a is 5 times higher than the transition frequency between states S0 and S1. As yet another example, the transition frequency between states S1b and S1a is 2 to 100 times higher than the transition frequency between states S0 and S1.

In various embodiments, pulsing of signal 202 between state S1a and state S1b may cause a chemistry impasse, eg, entry time of gases, etc., to occur within the plasma chamber, or It should be noted that it enables the achievement of pressure within the chamber, the achievement of temperature within the plasma chamber, or the achievement of a gap between the lower and upper electrodes of the plasma chamber. Furthermore, in some embodiments, the pulsing of signal 202 between states S1a and S1b is configured to control etching of the substrate or etching of a layer deposited on the substrate. In some embodiments, the pulsing of the signal 202 between the states S1a and S1b is overlaid on features of the wafer, eg, deposited layers, silicon, traces, etc., or an integrated circuit. ) reduces the chance of generating a significant amount of energy to destroy features, eg, circuit components, etc. Further, in some embodiments, state S1a facilitates generation of a significant amount of energy that produces a significant amount of ions within the plasma chamber, and state S1b is compared to during a process, eg, etching, cleaning, state S0. thus facilitating movement of ions within the plasma chamber to facilitate deposition rate lowering, and the like.

It should be noted that during state S0 of clock signal 204 , the amount of power generated by the x MHz RF generator is less than the amount of power generated during states S1a and S1b of pulsed signal 204 . The lower positive power results in a lower positive ion energy than the ion energy of the ions of the plasma generated during states S1a and S1b and/or an ion density lower than the ion density of the ions during states S1a and S1b.

2B is a diagram of one embodiment of a graph 210 to illustrate the use of an x MHz RF generator with a y MHz RF generator. Examples of y include 27 and 60. In some embodiments, y is within a predetermined range of 27. For example, y is 25 to 29 MHz. As another example, y is 57 to 63 MHz. As yet another example, y is between 24 and 30 MHz. As another example, y is between 55 and 65 MHz.

In some embodiments, when x is 2, y is 27. In various embodiments, when x is 27, y is 60. In some embodiments, when x is 2, y is 60.

Graph 210 plots the delivered power versus time of an RF signal generated by an RF generator. It should be noted that the transmitted power is the difference between the forward power and the reflected power. In some embodiments, the forward power is power generated by the RF generator and supplied to the plasma chamber by the RF generator, and the reflected power is the power reflected from the plasma chamber towards the RF generator.

The graph 210 includes an RF signal 212 similar to the pulsed signal 202 ( FIG. 2A ). For example, RF signal 212 includes states S0, S1a, and S1b, and transitions between states S0, S1a, and S1b in a manner similar to that the pulsed signal 202 transitions between states. do. The RF signal 212 has the same frequency as the pulsed signal 202 and the TTL3 signal. The RF signal 212 is generated from transmitted power generated based on the RF signal supplied by the x MHz RF generator and the RF signal reflected towards the x MHz RF generator.

During state SO of RF signal 212, the y MHz generator supplies the RF signal. When the RF signal is supplied by the y MHz RF generator, power is reflected from the plasma chamber towards the y MHz RF generator to further generate an RF signal 214 of the delivered power. RF signal 214 has state SO and has the same frequency as the TTL1 signal. Moreover, during the states S1a and S1b of the RF signal 212 , the RF signal 214 has a state S1 . RF signal 212 transitions between state S1 and state S0. For example, when RF signal 212 transitions between states S0, S1a, and S1b, RF signal 214 transitions between states S1 and S0.

2C is a diagram of one embodiment of a graph 220 to illustrate a pulsed signal 222 having a non-zero logic level during state S1b. Pulsed signal 222 is similar to pulsed signal 202 ( FIG. 2B ) except that pulsed signal 222 has a non-zero logic level during state S1b . For example, the pulsed signal 222 is the pulsed signal 202 except that the pulsed signal 222 falls from the state S1a to the state S1b having a level higher than the level of the state S0 of the pulsed signal 204 . ) is created in a similar way to The pulsed signal 222 then falls from the level of state S1b to the level of state S0 to transition from state S1b to state S0. Pulsed signal 222 has the same frequency as digital pulsed signal TTL3.

2D is a diagram of one embodiment of a graph 230 to illustrate the use of a pulsed signal 232 having a non-zero logic level during state S1b with a pulsed signal 214 generated by a y MHz RF generator. . Pulsed signal 232 is similar to pulsed signal 212 ( FIG. 2B ) except that pulsed signal 232 has a non-zero logic level during state S1b . For example, pulsed signal 232 is pulsed signal 212 except that pulsed signal 232 transitions from state S1a to a level higher than the delivered power level of state SO of pulsed signal 214. generated in a similar way to A higher level is achieved during state S1b. After achieving a higher level during state S1b, pulsed signal 232 transitions to the level of pulsed signal 214 in state SO. Pulsed signal 232 has the same frequency as digital pulsed signal TTL3.

Although the pulsed signal 214 generated based on the RF signal supplied by the y MHz RF generator is shown with a high amount of delivered power level of about 100 W and a small amount of about 10 W of delivered power level, , it should be noted that in some embodiments, the pulsed signal 214 has a high power level of 60 W to 160 W during state S1 and a low power level of 1 W to 55 W during state S0. . In various embodiments, the highest power level of the pulsed transmitted power signal generated based on the RF signal supplied by the x MHz RF generator during state S1a is at the RF signal supplied by the y MHz RF generator during state S1. higher than the highest power level of the pulsed transmitted power signal generated based on it. In some embodiments, the lowest power level of the transmitted power pulsed signal generated based on the RF signal supplied by the x MHz RF generator during the x MHz RF generator state S0 is supplied by the y MHz RF generator during the state S0. The transmitted power generated based on the transmitted RF signal is lower than the lowest power level of the pulsed signal.

In various embodiments, the time duration of occurrence of state S0 is equal to the duration of occurrence of both states S1a and S1b. For example, state S0 occurs during one half of the clock cycle of the clock signal TTL1 and states S1a and S1b occur during the other half of the clock cycle. In some embodiments, the time period of occurrence of state S0 is less than or greater than half a clock cycle of clock signal TTL1 and states S1a and S1b occur during the remainder of the clock cycle.

FIG. 2E is a diagram of one embodiment of a graph 240 to illustrate the duty cycle during state S1 different from a duty cycle of 50%. Graph 240 plots the power delivered by a 2 MHz RF generator versus time t. The delivered power is shown as a pulsed signal 242 . Note that the duty cycle of signal 242 during state S1 is greater than 50% and the time at which state S1 occurs is equal to the time at which state S0 occurs. For example, signal 242 occupies a greater amount of time during state S1a than the amount of time occupied during state S1b. In some embodiments, the duty cycle of signal 242 during state S1 is less than 50%. For example, the propagated RF signal occupies an amount of time during state S1a that is less than the amount of time occupied during state S1b.

It should be noted that the duty cycle of each of signals 202 , 212 , 222 , and 232 ( FIGS. 2A-2D ) during state S1 is 50%.

In some embodiments, the time at which state S1 occurs for power delivered by the x MHz RF generator is less than or greater than the time at which state S0 occurs for power delivered by the x MHz RF generator. In these embodiments, the duty cycle of the power delivered during state S1 is 50%.

In various embodiments, the time at which state S1 occurs for power delivered by the x MHz RF generator is less than or greater than the time at which state S0 occurs for power delivered by the x MHz RF generator. In these embodiments, the duty cycle of the power delivered during state S1 is greater than or less than 50%.

In some embodiments, the TTL signal has the same frequency as the pulsed signal 242 during state S1 . The TTL signal is generated by a device that generates a TTL3 signal. For example, a digital signal processor (DSPx) of an x MHz RF generator described below generates a TTL signal from a TTL1 signal and a modulated signal. The modulated signal modulates the TTL1 signal to generate a TTL signal.

3A is a diagram of one embodiment of a system 300 for controlling the energy of ions during state S1 of a TTL1 signal. System 300 includes an x MHz RF generator and a y MHz RF generator. The system 300 further includes an impedance matching circuit 302 , a plasma chamber 304 , and a tool user interface (UI) system 306 . Examples of tool UI system 306 include desktop computers, servers, virtual machines, laptop computers, tablets, cell phones, smart phones, and the like. In various embodiments, the tool UI system 306 includes a processor and a memory device, examples of which are provided below. In some embodiments, the tool UI system 306 is an x MHz RF generator and a y MHz RF generator via a computer network, eg, a wide area network (WAN), a local area network (LAN), the Internet, an intranet, etc. is coupled to

An impedance matching circuit 302 is coupled to the output of the x MHz RF generator via an RF cable 308 . Similarly, an impedance matching circuit 302 is coupled to the output of the y MHz RF generator via an RF cable 310 . The impedance matching circuit 302 matches the impedance of a load coupled to the impedance matching circuit 302 on one side with the impedance of a source coupled to the impedance matching circuit 302 on the other side. For example, the impedance matching circuit 302 may include the impedance of the RF transmission line 312 and the plasma chamber 304 and the impedance of the x MHz RF generator, the y MHz RF generator, the RF cable 308 , and the RF cable 310 . match with

The plasma chamber 304 is coupled to an impedance matching circuit 302 via an RF transmission line 312 . The plasma chamber 304 includes a chuck 314 , an upper electrode 316 , and other components (not shown), such as an upper dielectric ring surrounding the upper electrode 316 , and an upper electrode surrounding the upper dielectric ring. an extension, a lower dielectric ring surrounding the lower electrode of the chuck 314, a lower electrode extension surrounding the lower dielectric ring, an upper plasma exclusion zone (PEZ) ring, a lower PEZ ring, and the like. The upper electrode 316 is positioned opposite and opposite the chuck 314 . A wafer 318 , eg, a dummy wafer, semiconductor wafer, etc., is supported on the top surface 320 of the chuck 314 . Various processes, for example, chemical vapor deposition (CVD), cleaning, deposition, stuffing, etching, ion implantation, resist stripping, etc., are performed on a semiconductor wafer during production. BACKGROUND Integrated circuits, eg, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., are deployed on semiconductor wafers, and integrated circuits are used for various electronic items, eg, cell phones, tablets, It is used in smart phones, computers, laptops, networking equipment, and the like.

Each of the lower and upper electrodes 316 is made of a metal, for example, aluminum, an aluminum alloy, copper, or the like. The chuck 314 may be an electrostatic chuck (ESC) or a magnetic chuck.

Tool UI system 306 is a clock source that generates a clock signal, eg, a digitally pulsed signal, a TTL1 signal supplied via cable 313 to DSPx of an x MHz RF generator, and the like. As used herein, a processor may be a central processing unit (CPU), microprocessor, ASIC, PLD, controller, or the like. Clock signal TTL1 is also supplied by tool UI system 306 to DSP (DSPy) of the y MHz RF generator via cable 314 . Examples of each of the cables 313 and 314 include a universal serial bus (USB) cable, a serial cable, a parallel cable, an Ethernet cable, and the like.

Tool UI system 306 x recipe, eg, a data file containing performance parameters, eg, duty cycle, time interval for occurrence and existence of a state, power level, frequency level, etc. Provided for each MHz RF generator and y MHz RF generator. For example, the tool UI system 306 provides the recipe used to operate the x MHz RF generator to DSPx and the recipe used to operate the y MHz RF generator to DSPy. Recipe is stored in DSPx and DSPy.

DSPx receives the clock signal TTL1 and generates a digitally pulsed signal from the clock signal TTL1, eg, a TTL3 signal, and the like. For example, DSPx receives the clock signal TTL1 and modifies the TTL1 signal during state S1 to add sub-pulses during state S1 of the clock signal TTL1. As another example, DSPx receives clock signal TTL1 and modifies clock signal TTL1 during state S1 to increase the frequency of clock signal TTL1 during state S1 to generate a digitally pulsed signal TTL3. In this example, DSPx does not modify clock signal TTL1 during state SO. As yet another example, DSPx includes a clock source that receives the clock signal TTL1 and generates the clock signal TTL2. The clock signal TTL2 has the same frequency as the digitally pulsed signal TTL3 during state S1. Also, the clock signal TTL1 has the same frequency as the clock signal TTL3 during state S0. DSPx multiplies the clock signal TTL1 and the clock signal TTL2 to generate a clock signal TTL3.

In some embodiments, instead of receiving the clock signal TTL1 from the tool UI system 306 , DSPx includes a clock source that generates the clock signal TTL1 . In various embodiments, instead of receiving the clock signal TTL1 from the tool UI system 306 , the x MHz RF generator includes a clock source that generates the clock signal TTL1 .

In various embodiments, the clock signal TTL2 is received from a clock source located within the tool UI system 306 . In some embodiments, the clock signal TTL2 is generated by a clock source within an x MHz RF generator.

During state S1b, a digitally pulsed signal TTL3 and a clock signal TTL1 are provided from DSPx to a power controller (PWRS1bx) for state S1b and an auto frequency tuner (AFT) (AFTS1bx) for state S1b. For example, a portion of the TTL3 signal with state S1b is provided from DSPx to a power controller (PWRS1bx) and an automatic frequency tuner (AFTS1bx).

In some embodiments, the RF generator's power controller and the RF generator's AFT are components of the RF generator's DSP. For example, the automatic frequency tuners (AFTS0x, AFTS1ax, and AFTS1bx) of the x MHz RF generator, and the power controllers (PWRS1ax, PWRS1bx, and PWRS0x) are circuits integrated into the circuitry of DSPx. As another example, the automatic frequency tuners (AFTS0x, AFTS1ax, and AFTS1bx), and power controllers (PWRS1ax, PWRS1bx, and PWRS0x) are part of a computer program executed by DSPx.

A power controller (PWRS1bx) receives the digital pulsed signal TTL3 for state S1b and the clock signal TTL1 for state S1, and determines or identifies the power level of the RF signal to be generated and supplied by the x MHz RF generator. The power level of the RF signal to be generated and supplied by the x MHz RF generator has the same frequency as the digitally pulsed signal TTL3 during state S1b. In some embodiments, the power level corresponding to the state S1b of the TTL3 signal, eg mapped, linked, etc., corresponding to the state S1 of the TTL1 clock signal is stored in the memory device of the power controller PWRS1bx . Examples of memory devices include read-only memory (ROM), random access memory (RAM), or a combination thereof. In some embodiments, the memory device is a flash memory, a redundant array of storage disk (RAID), a hard disk, or the like.

In various embodiments, the power level for the state S1b of the TTL3 signal and the state S1 of the TTL1 signal is a processing rate to be achieved, eg, an etch rate to be achieved, a deposition rate to be achieved, a cleaning rate to be achieved, stuffing to be achieved. It is determined based on the rate, etc. The etch rate is the rate at which the wafer 318 is etched. The deposition rate is the rate at which materials are deposited on the wafer 318 , eg, polymers, photo-mask, monomers, and the like. The cleaning rate is the rate at which the wafer 318 is cleaned via cleaning, eg, via etching, via deposition, deposition and etching, and the like. The sputtering rate is the rate at which the wafer 318 or material deposited on the wafer 318 is sputtered.

In addition, the automatic frequency tuner AFTS1bx receives the digital pulsed signal TTL3 during state S1b and the clock signal TTL1 during state S1, and receives the amount of radio frequencies or the amount of radio frequencies of the RF signal to be generated by the x MHz RF generator. determine or identify a set of In some embodiments, the amount of radio frequency or the set of quantities of radio frequencies corresponding to the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is stored in the memory device of the automatic frequency tuner AFTS1bx.

The power level corresponding to the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is provided from the power controller (PWRS1bx) to the RF power supply 322 of the x MHz RF generator. In addition, the amount of radio frequency or the set of quantities of radio frequencies is provided to the RF power supply 322 by an automatic frequency tuner (AFTS1bx). Upon receipt of a power level and an amount of radio frequency or a set of radio frequencies for the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal, the RF power supply 322 provides this power level and the radio frequency amount or radio frequency generate an RF signal having a set of quantities of The RF signal generated by the RF power supply 322 is supplied to the impedance matching circuit 302 via an RF cable 308 .

Also, during state S1 of the TTL1 signal, DSPy of the y MHz RF generator provides a clock signal TTL1 to the power controller PWRS1y of the y MHz RF generator. In addition, DSPy of the y MHz RF generator provides the clock signal TTL1 to the automatic frequency tuner (AFTS1y) of the y MHz RF generator. Upon receipt of the clock signal TTL1, the power controller PWRS1y determines or identifies the power level of the RF signal to be generated by the y MHz RF generator. For example, the correspondence relationship between the state of the clock signal TTL1 and the power level of the RF signal to be generated by the y MHz RF generator, eg, matching, link, one-to-one relationship, etc., is stored in the memory of the power controller PWRS1y. stored on the device.

Furthermore, upon receipt of the clock signal TTL1, the automatic frequency tuner AFTS1y determines or identifies an amount of radio frequency or a set of amounts of radio frequencies of the RF signal to be generated by the y MHz RF generator. For example, the correspondence between the state of the clock signal TTL1 and the amount of radio frequency or the set of amounts of radio frequencies of the RF signal to be generated by the y MHz RF generator is stored in the memory device of the automatic frequency tuner AFTS1y.

The power level corresponding to state S1 is provided from the power controller PWRS1y to the RF power supply 324 of the y MHz RF generator. In addition, the amount of radio frequency or the set of quantities of radio frequencies is provided to the RF power supply 324 by an automatic frequency tuner AFTS1y. Upon receipt of the power level and the amount of radio frequency or the set of radio frequencies for the state S1, the RF power supply 324 generates an RF signal having this power level and this radio frequency amount or set of radio frequencies. create The RF signal generated by the RF power supply 324 is supplied to the impedance matching circuit 302 via the RF cable 310 .

It should be noted that, in some embodiments, DSPx provides a TTL3 signal to DSPy over a cable. During state S1, DSPy determines, based on the TTL3 signal, a transition time from state S1a to state S1b and a transition time from state S1b to state S1a. Furthermore, during state S1, DSPy sends a signal to the power controller PWRS1y to adjust the power determined by the power controller PWRS1y at the transition time from state S1a to state S1b or the transition time from state S1b to state S1a. The determined power is adjusted based on the change in plasma impedance that occurs when the power delivered or supplied by the x MHz RF generator transitions between states S1a and S1b. To compensate for the adjustment of the power delivered or supplied by the x MHz RF generator during the transition between states S1a and S1b, a TTL3 signal is sent from DSPx to DSPy. Adjustment of the power delivered or supplied by the x MHz RF generator creates a change in plasma impedance.

Furthermore, during state S1, DSPy sends a signal to the automatic frequency tuner AFTS1y to adjust the frequency determined by the automatic frequency tuner AFTS1y at the transition time from state S1a to state S1b, or from state S1b to state S1a. send. The determined frequency is adjusted based on the change in plasma impedance that occurs when the power supplied by the x MHz RF generator transitions between states S1a and S1b. To compensate for the adjustment of the frequency of the RF signal generated by the x MHz RF generator during the transition between states S1a and S1b, a TTL3 signal is sent from DSPx to DSPy. Adjusting the frequency of the RF signal supplied by the x MHz RF generator creates a change in plasma impedance.

In some embodiments, instead of transmitting the TTL3 signal from DSPx to DSPy over a cable, information about the TTL3 signal, e.g., the frequency of the TTL3 signal, the duty cycle of the TTL3 signal during state S1, It should also be noted that the time that occurs, the time that state S1b occurs in the TTL3 signal, etc. is provided by the tool UI system 306 to DSPy via cable 314 or another cable similar to cable 314 . Another cable connects the tool UI system 306 to DSPy. For example, information about the TTL3 signal is provided from the tool UI system 306 to DSPy in a data file. DSPy includes a virtual phase-locked loop (PLL) that generates a signal fixed to the frequency of the TTL3 signal, which signal is used to adjust the power determined by a power controller (PWRS1y) and/or by an automatic frequency tuner (AFTS1y). Used to tune the determined frequency.

The impedance matching circuit 302 generates a modified RF signal from the RF signal received from the x MHz RF generator during state S1b of the TTL3 signal and state S1 of the TTL1 clock signal and from the RF signal received from the y MHz RF generator during state S1. Match the impedance of the load with the source for For example, a portion of the modified RF signal corresponding to the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is generated by the impedance matching circuit 302 during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal. The modified RF signal generated during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is transmitted to the lower electrode of the chuck 314 via the RF transmission line 312 . The upper electrode 316 includes one or more gas inlets, eg, holes, etc. coupled to a central gas feed (not shown). A central gas feed receives one or more process gases from a gas reservoir (not shown). Examples of process gases include oxygen containing gases, such as O ₂ . Other examples of process gases include fluorine-containing gases, such as tetrafluoromethane (CF ₄ ), sulfur hexafluoride (SF ₆ ), hexafluoroethane (C ₂ F ₆ ), and the like. The upper electrode 316 is grounded. The chuck 314 is coupled to the x MHz RF generator via an RF transmission line 312 , an impedance matching circuit 302 , and an RF cable 308 . In addition, the chuck 314 is coupled to the y MHz RF generator via an RF transmission line 312 , an impedance matching circuit 302 , and an RF cable 310 .

In some embodiments, when a process gas is supplied between the upper electrode 316 and the chuck 314 and the x MHz RF generator and/or the y MHz RF generator is connected to the impedance matching circuit 302 and the RF transmission line 312 . When supplying the RF signals for the state S1b to the chuck 314 via , the impedance of the plasma in the plasma chamber 304 is affected, eg, increased, decreased, etc. FIG. The plasma affected during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal has the ion energy of the plasma ions. The ion energy during state S1b of the TTL3 signal and state S1 of the TTL1 clock signal is used to increase the deposition rate compared to during state S0 or S1a, or to perform etching rather than deposition during state S0, or to perform state S0. is used to perform an etch rather than not process the wafer 318 during state S1a, or to reduce an etch rate compared to during state S1a, or to perform deposition as compared to performing an etch during state S1a.

Also, during state S1a of the TTL3 signal and state S1 of the TTL1 signal, DSPx provides a digitally pulsed signal TTL3 and a clock signal TTL1 to the power controller PWRS1ax of the x MHz RF generator. For example, DSPx provides a portion of the digitally pulsed signal TTL3 for state S1a and a clock signal TTL1 for state S1 to power controller PWRS1ax. The power controller PWRS1ax determines or identifies the power level of the RF signal to be generated by the x MHz RF generator upon receipt of the digital pulsed signal TTL3 for state S1a and the clock signal TTL1 for state S1. The power level of the RF signal corresponding to the state S1a of the TTL3 signal and the state S1 of the clock signal TTL1 is stored in the memory device of the power controller PWRS1ax. The power level is provided to the RF power supply 322 during state S1a of the digitally pulsed signal TTL3 and state S1 of the clock signal TTL1.

Furthermore, during the state S1a of the TTL3 signal and the state S1 of the TTL1 signal, DSPx provides the digitally pulsed signal TTL3 and the clock signal TTL1 to the automatic frequency tuner AFTS1ax of the x MHz RF generator. Upon receipt of the digital pulsed signal TTL3 for the state S1a and the clock signal TTL1 for the state S1, the automatic frequency controller AFTS1ax determines whether the radio frequency amount or radio frequency corresponding to the state S1a of the digitally pulsed signal TTL3 and the state S1 of the clock signal TTL1 is received. Determine or identify a set of quantities of frequencies. For example, the corresponding relationship between the state S1a of the digitally pulsed signal TTL3, the state S1 of the clock signal TTL1 and the quantity of radio frequency or the set of quantities of radio frequencies is stored in the memory device of the automatic frequency tuner AFTS1ax.

An automatic frequency tuner (AFTS1ax) provides an amount of radio frequency or a set of amounts of radio frequencies to the RF power supply 322 . An amount of radio frequency or a set of quantities of radio frequencies upon receipt of the power level for state S1a of the digital pulsed signal TTL3 and the state S1 of the clock signal TTL1 and for the state S1a of the digitally pulsed signal TTL3 and the state S1 of the clock signal TTL1 Upon receipt of the RF power supply 322, the RF power supply 322 generates an RF signal having this power level and this amount of radio frequency or a set of amounts of radio frequencies for state S1a of the digitally pulsed signal TTL3 and state S1 of the clock signal TTL1. do.

The impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator for the state S1a of the digitally pulsed signal TTL3 and the state S1 of the clock signal TTL1, and receives the RF signal generated by the y MHz RF generator for the state S1. Receive the signal and match the impedance of the load using the source during state S1a to generate a modified RF signal from the RF signals for state S1a. For example, a portion of the modified RF signal corresponding to state S1a of digitally pulsed signal TTL3 and state S1 of clock signal TTL1 is generated by impedance matching circuit 302 during state S1a. The modified RF signal associated with the state S1a of the digitally pulsed signal TTL3 and the state S1 of the clock signal TTL1 is transmitted from the impedance matching circuit 302 via the RF transmission line 312 to the chuck 314 .

Upon receipt of the modified RF signal corresponding to state S1a of the digitally pulsed signal TTL3 and state S1 of the clock signal TTL1 , plasma ions in the plasma chamber 304 are transferred to processes on the wafer 318 , eg, state S0 or increasing the etch rate as compared to during S1b, decreasing the deposition rate compared to during state S0 or S1b, increasing the cleaning rate compared to during state S0 or S1b, and increasing the stuffing rate than during state S0 or S1b; excited to do the same.

During state SO, DSPx provides a digitally pulsed signal TTL3 to the power controller (PWRS0x) of the x MHz RF generator. For example, DSPx sends a portion of the digital pulsed signal TTL3 corresponding to state SO to the power controller PWRS0x. It should be noted that during state S0, the TTL3 signal is the same as the TTL1 signal. Upon receipt of the digital pulsed signal TTL3 associated with state SO, power controller PWRS0x determines or identifies a power level for state SO. For example, the power level corresponding to state SO is stored in and identified from the memory device of the power controller PWRS0x. This power level is provided to the RF power supply 322 by a power controller (PWRS0x). Upon receipt of the power level for state SO, the RF power supply 322 generates an RF signal having a power level associated with state SO.

Furthermore, during state SO, DSPx provides a digitally pulsed signal TTL3 to the automatic frequency tuner (AFTS0x) of the x MHz RF generator. For example, DSPx provides a portion of the digital pulsed signal TTL3 with state SO to the automatic frequency tuner AFTS0x. Upon receipt of the digital pulsed signal TTL3 corresponding to state SO, the automatic frequency tuner AFTS0x determines or identifies an amount of radio frequency or a set of amounts of radio frequencies. For example, automatic frequency tuner AFTS0x identifies an amount of radio frequency or a set of amounts of radio frequencies from a memory device of automatic frequency tuner AFTS0x. An automatic frequency tuner (AFTS0x) provides an amount of radio frequency or a set of amounts of radio frequencies to the RF power supply 322 .

During state S0, upon receipt of an amount of radio frequency or an amount of radio frequencies and an amount of power associated with state S0, RF power supply 322 generates an RF signal corresponding to state S0. An RF signal corresponding to state S0 has a power level associated with state S0 and an amount of radio frequency or a set of amounts of radio frequencies.

Also, during state SO, DSPy provides a clock signal TTL1 to the y MHz RF generator's power controller (PWRS0y) and automatic frequency tuner (AFTS0y). For example, DSPy sends a portion of the clock signal TTL1 with state SO to the power controller (PWRS0x) and the automatic frequency tuner (AFTS0y). Upon receipt of the clock signal TTL1 associated with state S0, the power controller PWRS0y determines or identifies the power level of the RF signal to be generated by the y MHz RF generator, and the automatic frequency tuner AFTS0y determines the amount of radio frequency of the RF signal. or determine or identify a set of quantities of radio frequencies. The power level associated with state SO is provided from the power controller PWRS0y to the RF power supply 324 , and the amount of radio frequency or set of quantities of radio frequencies is provided from the automatic frequency tuner AFTS0y to the RF power supply 324 . do. Upon receipt of the power level for state S0 from the power controller PWRS0y and upon receipt of the amount of radio frequency or the set of amounts of radio frequencies from the automatic frequency tuner AFTS0y, the RF power supply 324 controls this power level and an RF signal having an amount of radio frequency or a set of quantities of radio frequencies.

The impedance matching circuit 302 receives the RF signal supplied by the RF power supply 322 over the RF cable 308 during state S0 and receives the RF signal supplied by the RF power supply 324 during the state S0 over the RF cable 310 and match the impedance of the load using the source to generate a modified RF signal for state S0. The modified RF signal associated with state SO is provided to chuck 304 via RF transmission line 312 .

In some embodiments, the modified RF signal corresponding to state S0 raises the deposition rate of depositing materials on wafer 318 as compared to during state S1a or S1b. In various embodiments, the modified RF signal corresponding to state S0 reduces an etch rate of the etch of the wafer 318 or layers on the wafer 318 compared to during state S1a or S1b. In some embodiments, the modified RF signal corresponding to state S0 is used to deposit materials on the wafer 318 , and the modified RF signal generated during state S1a or the modified RF signal generated during state S1b is applied to the wafer ( It is used to etch the layers or wafer 318 on 318 . In some embodiments, a portion of the modified RF signal generated during state SO is used to generate a plasma, such as striking the plasma within the plasma chamber 304 . For example, when a process gas is supplied to the plasma chamber 304 and one or more RF signals are supplied by one or more of an x MHz RF generator and a y MHz RF generator, the process gas generates plasma within the plasma chamber 304 . ignited to create

In various embodiments, instead of coupling each of the power controllers (PWRS0x, PWRS1ax, and PWRS1bx) of the x MHz RF generator to different outputs of DSPx, the power controllers PWRS0x, PWRS1ax, and PWRS1bx are switched, e.g., It is connected to one or the same output of DSPx through a multiplexer, etc. The switch couples DSPx to power controller (PWRS0x) during state S0, DSPx to power controller (PWRS1ax) during state S1a, and DSPx to power controller (PWRS1bx) during state S1b.

Similarly, in some embodiments, instead of coupling each of the power controllers (PWRS0y and PWRS1y) of the y MHz RF generator to a different output of DSPy, the power controllers PWRS0y and PWRS1y are one of DSPy and the same output via a switch. is connected to The switch couples DSPy to power controller (PWRS0y) during state S0 and DSPy to power controller (PWRS1y) during state S1.

Also, in various embodiments, instead of coupling each of the automatic frequency tuners (AFTS0x, AFTS1ax, and AFTS1bx) of the x MHz RF generator to different outputs of DSPx, the automatic frequency tuners (AFTS0x, AFTS1ax, and AFTS1bx) are It is connected to one of the DSPx and the same output through a switch, eg, a multiplexer, etc. The switch connects DSPx to the automatic frequency tuner (AFTS0x) during state S0, DSPx to the automatic frequency tuner (AFTS1ax) during state S1a, and DSPx to the automatic frequency tuner (AFTS1bx) during state S1b.

Similarly, in some embodiments, instead of coupling each of the automatic frequency tuners AFTS0y and AFTS1y of the y MHz RF generator to a different output of DSPy, the automatic frequency tuners AFTS0y and AFTS1y are one of DSPy via a switch and Connect to the same output. The switch connects DSPy to the automatic frequency tuner (AFTS0y) during state S0 and DSPy to the automatic frequency tuner (AFTS1y) during state S1.

3B is a diagram of one embodiment of a system 350 for controlling ion energy during state S1. The system 350 includes an x MHz RF generator, a y MHz RF generator, an impedance matching circuit 302 , a plasma chamber 304 , and a tool UI system 307 . System 350 operates in a similar manner to system 300 ( FIG. 3A ) except that DSPx in system 350 generates a clock signal TTL1 and a digitally pulsed signal TTL3 . The x MHz RF generator is the master RF generator and the y MHz RF generator is the slave RF generator. The clock signals TTL1 and TTL3 signals are transmitted over a cable from DSPx in the x MHz RF generator to DSPy in the y MHz RF generator.

Tool UI system 307 provides a corresponding recipe including performance parameters to each of the x MHz RF generator and the y MHz RF generator. The corresponding recipe is stored in each of DSPx and DSPy.

In some embodiments, the power of the RF signal supplied by the x MHz RF generator is signal 202 ( FIG. 2A ) or signal 212 ( FIG. 2B ) or signal 222 ( FIG. 2C ) or signal 232 . (Fig. 2d) has the same frequency.

In various embodiments, instead of sending the TTL3 signal over the cable from DSPx to DSPy, information about the TTL3 signal is provided from DSPx to DSPy via the cable connecting DSPx to DSPy. For example, information about the TTL3 signal is provided in the DSPx to DSPy data file. DSPy includes a virtual phase locked loop that generates a signal fixed to the frequency of the TTL3 signal, the signal to adjust the power determined by the power controller (PWRS1y) and/or to adjust the frequency determined by the automatic frequency tuner (AFTS1y) used

4A is a diagram of one embodiment of a graph 400 illustrating an x MHz RF generator operating in two states S1 and S0, and a y MHz RF generator operating in states S1, S0a, and S0b. Graph 400 includes a propagated power signal 402 generated from an RF signal supplied by an x MHz RF generator and a propagated power signal 404 generated from an RF signal supplied by a y MHz RF generator. Graph 400 plots the delivered power versus time. Transmitted power signal 404 has the same frequency as digital pulsed signal TTL3.

The delivered power signal 404 transitions, eg, alternates between states S0a and S0b, and the like, for a period of time during which the delivered power signal 402 is in state S0. The transferred power signal 404 does not transition between the two states during the period of time during which the transferred power signal 402 is in state S1 . During a period of time during which the transferred power signal 402 is in state S1 , the transferred power signal 404 is also in a state of state S1 .

The power level of the power signal 402 conveyed during state S0, e.g., a power level of zero, a power level less than 5 W, etc., increases the deposition rate, or decreases the etch rate, or decreases the stuffing rate; ease the back. The power level of the power signal 402 delivered during state S0 is lower than the power level of the power signal 402 delivered during state S1.

Moreover, the transition between states S0a and S0b of the transmitted power signal 404 during the state S0 of the transmitted power signal 402 is a control of the impedance of the plasma generated in the plasma chamber 304 ( FIG. 3A ), e.g. For example, to facilitate an increase, a decrease, and the like. Controlling the impedance increases the stability of the plasma. For example, when the x MHz RF generator generates an RF signal to further provide a delivered power signal 402 to the plasma chamber 304 to achieve a coarse etch rate, the y MHz RF generator states An RF signal is generated to further provide a transferred power signal 404 that transitions between Soa and Sob. Transitioning between states S0a and S0b by the delivered power signal 404 is performed to achieve a fine etch rate. As another example, when the x MHz RF generator generates an RF signal to further provide the delivered power signal 402 to the plasma chamber 304 to achieve a coarse deposition rate, the y MHz RF generator enters state S0a and An RF signal is generated to further provide a transferred power signal 404 that transitions between states S0b. Transitioning between states S0a and S0b by the delivered power signal 404 is performed to achieve good deposition rates. As another example, when an x MHz RF generator generates an RF signal to further provide a delivered power signal 402 to the plasma chamber 304 to achieve a coarse sputtering rate, the y MHz RF generator generates a state S0a and An RF signal is generated to further provide a transferred power signal 404 that transitions between states S0b. Transitioning between states S0a and S0b by the delivered power signal 404 is performed to achieve a good sputtering rate.

In some embodiments, the coarse rate has a wider range than the good rate. For example, a coarse etch rate ranges from D A/min to E A/min and a good etch rate ranges from F A/min to G A/min. The range from F Å/min to G Å/min falls within the range between D Å/min and E Å/min. In various embodiments, the range of F A/min to G A/min is less than the range of D A/min to E A/min.

In various embodiments, during state S0b of the transferred power signal 404 , the amount of ion energy in the plasma chamber 304 ( FIG. 3A ) is an ion in the plasma chamber 304 during state S0a of the transferred power signal 404 . less than the amount of energy. The lower amount of ion energy generated by the RF signal generated by the y MHz RF generator facilitates control of the plasma within the plasma chamber 304 to achieve stability of the plasma and further achieve repeatability of the rate. Furthermore, the generation of a lower amount of ion energy during the period of time during which the transmitted power signal 402 is in the state of state S0 results in the majority of the power supplied by the RF signals generated by the x MHz RF generator and the y MHz RF generator. Reflect towards these generators. The reflection of most of the power improves the stability of the plasma within the plasma chamber 304 .

4B is a diagram of one embodiment of a graph 410 illustrating the level of a delivered power signal 412 derived based on an RF signal generated by a y MHz RF generator. Graph 410 plots the delivered power versus time. During state S0a, the delivered power signal 412 has a higher level than the level of the delivered power signal 404 (FIG. 4A) during state S0b. The propagated power signal 412 has the same frequency as the digitally pulsed signal TTL3.

In various embodiments, during state S0a, the delivered power signal 412 has a higher level than the level of the delivered power signal 404 . In various embodiments, during state S0a, the delivered power signal 412 has a level that is lower than the level of the delivered power signal 404 .

4C is a diagram of one embodiment of a graph 420 illustrating the level of a delivered power signal 422 derived based on an RF signal generated by a y MHz RF generator. Graph 420 plots the delivered power versus time. During state S0b, the delivered power signal 422 has a level that is lower than the level of the delivered power signal 404 ( FIG. 4A ) during state S0a. Furthermore, during state S0a, the delivered power signal 422 has a lower level than the level of the delivered power signal 422 during state S1. The delivered power signal 422 has the same frequency as the digitally pulsed signal TTL3.

4D is a diagram of one embodiment of a graph 430 to illustrate the use of different levels of the delivered power signal 432 compared to the levels shown in the graph 400 ( FIG. 4A ). The propagated power signal 432 has the same frequency as the digitally pulsed signal TTL3. The transmitted power signal 432 is coupled to the RF signal supplied by the y MHz RF generator via an RF transmission line 312 , an impedance matching circuit 302 , and an RF cable 310 ( FIG. 3A ) to the plasma chamber 304 . is a function of the RF signal reflected from y MHz towards the RF generator. The power level of the power signal 432 delivered during state S0a is lower than the power level of the power signal 404 ( FIG. 4A ) delivered during state S0a. Moreover, the power level of the power signal 432 delivered during state S0a is lower than the power level of the power signal 402 delivered during state S1. Also, the power level of the power signal 432 delivered during state S0b is higher than the power level of the power signal 402 delivered during state S0b. The power level of the power signal 432 delivered during state S0b is lower than the power level of the power signal 402 delivered during state S1 and higher than the power level of the power signal 402 delivered during state S0.

In various embodiments, the power level of the power signal 402 delivered during state S0 is higher than the power level of the power signal 432 delivered during state S0b. In some embodiments, the power level of the power signal 402 delivered during state S1 is lower than the power level of the power signal 432 delivered during state S0a.

In some embodiments, the time period of occurrence of state S1 is equal to the time period of occurrence of states S0a and S0b. For example, state S1 occurs during one half clock cycle of the clock signal TTL1, and states S0a and S0b occur during the other half clock cycle. In some embodiments, the time period of occurrence of state S1 is less than or greater than one-half clock cycle of clock signal TTL1, and states S0a and S0b occur during the remainder of the clock cycle.

4E is an embodiment of a graph 440 to illustrate a duty cycle different from a duty cycle of 50% during state SO. Graph 440 plots the power delivered by a 60 MHz RF generator versus time t. The delivered power is shown as a pulsed signal 442 . The duty cycle of signal 442 during state S0 is greater than 50%, and the time during which state S1 occurs is equal to the time during which state S0 occurs. For example, signal 442 occupies a greater amount of time during state S0a than the amount of time occupied during state S0b. In some embodiments, the duty cycle of signal 442 during state SO is less than 50%. For example, a propagated signal occupies an amount of time during state S0a that is less than the amount of time occupied during state S0b.

It should also be noted that the duty cycle of each of signals 404 , 412 , 422 , and 432 ( FIGS. 4A-4D ) during state SO is 50%.

In some embodiments, the time during which state S0 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of the power delivered during state SO is 50%.

In various embodiments, the time during which state S0 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of power delivered during state S0 is greater than or less than 50%.

In some embodiments, the TTL signal has the same frequency as the pulsed signal 442 . The TTL signal is generated by a device that generates a TTL3 signal. For example, DSPx generates a TTL signal from a TTL1 signal and a modulated signal. The modulated signal modulates the TTL1 signal to generate a TTL signal.

FIG. 5A is a diagram of one embodiment of a system 500 to illustrate generation by a y MHz RF generator of an RF signal having states S1, S0a, and S0b. The system 500 includes a plasma chamber 304 , an x MHz RF generator, a y MHz RF generator, and a tool UI system 306 . The clock source of the tool UI system 306 provides clock signals TTL1 to DSPx of the x MHz RF generator and DSPy of the y MHz RF generator. DSPx generates a digitally pulsed signal TTL3 signal based on the clock signal TTL1 and provides the TTL3 signal to DSPy. For example, DSPx provides DSPy a portion of the digitally pulsed signal TTL3 with state S0b.

In some embodiments, instead of DSPx generating the TTL3 signal and providing the TTL3 signal to DSPy, DSPy generates the TTL3 signal based on the clock signal TTL1. For example, DSPy generates the TTL3 signal from a clock signal received from a clock source of the tool UI system 306 or from a clock source internal to DSPx. As another example, DSPy generates a TTL3 signal from a clock signal TTL1 generated by a clock source inside DSPy. As yet another example, DSPy generates a TTL3 signal from a clock signal TTL1 generated by a clock source inside a y MHz RF generator.

During state S0b, DSPx provides a digitally pulsed signal TTL3 over the cable to DSPy. DSPy provides a digitally pulsed signal TTL3 and a clock signal TTL1 to the power controller (PWRS0by) of the y MHz RF generator during state S0b. For example, DSPy provides a portion of a digital pulsed signal TTL3 having state S0b and a clock signal TTL1 having state S0. A power controller PWRS0by determines or identifies a power level of an RF signal to be generated by the y MHz RF generator in response to receiving the digital pulsed signal TTL3 and the clock signal TTL1. For example, power controller PWRS0by identifies, within the memory device of power controller PWRS0by, a power level mapped to state S0b of digitally pulsed signal TTL3 and state S0 of clock signal TTL1. Power controller PWRS0by sends the power level to RF power supply 324 .

Furthermore, during state S0b of digital pulsed signal TTL3 and state S0 of clock signal TTL1, DSPy provides digital pulsed signal TTL3 and clock signal TTL1 to the automatic frequency tuner AFTS0by of the y MHz RF generator. An automatic frequency tuner AFTS0by determines or identifies a frequency level of the RF signal to be generated by the y MHz RF generator in response to receipt of the digital pulsed signal TTL3 and the clock signal TTL1. For example, the automatic frequency tuner AFTS0by identifies the frequency levels mapped to the state S0b of the digitally pulsed signal TTL3 and the state S0 of the clock signal TTL1 from the memory device of the automatic frequency tuner AFTS0by. An automatic frequency tuner AFTS0by provides a frequency level to the RF power supply 324 . Upon receipt of the power level from the power controller PWRS0by during state S0b and the frequency level from the automatic frequency tuner AFTS0by during state S0 of the digital pulsed signal TTL3 and the state S0 of the clock signal TTL1, the RF power supply 324 is It generates an RF signal having this frequency level and power level.

The power level and frequency level during the state S0b of the digitally pulsed signal TTL3 and the state S0 of the clock signal TTL1 is determined by achieving a rate, eg, an etch rate, or a deposition rate, or a cleaning rate, or a stuffing rate, etc. related For example, the RF signal generated by the y MHz RF generator during state S0b of digitally pulsed signal TTL3 and state S0 of clock signal TTL1 is etched wafer 318 or during good tuning of material deposited on wafer 318 . It helps to achieve a balance between the plurality of etch rates. One of the plurality of etch rates is associated with state S0b and another of the plurality of rates is associated with state S0a.

Furthermore, during state S0b of the y MHz RF generator, the x MHz RF generator operates in state S0. During state SO, DSPx sends a clock signal TTL1 to the power controller (PWRS0x) and to the automatic frequency tuner of the x MHz RF generator (AFTS0x). Upon receipt of the clock signal TTL1, the power controller PWRS0x determines or identifies the power level. The power level is identified from the memory device of the power controller (PWRS0x). The power level is provided to an RF power supply 322 .

Further, upon receipt of the clock signal TTL1, the automatic frequency tuner AFTS0x determines or identifies the frequency level. The frequency level is identified from the memory device of the automatic frequency tuner (AFTS0x). An automatic frequency tuner (AFTS0x) provides a frequency level to the RF power supply 322 . Upon receipt of the power level and frequency level during state SO, the RF power supply 322 generates an RF signal having this frequency level and power level.

The frequency level and power level during state S0 of the RF signal generated by the x MHz RF generator helps achieve a processing rate, eg, a deposition rate, an etch rate, a cleaning rate, a sputtering rate, and the like. For example, during state SO, an RF signal is generated by the x MHz RF generator that has a power level that maps to a coarse etch level and/or maps to a coarse frequency level.

Impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator during state S0 and the RF signal generated by the y MHz RF generator during state S0b, and generates a modified RF signal between the source and load to generate a modified RF signal. Match the impedance. The modified RF signal is provided to the chuck 314 by the impedance matching circuit 302 to create or modify a plasma that will process the wafer 318 to achieve the rate.

Furthermore, during state S0a, DSPx provides a digitally pulsed signal TTL3 over the cable to DSPy and a clock signal TTL1 over the cable to DSPy. DSPy provides a digitally pulsed signal TTL3 and a clock signal TTL1 to the power controller (PWRS0ay) of the y MHz RF generator during state S0a. For example, DSPy provides a portion of the digital pulsed signal TTL3 with state S0a and a clock signal TTL1 with state S0. A power controller (PWRS0ay) determines or identifies a power level of an RF signal to be generated by the y MHz RF generator in response to receipt of the digital pulsed signal TTL3 and the clock signal TTL1. For example, power controller PWRS0ay identifies a power level mapped within the memory device of power controller PWRS0ay to state S0a of digitally pulsed signal TTL3 and state S0 of clock signal TTL1. The power controller (PWRS0ay) sends the power level to the RF power supply 324 .

Furthermore, during state S0a of the digital pulsed signal TTL3 and state S0 of the clock signal TTL1, DSPy provides the digitally pulsed signal TTL3 to the automatic frequency tuner (AFTS0ay) of the y MHz RF generator. An automatic frequency tuner AFTS0ay determines or identifies a frequency level of an RF signal to be generated by the y MHz RF generator in response to receipt of a digital pulsed signal TTL3 having a state S0a and a clock signal TTL1 having a state S0. For example, automatic frequency tuner AFTS0ay identifies, from the memory device of automatic frequency tuner AFTS0ay, a frequency level mapped to state S0a of digital pulsed signal TTL3 and state S0 of clock signal TTL1. An automatic frequency tuner (AFTS0ay) provides this frequency level to the RF power supply 324 . Upon receiving the power level from the power controller PWRS0ay during state S0a and the frequency level from the automatic frequency tuner AFTS0ay during state S0a, the RF power supply 324 generates an RF signal having this frequency level and power level.

The power level and frequency level during state S0a of the digitally pulsed signal TTL3 and state S0 of the clock signal TTL1 are determined to achieve a processing rate, e.g., an etch rate, or a deposition rate, or a stuffing rate, or a cleaning rate, etc. related to For example, the RF signal generated by the y MHz RF generator during state S0a of digitally pulsed signal TTL3 and state S0 of clock signal TTL1 is excellent in etching wafer 318 or etching of material deposited on wafer 318. Helps achieve balancing during tuning. To illustrate, the RF signal generated by the y MHz RF generator during state S0a of digitally pulsed signal TTL3 and state S0 of clock signal TTL1 is used to further achieve a balance between increased and reduced etch rates during state S0b. To assist in increasing the etch rate of the etched wafer 318 or material deposited on the wafer 318 .

Also, during state S0a of the y MHz RF generator, the x MHz RF generator operates in state S0. The operations of the x MHz RF generator during state S0 have been described above. Impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator during state S0 and the RF signal generated by the y MHz RF generator during state S0a, and generates a modified RF signal between a source and a load. Match the impedance. The modified RF signal is impedance modified to modify a plasma for processing a process, eg, etching the wafer 318 , depositing materials on the wafer 318 , or processing the materials deposited on the wafer 318 . provided to the chuck 314 by a matching circuit 302 .

During state S1, DSPy provides a TTL3 signal to the power controller PWRS1y. For example, DSPy provides a portion of the TTL3 signal to the power controller (PWRS1y) during state S1. It should be noted that the TTL3 signal is the same as the TTL1 signal during state S1. Upon receiving the TTL3 signal, the power controller PWRS1y determines or identifies a power level and provides this power level to the RF power supply 324 . In addition, during state S1, DSPy provides a TTL3 signal to the automatic frequency tuner AFTS1y. Upon receiving the TTL3 signal, the automatic frequency tuner AFTS1y determines or identifies a frequency level and provides this frequency level to the RF power supply 324 . The RF power supply 324 generates an RF signal having this power level and frequency level during state S1 and provides the RF signal to the impedance matching circuit 302 .

In addition, during state S1, DSPx provides a TTL3 signal to the power controller (PWRS1x) and the automatic frequency tuner (AFTS1x). Upon receiving the TTL3 signal, the power controller PWRS1x determines or identifies the power level associated with state S1. For example, power controller PWRS1x identifies the power level stored in the memory device of power controller PWRS1x. A power controller (PWRS1x) provides this power level to the RF power supply 322 . Also, upon receiving the TTL3 signal, the automatic frequency tuner AFTS1x determines or identifies the frequency level associated with state S1. By way of example, automatic frequency tuner AFTS1x identifies a frequency level mapped to state S1 and stored in the memory device of automatic frequency tuner AFTS1x. This frequency level is provided to the power supply 322 from an automatic frequency tuner (AFTS1x). During state S1 , power supply 322 generates an RF signal having a frequency level and power level associated with state S1 .

Impedance matching circuit 302 receives RF signals from RF power supplies 322 and 324 during state S1 and matches the impedance of the source and load to generate a modified RF signal. In some embodiments, the impedance of the source is based on one or more RF signals received by the impedance matching circuit 302 from corresponding one or more RF generators that generate the one or more RF signals. The modified RF signal generated during state S1 is transmitted from the impedance matching circuit 302 to the chuck 314 via the RF transmission line 312 .

In various embodiments, during state S1, the achieved etch rate is higher than the etch rate during state S0, the achieved deposition rate is higher than the deposition rate during state S0, or the achieved sputtering rate is sputtering during state SO higher than the rate, or the cleaning rate achieved is higher than the cleaning rate during state SO.

It should be noted that in some embodiments, the power controllers and automatic frequency tuners of the y MHz RF generator are part of DSPy. For example, the power controllers (PWRS0ay, PWRS0by, and PWRS1y) and automatic frequency tuners (AFTS1y, AFTS0ay, and AFTS0by) are parts of a computer program executed by DSPy. As another example, the power controllers (PWRS0ay, PWRS0by, and PWRS1y) and automatic frequency tuners (AFTS1y, AFTS0ay, and AFTS0by) are circuits integrated within the circuitry of DSPy.

In various embodiments, instead of coupling each of the power controllers (PWRS0ay, PWRS0by, and PWRS1y) of the y MHz RF generator to different outputs of DSPy, the power controllers (PWRS0ay, PWRS0by, and PWRS1y) use a switch, e.g. For example, through a multiplexer, etc. one of the DSPys is connected to the same output. During state S1 the switch couples DSPy to the power controller (PWRS1y), during state S0a it couples DSPy to the power controller (PWRS0ay), and during state S0b it couples DSPy to the power controller (PWRS0by).

Similarly, in some embodiments, instead of coupling the power controllers (PWRS0x and PWRS1x) of the x MHz RF generator to different outputs of DSPx, the power controllers (PWRS0x and PWRS1x) are via a switch one of the DSPx and the same connected to the output. The switch couples DSPx to the power controller (PWRS0x) during state S0 and connects DSPx to the power controller (PWRS1x) during state S1.

In various embodiments, instead of coupling each of the automatic frequency tuners (AFTS1y, AFTS0ay, and AFTS0by) of the y MHz RF generator to a different output of DSPy, the automatic frequency tuners (AFTS1y, AFTS0ay, and AFTS0by) are switched, For example, via a multiplexer, etc. one of the DSPys is connected to the same output. The switch couples DSPy to automatic frequency tuner (AFTS1y) during state S1, DSPy to automatic frequency tuner (AFTS0ay) during state S0a, and DSPy to automatic frequency tuner (AFTS0by) during state S0b.

Similarly, in some embodiments, instead of coupling the automatic frequency tuners (AFTS0x and AFTS1x) of the x MHz RF generator to different outputs of DSPx, the automatic frequency tuners (AFTS0x and AFTS1x) are connected via a switch to one of the DSPx and connected to the same output. The switch connects DSPx to the automatic frequency tuner (AFTS0x) during state S0 and DSPx to the automatic frequency tuner (AFTS1x) during state S1.

5B is a diagram of one embodiment of a system 510 to illustrate generation of a TTL1 signal and a TTL3 signal by DSPx of an x MHz RF generator. Instead of receiving the clock signal TTL1 from the clock source of the tool UI system 306 , the clock signal TTL1 is generated by a clock source internal to DSPx. Clock signal TTL1 is used by DSPx to generate a digitally pulsed signal TTL3. The TTL3 signal and the clock signal TTL1 are provided by DSPx to DSPy. In addition, the tool UI system 307 provides the recipe associated with the x MHz RF generator to DSPx and the recipe associated with the y MHz RF generator to DSPy.

For example, the RF signal supplied by the y MHz RF generator may be signal 404 (FIG. 4A) or signal 412 (FIG. 4B) or signal 432 (FIG. 4C) or signal 432 (FIG. 4D) has the same frequency as

6A is a diagram of one embodiment of a graph 600 to illustrate pulsing of an RF signal generated by an x MHz RF generator during both states S1 and S0. The pulsing of the RF signal generated by the x MHz RF generator generates two sub-states S1a and sub-state S1b during state S1, and also two sub-states S0a and sub-state S0b during state S0. Graph 600 plots the power level of propagated RF signal 602 versus time as a function of the RF signal generated by the x MHz RF generator and the RF signal reflected towards the RF generator.

During state S0 of the TTL1 signal, the RF signal 602 fluctuates between states S0a and S0b. Furthermore, during state S1 of the TTL1 signal, the RF signal 602 fluctuates between states S1a and S1b.

In some embodiments, the power level of the RF signal 602 during state S0b is lower or higher than the power level of the RF signal 602 during state S1b.

Note that the use of states S0a and S0b of RF signal 602 helps coarse tuning of processing rate, eg, etch rate or deposition rate or stuffing rate or cleaning rate, etc., during state S0 of the TTL1 signal. Should be.

6B is a graph 610 to illustrate the use of a y MHz RF generator in conjunction with the use of an x MHz RF generator to generate an RF signal 602 having four sub-states S0a, S0b, S1a, and S1b. A drawing of one embodiment. The y MHz RF generator further provides a delivered power RF signal 604 having a state S0, when the x MHz RF generator generates an RF signal to further provide an RF signal 602 having states S0a and S0b to generate an RF signal. In some embodiments, the use of states S0a and S0b of the RF signal 602 generated by the x MHz RF generator allows for constant or good control of the rate, eg, etch rate, deposition rate, sputtering rate, etc. When substantially constant, this allows for coarse control of the rate. In some embodiments, good control of the rate is substantially constant when the y MHz RF generator is operated at a power level corresponding to state SO. In addition, the y MHz RF generator facilitates the provision of the RF signal 604 having the state S1 when the x MHz RF generator facilitates the provision of the RF signal 602 having the states S1a and S1b.

6C is a diagram of one embodiment of a graph 620 to illustrate a duty cycle during state S0 of a TTL1 signal that is different from the duty cycle during state S1 of the TTL1 signal. Graph 620 plots the power delivered by a 2 MHz RF generator versus time. The delivered power is shown as a pulsed signal 622 . It should be noted that the duty cycle of the pulsed signal 622 during state S0 is greater than 50% and the time during which state S1 occurs equals the time during which state S0 occurs. For example, signal 622 occupies a greater amount of time during state S0a than the amount of time occupied during state S0b. It should be noted that the duty cycle of the transmitted power signal 622 during state S1 is 50%.

In some embodiments, the duty cycle of signal 622 during state SO is less than 50%. For example, a propagated signal occupies less amount of time during state S0a than the amount of time occupied during state S0b.

It should also be noted that the duty cycle of signal 602 ( FIGS. 6A and 6B ) during each of states S0 and S1 is 50%. For example, signal 622 occupies an amount of time during state S0a equal to the amount of time occupied during state S0b.

In some embodiments, the duty cycle of the pulsed power signal delivered by the 2 MHz RF generator during state S1 is less than 50%, and the duty cycle of the pulsed delivered power signal during state S0 is 50%.

In various embodiments, the duty cycle of the transmitted power signal pulsed by the 2 MHz RF generator during state S1 is greater than or less than 50%, and the duty cycle of the transmitted power signal pulsed during state S0 is greater than 50% or smaller than

In some embodiments, the time during which state S0 occurs for power delivered by the x MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the x MHz RF generator . In these embodiments, the duty cycle of the power delivered during each of states S0 and S1 is 50%.

In various embodiments, the time during which state S0 occurs for power delivered by the x MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the x MHz RF generator . In these embodiments, the duty cycle of power delivered during state S0 is greater than or less than 50%, and the duty cycle of power delivered during state S1 is equal to 50%.

In some embodiments, the time during which state S0 occurs for power delivered by the x MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the x MHz RF generator . In these embodiments, the duty cycle of power delivered during state S0 is equal to 50%, and the duty cycle of power delivered during state S1 is greater than or less than 50%.

In various embodiments, the time during which state S0 occurs for power delivered by the x MHz RF generator is less than or greater than the time during which state S1 occurs for power delivered by the x MHz RF generator . In these embodiments, the duty cycle of power delivered during state S0 is greater than or less than 50%, and the duty cycle of power delivered during state S1 is greater than or less than 50%.

In some embodiments, the TTL signal has the same frequency as the pulsed signal 622 . The TTL signal is generated by a device that generates a TTL5 signal. For example, DSPx generates a TTL signal from a TTL1 signal and a modulated signal. The modulated signal modulates the TTL1 signal to generate a TTL signal.

7A is a diagram of one embodiment of a system 700 to illustrate the use of four sub-states S0a, S0b, S1a, and S1b within an x MHz RF generator. The system 700 includes a plasma chamber 304 , an x MHz RF generator, a y MHz RF generator, and a tool UI system 306 . A clock source of tool UI system 306 generates clock signal TTL1 and provides clock signal TTL1 via cable 313 to DSPx and DSPy.

During state S0a, DSPx generates a TTL5 signal from the TTL1 signal and provides a TTL5 signal to DSPy. For example, DSPx generates a TTL5 signal by modulating a TTL1 signal using a TTL4 signal. As another example, DSPx generates the TTL5 signal by multiplying the logic level clock signal TTL1 and the logic level TTL4 signal. In various embodiments, the RF signal 602 ( FIGS. 6A and 6B ) has the same frequency as the TTL5 signal. In some embodiments, the RF signal 602 has the same frequency as the TTL4 signal.

During state S0b, DSPx provides a TTL5 signal and a TTL1 signal to the x MHz RF generator's power controller (PWRS0bx) and the x MHz RF generator's automatic frequency tuner (AFTS0bx). For example, during state S0b, DSPx provides a portion of the TTL5 signal with state S0b and a clock signal TTL1 with state S0 to the power controller (PWRS0bx) and automatic frequency tuner (AFTS0bx). The power controller PWRS0bx determines or identifies a power level corresponding to the state S0b of the TTL5 signal and the state S0 of the clock signal TTL1 upon receipt of the TTL5 signal. For example, power controller PWRS0bx identifies a power level that maps from the memory device of power controller PWRS0bx to state S0b of the TTL5 signal and state S0 of the clock signal TTL1. Power controller PWRS0bx provides a power level associated with state S0b of TTL5 signal and state S0 of clock signal TTL1 to RF power supply 322 .

In addition, during the state S0b of the TTL5 signal and the state S0 of the clock signal TTL1, the automatic frequency tuner AFTS0bx determines or identifies the frequency level upon receiving the TTL5 signal and the TTL1 signal. For example, automatic frequency tuner AFTS0bx identifies a frequency level that maps from the memory device of automatic frequency tuner AFTS0bx to state S0b of the TTL5 signal and state S0 of the TTL1 signal. An automatic frequency tuner (AFTS0bx) provides this frequency level to the RF power supply 322 .

Upon receipt of the power level and frequency level corresponding to the state S0b of the TTL5 signal and the state S0 of the clock signal TTL1, the RF power supply 322 generates an RF signal having this power level and frequency level for the state S0b. The RF signal generated during the state S0b of the TTL5 signal and the state S0 of the clock signal TTL1 is supplied to the impedance matching circuit 302 via the RF cable 308 .

In some embodiments, the power level and/or frequency level during state S0b of the TTL5 signal and state S0 of the clock signal TTL1 is the processing rate, eg, the rate of depositing materials on the wafer 318 , or the wafer 318 . ) or the etch rate of the materials on the wafer 318 , or the stuffing rate of the wafer 318 or materials deposited on the wafer 318 , or the cleaning rate of the materials on the wafer 318 or substrate, etc. in a crude manner. Note that it is used to control.

In addition, during state SO, DSPy receives the TTL1 signal from the tool UI system 306 and provides the TTL1 signal to the power controller PWRS0y. The rest of the operation of the y MHz RF generator is similar to that described above with reference to FIG. 3A for the generation of the RF signal.

During state S0 of the y MHz RF generator and state S0b of the x MHz RF generator, impedance matching circuit 302 receives RF signals from the x MHz RF generator and y MHz RF generator via RF cables 308 and 310 and , match the impedance of the source and load to generate a modified RF signal. The modified RF signal is provided to the chuck 314 via an RF transmission line 312 . In some embodiments, the modified RF signal generated during state S0b is a processing rate, eg, a deposition rate of materials on wafer 318 or an etch rate of wafer 318 or material deposited on wafer 318 . or control of the sputtering rate of the wafer 318 or materials deposited on the wafer 318 or the cleaning rate of the materials deposited on the wafer 318 or substrate, and the like.

Also, during state S0a, DSPx provides the TTL5 signal and the TTL1 signal to the power controller (PWRS0ax) of the x MHz RF generator and the automatic frequency tuner (AFTS0ax) of the x MHz RF generator. For example, during state S0a, DSPx provides a portion of the TTL5 signal with state S0a and a TTL1 signal with state SO to the power controller (PWRS0ax) and automatic frequency tuner (AFTS0ax). A power controller (PWRS0ax) determines or identifies a power level upon receipt of the TTL5 signal and the TTL1 signal. For example, power controller PWRS0ax identifies from the memory device of power controller PWRS0ax a power level that maps to state S0a of signal TTL5 and state S0 of clock signal TTL1. A power controller (PWRS0ax) provides this power level to the RF power supply 322 .

In addition, during the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1, the automatic frequency tuner AFTS0ax determines or identifies the frequency level upon reception of the TTL5 signal. For example, the automatic frequency tuner AFTS0ax identifies, from the memory device of the automatic frequency tuner AFTS0ax, a frequency level that maps to the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1. An automatic frequency tuner (AFTS0ax) provides this frequency level to the RF power supply 322 .

Upon receiving the power level and frequency level corresponding to the state S0a, the RF power supply 322 generates an RF signal having this power level and frequency level for the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1. The RF signal generated during the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1 is supplied to the impedance matching circuit 302 via the RF cable 308 .

In some embodiments, the power level and/or frequency level during state S0a of the TTL5 signal and state S0 of the clock signal TTL1 is a processing rate, eg, a deposition rate of materials on wafer 318 , or wafer 318 . or the etch rate of the materials on the wafer 318 , or the stuffing rate of the wafer 318 or materials deposited on the wafer 318 , or the cleaning rate of the wafer 318 or deposition on the wafer 318 . Note that it is used to control the cleaning rate of old materials, etc. in a crude way.

Furthermore, the operation of the y MHz RF generator during state S0 has been described above.

During state S0 of the y MHz RF generator and state S0a of the x MHz RF generator, impedance matching circuit 302 receives RF signals from the x MHz RF generator and y MHz RF generator via RF cables 308 and 310, Match the impedance of the source and load to generate a modified RF signal. The modified RF signal is provided to the chuck 314 via an RF transmission line 312 . In some embodiments, the modified RF signal generated during state S0b is the deposition rate of materials on wafer 318 or etch rate of wafer 318 or material deposited on wafer 318 or wafer 318 or wafer Allows control of the sputtering rate of materials deposited on 318 .

During state S0, DSPy controls power controller PWRS0y to adjust the power determined by power controller PWRS0y upon transition of the x MHz RF generator from state S0a to state S0b or transition of the x MHz RF generator from state S0b to state S0a. ) to transmit a signal. The determined power is adjusted based on the change in plasma impedance that occurs when the power delivered by the x MHz RF generator transitions between states S0a and S0b. To compensate for the adjustment of the power delivered by the x MHz RF generator during the transition between states Soa and Sob, a TTL5 signal is sent from DSPx to DSPy. Adjustment of the power delivered by the x MHz RF generator creates a change in plasma impedance.

Moreover, during state S0, DSPy automatically adjusts the frequency determined by the automatic frequency tuner AFTS0y upon transition of the x MHz RF generator from state S0a to state S0b or the transition of the x MHz RF generator from state S0b to state S0a. Send the signal to the frequency tuner (AFTS0y). The determined frequency is adjusted based on the change in plasma impedance that occurs when the frequency of the x MHz RF generator transitions between states S0a and S0b. To compensate for the adjustment of the frequency of the RF signal generated by the x MHz RF generator during the transition between states Soa and Sob, a TTL5 signal is sent from DSPx to DSPy. Adjustment of the frequency of the RF signal supplied by the x MHz RF generator results in a change in plasma impedance.

In some embodiments, instead of sending the TTL5 signal over the cable from DSPx to DSPy, information about the TTL5 signal, e.g., the frequency of the TTL5 signal during state S1, the duty cycle of the TTL5 signal during state S1, in the TTL5 signal time at which state S1a occurs, time at which state S1b occurs in TTL5 signal, frequency of TTL5 signal during state S0, duty cycle of TTL5 signal during state S0, time at which state S0a occurs at TTL5 signal, time at which state S0b occurs at TTL5 signal It should be noted that the generated time, etc. is provided by the tool UI system 306 to DSPy via cable 314 or another cable similar to cable 314 . Another cable connects the tool UI system 306 to DSPy. For example, information regarding the TTL5 signal is provided in a data file from the tool UI system 306 to DSPy. DSPy is a virtual phase generating a signal fixed to the frequency of the TTL5 signal, and a signal used to adjust the power determined by the power controller PWRS0y and/or the frequency determined by the automatic frequency tuner AFTS0y. Includes fixed loops.

Also, the operation of the x MHz RF generator during states S1a and S1b and the operation of the y MHz RF generator during state S1 are similar to those described above with reference to FIG. 3A .

FIG. 7B is a diagram of one embodiment of a system 710 in which DSPx generates a clock signal TTL1 instead of the tool UI system 306 ( FIG. 7A ). System 710 includes a tool UI system 307 . DSPx includes a clock source that generates clock signal TTL1 and provides clock signals TTL1 and TTL5 signals to DSPy of the y MHz RF generator. The remaining operation of the system 710 is similar to the system 700 of FIG. 7A .

In some embodiments, the power of the RF signal supplied by the x MHz RF generator during states S1a, S1b, S0a, and S0b has the same frequency as signal 602 ( FIG. 6A ).

In various embodiments, instead of sending the TTL5 signal over the cable from DSPx to DSPy, information about the TTL5 signal is provided from DSPx to DSPy over the cable connecting DSPx to DSPy. For example, information about the TTL5 signal is provided in the DSPx to DSPy data file. DSPy is a virtual phase lock generating a signal fixed to the frequency of the TTL5 signal, and a signal used to adjust the power determined by the power controller (PWRS0y) and/or the frequency determined by the automatic frequency tuner (AFTS0y). include loops.

8A is a diagram of one embodiment of a graph 800 to illustrate pulsing of an RF signal generated by a y MHz RF generator during both states S1 and S0. The pulsing of the RF signal generated by the y MHz RF generator generates two sub-states S1a and sub-state S1b during state S1 and also two sub-states S0a and sub-state S0b of state S0. Graph 800 plots the transmitted power, e.g., power level, light versus time of RF signal 802 as a function of the RF signal generated by the y MHz RF generator and the RF signal reflected towards the y MHz RF generator. plot it

During state S0 of the TTL1 signal, the RF signal 802 alternates between states S0a and S0b. Moreover, during state S1 of the TTL1 signal, the RF signal 802 alternates between states S1a and S1b.

In some embodiments, the power level of the RF signal 802 during state S0b is less than or greater than the power level of the RF signal 802 during state S1b.

It should be noted that the use of states S1a and S1b of RF signal 802 during state S1 of the TTL1 signal helps fine-tune the etch rate or deposition rate or stuffing rate or cleaning rate during state S1.

8B is a graph 810 to illustrate the use of an x MHz RF generator in conjunction with the use of a y MHz RF generator to generate an RF signal 802 having four sub-states S0a, S0b, S1a, and S1b. A drawing of one embodiment. The x MHz RF generator generates the RF signal 812 having the state S1 when the y MHz RF generator generates the RF signal 802 having the states S1a and S1b. In some embodiments, the use of states S1a and S1b of the RF signal 802 generated by the y MHz RF generator is a processing rate, eg, an etch rate, when coarse control of the rate is constant or substantially constant. , allowing excellent control of cleaning rates, deposition rates, sputtering rates, and the like. In some embodiments, the coarse control of the processing rate is substantially constant when the x MHz RF generator operates at a power level corresponding to state S1. In addition, the x MHz RF generator generates an RF signal 812 having a state S0 when the y MHz RF generator generates an RF signal 802 having states S0a and S0b.

8C is a diagram of one embodiment of a graph 820 to illustrate a different duty cycle during state S0 of the TTL1 signal than during state S1 of the TTL1 signal. Graph 820 plots the power delivered by a 60 MHz RF generator versus time. The delivered power is shown as a pulsed signal 822 . It should be noted that the duty cycle of the pulsed signal 822 during state S1 is greater than 50% and the time during which state S1 occurs is equal to the period during which state S0 occurs. For example, signal 822 occupies a greater amount of time during state S1a than the amount of time occupied during state S1b. It should be noted that the duty cycle of the transmitted power signal 822 during state S0 is 50%.

In some embodiments, the duty cycle of signal 822 during state S1 is less than 50%. For example, the delivered power signal occupies an amount of time during state S1a that is less than the amount of time occupied during state S1b.

It should also be noted that the duty cycle of signal 802 ( FIGS. 8A and 8B ) during states S0 and S1, respectively, is 50%.

In some embodiments, the duty cycle of the pulsed transmitted power signal generated by the 60 MHz RF generator during state S0 is greater than or less than 50%, and the power of the pulsed transmitted power signal during state S1 is 50% .

In various embodiments, the duty cycle of the pulsed transmitted power signal generated by the 60 MHz RF generator during state S0 is greater than or less than 50%, and the power of the pulsed transmitted power signal during state S1 is greater than 50% larger or smaller

In some embodiments, the time during which state S1 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S0 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of the power delivered during each of states S0 and S1 is 50%.

In various embodiments, the time during which state S1 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S0 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of power delivered during state S1 is greater than or less than 50%, and the duty cycle of power delivered during state S0 is equal to 50%.

In some embodiments, the time during which state S1 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S0 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of power delivered during state S1 is equal to 50%, and the duty cycle of power delivered during state S0 is greater than or less than 50%.

In various embodiments, the time during which state S1 occurs for power delivered by the y MHz RF generator is less than or greater than the time during which state S0 occurs for power delivered by the y MHz RF generator . In these embodiments, the duty cycle of power delivered during state S1 is greater than or less than 50%, and the duty cycle of power delivered during state S0 is greater than or less than 50%.

In some embodiments, the TTL signal has the same frequency as the pulsed signal 822 . The TTL signal is generated by a device that generates a TTL5 signal. For example, DSPx generates a TTL signal from a TTL1 signal and a modulated signal. The modulated signal modulates the TTL1 signal to generate a TTL signal.

9A is a diagram of one embodiment of a system 900 to illustrate the use of four sub-states S0a, S0b, S1a, and S1b of a y MHz RF generator. The system 900 includes a plasma chamber 304 , an x MHz RF generator, a y MHz RF generator, and a tool UI system 306 . A clock source of tool UI system 306 generates clock signal TTL1 and provides clock signal TTL1 via cable 313 to DSPx and DSPy.

During state S1b, DSPx generates a TTL5 signal from the TTL1 signal. In various embodiments, the RF signal 802 ( FIGS. 8A and 8B ) has the same frequency as the TTL5 signal. In some embodiments, the RF signal 802 has the same frequency as the TTL4 signal.

Furthermore, during state S1b, DSPx provides a TTL5 signal to DSPy. DSPy provides the received TTL5 signal and the received TTL1 signal to the y MHz RF generator's power controller (PWRS1by) and the y MHz RF generator's automatic frequency tuner (AFTS1by). For example, during state S1b, DSPy provides a portion of the TTL5 signal with state S1b and a TTL1 signal with state S1 to the power controller (PWRS1by) and the automatic frequency tuner (AFTS1by). A power controller (PWRS1by) determines or identifies a power level upon receipt of a TTL5 signal and a TTL1 signal. For example, power controller PWRS1by identifies a power level that maps from the memory device of power controller PWRS1by to state S1b of the TTL5 signal and state S1 of the TTL1 signal. A power controller (PWRS1by) provides this power level to the RF power supply 324 .

In addition, during the state S1b of the TTL5 signal and the state S1 of the TTL1 signal, the automatic frequency tuner AFTS1by determines or identifies the frequency level upon receiving the TTL5 signal. For example, the automatic frequency tuner AFTS1by identifies, from the memory device of the automatic frequency tuner AFTS1by, the frequency levels that map to the state S1b of the TTL5 signal and the state S1 of the TTL1 signal. An automatic frequency tuner AFTS1by provides this frequency level to the RF power supply 324 .

Upon receiving the power level and frequency level corresponding to the state S1b of the TTL5 signal and the state S1 of the TTL1 signal, the RF power supply 324 generates an RF signal having this power level and frequency level for the state S1b. The TTL5 signal and the RF signal generated during the state S1b during the state S1 of the TTL1 signal are supplied to the impedance matching circuit 302 via the RF cable 310 .

In some embodiments, the power level and/or frequency level is a processing rate during state S1b of the TTL5 signal and state S1 of the TTL1 signal, eg, a deposition rate of materials on the wafer 318 , or etching of the wafer 318 . The rate or etch rate of the materials on the wafer 318, or the sputtering rate of the wafer 318 or materials deposited on the wafer 318, or the cleaning rate of the wafer 318 or materials on the wafer 318, etc. Note that it is used to control in a way.

In addition, during state S1, DSPx receives the TTL1 signal from the tool UI system 306 and provides the TTL1 signal to the power controller PWRS1x. The remaining operation of the x MHz RF generator is similar to that described above with reference to FIG. 5A for the generation of the RF signal.

During state S1 of the x MHz RF generator and state S1b of the y MHz RF generator, impedance matching circuit 302 receives RF signals from the x MHz RF generator and y MHz RF generator via RF cables 308 and 310 and , match the impedance of the source and load to generate a modified RF signal. The modified RF signal is provided to the chuck 314 via an RF transmission line 312 . In some embodiments, the modified RF signal generated during state S1b is a processing rate, eg, a deposition rate of materials on wafer 318 or stuffing of materials deposited on wafer 318 or wafer 318 . Allows control of the rate or cleaning rate of the wafer 318 or materials on the wafer 318 , and the like.

Also, during the state S1a of the TTL5 signal and the state S1 of the TTL1 signal, DSPy provides the received TTL5 signal and the TTL1 signal to the power controller (PWRS1ay) of the y MHz RF generator and the automatic frequency tuner (AFTS1ay) of the y MHz RF generator. For example, during state S1a of the TTL5 signal and state S1 of the TTL1 signal, DSPy provides a portion of the TTL5 signal with state S1a and the TTL1 signal with state S1 to the power controller (PWRS1ay) and automatic frequency tuner (AFTS1ay) . A power controller (PWRS1ay) determines or identifies a power level upon receipt of the TTL5 signal and the TTL1 signal. For example, power controller PWRS1ay identifies from the memory device of power controller PWRS1ay a power level that maps state S1a of the TTL5 signal and state S1 of the TTL1 signal. A power controller (PWRS1ay) provides this power level to the RF power supply 324 .

In addition, during the state S1a of the TTL5 signal and the state S1 of the TTL1 signal, the automatic frequency tuner AFTS1ay determines or identifies the frequency level upon receiving the TTL5 signal. For example, the automatic frequency tuner AFTS1ay identifies, from the memory device of the automatic frequency tuner AFTS1ay, a frequency level that maps the state S1a of the TL5 signal and the state S1 of the TTL1 signal. An automatic frequency tuner AFTS1ay provides this frequency level to the RF power supply 324 .

Upon receiving the power level and frequency level corresponding to the state S1a of the TTL5 signal and the state S1 of the TTL1 signal, the RF power supply 324 generates an RF signal having this power level and frequency level for the state S1a. The RF signal generated during the state S1a of the TTL5 signal and the state S1 of the TTL1 signal is supplied to the impedance matching circuit 302 through the RF cable 310 .

In some embodiments, the power level and/or frequency level during state S1a of the TTL5 signal and state S1 of the TTL1 signal is the processing rate associated with the wafer 318 , eg, a deposition rate of material on the wafer 318 , or The etch rate of the wafer 318 or the etch rate of the materials on the wafer 318 , or the sputtering rate of the wafer 318 or materials deposited on the wafer 318 , or the rate of the materials on the wafer 318 or wafer 318 . It should be noted that it is used to control the cleaning rate, etc. in a good way.

Furthermore, the operation of the x MHz RF generator during state S1 has been described above.

During state S1 of the x MHz RF generator and state S1a of the y MHz RF generator, impedance matching circuit 302 receives RF signals from the x MHz RF generator and y MHz RF generator via RF cables 308 and 310 and , match the impedance of the source and load to generate a modified RF signal. The modified RF signal is provided to the chuck 314 via an RF transmission line 312 . In some embodiments, the modified RF signal generated during state S1a is a processing rate, eg, a deposition rate of materials on wafer 318 or an etch rate of wafer 318 or material deposited on wafer 318 . or control of the sputtering rate of the wafer 318 or materials deposited on the wafer 318 or the cleaning rate of the wafer 318 or materials on the wafer 318, and the like.

Also, the operation of the y MHz RF generator during states S0a and S0b and the operation of the x MHz RF generator during state S0 are similar to those described above with reference to FIG. 1 .

FIG. 9B is a diagram of one embodiment of a system 910 in which DSPx generates a clock signal TTL1 instead of the tool UI system 306 ( FIG. 7A ). System 910 includes a tool UI system 307 . DSPx includes a clock source that generates a clock signal TTL1. DSPx generates digital pulsed signal TTL5 from clock signal TTL1, provides digital pulsed signal TTL5 via cable to DSPy of the y MHz RF generator, and provides TTL1 signal to DSPy via cable. The remaining operation of the system 910 is similar to the system 900 of FIG. 9A .

In some embodiments, the power of the RF signal supplied by the y MHz RF generator during states S1a, S1b, S0a, and S0b has the same frequency as signal 802 ( FIG. 8A ).

10A is a diagram of one embodiment of a graph 1000 to illustrate a plurality of sub-states of both an x MHz RF generator and a y MHz RF generator. Graph 1000 plots delivered power versus time. Power is delivered by the x MHz RF generator and the y MHz RF generator in graph 1000 . When the x MHz RF generator transitions from state S1bx to state S1ax during state S1 of the TTL1 signal, the y MHz generator transitions from state S1by to state S1ay. Furthermore, when the x MHz RF generator transitions from state S1ax to state S1bx during state S1 of the TTL1 signal, the y MHz generator transitions from state S1ay to state S1by. Also, when the x MHz RF generator is in the state S1ax during the state S1 of the TTL1 signal, the y MHz RF generator is in the state S1ay. Also, when the x MHz RF generator is in the state S1bx during the state S1 of the TTL1 signal, the y MHz RF generator is in the state S1by.

When the x MHz RF generator transitions from state S0bx to state S0ax during state S0 of the TTL1 signal, the y MHz generator transitions from state S0by to state S0ay. Furthermore, when the x MHz RF generator transitions from state S0ax to state S0bx during state S0 of the TTL1 signal, the y MHz generator transitions from state S0ay to state S0by. Also, when the x MHz RF generator is in state S0ax during state S0 of the TTL1 signal, the y MHz RF generator is in state S0ay. Also, when the x MHz RF generator is in state S0bx during state S0 of the TTL1 signal, the y MHz RF generator is in state S0by.

It should be noted that the delivered power level of the power signal 1002 delivered by the y MHz RF generator is higher during state S1ay than during state S1by. Moreover, the delivered power level of the power signal 1004 delivered by the x MHz RF generator is higher during state S1ax than during state S1bx.

Furthermore, it should be noted that the delivered power level of the power signal 1002 delivered by the y MHz RF generator is higher during state S0ay than during state S0by. Moreover, the delivered power level of the power signal 1004 delivered by the x MHz RF generator is higher during state S0ax than during state S0bx.

In some embodiments, the delivered power level of the power signal 1002 delivered by the y MHz RF generator is greater than the delivered power level of the power signal 1004 delivered by the x MHz RF generator during state S0bx. lower than during

In some embodiments, the delivered power level of the power signal 1002 delivered by the y MHz RF generator is higher than the delivered power level of the power signal 1004 delivered by the x MHz RF generator during state S1bx. lower than during

10B is a diagram of one embodiment of a graph 1010 to illustrate a plurality of sub-states of both an x MHz RF generator and a y MHz RF generator. Graph 1010 plots the delivered power versus time. Power is delivered by the x MHz RF generator and the y MHz RF generator in graph 1010 . The x MHz RF generator transitions from state S1bx to state S1ax during state S1 of the TTL1 signal, and the y MHz generator transitions from state S1ay to state S1by. Furthermore, when the x MHz RF generator transitions from state S1ax to state S1bx during state S1 of the TTL1 signal, the y MHz generator transitions from state S1by to state S1ay. Also, when the x MHz RF generator is in the state S1ax during the state S1 of the TTL1 signal, the y MHz RF generator is in the state S1by. Also, when the x MHz RF generator is in the state S1bx during the state S1 of the TTL1 signal, the y MHz RF generator is in the state S1ay.

When the x MHz RF generator transitions from state S0bx to state S0ax during state S0 of the TTL1 signal, the y MHz generator transitions from state S0ay to state S0by. Moreover, when the x MHz RF generator transitions from state S0ax to state S0bx during state S0 of the TTL1 signal, the y MHz generator transitions from state S0by to state S0ay. Also, when the x MHz RF generator is in state S0ax during state S0 of the TTL1 signal, the y MHz RF generator is in state S0by. Also, when the x MHz RF generator is in state S0bx during state S0 of the TTL1 signal, the y MHz RF generator is in state S0ay.

It should be noted that the delivered power level of the transmitted power signal 1012 generated by the y MHz RF generator is higher during state S1ay than during state S1by. Moreover, the delivered power level of the transmitted power signal 1014 generated by the x MHz RF generator is higher during state S1ax than during state S1bx.

Furthermore, it should be noted that the delivered power level of the delivered power signal 1012 generated by the y MHz RF generator is higher during state S0ay than during state S0by. Moreover, the delivered power level of the transmitted power signal 1014 generated by the x MHz RF generator is higher during state S0ax than during state S0bx.

In some embodiments, the delivered power level of the delivered power signal 1012 generated by the y MHz RF generator is the delivered power of the delivered power signal 1014 generated by the x MHz RF generator during state S0bx. lower than the level during state S0by.

In some embodiments, the delivered power level of the delivered power signal 1012 generated by the y MHz RF generator is the delivered power of the delivered power signal 1014 generated by the x MHz RF generator during state S1bx. lower than the level during state S1by.

11A is a diagram of one embodiment of a system 1100 to illustrate the use of sub-pulsing simultaneously in both an x MHz RF generator and a y MHz RF generator. Tool UI system 306 includes a clock source that generates a corresponding TTL1 signal and provides it via corresponding cables to both DSPx and DSPy. DSPx generates a TTL5 signal upon receipt of clock signal TTL1 and provides clock signal TTL5 to DSPy. The remaining operation of the x MHz RF generator is similar to that described above with respect to FIG. 7A. Moreover, the rest of the operation of the y MHz RF generator is similar to that described above with respect to FIG. 9A.

11B is a diagram of one embodiment of a system 1110 to illustrate the use of sub-pulsing in both the x MHz RF generator and the y MHz RF generator simultaneously when the x MHz RF generator functions as a master generator. DSPx generates a TTL1 signal and a TTL5 signal, and provides both signal TTL1 and signal TTL5 to DSPy via corresponding cables. The rest of the operation of the x MHz RF generator is similar to that described above with respect to FIG. 7B. Furthermore, the rest of the operation of the y MHz RF generator is similar to that described above with respect to FIG. 9B .

12 is a system 1200 to illustrate the use of a switch 1202 to select one of four sub-states (S1a, S1b, S0a, and S0b) in an x MHz RF generator or a y MHz RF generator. It is a drawing of an embodiment. An example of a switch 1202 includes a multiplexer. In some embodiments, switch 1202 is implemented as a computer program or as hardware within a DSP, eg, DSPx or DSPy. A switch 1202 is coupled to the DSP. For example, when switch 1202 is positioned in an x MHz RF generator, switch 1202 is coupled to DSPx and when switch 1202 is positioned in a y MHz RF generator, switch 1202 is coupled to DSPy. do.

DSP generates bits "00" when the state of a TTL signal, eg, digitally pulsed signal TTL3, digitally pulsed signal TTL5, etc., is in S0a, and when the state of the TTL signal is in S0b, the bit Generates “01”, generates bits “10” when the state of the TTL signal is in S1a, and generates bits “11” when the state of the TTL signal is in S1b. The TTL signal is generated by or received by the DSP. For example, DSPx generates a digital pulsed signal TTL3 or TTL signal TTL5, and DSPy receives the digital pulsed signal TTL3 or digital pulsed signal TTL5.

When the switch 1202 of the RF generator receives bits “00”, the switch 1202 sends a signal to the parameter controller PRS0a, eg, the power controller of the RF generator, an automatic frequency tuner, or the like. Upon receipt of a signal indicating bits “00” from switch 1202 , parameter controller PRS0a is configured to generate a parameter level, eg, a frequency level, a power level, etc. to identify

Similarly, when the switch 1202 of the RF generator receives bits “01”, the switch 1202 sends a signal to the parameter controller PRS0b of the RF generator. Upon receipt of the signal indicating bits “01” from switch 1202, parameter controller PRS0b identifies the parameter level from the mapping between bits “00” and the parameter level.

Also, when the switch 1202 of the RF generator receives bits “10”, the switch 1202 sends a signal to the parameter controller PRS1a of the RF generator. Upon receipt of the signal indicating bits “10” from switch 1202, parameter controller PRS1a identifies the parameter level from the mapping between bits “10” and the parameter level.

In addition, when the switch 1202 of the RF generator receives bits “11”, the switch 1202 sends a signal to the parameter controller PRS1b of the RF generator. Upon receipt of the signal indicating bits “11” from switch 1202, parameter controller PRS1b identifies the parameter level from the mapping between bits “11” and the parameter level.

13A is a diagram of one embodiment of a DSP 1300 to illustrate generation of a TTL3 digital pulsed signal. DSP 1300 includes an internal clock source 1302 and processing logic 1104, eg, a computer program, ASIC, PLD, and the like. In some embodiments, DSP 1300 includes a memory device for storing processor logic 1104 .

The TTL1 signal is generated by an external clock source, eg, a clock source of the tool UI system 306 ( FIG. 3A ), another clock source external to the tool UI system 306 , or the like. In addition, the TTL2 signal is generated by the internal clock source 1302 . For example, the TTL2 signal has a higher frequency than the TTL1 signal.

The processing logic 1104 receives the TTL1 clock signal and the TTL2 signal, and multiplies the signal TTL1 and the signal TTL2 to generate a TTL3 signal, wherein the TTL3 signal is a parameter controller of an RF generator, e.g., a DSP ( 1300) is supplied to the parameter controller of the located x MHz RF generator, y MHz RF generator, etc. or another RF generator, eg, a y MHz RF generator, x MHz RF generator, etc.

In various embodiments, DSP 1300 includes a switch to select between a TTL1 signal and a TTL2 signal based on a state of the TTL1 signal. For example, when the TTL1 signal is in state SO, the switch selects the TTL1 signal for providing to the parameter controller of another RF generator or the parameter controller of an RF generator having DSP 1300 located therein. Furthermore, in this example, when the TTL1 signal is in state S1 , the switch selects the TTL2 signal for providing to the parameter controller of another RF generator or the parameter controller of an RF generator in which the DSP 1300 is located. In this example, the portion of the TTL2 signal having states S1a and S1b is selected during the state S1 of the TTL1 signal.

13B is a diagram of one embodiment of a DSP 1320 used to generate a TTL5 signal. Examples of DSP 1320 include DSPx and DSPy. The DSP 1320 includes an internal clock source 1302 , an inverter 1322 , another internal clock source 1324 , processing logic 1326 , and a summer 1328 .

In some embodiments, summer 1328 , processing logic 1326 , and inverter 1322 are implemented as hardware, eg, using logic gates, or the like. In various embodiments, summer 1328 , processing logic 1326 , and inverter 1322 are implemented as a computer program, eg, processing logic executed by DSP 1320 , or the like.

An internal clock source 1302 generates a clock signal, a TTL4-2 signal, eg, a TTL2 signal, and the like. Processing logic 1326 processes the TTL4-2 signal and the clock signal TTL1 to generate a TTL3 signal. For example, processing logic 1326 multiplies the TTL4-2 signal by the clock signal TTL1 to generate a TTL3 digital pulsed signal. The digital pulsed signal TTL3 is provided to summer 1328 .

In addition, inverter 1322 receives the TTL1 signal and inverts the logic levels of the TTL1 signal. For example, logic level 1 of the TTL1 signal is inverted to logic level 0, and logic level 0 of the TTL1 signal is inverted to logic level 1. Processing logic 1326 receives the inverted TTL1 signal generated by inverter 1322 . In addition, an internal clock source 1324 generates a clock signal TTL4-1 for providing to processing logic 1326 . Processing logic 1326 processes the clock signals TTL4-1 and TTL1 clock signal to generate a TTL signal, which is summed to the TTL3 signal by summer 1328 to generate a TTL5 signal.

It should be noted that in some embodiments, the frequency of each of the TTL4-1 signal and the TTL4-2 signal is greater than the frequency of the TTL1 signal. In various embodiments, the frequency of the TTL4-1 signal is the same as the frequency of the TTL4-2 signal.

In some embodiments, DSP 1320 includes a clock source having a frequency equal to the frequency of pulsed signal 602 ( FIG. 6A ) or pulsed signal 802 ( FIG. 8A ).

14 is a diagram of one embodiment of a DSP 1400 that uses a modulating signal 1203 to generate a sub-state Sna and a sub-state Snb or to determine whether to generate a state Sm. DSPx and DSPy are each an example of DSP 1400 . DSP 1400 receives a clock signal Clk, eg, a TTL1 signal with states Sm and Sn, and the like. In some embodiments, state Sm is a high logic level state and state Sn is a low logic level state. The high logic level is higher than the low logic level.

The DSP 1400 also receives a modulated signal 1203 having three logic levels including a high logic level, a medium logic level, and a low logic level. The middle logic level is higher than the low logic level and the high logic level is higher than the middle logic level. In addition, the intermediate logic level is achieved with a transition from a low logic level that is longer than a transition from a medium logic level to a high logic level.

The DSP 1400 determines that the modulated signal 1203 has a slower transition from the state Sn to the state Sm of the clock signal Clk than the transition from the state Sm to the state Sn of the clock signal Clk. Furthermore, DSP 1400 determines that modulated signal 1203 achieved an intermediate logic level during state Sm of clock signal Clk. DSP 1400 determines that the transition from state Sn to state Sm of clock signal Clk is slower than the transition from state Sm to state Sn of clock signal Clk and modulating signal 1203 is intermediate during state Sm of clock signal Clk. Upon determining that the logic level has been achieved, generate a clock clock 1 signal (Clk1) with state Sm, eg, a TTL3 signal, and the like.

Furthermore, the DSP 1400 determines that the modulated signal 1203 has a faster transition from the state Sm to the state Sn of the clock signal Clk than the transition from the state Sn to the state Sm of the clock signal Clk. Furthermore, DSP 1400 determines that modulated signal 1203 achieved a high logic level during state Sn of clock signal Clk. DSP 1400 determines that the transition from state Sm to state Sn of clock signal Clk is greater than the transition from state Sn to state Sm of clock signal Clk and modulates signal 1203 logic high during state Sn of clock signal Clk. Upon determining that the level has been achieved, generate a Clk1 signal with sub-state Sna and sub-state Snb.

It should also be noted that a single clock source, eg, a clock source generating the clock signal Clk, was used in the technique of FIG. 14 .

In various embodiments, as used herein, a level includes a range. For example, a power level includes a range of amounts of power, e.g., a range of 1950 W to 2050 W, a range of 1900 W to 2100 W, a range of 950 W to 1050 W, a range of 900 W to 1300 W, etc. . As another level, the frequency level is a range of frequencies, eg, in the range of 1.9 MHz to 2.1 MHz, in the range of 1.7 to 2.3 MHz, in the range of 58 MHz to 62 MHz, in the range of 55 MHz to 65 MHz, in the range of 25 to 29 MHz. in the range of MHz, in the range of 23 to 31 MHz, and the like.

Moreover, in various embodiments, the level identified from the memory device of the controller or the memory device of the automatic frequency tuner is a processing rate, eg, an etch rate, or a deposition rate, or a sputtering rate, etc., or wafer 318 . of processing and association, eg, mapping, linking, etc.

Although the operations described above have been described with reference to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, etc., in some embodiments, the operations described above may be applied to other types of plasma chambers, e.g., It is also noted that it applies to plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, and the like. For example, an x MHz RF generator and a y MHz RF generator are coupled to an inductor in the ICP plasma chamber.

Although the above operations have been described as being performed by a DSP, in some embodiments, the operations are performed by one or more processors of the tool UI system 306 ( FIG. 3A ) or by a plurality of processors of the plurality of tool UI systems. or by a combination of the DSP of the RF generator and the tool UI system 306 processor.

Although the embodiments described above relate to providing one or more RF signals to the lower electrode of the chuck 314 of the plasma chamber 304 and grounding the upper electrode 316 of the plasma chamber 304 , some embodiments It should be noted that one or more RF signals are provided to the upper electrode 316 while the lower electrode is grounded.

Embodiments described herein may be practiced in various computer system configurations, including portable hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. Embodiments may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

In some embodiments, the controller is part of a system, which may be part of the examples described above. Such a system includes a semiconductor processing equipment including a processing tool or tools, chamber or chambers, platform or platforms for processing and/or specific processing components (wafer pedestal, gas flow system, etc.). These systems are integrated with electronic devices for controlling the operation of a semiconductor wafer or substrate before, during or after processing thereof. These electronic devices are referred to as “controllers” that may control the system or various components or subparts of the systems. The controller is programmed to control any of the processes described herein according to processing requirements and/or system type, such as delivery of process gases, setting a temperature (eg, heating and/or cooling), setting a pressure. , vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid transfer settings, position and motion settings, and tools and other transfer tools and/or loads that connect to or interface with the system. wafer transfer in and out of locks, and the like.

Generally speaking, in various embodiments, a controller is defined as electronic devices having various integrated circuits, logic, memory, and/or software, which receive instructions, issue instructions, control operation, and perform cleaning operations. Enable and enable endpoint measurements, etc. An integrated circuit includes chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors that execute program instructions (eg, software), or microcontrollers. Program instructions are instructions communicated to a controller or system in the form of various individual settings (or program files) that define operating parameters for executing a process on or for a semiconductor wafer. The operating parameters are, in some embodiments, configured to achieve one or more processing steps during fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. It is part of a recipe prescribed by process engineers.

The controller is, in some embodiments, coupled to or part of a computer integrated into, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller is in the “cloud” or is part or all of a fab host computer system, which allows remote access for wafer processing. The computer enables remote access to the system to monitor the current progress of manufacturing operations, examines a history of past manufacturing operations, examines trends or performance metrics from a plurality of manufacturing operations, and performs current processing change the parameters of , set the processing steps to follow the current processing, and start a new process.

In some embodiments, a remote computer (eg, server) provides process recipes to the system via a network, including a local network or the Internet. The remote computer includes user interfaces that allow input or programming of parameters and/or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data of settings specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, a controller is distributed by including, for example, one or more separate controllers networked together and operating for a common purpose, such as, for example, the processes and controls described herein. An example of a distributed controller for this purpose is one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (eg, at platform level or as part of a remote computer) that are coupled to each other to control a process on the chamber. include circuits.

In various embodiments, without limitation, exemplary systems include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, Physical vapor deposition (PVD) chamber or module, CVD (chemical vapor deposition) chamber or module, ALD (atomic layer deposition) chamber or module, ALE (atomic layer etch) chamber or module, ion implantation chamber or module, tracking chamber or module , and any other semiconductor processing systems used or associated in manufacturing and/or manufacturing semiconductor wafers.

As described above, depending on the process step or steps to be performed by the tool, the controller controls other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, factory It communicates with one or more of the globally located tools, a main computer, another controller, or tools used in transferring material moving containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing plant.

With the above embodiments in mind, it should be understood that some embodiments employ various computer-implemented operations involving data stored within computer systems. These operations are those that physically manipulate physical quantities. Any operations described herein that form part of the embodiments are useful machine operations.

Some embodiments also relate to a hardware unit or apparatus for performing these operations. These devices are specially configured for special purpose computers. When defined as a special purpose computer, the computer can operate for that special purpose, but perform other processing, program execution, or routines that are not part of the special purpose.

In some embodiments, these operations are performed by a computer that is selectively activated, or constituted by one or more computer programs stored in computer memory, cache, or obtained via a computer network. When data is obtained via a computer network, the data may be processed by other computers on the computer network, eg, a cloud of computing resources.

One or more embodiments may also be manufactured as computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit that stores data that is thereafter read by a computer system, eg, a memory device, and the like. Examples of non-transitory computer-readable media are hard drives, network attached storage (NAS), ROM, RAM, compact disk-ROMs (CD-ROMs), CD-Rs (CD-Recordables), CD- CD-rewritables (RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, non-transitory computer-readable medium includes a computer-readable tangible medium that is distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

Although some method acts described above have been presented in a specific order, in various embodiments, other housekeeping operations are performed between the operations, or method operations are coordinated to occur at slightly different times, or at various intervals. It should be understood that the method actions may be distributed in a system to occur, or performed in an order different from that described above.

It is also noted that in one embodiment, one or more features from any of the embodiments described above are combined with one or more features of any other embodiments without departing from the scope described in the various embodiments described in this disclosure. should be understood

Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments should not be construed as illustrative and not restrictive, and the embodiments should not be limited to the details given herein but may be modified within the scope and equivalents of the appended claims.

Claims (20)

generating a pulsed signal; and
providing the pulsed signal to control power of an RF signal generated by a radio frequency (RF) generator, the power being controlled to have a plurality of states and a plurality of sub-states, the RF signal being controlled to have a plurality of states and a plurality of sub-states; providing the pulsed signal, wherein the plurality of sub-states of are alternate with respect to each other in a first one of the plurality of states of the RF signal at a frequency higher than the frequency of the plurality of states; Way. The method of claim 1,
and the power is controlled to be synchronized with the pulsed signal to have a frequency equal to the frequency of the pulsed signal. The method of claim 1,
The plurality of states includes a high state and a low state,
wherein the high state has a higher power level than the low state. The method of claim 1,
the plurality of states comprises two states and the plurality of sub-states comprises two sub-states, and the RF signal is from a second one of the two states to a second one of the two sub-states. transition to one sub-state, then transition from the first one of the two sub-states to the second one of the two sub-states, and then one of the two sub-states transition from the second sub-state to the first one of the two sub-states, then from the first one of the two sub-states to the one of the two sub-states transitioning to a second sub-state, and then transitioning from the second one of the two sub-states to the second one of the two states. 5. The method of claim 4,
the power of the RF signal comprises a plurality of power levels;
and one of the power levels during a low one of the plurality of sub-states is greater than or equal to another one of the power levels during the low one of the plurality of states. The method of claim 1,
generating, by an additional RF generator, an additional RF signal;
providing the RF signal and the additional RF signal to an impedance matching circuit;
generating, by the impedance matching circuit, a modified RF signal based on the RF signal and the additional RF signal, wherein the modified RF signal includes impedances of a plasma chamber and an RF transmission line and the RF generator, the additional RF signal. generating the modified RF signal generated by matching the impedances of an RF generator, an RF cable, and an additional RF cable;
the RF transmission line couples the plasma chamber to the impedance matching circuit;
the RF cable couples the RF generator to the impedance matching circuit, and
and the additional RF cable couples the additional RF generator to the impedance matching circuit. The method of claim 1,
the plurality of sub-states of the RF signal have four sub-states including a first sub-state, a second sub-state, a third sub-state, and a fourth sub-state;
the RF signal transitions from a first power level of the plurality of power levels of the first sub-state to a second power level of the plurality of power levels of the second sub-state, followed by the plurality of power levels transition from the second one of the power levels to the first one of the plurality of power levels of the first sub-state, and then from the first one of the plurality of power levels to the second sub-state transition to the second one of the plurality of power levels of a state, and then from the second one of the plurality of power levels to a third one of the plurality of power levels of the third sub-state and then transition from the third one of the plurality of power levels to a fourth one of the plurality of power levels to achieve the fourth sub-state, and then change the third sub-state to transition from the fourth one of the plurality of power levels to the third one of the plurality of power levels, and then from the third one of the plurality of power levels to the plurality of power levels transitioning to the fourth one of the levels. 8. The method of claim 7,
the second power level of the plurality of power levels is equal to, less than the fourth power level of the plurality of power levels, or the plurality of power levels higher than the fourth power level,
wherein the first power level of the plurality of power levels is lower than the third power level of the plurality of power levels. 8. The method of claim 7,
the second power level of the plurality of power levels is equal to, less than the fourth power level of the plurality of power levels, or the plurality of power levels higher than the fourth power level,
and the first one of the plurality of power levels is higher than the third one of the plurality of power levels. processor; and
a memory device coupled to the processor;
The processor is:
generate a pulsed signal; and
configured to provide the pulsed signal to control the power of a radio frequency (RF) signal,
The power is controlled to have a plurality of states and a plurality of sub-states, the plurality of sub-states of the RF signal being one of the plurality of states of the RF signal at a frequency higher than a frequency of the plurality of states. alternating with respect to each other in a first state. 11. The method of claim 10,
a power controller coupled to the processor; and
a frequency tuner coupled to the processor;
The power controller determines a power level based on a mapping between a plurality of states of the pulsed signal and a plurality of power levels and based on a mapping between a plurality of sub-states and a plurality of power levels of the pulsed signal. configured to identify, and
The frequency tuner is configured to determine a frequency level based on a mapping between a plurality of frequency levels and a plurality of states of the pulsed signal and based on a mapping between a plurality of frequency levels and a plurality of sub-states of the pulsed signal. A controller system configured to identify 11. The method of claim 10,
The plurality of states includes two states, and the RF signal transitions from a second one of the two states to the plurality of sub-states, and then from the plurality of sub-states to the two states. and transition to the second one of the states. A processor, the processor to generate a pulsed signal; and provide the pulsed signal to control a power of a radio frequency (RF) signal, wherein the power is controlled to have a plurality of states and a plurality of sub-states, the plurality of sub-states of the RF signal -states alternate with respect to each other in a first one of said plurality of states of said RF signal at a frequency higher than a frequency of said plurality of states;
an RF power supply configured to generate the RF signal having the power;
an RF cable coupled to the RF power supply;
an impedance matching circuit coupled to the RF power supply, the impedance matching circuit configured to receive the RF signal via the RF cable, the impedance matching circuit configured to generate a modified RF signal from the RF signal the impedance matching circuit configured to match an impedance of a load coupled to the impedance matching circuit and an impedance of a source coupled to the impedance matching circuit; and
a plasma chamber coupled to the impedance matching circuit, the plasma chamber configured to receive the modified RF signal to change an impedance of the plasma. 14. The method of claim 13,
an RF transmission line coupling the plasma chamber to the impedance matching circuit;
the load comprises the plasma chamber and the RF transmission line;
wherein the source comprises the RF cable and an RF generator. 14. The method of claim 13,
the plurality of states has two states, the RF signal transitions from a second one of the two states to a first one of the plurality of sub-states, and then the plurality of sub-states transition from the first sub-state of the to a second sub-state of the plurality of sub-states, and then from the second sub-state of the plurality of sub-states to the one of the plurality of sub-states transition to a first sub-state, then transition from the first one of the plurality of sub-states to the second one of the plurality of sub-states, and then the plurality of sub-states transitioning from the second one of states to the second one of the two states. 14. The method of claim 13,
The plurality of states includes two states, and the RF signal transitions from a second one of the two states to the plurality of sub-states, and then from the plurality of sub-states to the two states. and transitioning to the second state. delete delete delete delete

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