KR102376590B1 - organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device, wherein the drain electrode of an electrostatic discharge (ESD) transistor formed in the non-display area on the source pad side (S-Pad) or non-pad side (X-Pad) of an OLED display panel is a drain contact. By being electrically connected to the cathode electrode layer by a hole, a separate base voltage (VSS) wiring may not be formed in the ESD transistor area, and therefore, short or burnt ( Burnt) can be prevented and the width of the driving voltage (VDD) wiring can be increased, providing convenience in design and reducing power consumption by reducing resistance.

Description

Organic light emitting display device {ORGANIC LIGHTING EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display panel or organic electric field display device including an electrostatic discharge element.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, liquid crystal displays (LCDs), plasma displays (PDPs: plasma display panels), and organic light emitting devices are increasing. Various display devices such as OLED (Organic Light Emitting Display Device) are being used. These various display devices include display panels suitable for them.

The display panel included in such a display device may be one of several display panels made from one substrate. That is, according to various process procedures, elements constituting pixels, signal lines, or power lines can be formed for each display panel unit on one substrate. In addition, the display panel has a number of thin film transistors and a pixel area controlled by these thin film transistors, and an OLED display panel that uses an organic light emitting element as an element that emits light in the pixel area has a thin film transistor element to control the organic light emitting element. Each is connected.

During the manufacturing process or testing process of the conventional OLED display panel, there was a problem in which abnormal static electricity was generated, causing damage to various elements inside the display panel. To this end, anti-static transistors (Electro-Static Discharge Transistor) Anti-static elements may be used.

The drain or output terminal of these anti-static devices must be connected to a low-potential power supply voltage or base voltage (VSS), and for this purpose, a base voltage wiring must be formed near the anti-static device. In this case, the base voltage wiring for the anti-static device. There was a risk of overlapping with the driving voltage (Vdd) wiring and causing a brunt between the two wirings.

In addition, the base voltage wiring for these anti-static devices occupies a certain area of the edge of the display panel, which not only has a negative impact on the wiring design and design margin of the non-display area, but also creates a narrow bezel. There was a problem that acted as an obstacle.

Against this background, the purpose of the present invention is to provide an organic light emitting display device including an anti-static device with a simple structure.

Another object of the present invention is to directly connect one of the terminals of the anti-static transistor disposed in the non-display area of the OLED display panel to the cathode electrode layer to eliminate the base voltage (Vss) wiring for connecting the anti-static element, thereby reducing the gap between voltage wiring. The goal is to provide an OLED display panel that can prevent brunt.

Another object of the present invention is to directly connect one of the terminals of the anti-static switching device disposed in the non-display area of the OLED display panel to the cathode layer, eliminating the base voltage (Vss) wiring for connecting the anti-static device, thereby improving wiring design. The goal is to provide an OLED display panel that can achieve narrow bezels by securing margins.

Another object of the present invention is to provide an OLED display panel that can reduce power consumption by reducing resistance by increasing the width of the driving voltage wiring instead of eliminating the base voltage (Vss) wiring for connecting anti-static elements.

In order to achieve the above-described object, according to an embodiment of the present invention, an anode electrode layer connected to the drain electrode of the driving transistor, a cathode electrode layer to which a base voltage (VSS) is applied, and an organic light emitting layer disposed between both electrode layers. An organic light emitting display device comprising an electrostatic discharge (ESD) transistor disposed in a non-display area of the organic light emitting display device, wherein the electrostatic discharge transistor includes a source electrode electrically connected to one or more data pads or an end of a data line; An organic light emitting display device is provided including a drain electrode electrically connected to the cathode electrode layer.

According to one embodiment of the present invention, one of the terminals of the anti-static switching device disposed in the non-display area of the OLED display panel is directly connected to the cathode layer to eliminate the base voltage (Vss) wiring for connecting the anti-static device, Brunts between voltage wires can be prevented, and the gap between wires can be increased or a narrow bezel can be achieved by securing a wiring design margin.

In addition, according to one embodiment of the present invention, one of the terminals of the anti-static switching device disposed in the non-display area of the OLED display panel is directly connected to the cathode layer to eliminate the base voltage (Vss) wiring for connecting the anti-static device. By increasing the width of other wiring, there is an effect of reducing power consumption by reducing resistance.

1 is a diagram illustrating a schematic configuration of a display device and an equivalent circuit of a pixel according to embodiments.
FIG. 2 is a cross-sectional view showing the stacked structure of the driving transistor area of FIG. 1.
Figure 3 shows a non-display area of an OLED display panel in which an electro-static discharge (ESD) transistor to which an embodiment of the present invention is applied is formed.
Figure 4 is a plan view and cross-sectional view of a general electro-static discharge (ESD) transistor on the data pad side (S-Pad).
Figure 5 is a top view of a typical electrostatic discharge (ESD) transistor on the non-pad side (X-Pad).
Figure 6 is a plan view showing an ESD transistor formed on the source pad side (S-Pad) according to an embodiment of the present invention.
FIG. 7 is a cross-sectional structure of the ESD transistor according to the embodiment of FIG. 6, taken along line II' of FIG. 6.
Figure 8 is a plan view showing an ESD transistor formed on the non-pad side (X-Pad) according to another embodiment of the present invention.
FIG. 9 is a cross-sectional structure of the ESD transistor according to the embodiment of FIG. 8, taken along line II-II' of FIG. 8.
Figure 10 is a top view of an ESD transistor on the source pad side (S-Pad) according to another embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Additionally, when describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

1 is a schematic configuration diagram of a display device to which an embodiment of the present invention can be applied and a diagram showing an equivalent circuit of a pixel.

Referring to FIG. 1, an OLED display panel or OLED display device 100 to which an embodiment of the present invention can be applied has a plurality of first lines (VL1 to VLm) formed in a first direction (e.g., vertical direction), A display panel 110 in which a plurality of second lines (HL1 to HLn) are formed in a second direction (e.g., horizontal direction), and a first driving unit that supplies the first signal to the plurality of first lines (VL1 to VLm) (120), a second driving unit 130 that supplies a second signal to a plurality of second lines (HL1 to HLn), and a timing controller 140 that controls the first driving unit 120 and the second driving unit 130. ), etc.

The display panel 110 includes a plurality of first lines (VL1 to VLm) formed in a first direction (e.g., vertical direction) and a plurality of second lines (HL1 to HLn) formed in a second direction (e.g., horizontal direction). Multiple pixels (P: Pixel) are defined according to the intersection of .

Each of the above-described first driving unit 120 and second driving unit 130 may include at least one driving integrated circuit (Driver IC) that outputs a signal for image display.

As an example, the plurality of first lines (VL1 to VLm) formed in the first direction on the display panel 110 are formed in the vertical direction (first direction) and transmit data voltage (first signal) to the pixel column in the vertical direction. The first driver 120 may be a data driver that supplies data voltage to the data line.

In addition, the plurality of second lines (HL1 to HLn) formed in the second direction on the display panel 110 are formed in the horizontal direction (second direction) and are gates that transmit a scan signal (first signal) to the pixel column in the horizontal direction. It may be a wiring, and the second driver 130 may be a gate driver that supplies a scan signal to the gate wiring.

Additionally, a pad portion is formed in the display panel 110 to connect the first driving unit 120 and the second driving unit 130. When the first signal is supplied from the first driving unit 120 to the plurality of first lines (VL1 to VLm), the pad unit transmits it to the display panel 110, and similarly, the second driving part 130 transmits the first signal to the plurality of second lines (VL1 to VLm). When the second signal is supplied to HL1 to HLn), it is transmitted to the display panel 110. Therefore, the pad portion can be formed together in the process of forming the pixel area of the display panel 110.

In this specification, among the four edges of the display panel, the edge on the side of the first driver 120, which is the data driver (D-IC or S-IC), is referred to as the source pad side (S-Pad), and the opposite edge is referred to as the non-pad side. It is expressed as (X-Pad).

A plurality of data pads or source pads are formed on the source pad side (S-Pad) as terminals connected to data wires or data lines, and generally no data pads are formed on the non-pad side (X-Pad).

The enlarged display area in FIG. 1 shows an equivalent circuit of the pixel structure of an OLED display device to which embodiments of the present invention are applied.

Each of the plurality of pixels included in the OLED display panel 110 is basically an organic light emitting diode (OLED), a driving transistor (DT), a first transistor (T1), a second transistor (T2), and a storage capacitor (Cstg). Includes etc. Each transistor is a thin film transistor (or TFT).

An organic light emitting diode (OLED) has a first electrode (e.g. anode or cathode) connected to a driving transistor (DT), and a second electrode (e.g. cathode or anode) that supplies a base voltage (Vss or EVSS). It can be connected to Dan.

The driving transistor (DT) is a transistor for driving an organic light emitting diode (OLED). It is controlled by the voltage applied to the second node (N2), which is the gate node, and is driven from the driving voltage line (DVL). A voltage (VDD: Driving Voltage, or EVDD) is applied to the third node (N3), and current is supplied to the organic light-emitting diode (OLED), allowing the organic light-emitting diode (OLED) to emit light.

The first transistor (T1) is a transistor connected between the reference voltage supply node (Nref: Reference Node) to which the reference voltage (Vref: Reference Voltage) is supplied and the first node (N1) of the driving transistor (DT), and is a gate transistor. It is controlled by the scan signal (SCAN) supplied through the line (GL), and the reference voltage (Vref) applied to the reference voltage supply node (Nref) can be applied to the first node (N1) of the driving transistor (DT). there is.

The second transistor (T2) is a transistor connected between the data line (DL) and the second node (N2) of the driving transistor (DT), and receives a scan signal (SCAN) applied to the gate node of the first transistor (T2). is controlled by being applied to the gate node, and the data voltage (Vdata) supplied through the data line (DL) is supplied to the second node (N2), which is the gate node of the driving transistor (DT).

The storage capacitor Cstg is connected between the first node N1 and the second node N2 of the driving transistor DT and serves to maintain the voltage for one frame.

As described above, the first transistor T1 and the second transistor T2 simultaneously receive the scan signal SCAN through one gate line GL. Accordingly, the gate nodes of the first transistor (T1) and the second transistor (T2) are connected to each other in a circuit manner.

Meanwhile, in this specification and drawings, all transistors are described as N-type examples, but depending on the circuit design method, all or some transistors may be designed as P-type.

FIG. 2 is a diagram showing the configuration of a portion (N1) of the driving transistor of FIG. 1 and an organic light emitting layer (OLED). As seen in FIG. 2, the electrode that drives the OLED device is connected to the first node (N1) of the driving transistor (DT).

Figure 2 illustrates a case where the driving transistor is a bottom gate type in which the gate is placed below the source/drain, and although not shown, on the contrary, a top gate type in which the gate is placed above the source/drain. It may be a method.

In Figure 2, on the substrate 200, the gate 210 of the driving transistor, the gate insulating film 215, the drain 220 of the driving transistor, a passivation layer 225, and a planarization layer (or a planarization film, an overcoat layer). , 230) is formed, and a contact hole is formed on the passivation layer 225 and the planarization layer 230.

The anode layer 240 constituting the pixel electrode contacts the drain 220 through a contact hole. A bank 250 is formed on the anode 240 and other planarization layers 230 to demarcate the OLED light-emitting area, and then the organic light-emitting layer 260 and the cathode layer (270) are formed.

Figure 3 shows a non-display area of an OLED display panel in which an anti-static (Electro-Static Discharge; hereinafter referred to as 'ESD') transistor to which an embodiment of the present invention is applied is formed, and Figure 3 (b) shows the ESD transistor's non-display area. The equivalent circuit is shown.

Figure 3(a) particularly shows the vicinity of the ESD transistor in the non-display area on the source-pad side (S-Pad) of the OLED display panel.

As shown in Figure 3 (a), the source-pad side (S-Pad) of the OLED display panel has a number of terminals such as a data pad 320, which is a terminal connected to the data line, and a reference voltage (Vref) pad 310. A signal pad is formed.

In addition, among the signal pads, an ESD transistor (ESD Tr; 350) is formed between the data pad 320 or the source pad and the base voltage line (VSS; 340) as an ESD switching element to dissipate static electricity generated in the data line.

Figure 3 (b) is an equivalent circuit of the ESD transistor 350. When a large amount of static electricity is generated in the data line (Vdata) during the display panel manufacturing process or testing process, a voltage is applied to the gate and source of the ESD transistor. As a result, the ESD transistor is turned on, and as a result, electrostatic charges are discharged through the base voltage wiring 340.

Figure 4 is a plan view and cross-sectional view of a general electro-static discharge (ESD) transistor on the data pad side (S-Pad).

As shown in FIG. 4, looking at the ESD transistor structure on the data pad side (S-Pad), there is a gap between the data pad 320, which is a plurality of signal pads formed of a gate metal layer, and the base voltage line 340, which is also formed of a gate layer. The ESD transistor 400 is formed.

The ESD transistor 400 includes a gate electrode 430, a source electrode 410, and a drain electrode 420. The source electrode is electrically connected to the data pad 320, and the drain electrode 420 is connected to the drain contact hole. It is electrically connected to the base voltage (VSS) wiring pattern at the bottom through (422).

The stacked structure and manufacturing process of the ESD transistor will be described with reference to the cross-sectional view in FIG. 4(b) as follows.

First, a gate metal layer is formed on the substrate 500 and then patterned to form the gate electrode 430 of the ESD transistor 400, the base voltage line 340, and the data pattern 320, and form a pattern on the top of the gate metal layer. A gate insulating layer 515 is formed.

Next, the active layer 516, which becomes the channel of the ESD transistor 400, is formed in the upper area of the gate electrode, and then the source electrode 410 and drain electrode 420 of the ESD transistor, which are formed as source/drain metal layers, are formed on the upper area of the gate electrode. form At this time, the source electrode 410 and drain electrode 420 of the ESD transistor must be connected to the data pad 320 and the base voltage (VSS) wire formed as a gate layer at the bottom, respectively, so that the source contact is made to the gate insulating layer 515. After forming the hole 412 and the drain contact hole 422, source/drain layers are deposited.

As shown in FIG. 4, a base voltage wire 340 is necessary to connect the drain electrode 420 to the base voltage (VSS), and this base voltage wire 340 has a constant width as a gate layer pattern. It extends in the horizontal direction (second direction).

Meanwhile, a driving voltage wiring (VDD) 350 is formed to extend in the vertical direction (first direction) between the data lines on both sides. This driving voltage wiring 350 is formed as a gate layer. ') and a second driving voltage line (350") formed of source/drain layers.

For the ESD transistor 400 as shown in Figure 4. A base voltage line 340 that has a constant width as a gate layer pattern and extends in the horizontal direction (second direction), and a second drive voltage that has a constant width and extends in the vertical direction (first direction) as a source/drain pattern. As the wires 350" intersect, an overlap area 360 is created.

Since both metal layers are formed in this overlap area 360 with only the gate insulating layer 515 in between, a short or burn phenomenon occurs between the two power supply wires (VSS, VDD) during the manufacturing process, etc. There was a problem.

Figure 5 is a top view of a typical electrostatic discharge (ESD) transistor on the non-pad side (X-Pad).

As shown in Figure 5, the ESD transistor 500 is formed in the non-display area on the non-pad side (X-Pad), which is the edge where data pads, etc. are not formed, and the ESD transistor 500 on the non-pad side is formed as a gate layer. It includes a gate electrode 530, a source electrode 510 extending from a data line that is a source/drain layer, and a drain electrode 520 integrally extending from a base voltage line 340 that is also formed as a source/drain layer. .

Meanwhile, as shown in FIG. 5, on the non-pad side, the driving voltage wiring (VDD) 350 is formed to extend in both the vertical and horizontal directions, and the base voltage wiring 340 is a source/drain layer and has a certain width and extends in the horizontal direction. It is formed to extend to a certain length.

Therefore, as shown in FIG. 5, for the non-pad side ESD transistor 500, both the base voltage wiring 340 extending in the horizontal direction and the driving voltage wiring 350 extending parallel thereto must be formed. Meanwhile, since the space margin of the non-display area where the ESD transistor is formed is not large, it is difficult to keep the width (w1) of the driving voltage line (VDD) 350 above a certain size.

Meanwhile, the smaller the electrical resistance of the driving voltage line (VDD) 350, the lower the power consumption. Therefore, in order to reduce the resistance of the driving voltage line, the driving voltage line 350 is connected to the first driving voltage line 350' of the gate layer. It is advantageous not only to form the second driving voltage wiring 350", which is the source/drain layer, but also to increase the width w1 of the driving voltage wiring.

However, according to the non-pad side ESD transistor 500 as shown in FIG. 5, the base voltage wiring 340 must be formed in the horizontal direction, and the width of the driving voltage wiring cannot be sufficiently large due to the limited margin of the non-display area. When the width of the driving voltage wiring is increased in consideration of efficiency, there is a problem in that the non-display area becomes larger, making it difficult to achieve a narrow bezel.

In order to overcome this problem, an embodiment of the present invention directly connects the drain electrode of the electrostatic discharge (ESD) transistor formed in the non-display area of the OLED display panel to the cathode electrode layer to which the base voltage (VSS) is applied, thereby forming the ESD transistor. We aim to solve the various problems described above by removing the base voltage wiring in the area.

Looking at the specific configuration of the present invention, a non-display area of an organic light emitting display device including an anode electrode layer connected to the drain electrode of a driving transistor, a cathode electrode layer to which a base voltage (VSS) is applied, and an organic light emitting layer disposed between both electrode layers. It includes a static discharge transistor disposed in, and the static discharge transistor may include a source electrode electrically connected to one or more data pads or an end of a data line, and a drain electrode electrically connected to the cathode electrode layer.

Figure 6 is a plan view showing an ESD transistor formed on the source pad side (S-Pad) according to an embodiment of the present invention, and Figure 7 is a cross-sectional structure of the ESD transistor according to the embodiment of Figure 6, I of Figure 6 This is a cross-sectional view cut along -I'.

The organic light emitting display device according to an embodiment of the present invention shown in FIG. 6 includes an electrostatic discharge transistor (ESD Tr; 700) formed in a portion of the non-display area on the source pad side (S-Pad) of the display device, The ESD transistor 700 is formed at the top by a gate electrode 730 on which a gate layer is formed, a source electrode 710 electrically connected to the data pad 620 formed on the source pad side, and a drain contact hole 722. It may be configured to include a drain electrode 720 that is electrically connected to a cathode electrode layer (570 in FIG. 7) to which a low voltage (VSS) is applied.

To be more specific, the non-display area on the source pad side (S-Pad) of the organic light emitting display device includes a reference voltage pad 610 and a driving voltage line 650 formed at the end of the reference voltage line extending from the display area. and a data pad 620 extending from two data lines is formed between them.

The reference voltage pad 610 and data pad 620 on the source pad side (S-Pad) may be formed of a gate metal layer, and the driving voltage line 650 is a gate layer that extends only to a portion of the non-display area. It may be configured to include 1 driving voltage wiring 650' and a second driving voltage wiring 650" of the source/drain layer that partially overlaps the first driving voltage wiring 650' and extends to the remaining non-display area. there is.

At this time, the ESD transistor 700 according to an embodiment of the present invention includes a gate electrode 730, an active layer (740 in FIG. 7) formed on the gate electrode 730, and a source formed on the source/drain layer on the upper part of the active layer to be spaced apart from each other. It is configured to include an electrode 710 and a drain electrode 720.

Since the source electrode 710 of the ESD transistor 700 must be electrically connected to the data pad 620, although not shown, the source electrode 710 is a gate leading edge layer ( It may be connected to the data pad 620 through a source contact hole penetrating a portion of 515).

In addition, unlike the method shown in FIG. 4, the drain electrode 720 of the ESD transistor 700 according to the embodiment of FIG. 6 is not connected to a separate base voltage wire (340 in FIG. 4), but is connected to the drain electrode ( It is connected to the cathode electrode layer (570 in FIG. 7) formed at the top through the drain contact hole 722 formed at the top of 720).

At this time, the drain contact hole 722 may be formed through one or more of the passivation layer, overcoater (OC) layer, and bank layer deposited on the source/drain layer, see FIG. 7 for this. For reference, this is explained in more detail below.

That is, the organic light emitting display device according to the embodiment of FIG. 6 does not separately include a base voltage wiring pattern extending in the horizontal direction to be connected to the drain electrode of the ESD transistor in the ESD transistor area, and the base voltage (VSS) is applied. It is connected to the top layer, the cathode layer.

As described above, according to the first embodiment of the present invention as shown in FIGS. 6 and 7, a base voltage is applied to the drain electrode of the ESD transistor formed in the non-display area of the source pad side (S-Pad) of the OLED display device. Since there is no need for a separate base voltage wiring (340 in FIG. 4), as in the case of FIG. 4, an overlap area 360 where the electromotive voltage wiring 340 and the driving voltage wiring 350" intersect in the ESD transistor area. There is no room for this to occur, and therefore, the occurrence of a short or burn in the overlap area of the electromotive voltage wiring and the driving voltage wiring can be fundamentally blocked.

Meanwhile, in the embodiment of FIG. 6, the source electrode 710 of the ESD transistor 700 is formed further outside the drain electrode 720. That is, the source electrode 720 of the ESD transistor connected to the data pad 620 is formed further outside the non-display area, and the drain electrode 720 of the ESD transistor connected to the cathode electrode layer 570 is formed further outside the display area. It is placed on the nearby side.

Constructed in this way, according to the embodiment of the present invention, the drain electrode 720 must be connected to the cathode electrode layer 570, and therefore the cathode electrode layer 570 must be deposited up to the upper area of the drain electrode 720. Therefore, when the drain electrode 720 is placed on the outer side of the non-display area, the deposition area of the cathode electrode layer 570 must also be wider, so the drain electrode 720 of the ESD transistor is placed closer to the display area as shown in FIG. 6. When placed, there is an effect of minimizing the formation area of the cathode electrode layer 570.

Hereinafter, the cross-sectional structure and manufacturing process of the ESD transistor according to an embodiment of the present invention will be described in detail with reference to FIG. 7.

Meanwhile, the left side of FIG. 7 shows the cross-sectional structure of the ESD transistor (II' cross-section in FIG. 6) according to an embodiment of the present invention, and to aid understanding, the right side shows the cross-sectional structure of the driving transistor (DTr) included in each pixel of the display area. are shown together.

The drawing of FIG. 7 shows a bottom gate type OLED display panel, but the present invention is not limited to this bottom gate type, and the drain electrode 720 of the ESD transistor is connected to the uppermost cathode electrode layer. As long as it can be connected, it can also be applied to top gate OLED.

The organic electroluminescent device consists of a first substrate on which a driving and switching thin film transistor (DTr, not shown) and an organic electroluminescent diode (E) are formed, and a second substrate for encapsulation, shown on the right side of FIG. 7. As described above, the configuration of the first substrate is first described as follows.

A gate wiring (not shown) extending in one direction is deposited on the insulating substrate 500 with a low-resistance metal material, such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), or copper alloy, and patterned. ) and a driving voltage line (VDD; 650) are formed, and at the same time, a gate electrode 310 is formed in the switching area and the driving area (DA, not shown).

At this time, the ESD transistor area according to the embodiment of the present invention includes the gate electrode 730 of the ESD transistor, the reference voltage (Vref) line and the reference voltage pad 610 at its end, and each data line and its end. A data pad 620 and the like are also formed.

Next, an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiNx), is deposited on the gate electrode 310 of the driving transistor and the gate electrode 730 of the ESD transistor to form a gate insulating layer 515.

Thereafter, an active layer 315 of pure amorphous silicon is formed on the gate insulating layer 515 on top of the gate electrodes 310 and 730 of the driving transistor and the ESD transistor, and an impurity amorphous silicon pattern (not shown) made of impurity amorphous silicon is formed on the active layer 315 of pure amorphous silicon. form a poem).

Next, a metal material constituting a source/drain layer is deposited on the front surface of the impurity amorphous silicon pattern (not shown) and patterned to define a pixel area (P) by intersecting the gate wiring (not shown) on the gate insulating film. It forms a data wire (not shown) and a power wire (not shown) arranged in parallel and spaced apart from this, and at the same time, the source and drain electrodes 318 of the driving transistor are spaced apart from each other on the impurity amorphous silicon pattern (not shown). , 320). At this time, the source electrode (not shown) formed in the switching area (not shown) is connected to the data wire (not shown).

At this time, the source electrode 710 and the drain electrode 720 of the ESD transistor are formed together in the ESD transistor area according to the embodiment of the present invention.

In particular, in the embodiment of FIG. 6, since the source electrode 720 of the ESD transistor must be electrically connected to the data pad, which is the gate layer, the source penetrating a portion of the gate insulating layer 515 on top of the data pad 620 After forming a contact hole (not shown) and forming a source/drain layer on top of it, the source electrode 720 of the ESD transistor must be patterned.

Next, an ohmic contact layer is formed by removing the impurity amorphous silicon pattern (not shown) exposed between the source and drain electrodes 318 and 320 of the driving transistor. As a result, the semiconductor layer consisting of the gate electrode 310, the gate insulating film 515, the active layer 315, and the ohmic contact layer, and the source and drain electrodes 318 and 320 spaced apart from each other are used as a switching or driving thin film transistor ( Not shown, DTr).

Of course, in the process of forming the active layer 315 and/or the semiconductor layer of the driving transistor, the active layer for the ESD transistor 700 according to the present invention is formed on the gate electrode 730 of the ESD transistor.

Next, a passivation layer or protective layer 525 is formed on the driving and switching thin film transistor (DTr, not shown) in the pixel area and the ESD transistor 700 in the non-display area and patterned to form the driving thin film transistor (DTr). ) A drain contact hole is formed to expose the drain electrode 320.

In this process, the drain contact hole 722 of the ESD transistor 700 according to an embodiment of the present invention is formed. That is, a portion of the protective layer (PAS) 525 deposited on the drain electrode 720 of the ESD transistor 700 is etched to form a drain contact hole 722 that exposes a portion of the drain electrode 720. And, the drain electrode 720 of the ESD transistor 700 is electrically connected to the cathode electrode layer 570 by depositing the cathode electrode layer 570 on the top.

Of course, in Figure 7, the drain contact hole 722 is shown as penetrating only the protective layer 525, but if the anode (Anode) 340, overcoat layer (OC layer), and bank extend to the non-display area where the ESD transistor is formed, In the case where the layer 350 is deposited, the drain contact hole 722 must be formed penetrating not only the protective layer 525 but also the anode, overcoat layer (OC layer), and bank layer.

Next, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), which are transparent conductive materials with a relatively high work function value, is deposited and patterned onto the protective layer 525 to have a thickness of several thousand Å, thereby forming each pixel. An anode electrode layer 340, which is a first electrode in contact with the drain electrode 320 of the driving thin film transistor (DTr), is formed for each region (P) through a drain contact hole, and an organic insulating material, such as an organic insulating material, is applied to the top of the anode electrode layer 340. For example, photo acryl or benzocyclobutene (BCB) is applied to form a first organic insulating material layer (not shown), and then patterned to form a bank layer 350 bordering each pixel area (P). form

An organic light-emitting layer (EL layer; 360) is formed on the top, and a metal material with a relatively low work function value, such as aluminum (Al), aluminum alloy, silver (Ag), magnesium (Mg), and gold, is placed on top of the organic light-emitting layer (EL layer; 360). A cathode electrode layer 370, which is a second electrode, is formed on the entire surface to have a relatively thin thickness of about 5Å to 50Å by performing thermal evaporation or ion beam evaporation of (Au). These cathode electrode layers 370, 570 are formed across the entire panel to extend to the entire display area and a portion of the non-display area, and are electrically connected to the base voltage (VSS) wiring pattern (not shown) formed in the display area or other areas. It is connected and receives base voltage (VSS).

As a result, the drain electrode 720 of the ESD transistor 700 is connected to the cathode electrode layer 570 through the drain contact hole 722, thereby enabling the ESD transistor to be connected without forming a separate base voltage (VSS) wiring in the ESD transistor area. The drain electrode of can be connected to the base voltage, and therefore, as in the case of FIG. 4, the occurrence of a short or burn due to the overlap of the electromotive voltage wiring and the driving voltage wiring in the ESD transistor area can be prevented.

Meanwhile, although the bottom gate type transistor structure is explained in FIG. 7, the present invention can be equally applied to the top gate type transistor structure.

Figures 8 and 9 show the structure of the non-pad side (X-Pad) of an OLED display panel as another embodiment of the present invention.

More specifically, FIG. 8 is a plan view showing the ESD transistor formed on the non-pad side (X-Pad), and FIG. 9 is a cross-sectional structure of the ESD transistor according to the embodiment of FIG. 8, taken along line II-II' of FIG. 8. This is a cut cross-sectional view.

As shown in Figures 8 and 9, a number of data lines are extended and formed in the non-display area of the non-pad side (X-Pad) of the OLED display panel, and a driving voltage wire 850 is located in the middle of the data line pair. ) is formed.

The data line extension formed on the non-pad side (X-Pad) of the OLED display panel is formed as a source/drain layer, and the driving voltage (VDD) wiring 850 extends in both the vertical and horizontal directions in a "T" shape. It is formed and includes a first driving voltage wiring 850' formed as a gate layer and a second driving voltage wiring 850" formed as a source/drain layer.

At this time, the ESD transistor 800 according to an embodiment of the present invention, similar to the embodiment of FIG. 6, includes a gate electrode 830, an active layer or semiconductor layer on the upper part, and a source electrode ( 810) and a drain electrode 820, and the source electrode 810 of the ESD transistor 800 extends integrally from the data line.

In addition, the drain electrode 820 of the ESD transistor 800 is formed in the source/drain layer at a certain distance from the source electrode 810, and is connected to the uppermost part through the drain contact hole 822 formed on the top of the drain electrode 820. It is connected to the cathode electrode layer 570.

As described above, in the embodiments of FIGS. 8 and 9, when forming the ESD transistor 800 on the non-pad side (X-Pad) of the OLED display device, the ESD drain electrode is directly connected to the cathode electrode layer formed on the uppermost layer to form the drain. A separate base voltage wire (340 in FIG. 5) to apply the base voltage (VSS) to the electrode is no longer needed.

Therefore, in the case of FIG. 5, the width of the driving voltage wiring 350 had to be designed as small as w1 due to the separate base voltage wiring 340. However, according to the embodiment of FIG. 8, the width of the driving voltage wiring 850 was reduced to w1. By making the width w2 larger, it is possible to achieve a reduction in electrical resistance and a corresponding reduction in power consumption.

In addition, if it is relatively less sensitive to power consumption and the width of the driving voltage wiring can be kept the same as before, there is no need for a separate horizontal base voltage wiring for the ESD transistor as in the embodiment of FIG. 8, so not displayed. The area can be relatively reduced, and as a result, a narrow bezel can be achieved.

FIG. 9 is for explaining the cross-sectional structure and manufacturing process of the ESD transistor according to the embodiment of FIG. 8. Since most of it overlaps with the description of FIG. 7, the overlapping description will be omitted and only the main parts will be described.

The left side of Figure 9 shows the cross-sectional structure (II-II' cross-section of Figure 8) of the ESD transistor formed on the non-pad side (X-Pad) according to an embodiment of the present invention, and to aid understanding, the display area angle is shown on the right side. The cross-sectional structure of the driving transistor (DTr) included in the pixel is also shown.

In the same process as the formation process of the gate electrode 310, active layer 315, and source/drain electrodes 318 and 320 of the driving transistor (DTr), the gate electrode 830, active layer, and source electrode of the ESD transistor 800 are formed. 810 and a drain electrode 820 are formed. At this time, the source electrode 810 of the ESD transistor is formed integrally with the extension part of the data line.

Next, after depositing a passivation layer or protective layer (PAS) 525 on the source-drain layer, a portion of the protective layer (PAS) 525 deposited on the drain electrode 820 of the ESD transistor 800 is etched. Thus, a drain contact hole 822 is formed to expose a portion of the drain electrode 820.

Next, an anode electrode layer 340, a bank layer 350, and an organic light emitting layer (EL) 360 are sequentially formed in the driving transistor area, and then a cathode electrode layer 370 is deposited on top of them. At this time, the cathode electrode layer 570 is also deposited in the ESD transistor area, and the cathode electrode layer is directly connected to the drain electrode 820 of the ESD transistor through the pre-formed drain contact hole 822.

Figure 10 is a top view of an ESD transistor on the source pad side (S-Pad) according to another embodiment of the present invention.

The embodiment of FIG. 10 has a different arrangement relationship between the source electrode and drain electrode of the ESD transistor compared to the embodiment of FIG. 6.

That is, in the embodiment of FIG. 6, the drain electrode 720 of the ESD transistor 700 is formed closer to the display area, while in the embodiment of FIG. 10, the source electrode 1100 of the ESD transistor 100 is formed closer to the display area. Formed close to .

The drain electrode 1200 of the ESD transistor according to the embodiment of FIG. 10 is formed further outside the source electrode 1100, and is connected to the uppermost cathode electrode layer through the drain contact hole 1220 provided at the top.

6 has the advantage of reducing the formation area of the cathode electrode layer 570 by forming the drain electrode 720 of the ESD transistor closer to the display area than the source electrode 710, but is electrically connected to the data line. By placing the source electrode 710 outside the non-display area, there could have been a disadvantage in making the design a bit more complicated.

Therefore, in the embodiment of FIG. 10, when there is no limitation on the formation area of the cathode electrode layer, the design of the electrode pattern can be simplified by forming the source electrode 1100 on the side closer to the data pad.

According to an embodiment of the present invention as described above, the drain electrode of the ESD transistor formed on the source pad side (S-Pad) of the OLED display panel is electrically connected to the cathode electrode layer through a drain contact hole, thereby forming an ESD transistor area. A separate base voltage (VSS) wiring may not be formed, which has the effect of preventing short circuits or burns due to overlap between the electromotive voltage wiring and the driving voltage wiring in the ESD transistor area.

In addition, according to another embodiment of the present invention, a separate base voltage (VSS) wire may not be formed to provide a base voltage to the drain electrode of the ESD transistor formed on the non-pad side (X-Pad) of the OLED display panel. Therefore, by increasing the width of the driving voltage (VDD) wiring, it is possible to provide convenience in design and reduce power consumption by reducing resistance.

In addition, a separate horizontal base voltage (VSS) wire may not be formed to provide base voltage to the drain electrode of the ESD transistor formed on the non-pad side (X-Pad) of the OLED display panel, so that the non-display area There is an effect of achieving a narrow bezel through reduction.

The above description and attached drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art will be able to combine the components without departing from the essential characteristics of the present invention. , various modifications and transformations such as separation, substitution, and change will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

700, 800, 1000: Electrostatic discharge (ESD) transistors
710, 810, 1100: source electrode 720, 820, 1200: drain electrode
730, 830, 1300: Gate electrode 722, 822, 1220: Drain contact hole
370, 570: cathode electrode layer 340: base voltage (VSS) wiring
350, 650, 850: Driving voltage (VDD) wiring
525: Protective layer (passivation layer; PAS) 620: Data pad

Claims (8)

Static electricity disposed in the non-display area of a display panel including an organic light emitting diode including an anode electrode layer connected to the drain electrode of the driving transistor, a cathode electrode layer to which a base voltage (VSS) is applied, and an organic light emitting layer disposed between both electrode layers. An organic light emitting display device including an emission (ESD) transistor,
The static discharge transistor includes a source electrode electrically connected to one or more data pads or an end of a data line; and,
a drain electrode electrically connected to the cathode electrode layer;
Including,
The cathode electrode layer extends from the display area of the display panel to at least a portion of the non-display area and is positioned to overlap a drain electrode of the static discharge transistor. According to paragraph 1,
An organic light emitting display device in which the drain electrode of the static discharge transistor is electrically connected to the cathode electrode layer through a drain contact hole disposed on the drain electrode. According to paragraph 1,
The static discharge transistor is disposed on the source pad side (S-Pad) of the organic light emitting display device, and the source electrode of the static discharge transistor is electrically connected to the data pad provided as the gate layer through the source contact hole. Display device. According to paragraph 2,
The drain contact hole is provided through one or more of a passivation layer, an overcoater (OC) layer, and a bank layer deposited on the source/drain layer. According to paragraph 3,
The organic light emitting display device wherein the drain electrode is disposed closer to the data pad than the source electrode. According to paragraph 1,
An organic light emitting display device in which the drain electrode of the static electricity dissipation transistor is not connected to a separate base voltage wire but receives a base voltage through connection to the cathode electrode layer. According to paragraph 1,
The static discharge transistor is disposed on a non-pad side (X-Pad) of the organic light emitting display device, and the source electrode of the static discharge transistor extends integrally with the end of the data line provided to the source/drain layer. Display device. According to paragraph 1,
The organic light emitting display device does not include a base voltage wiring pattern extending in a horizontal direction to connect the static discharge transistor area to the drain electrode of the static discharge transistor.

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