KR102375948B1 - Apparatus and method for analog-digital converting - Google Patents

Abstract

The analog-to-digital converter according to an embodiment of the present invention is connected to a Most Significant Bit (MSB)-Digtla Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, and the trim capacitor and (coupled), LSB (Least Significant Bit)-DAC for converting a digital signal to an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, and a voltage between the MAB-DAC and the LSB-DAC A comparator that measures a value and outputs a result of comparison with the sampled voltage value, applies a reference voltage to the unit capacitor of the MSB-DAC to digitally convert the first measured value output from the comparator to obtain the first measured data generating second measurement data by digitally converting the second measurement value output from the comparator by applying a reference voltage value to the capacitor of the LSB-DAC, and comparing the first and second measurement data to the and a control unit for controlling the trim capacitor.

Description

Analog-to-digital conversion device and its operation method {APPARATUS AND METHOD FOR ANALOG-DIGITAL CONVERTING}

The present invention relates to an apparatus for analog-to-digital conversion and an operating method thereof.

A successive approximation register (SAR) analog-digital converter (ADC) is one of the low-power ADC types. In order to use a high resolution (eg, 10-bit or more) SAR ADC, a split capacitor DAC arrangement is a very effective structure for small circuit area and low power consumption. The main disadvantage of the split capacitor DAC arrangement is that the performance is highly dependent on the exact value of the bridge capacitor. If the value of the bridge capacitor is not correct, an error may occur. Therefore, the correction of the bridge capacitor is essential for the split capacitor DAC arrangement structure. Therefore, there is a need for a method for correcting the bridge capacitor.

An embodiment of the present invention provides an apparatus and method for controlling an ADC.

Another embodiment of the present invention provides an apparatus and method for controlling a trim capacitor in a SAR ADC.

The analog-to-digital converter according to an embodiment of the present invention is connected to a Most Significant Bit (MSB)-Digtla Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, and the trim capacitor and (coupled), LSB (Least Significant Bit)-DAC for converting a digital signal to an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, and a voltage between the MAB-DAC and the LSB-DAC A comparator that measures a value and outputs a result of comparison with the sampled voltage value, applies a reference voltage to the unit capacitor of the MSB-DAC to digitally convert the first measured value output from the comparator to obtain the first measured data generating second measurement data by digitally converting the second measurement value output from the comparator by applying a reference voltage value to the capacitor of the LSB-DAC, and comparing the first and second measurement data to the and a control unit for controlling the trim capacitor.

The method of the analog-to-digital conversion apparatus according to an embodiment of the present invention includes a Most Significant Bit for converting a digital signal into an analog signal, a digital-to-analog conversion unit ( MSB-DAC) applying a reference voltage value to the unit capacitor to measure the voltage output from the MSB-DAC, and then convert the measured value to digital to generate first measurement data; and converting the digital signal into an analog signal. The least significant bit digital-to-analog converter (LSB-DAC) applies a reference voltage, measures the voltage output from the LSB-DAC, and then converts the measured value to digital to generate second measurement data. and controlling a trim capacitor by comparing the first and second measurement data, wherein the MSB-DAC and the LSB-DAC are connected through a bridge capacitor.

According to an embodiment of the present invention, the ADC device may be corrected regardless of the offset of the comparator by performing ADC control.

1 shows the configuration of an apparatus for controlling an ADC according to an embodiment of the present invention.
2A shows the configuration of the MSB DAC 130 of FIG. 1 according to an embodiment of the present invention.
2B shows the configuration of the LSB DAC 110 of FIG. 1 according to an embodiment of the present invention.
3A and 3B show an example of a digital value acquisition process through comparison of a sampled voltage and a DAC output voltage according to an embodiment of the present invention.
4A and 4B show examples of output results according to each DAC sample according to an embodiment of the present invention.
5 shows the configuration of a correction unit according to an embodiment of the present invention.
6 illustrates an ADC operation according to another embodiment of the present invention.
7 is a flowchart illustrating an ADC calibration process according to an embodiment of the present invention.
8 is a flowchart illustrating an ADC control process according to an embodiment of the present invention.
9 is a block diagram of an electronic device according to an embodiment of the present invention.
10 shows a simulation result according to an embodiment of the present invention.

Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings. However, it is not intended to limit the technology described in this document to specific embodiments, and it should be understood to include various modifications, equivalents, and/or alternatives of the embodiments of this document. . In connection with the description of the drawings, like reference numerals may be used for like components.

In this document, expressions such as "have," "may have," "includes," or "may include" refer to the presence of a corresponding characteristic (eg, a numerical value, function, operation, or component such as a part). and does not exclude the presence of additional features.

In this document, expressions such as "A or B," "at least one of A or/and B," or "one or more of A or/and B" may include all possible combinations of the items listed together. . For example, "A or B," "at least one of A and B," or "at least one of A or B" means (1) includes at least one A, (2) includes at least one B; Or (3) it may refer to all cases including both at least one A and at least one B.

As used herein, expressions such as "first," "second," "first," or "second," may modify various elements, regardless of order and/or importance, and refer to one element. It is used only to distinguish it from other components, and does not limit the components. For example, the first user equipment and the second user equipment may represent different user equipment regardless of order or importance. For example, without departing from the scope of the rights described in this document, a first component may be referred to as a second component, and similarly, the second component may also be renamed as a first component.

One component (eg, a first component) is "coupled with/to (operatively or communicatively)" to another component (eg, a second component); When referring to "connected to", it should be understood that the certain element may be directly connected to the other element or may be connected through another element (eg, a third element). On the other hand, when it is said that a component (eg, a first component) is "directly connected" or "directly connected" to another component (eg, a second component), the component and the It may be understood that other components (eg, a third component) do not exist between other components.

The expression "configured to (or configured to)" as used in this document, depending on the context, for example, "suitable for," "having the capacity to ," "designed to," "adapted to," "made to," or "capable of." The term "configured to (or configured to)" may not necessarily mean only "specifically designed to" in hardware. Instead, in some circumstances, the expression “a device configured to” may mean that the device is “capable of” with other devices or parts. For example, the phrase "a processor configured (or configured to perform) A, B, and C" refers to a dedicated processor (eg, an embedded processor) for performing the corresponding operations, or by executing one or more software programs stored in a memory device. , may mean a generic-purpose processor (eg, a central processing unit (CPU) or an application processor (AP)) capable of performing corresponding operations.

Terms used in this document are only used to describe specific embodiments, and may not be intended to limit the scope of other embodiments. The singular expression may include the plural expression unless the context clearly dictates otherwise. Terms used herein, including technical or scientific terms, may have the same meanings as commonly understood by one of ordinary skill in the art described in this document. Among terms used in this document, terms defined in a general dictionary may be interpreted with the same or similar meaning as the meaning in the context of the related art, and unless explicitly defined in this document, ideal or excessively formal meanings is not interpreted as In some cases, even terms defined in this document cannot be construed to exclude embodiments of this document. The capacitor array of the present invention includes at least one or more capacitors, and each capacitor constituting the capacitor array may be connected to a switch and controlled as the switch is turned on or off.

Hereinafter, the present invention describes a control technology for analog-digital conversion.

An ADC converter may be used to convert an analog signal to a digital signal. Among the types of ADC converters, the Successive Approximation Register (SAR ADC) has a relatively simple structure and low power consumption. Among the methods for implementing the SAR ADC, there is a divided capacitor array structure in which the ADC is operated by dividing the capacitor. The split capacitor array structure uses a bridge capacitor to reduce the chip size and power consumption. A most significant bit (MSB) digital-to-analog converter (MSB DAC) and a least significant bit (LSB) are used to reduce the chip size and power consumption. ) The conversion unit (LSB DAC) is divided and used. When the split capacitor array structure is used, a difference in matching between the capacitor array of the MSB DAC and the capacitor array of the LSB DAC may occur because the bridge capacitor used to split the entire capacitor of the ADC has a very small value. . In order to overcome this matching difference, correction of the bridge capacitor is required. In order to correct the bridge capacitor, in the present invention, the trim capacitor may be adjusted by comparing digital values.

1 shows the configuration of an apparatus for controlling an ADC according to an embodiment of the present invention.

The electronic device for ADC correction according to an embodiment of the present invention includes a maximum effective bit digital-analog converter (hereinafter referred to as MSB-DAC) 110 , a bridge capacitor 120 , and a minimum effective bit digital-analog converter ( (hereinafter referred to as LSB-DAC) 130 , a comparison unit 140 , a control unit 150 , and a trim capacitor 160 , and the control unit 150 includes a SAR logic unit 153 and a correction unit 151 . include

The LSB DAC 110 and the MSB DAC 130 convert a digital signal into an analog signal. The LSB DAC 110 and the MSB DAC 130 may output a digital signal as an analog signal based on the digital signal received from the controller 150 . For example, the LSB DAC 110 may receive a digital signal from the controller 150 and output an analog signal (eg, voltage) corresponding thereto. Also, the MSB DAC 130 may receive a digital signal from the controller 150 and output an analog signal (eg, voltage) corresponding thereto. For example, in the LSB DAC 110 , the capacitor array state of the LSB DAC 110 is determined according to the first digital signal of the controller 150 , and a voltage signal according to a capacitor value corresponding to the determined capacitor array state can be output. Similarly, in the MSB DAC 130 , the capacitor array state of the MSB DAC 130 is determined according to the second digital signal of the controller 150 , and a voltage signal according to a capacitor value corresponding to the determined capacitor array state can be output.

The bridge capacitor 120 may connect the LSB DAC 110 and the MSB DAC 130 . The electronic device may separate each capacitor array of the LSB DAC 110 and the MSB DAC 130 by using the bridge capacitor 120 . Also, the bridge capacitor 120 may couple the output voltage signal of the LSB DAC 110 and the output voltage signal of the MSB DAC 130 . For example, a signal generated by combining the output voltage signal of the LSB DAC 110 and the output voltage signal of the MSB DAC 130 may be used as the input signal of the comparator 140 . For example, the generated signal may be a voltage signal corresponding to a digital code obtained by combining the LSB DAC 110 and the MSB DAC 130 .

When the voltage output by the bridge LSB DAC 110 is combined with the voltage output by the MSB DAC 130 , in the process of transferring the output voltage by the bridge capacitor 120 , a capacitor mismatch and parasitic An error may occur due to parasitic capacitance. In the present invention, the trim capacitor is corrected in order to reduce the mismatch caused by the bridge capacitor 120 .

The comparator 140 may compare an input voltage signal with a voltage signal corresponding to a digital code obtained by combining the LSB DAC 110 and the MSB DAC 130 . The input voltage signal is a sampling signal of the input signal or a voltage signal obtained by applying a reference voltage Vrefp to a unit capacitor coupled to a capacitor array of the MSB DAC 130 to correct the bridge capacitor, It may be a voltage signal obtained after applying the reference voltage Vrefp to all capacitors constituting the capacitor array of the LSB-DAC 110 . The reference voltage Vrefp may be a maximum voltage that can be output from the LSB DAC 110 or the MSB DAC 130 .

The comparison result may be output as a code value of 0 or 1 according to a criterion. For example, when the input voltage signal is greater than the voltage signal corresponding to the digital code, 1 may be output, and if the input voltage signal is smaller than the voltage signal corresponding to the digital code, 0 may be output. In various embodiments, when the input voltage signal is greater than the voltage signal corresponding to the digital code, 0 may be output, and when the input voltage signal is smaller than the voltage signal corresponding to the digital code, 1 may be output.

The control unit 150 performs a first half control for correction and analog-to-digital conversion of the electronic device. Specifically, the SAR logic unit 153 of the control unit 150 performs control and digital value storage for analog-to-digital conversion. The SAR logic unit 153 may sequentially convert an analog value into a digital value in 1-bit units using a binary search algorithm. The SAR logic unit 153 controls the LSB DAC 110 and the MSB DAC 130 to store the value of each bit through comparison of analog signals in the order from the most significant bit (MSB) to the least significant bit (LSB). and convert the analog value into a digital value using the stored value.

When the SAR logic unit 153 compares the voltages of the two inputs through the comparison unit 140, a comparison error may occur due to a change in the input value due to physical noise, mismatch of capacitor values due to bridge capacitors, etc. can In order to correct this error, a method of reducing the comparison error by adjusting the offset of the comparator 140 is conventionally used. When the offset of the comparator 140 is adjusted, circuit complexity may increase. However, in the present invention, the mismatch of the capacitor values is corrected by adjusting the trim capacitor value through the correction unit 151 instead of adjusting the offset of the comparator 140 .

The correction unit 151 receives the digital value from the SAR logic unit 153 and performs correction by comparing the received digital value. Specifically, the compensator 151 samples a reference voltage to the unit capacitor of the MSB DAC 130, and then based on the sampled value, the value output through the comparator 140, the SAR logic unit ( 153) and the SAR logic unit (hereinafter referred to as Dmsb) and the SAR logic unit ( 153) and compares the digital value (hereinafter referred to as Dlsb). The compensator 151 may compare the Dmsb with the Dlsb to generate a value for controlling the trim capacitor 160 .

The trim capacitor 160 may change the value of the capacitor belonging to the trim capacitor 160 through the control value received through the correction unit 151 . As the value of the trim capacitor 160 is changed, the sum of the capacitances of the trim capacitor 160, the LSB-DAC 110, and the bridge capacitor 120 changes, so that the bridge capacitor 120 is corrected. You can get the same result as

According to an embodiment of the present invention, in order to perform analog-to-digital conversion and correction of an electronic device, a sample is performed by applying a reference voltage Vrefp while a switch connected to the unit capacitor of the MSB-DAC 130 is turned on. After that, it is possible to obtain an output value of the SAR logic unit 153 based on the corresponding output value. In addition, the electronic device applies and samples the reference voltage Vrefp in a state in which switches connected to all capacitors of the LSB-DAC 110 are turned on, and then the output value of the SAR logic unit 153 based on the resulting output value. can get

2A illustrates the configuration of an electronic device for obtaining a digital output value by sampling the MSB DAC 130 according to an embodiment of the present invention.

Referring to FIG. 2A , the MSB DAC 130 includes an MSB capacitor array, and the MSB capacitor array includes a unit capacitor 210 and a plurality of capacitors 212 , 213 , 214 , 215 , 216 . ) may be included. The unit capacitor 231 is a capacitor used for correction of the bridge capacitor, and may not be used when the bridge capacitor is not corrected.

Although the figure includes five capacitors except for the unit capacitor 210, this is for illustrative purposes only, and the number of the plurality of capacitors 212, 213, 214, 215, 216 is limited to that shown in the figure. It may vary according to an embodiment of the invention (eg, according to a resolution).

According to an embodiment of the present invention, each of the LSB DAC 110 and the MSB DAC 130 is sampled for correction of a bridge capacitor connecting the LSB DAC 110 and the MSB DAC 130 in a separate SAR ADC. Thereafter, each result value may be compared through the SAR logic unit 153 and correction may be performed accordingly.

The MSB DAC 130 and the LSB DAC 110 of FIG. 2A of the present invention each show an example of a 6-bit converter. By adding the bits of the MSB DAC 130 and the LSB DAC 110, a 12-bit conversion function can be performed. In the present invention, an example of a 12-bit SAR ADC is given, but this is for illustrative purposes only, and the number of bits may vary according to an embodiment, and the present invention is not limited to a 12-bit SAR ADC. Hereinafter, in the present invention, an example of a 12-bit SAR ADC will be described.

The electronic device may sample a reference voltage Vrefp to the unit capacitor 210 of the MSB DAC 130 to correct the bridge capacitor. When the reference voltage is sampled on the unit capacitor 231 of the MSB DAC 130, each DAC of the present invention performs 6-bit conversion, so the minimum voltage can be 1/64 (26 = 64) of the reference voltage. there is. Therefore, when the reference voltage Vrefp is sampled to the unit capacitor 231 of the MSB DAC 130, the output voltage through the unit capacitor becomes Vrefp/64, and accordingly, the output to the MSB DAC 130 side is 000001 , since the output to the LSB DAC 110 side is a form to which no voltage is applied, it will have a form such as 000000, so the output value ( Dmsb) may be 000001000000.

2B illustrates the configuration of an electronic device for obtaining a digital output value by sampling the LSB DAC 110 according to an embodiment of the present invention.

Referring to FIG. 2B , the LSB DAC 110 includes an LSB capacitor array, and the LSB capacitor array includes a dummy capacitor 220 and a plurality of capacitors 221 , 222 , 223 , 224, 225, 226). Although 7 capacitors are included in the drawings, this is for illustrative purposes only, and the number of the plurality of capacitors is not limited to those illustrated in the drawings and may vary according to embodiments of the present invention.

2B of the present invention also shows an example in which the MSB DAC 130 and the LSB DAC 110 are each configured with a 6-bit converter, similarly to FIG. 2A. By adding the bits of the MSB DAC 130 and the LSB DAC 110, a 12-bit conversion function can be performed.

The electronic device samples the reference voltage Vrefp in a state in which switches of all capacitors 220 , 221 , 222 , 223 , 224 , 225 , and 226 of the LSB DAC 110 are turned on to perform correction. can do. When the reference voltages of all capacitors of the LSB DAC 110 (220, 221, 222, 223, 224, 225, 226) are sampled, the minimum voltage unit is 6 bits, so 26 = 64, the minimum voltage is that of the reference voltage. It becomes 1/64. Accordingly, when the reference voltage Vrefp is applied to all capacitors of the LSB DAC 110 , the output voltage to the LSB DAC 110 side accordingly is applied to all capacitors 220 , 221 , 222 , 223 , 224 , 225 , 226 . ) is connected, so it is the same as the reference voltage Vrefp. (1/64 x 64 = 1) Accordingly, all capacitors 220, 221, 222, 223, 224, 225, 226 of the LSB DAC 110 When a reference voltage is applied, the output through the LSB DAC 110 is 63C because the sum of the capacitor arrays of the LSB DAC 110 is 64C (32C + 16C + 8C + 4C + 2C + C + C = 64C) In case of , it is equal to the value obtained by adding the additional bit 000001 to the output value 111111. Accordingly, the output value of the LSB side becomes 111111 + 000001, that is, the LSB side becomes 000000 and one bit overflows the MSB side, and the digital output value Dlsb through the SAR logic unit 150 must be 000001000000. However, due to a matching difference between the capacitor on the MSB DAC 130 side and the capacitor on the LSB DAC 110 side, the Dlsb may have a value other than 000001000000. For example, as the Dlsb, a number greater than a value of 000001000000, for example, 000001000001 may be output. In order to correct such an error, in the present invention, the error may be corrected by adjusting the trim capacitor by comparing the Dmsb with the Dlsb.

3A and 3B show an example of a digital value acquisition process through comparison of a sampled voltage and a DAC output voltage according to an embodiment of the present invention.

3A shows an example of a process of acquiring a digital value of a voltage sampled in a state in which the switch of the unit capacitor 210 of the MSB DAC 130 is turned on according to an embodiment of the present invention. Referring to FIG. 3A , in section 311, the electronic device compares the sampled voltage (VS.MSB) with the voltage value (V32C) in a state in which the 32C capacitor 216 of the MSB DAC 130 is turned on. do. The state in which the capacitor of the 32C (216) is turned on is equal to 1/2 of the reference voltage VREF. As a result of the comparison, since the VS.MSB is smaller than the V32C, an output value through the comparator 140 becomes 0 at this time.

In section 312, the electronic device turns off the 32C capacitor 216 and compares the voltage V16C with the 16C capacitor 215 on with the sampled voltage VS.MSB. As a result of the comparison, since the sampled voltage VS.MSB is smaller than the V16C, an output value through the comparator 140 becomes 0 at this time.

Similarly, in section 313, the 8C capacitor 214 is turned on, in section 314, the 4C capacitor 213 is turned on, and in section 315, the 2C capacitor 212 is turned on. When compared with each of the sampled voltages (VS.MSB) in each comparison, since the magnitude of the sampled voltage (VS.MSB) is lower than the voltage value in a state in which each capacitor is turned on, the comparison unit The output value through (140) is also 0.

In section 316, the voltage V1C and the sampled voltage VS.MSB are compared with the 1C capacitor 210 turned on, and the comparison result at this time is that the sampled voltage VS.MSB is Since it is greater than V1C, the output value through the comparator 140 at this time becomes 1. Eventually, the summation result of the output values through the MSB-DAC 130 becomes 000001, the output result is stored in the SAR logic unit 153 and summed, and no voltage is applied to the LSB-DAC. The output value at this time becomes 000001000000.

FIG. 3B shows an example of a digital value acquisition process of a voltage sampled in a state in which switches of all capacitors of the LSB DAC 110 are turned on according to an embodiment of the present invention. Referring to FIG. 3B , in section 321, the electronic device compares the sampled voltage VS.LSB with the voltage value V32C in a state in which the 32C capacitor 226 of the LSB DAC 110 is turned on. do. The state in which the capacitor 226 of 32C is turned on is equal to the value obtained by halving the reference voltage VREF. As a result of the comparison, since the VS.LSB is greater than the V32C, an output value through the comparator 140 becomes 1 at this time.

In section 322, the electronic device turns off the 32C capacitor 226 and compares the voltage V16C with the 16C capacitor 225 on with the sampled voltage VS.LSB. As a result of the comparison, since the sampled voltage VS.LSB is greater than the V16C, an output value through the comparator 140 becomes 1 at this time.

Similarly, in the 323 section, the 32C capacitor 226 and the 16C capacitor 225 are turned off and the 8C capacitor 224 is turned on. In the 324 section, the 32C capacitor 226 and the 16C capacitor 225 and In a state in which the 8C capacitor 224 is turned off and the 4C capacitor 223 is turned on, in section 315, the 32C (226), 16C (225), 8C (224), 4C (223) capacitors are turned off. (off) and the 2C capacitor 222 is turned on, in the 326 section, the 32C (226), 16C (225), 8C (224), 4C (223), 2C (222) capacitors are turned off ( off) and when the 1C capacitor 221 is turned on, compared with the sampled voltage VS.LSB, as a result of each comparison, the magnitude of the sampled voltage VS.LSB is the same as that of each capacitor. Since it is larger than the voltage value in the controlled state, the output value through the comparator 140 is also 1.

The output result is stored in the SAR logic unit 153 and summed, and the sum of the outputs through the LSB DAC becomes 111111. Since the voltage value sampled to this value is larger than the value of filling all 6-bit bits with 64C, it is equal to the value obtained by adding 000001 to the sum of the outputs. Therefore, it is the sum of 000001 to 111111, and overflow occurs. In the end, since no voltage is applied to the MSB-DAC, the output value at this time becomes 000001000000.

4A and 4B show examples of output results according to each DAC sample according to an embodiment of the present invention.

Referring to FIG. 4A , FIG. 4A shows an example of an output value result according to FIGS. 2A and 3A . Referring to FIG. 4A , when the switch of the unit capacitor 410 of the MSB DAC 130 is turned on to apply the reference voltage Vrefp, the sample voltage becomes the minimum voltage Vrefp/64, and accordingly The digital result value 420 of the MSB DAC 130 is 000001, and since it is the same as that no voltage is applied to the LSB DAC 110 side, the digital result value 430 of the LSB DAC 110 becomes 000000, As a result, the output value 440 for the sample voltage obtained by turning on the switch of the unit capacitor 410 of the MSB DAC 130 becomes 000001000000.

Referring to FIG. 4B , FIG. 4B shows an example of output value results according to FIGS. 2B and 3B . Referring to FIG. 4B , when the switches of all capacitors 450 of the LSB DAC 110 are turned on to apply the reference voltage Vrefp, the sample voltage becomes Vrefp, which is the same voltage as the reference voltage, and accordingly The digital result value 470 of the LSB DAC 110 becomes a value exceeding 6 bits by 64C. That is, due to overflow, the digital result value of the LSB DAC 110 becomes a value obtained by adding the number of single-digit bits 000001 to 111111. Therefore, the value obtained by turning on the switches of all capacitors 450 of the LSB DAC 110 is the sum of 111111 and 000001 on the LSB side and becomes 000000, and on the MSB DAC side, no voltage is applied, but the value of the LSB side is 000001 due to overflow. That is, the output value 480 for the sample voltage obtained by summing the digital result values of the LSB side and the MSB side becomes 000001000000.

5 shows the configuration of a correction unit according to an embodiment of the present invention.

Referring to FIG. 5 , the correction unit 151 includes an LSB sample output receiving unit 510 , an MSB sample output receiving unit 520 , a digital comparing unit 530 , an adding unit 540 , and a digital value storage unit 550 . can do. The digital comparator 530 samples the reference voltage while all capacitors of the LSB DAC 110 are switched on through the LSB sample output receiving unit 510 to generate the SAR logic unit 153 . The digital value Dlsb obtained through the In addition, the digital comparator 530 samples a reference voltage while the switch of the unit capacitor of the MSB DAC 130 is turned on through the MSB sample output receiving unit 530 to generate the SAR logic unit 153 . The digital value (Dmsb) obtained through

The correction unit 151 may perform correction to maintain a constant ratio between the LSB DAC 110 and the MSB DAC 130 . For the SAR ADC to be completely compensated, there should be no error in the voltage value input to the comparator. The cause of the error of the input voltage value may be physical noise generated in the device, delay due to a bridge capacitor, and the like. In the present invention, in order to remove the above error, the digital result value output by the LSB-DAC 110 and the MSB-DAC 130 is compared instead of the method of adjusting the offset of the comparator or adjusting each individual capacitor. The error is corrected by performing correction so that the digital result value satisfies a predetermined criterion within a predetermined range. An error may be corrected by adjusting the size of the trim capacitor 160 through the digital result value. Adjusting the size of the trim capacitor 160 changes the sum of the trim capacitor 160 , all capacitors of the LSB-DAC 110 , and the bridge capacitor 120 . Consequently, the bridge capacitor 120 is corrected. may result in

The digital comparison unit 530 may compare magnitudes of values input to the LSB sample output receiving unit 510 and the MSB sample output receiving unit 520 . The digital comparator 530 may output 1 when the input value input through the LSB sample output receiving unit 510 is greater than the input value input through the MSB sample output receiving unit 520, and 0 otherwise. there is.

The adder 540 may add the values output from the digital comparator 530 . When the output value of the digital comparator 530 is 0, the adder 540 outputs the same value as that in which addition is not performed because the added value becomes 0, and the output value of the digital comparator 530 is 1 In this case, the digital value stored in the digital value storage unit 550 is added by 1 unit. The added result value is output as a digital value 560 for correction. The digital value 560 for the correction is used as a value for the correction of the trim capacitor 160 . The addition is performed until the magnitude of the value input to the LSB sample output receiver 510 is not greater than the magnitude of the value input to the MSB sample output receiver 520 .

When the operation of the correction unit 151 is summarized based on the above-mentioned contents, the correction unit 151 initializes the trim capacitor 160 before performing the correction operation. The compensator 151 samples a reference voltage in a state in which switches of all capacitors of the LSB-DAC 110 are turned on, and the digital output value Dlsb obtained from the SAR logic unit 153 and the MSB -Comparison of the digital output value Dmsb obtained from the SAR logic unit 153 by sampling a reference voltage in a state in which the switch of the unit capacitor of the DAC 130 is turned on, through the digital comparator 530 carry out The compensator 151 increases the value of the trim capacitor 160 by one step when the value of Dlsb is greater than the value of Dmsb. As a method of increasing the value of the trim capacitor 160 , if there is a digital value for correction stored in advance, the result of the addition unit 540 to the digital value for correction stored in advance in the digital value storage unit 550 By adding , a digital value 560 for correcting the trim capacitor 160 may be output. The correction is performed until the value of Dlsb is not greater than the value of Dmsb.

The voltage sampled and output as a reference voltage when the switch connected to the unit capacitor of the MSB-DAC 130 input to the comparator through the correction is turned on, and all capacitors of the LSB-DAC 110 A voltage sampled as a reference voltage in an on state of the switch connected to the , and output may be the same within a voltage error range corresponding to the minimum bit.

6 illustrates an ADC operation according to another embodiment of the present invention.

Although only one LSB DAC 110 and one MSB DAC 130 are shown in FIGS. 2A and 2B, in the present invention, as shown in FIG. 6, the LSB- The DAC 610 and the MSB-DAC 630 may be respectively connected to the LSB-DAC 620 and the MSB-DAC 640 to the negative (-) input. When a positive (+) voltage is applied to the comparator 140 , the negative (-) voltage input becomes a ground input, and when a negative (-) voltage is applied to the comparator 140 , a positive (-) voltage is applied. The input of the (+) voltage side becomes the ground input and the operation of the SAR ADC is performed. Accordingly, the overall operation of the electronic device and the SAR logic unit 153 may be the same as the operation of FIGS. 2A and 2B to 5 described above.

7 is a flowchart illustrating an ADC calibration process according to an embodiment of the present invention.

In step 710 of FIG. 7 , the electronic device sets the initial value of the trim capacitor to the minimum value. In various embodiments, the initial value of the trim capacitor may be set to an intermediate value or a maximum value.

In step 720, the electronic device samples the reference voltage while the switch of the unit capacitor of the MSB-DAC 130 is turned on. In step 730, the electronic device obtains a digital value Dmsb for the output voltage of the MSB-DAC 130 according to the sampling of the reference voltage in a state in which the unit capacitor of the MSB-DAC 130 is switched on. acquire

In step 740, the electronic device samples the reference voltage while all capacitors of the LSB-DAC 110 are switched on. In step 750, the electronic device obtains a digital value Dlsb of the output voltage of the LSB-DAC 110 according to the sampling of the reference voltage in a state in which all capacitors of the LSB-DAC 110 are switched on. acquire

In step 760, the electronic device compares the Dmsb value with the Dlsb value. When the Dlsb value is larger, the electronic device increases the value of the trim capacitor by one step in step 770 . The electronic device may perform the ADC correction by increasing the size of the trim capacitor until the Dlsb value is not greater than the Dmsb value. For example, when the Dlsb value is greater than the Dmsb value, an input voltage smaller than the previous input voltage may be supplied to the comparator 140 by increasing the size of the trim capacitor. As the input voltage to the comparator 140 decreases, the Dlsb value may be smaller than the previous value.

8 is a flowchart illustrating an ADC control process according to an embodiment of the present invention.

Referring to FIG. 8 , in step 810, the electronic device may digitally convert the MSB-DAC output voltage to generate first measurement data. The electronic device samples a reference voltage to the unit capacitor of the MSB-DAC 130, and a digital output value for the voltage output through the MSB-DAC 130, that is, only the minimum bit of the MSB side is turned on; The LSB side may acquire the first measurement data in an off state.

In step 820, the electronic device may digitally convert the LSB-DAC output voltage to generate second measurement data. The electronic device samples a reference voltage to all capacitors of the LSB-DAC 110 and a digital output value for the voltage output through the LSB-DAC 110, that is, all bits of the LSB side are turned on, and the MSB All bits of the side may acquire the second measurement data, which is a value that is turned off.

In step 830, the electronic device compares the first measurement data and the second measurement data. The electronic device determines the size of first measurement data, which is a digital output value for voltage output through the MSB-DAC 130 , and second measurement data, which is a digital output value for voltage output through the LSB-DAC 110 . In comparison, when the size of the second measurement data is larger, the correction may be performed by adjusting the trim capacitor value.

9 is a block diagram of an electronic device according to an embodiment of the present invention.

Referring to FIG. 9 , the electronic device may include a modem 910 and an RFIC 920 . The modem 910 may modulate a baseband signal according to a corresponding communication method and output it to the RFIC 920 or may receive a baseband signal from the RFIC 920 and demodulate it according to a corresponding communication method.

The RFIC 920 may convert a baseband signal output from the modem into an RF signal and output it to an antenna, or convert an RF signal received from the antenna into a baseband signal and output the converted baseband signal to the modem. The RFIC 920 according to an embodiment of the present invention may include a SAR ADC 930 . The SAR ADC 930 converts an analog signal into a digital signal so that it can be transmitted. Here, the SAR ADC 930 may be the analog-to-digital converter described in FIG. 1 .

10 shows a simulation result according to an embodiment of the present invention.

The DNL of the vertical axis of a and b of Fig. 10 represents differential nonlinearity, and the INL of the vertical axis of c and d of Fig. 9 represents integral nonlinearity. For reference, it can be seen that the range of DNL for each code of DNL after correction is reduced compared to DNL before correction, and referring to Fig. 9 c and d, INL for each code of INL after correction compared to INL before correction It can be seen that the range is reduced.

Methods according to the embodiments described in the claims or specifications of the present invention may be implemented in the form of hardware, software, or a combination of hardware and software.

When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. One or more programs stored in the computer-readable storage medium are configured to be executable by one or more processors in an electronic device (device). One or more programs include instructions for causing an electronic device to execute methods according to embodiments described in a claim or specification of the present invention.

Such programs (software modules, software) include random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable ROM (EEPROM: Electrically Erasable Programmable Read Only Memory), magnetic disc storage device, Compact Disc-ROM (CD-ROM), Digital Versatile Discs (DVDs), or any other form of It may be stored in an optical storage device or a magnetic cassette. Alternatively, it may be stored in a memory composed of a combination of some or all thereof. In addition, each configuration memory may be included in plurality.

In addition, the program is transmitted through a communication network composed of a communication network such as the Internet, an intranet, a local area network (LAN), a wide LAN (WLAN), or a storage area network (SAN), or a combination thereof. It may be stored on an attachable storage device that can be accessed. Such a storage device may be connected to a device implementing an embodiment of the present invention through an external port. In addition, a separate storage device on the communication network may be connected to the device implementing the embodiment of the present invention.

In the specific embodiments of the present invention described above, elements included in the invention are expressed in the singular or plural according to the specific embodiments presented. However, the singular or plural expression is appropriately selected for the context presented for convenience of description, and the present invention is not limited to the singular or plural element, and even if the element is expressed in plural, it is composed of the singular or singular. Even an expressed component may be composed of a plurality of components.

Meanwhile, although specific embodiments have been described in the detailed description of the present invention, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments and should be defined by the claims described below as well as the claims and equivalents.

Claims (22)

In the analog (analog)-digital (digital) conversion device,
a most significant bit (MSB)-digital analog converter (DAC) for converting a first digital signal into a first analog signal;
trim capacitors,
a least significant bit (LSB)-DAC coupled to the trim capacitor and converting a second digital signal into a second analog signal;
a bridge capacitor connecting the MSB-DAC and the LSB-DAC;
A reference voltage is applied to the unit capacitor 210 of the MSB-DAC to analog-digitally convert the first measured value output from the comparator to generate first measured data, and all capacitors 220 and 221 of the LSB-DAC , 222, 223, 224, 225, 226) by applying a reference voltage to analog-to-digital conversion of the second measured value output from the comparator to generate second measured data, and the first and second measured data and a control unit configured to compare and control the trim capacitor.
The method according to claim 1,
The LSB-DAC is connected in parallel with the trim capacitor,
The trim capacitor is controlled based on the first measurement data and the second measurement data.
The method according to claim 1,
The bridge capacitor is connected in series between the MSB-DAC and the LSB-DAC.
The method according to claim 1,
The MSB-DAC includes a unit capacitor 210,
The LSB-DAC includes a dummy capacitor.
The method according to claim 1,
The first measurement data is generated by activating the unit capacitor 210 of the MSB-DAC and deactivating all capacitors 212, 213, 214, 215, 216 except the unit capacitor of the MSB-DAC.
The method according to claim 1,
The second measurement data is generated by activating all capacitors (220, 221, 222, 223, 224, 225, 226) of the LSB-DAC.
The method according to claim 1,
The control unit is
An apparatus for comparing a value of the first measurement data with a value of the second measurement data to increase the capacitance of the trim capacitor when the value of the second measurement data is greater than the value of the first measurement data.
The method according to claim 1,
The control unit is
An apparatus for continuously measuring the voltages of the LSB-DAC and the MSB-DAC by comparing the values of the first measurement data and the second measurement data and when the second measurement data value is greater than the first measurement data value .
The method according to claim 1,
The control unit is
Device for stopping voltage measurement of the MSB-DAC and the LSB-DAC when the second measurement data value is not greater than the first measurement data value by comparing the values of the first measurement data and the second measurement data .
The method according to claim 1,
The MSB-DAC and the LSB-DAC include a plurality of capacitors,
The plurality of capacitors is a capacitor whose capacitance increases exponentially.
In the method of the analog (analog)-digital (digital) conversion device,
The most significant bit that converts a digital signal into an analog signal applies a reference voltage to the unit capacitor 210 of the digital-analog converter (MSB-DAC) and outputs it from the MSB-DAC A process of generating first measured data by measuring the voltage to be used and converting the measured value to analog-digital;
A reference voltage is applied to the least significant bit digital-to-analog converter (LSB-DAC) that converts a digital signal to an analog signal, the voltage output from the LSB-DAC is measured, and the measured value is converted to analog-digital The process of generating second measurement data by converting to
and controlling a trim capacitor by comparing the first and second measurement data, wherein the trim capacitor is connected to the LSB-DAC;
The MSB-DAC and the LSB-DAC are connected through a bridge capacitor. 12. The method of claim 11,
The LSB-DAC is connected in parallel with the trim capacitor.
12. The method of claim 11,
wherein the bridge capacitor is connected in series between the MSB-DAC and the LSB-DAC.
12. The method of claim 11,
The MSB-DAC includes a unit capacitor 210,
The LSB-DAC includes a dummy capacitor.
12. The method of claim 11,
The process of generating the first measurement data includes:
and activating the unit capacitor (210) of the MSB-DAC and deactivating all capacitors (212, 213, 214, 215, 216) except the unit capacitor of the MSB-DAC.
12. The method of claim 11,
The process of generating the second measurement data is,
and activating all capacitors (220, 221, 223, 223, 224, 224, 226) of the LSB-DAC.
12. The method of claim 11,
The process of controlling the trim capacitor by comparing the first and second measurement data includes:
Comparing the value of the first measurement data with the value of the second measurement data and increasing the capacitance of the trim capacitor when the value of the second measurement data is greater than the value of the first measurement data; .
12. The method of claim 11,
The process of controlling the trim capacitor comprises:
Comparing the values of the first measurement data and the second measurement data, when the second measurement data value is greater than the first measurement data value, continuously performing voltage measurement of the LSB-DAC and the MSB-DAC How to include.
12. The method of claim 11,
The process of controlling the trim capacitor comprises:
Comparing the values of the first measurement data and the second measurement data, when the second measurement data value is not greater than the first measurement data value, stopping voltage measurement of the LSB-DAC and the MSB-DAC How to include.
12. The method of claim 11,
The LSB-DAC and the MSB-DAC include a plurality of capacitors,
wherein the plurality of capacitors are capacitors whose capacitance increases exponentially.






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