KR102374642B1 - Magnetic memory device and method for fabricating the same - Google Patents

Abstract

A magnetic memory device according to an embodiment of the present invention includes a lower insulating layer on a substrate; an insulating structure on the lower insulating layer; a lower contact penetrating the lower insulating layer; a lower electrode passing through the insulating structure and electrically connected to the lower contact; and a magnetic tunnel junction pattern in contact with at least a portion of an upper surface of the insulating structure and at least a portion of an upper surface of the lower electrode, wherein the lower electrode protrudes toward the magnetic tunnel junction pattern from a bottom portion and an upper surface of the bottom portion Root-mean-square roughness of an upper surface of the insulating structure and an upper surface of the lower electrode, including a protrusion, wherein at least a portion of an upper surface of the bottom is in contact with the insulating structure and in contact with the magnetic tunnel junction pattern may be 0.01 nm to 1 nm.

Description

Magnetic memory device and method for fabricating the same

The present invention relates to a memory device, and more particularly, to a memory device using a magnetic tunnel junction.

As electronic devices become faster and lower in power, memory devices embedded therein are also required to have fast read/write operations and low operating voltages. A magnetic memory device is being researched as a memory device that satisfies these requirements. A magnetic memory device has been spotlighted as a next-generation memory because it may have high-speed operation and/or non-volatile characteristics.

A magnetic memory device is a memory device using a magnetic tunnel junction (MTJ). The magnetic tunnel junction includes two magnetic layers and an insulating layer interposed therebetween, and the resistance of the magnetic tunnel junction may vary depending on the magnetization directions of the two magnetic layers. Specifically, if the magnetization directions of the two magnetic layers are antiparallel, the resistance of the magnetic tunnel junction may be large, and if the magnetization directions of the two magnetic layers are parallel, the resistance of the magnetic tunnel junction may be small. The magnetic memory device can write/read data by using the difference in resistance of the magnetic tunnel junction.

In particular, Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is attracting attention as a highly integrated memory because the size of the write current also decreases as the size of the magnetic cell decreases. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a magnetic memory device having improved magnetic properties and reliability.

Another object of the present invention is to provide a method of manufacturing a magnetic memory device having improved magnetic properties and reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a magnetic memory device according to embodiments of the present invention includes: a lower insulating layer on a substrate; an insulating structure on the lower insulating layer; a lower contact penetrating the lower insulating layer; a lower electrode passing through the insulating structure and electrically connected to the lower contact; and a magnetic tunnel junction pattern in contact with at least a portion of an upper surface of the insulating structure and at least a portion of an upper surface of the lower electrode, wherein the lower electrode protrudes toward the magnetic tunnel junction pattern from a bottom portion and an upper surface of the bottom portion Root-mean-square roughness of an upper surface of the insulating structure and an upper surface of the lower electrode, including a protrusion, wherein at least a portion of an upper surface of the bottom is in contact with the insulating structure and in contact with the magnetic tunnel junction pattern may be 0.01 nm to 1 nm.

According to an embodiment, a contact area between the magnetic tunnel junction pattern and a top surface of the insulating structure may be greater than a contact area between the magnetic tunnel junction pattern and a top surface of the lower electrode.

According to an embodiment, the bottom part may be spaced apart from the magnetic tunnel junction pattern.

According to an embodiment, the insulating structure may be amorphous.

According to an embodiment, the lower electrode may be polycrystalline.

According to an embodiment, the roughness of the upper surface of the insulating structure may be smaller than the roughness of the upper surface of the protrusion.

According to an embodiment, the upper surface of the protrusion may be coplanar with the upper surface of the insulating structure.

In order to achieve the above object, a magnetic memory device according to a first embodiment of the present invention includes: a lower insulating film on a substrate; a lower contact penetrating the lower insulating layer; a first insulating pattern disposed on the lower insulating layer and having an opening exposing the lower contact; a lower electrode conformally covering a sidewall and a bottom surface of the opening; a second insulating pattern filling the opening; and a magnetic tunnel junction pattern in contact with at least a portion of an upper surface of the lower electrode, at least a portion of an upper surface of the first insulating pattern, and at least a portion of an upper surface of the second insulating pattern, wherein the magnetic tunnel junction pattern is in contact with Root-mean-square roughness of the upper surface of the lower electrode, the upper surface of the first insulating pattern, and the upper surface of the second insulating pattern may be 0.01 nm to 1 nm.

According to an embodiment, an insulating structure including the first insulating pattern and the second insulating pattern is defined, wherein an area between the magnetic tunnel junction pattern and an upper surface of the insulating structure is in contact with the magnetic tunnel junction pattern and the lower electrode The upper surface of the may be larger than the area in contact.

According to an embodiment, at least one of the first insulating pattern and the second insulating pattern may be amorphous.

According to an embodiment, the lower electrode may be polycrystalline.

According to an embodiment, the roughness of the upper surface of the first insulating pattern and the roughness of the upper surface of the second insulating pattern may be smaller than the roughness of the upper surface of the lower electrode.

According to an embodiment, the lower electrode may not extend over the first insulating pattern and the second insulating pattern.

According to an embodiment, the lower electrode may have a hollow cylinder shape with a closed lower portion, and the second insulating pattern may fill the hollow.

In order to achieve the above object, a magnetic memory device according to a second embodiment of the present invention includes a lower insulating layer on a substrate; a lower contact penetrating the lower insulating layer; a lower electrode having an L-shaped cross section on the lower contact; an insulating structure covering a sidewall of the lower electrode and exposing a top surface of the lower electrode; and a magnetic tunnel junction pattern in contact with at least a portion of the upper surface of the insulating structure and at least a portion of the uppermost surface of the lower electrode, wherein the root mean square roughness of the upper surface of the insulating structure and the upper surface of the lower electrode in contact with the magnetic tunnel junction pattern (root-mean-square roughness) may be 0.01 nm to 1 nm.

According to an embodiment, a contact area between the magnetic tunnel junction pattern and a top surface of the insulating structure may be greater than a contact area between the magnetic tunnel junction pattern and the uppermost surface of the lower electrode.

According to an embodiment, the insulating structure may be amorphous.

According to an embodiment, the lower electrode may be polycrystalline.

According to an embodiment, the roughness of the upper surface of the insulating structure may be smaller than the roughness of the uppermost surface of the protrusion.

According to an embodiment, the uppermost surface of the lower electrode may be coplanar with the upper surface of the insulating structure.

The details of other embodiments are included in the detailed description and drawings.

According to the magnetic memory device of the present invention, the magnetic tunnel junction pattern may be mainly formed on the insulating structure. Since the insulating structure is amorphous and the surface of the insulating structure is flat compared to the surface of the lower electrode, crystallinity of the magnetic tunnel junction pattern may be improved. Accordingly, the magnetic properties of the magnetic memory device may be improved.

According to the magnetic memory device of the present invention, the contact area between the magnetic tunnel junction pattern and the lower electrode is reduced, so that the contact resistance between the magnetic tunnel junction pattern and the lower electrode can be increased. Accordingly, when the current flows, the temperature of the magnetic tunnel junction pattern increases, so that the magnetization of the free layer can be easily switched.

According to the method of manufacturing a magnetic memory device of the present invention, when the magnetic tunnel junction pattern is formed, misalignment between the magnetic tunnel junction pattern and the lower electrode may occur, so that a portion of the lower electrode may be exposed. According to the method of manufacturing the magnetic memory device of the present invention, even if the misalignment occurs as described above, the area of the exposed upper surface of the lower electrode may be small. Accordingly, a phenomenon in which a portion of the lower electrode is redeposited and the magnetic patterns of the magnetic tunnel junction pattern are short-circuited may be reduced.

1A is a cross-sectional view illustrating a magnetic memory device according to a first embodiment of the present invention.
1B is a perspective view of a lower electrode included in the magnetic memory device according to the first embodiment of the present invention.
2A is a cross-sectional view illustrating a magnetic memory device according to a second embodiment of the present invention.
2B is a perspective view of a lower electrode included in a magnetic memory device according to a second exemplary embodiment of the present invention.
3A to 8A are plan views illustrating a method of manufacturing a magnetic memory device according to a first exemplary embodiment of the present invention.
3B to 8B are cross-sectional views taken along line I-I' of FIGS. 3A to 8A, respectively.
9A to 19A are plan views illustrating a method of manufacturing a magnetic memory device according to a second exemplary embodiment of the present invention.
9B to 19B are cross-sectional views taken along line II′ of FIGS. 9A to 19A, respectively.
20 is a conceptual diagram illustrating a magnetic tunnel junction pattern according to an embodiment of the present invention.
21 is a conceptual diagram for explaining a magnetic tunnel junction pattern according to another embodiment of the present invention.
22 is a cross-sectional view illustrating a general magnetic memory device.
23 is a block diagram illustrating an example of electronic systems including semiconductor devices according to embodiments of the present invention.
24 is a block diagram illustrating an example of memory cards including semiconductor devices according to embodiments of the present invention.

Advantages and features of the present invention, and methods for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains. It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprises' and/or 'comprising' means that a referenced component, step, operation and/or element is the presence of one or more other components, steps, operations and/or elements. or addition is not excluded.

Further, the embodiments described herein will be described with reference to cross-sectional and/or plan views, which are ideal illustrative views of the present invention. In the drawings, thicknesses of films and regions are exaggerated for effective description of technical content. Accordingly, the shape of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. Accordingly, the embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process. For example, the etched region shown at a right angle may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the drawings have a schematic nature, and the shapes of the illustrated regions in the drawings are intended to illustrate specific shapes of regions of the device and not to limit the scope of the invention.

1A is a cross-sectional view illustrating a magnetic memory device according to a first embodiment of the present invention. 1B is a perspective view of a lower electrode included in the magnetic memory device according to the first embodiment of the present invention.

1A and 1B , the magnetic memory device 100 includes a substrate 110 , a lower insulating layer 120 , a lower contact 130 , an insulating structure 140 , a lower electrode 150 , and a magnetic tunnel junction pattern 160 . ), an upper insulating layer 170 , and an upper electrode 180 .

A lower insulating layer 120 may be provided on the substrate 110 . The substrate 110 may be a substrate including a selection device (not shown) such as a transistor or a diode. The lower insulating layer 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The lower contact 130 may be provided while vertically penetrating the lower insulating layer 120 . The lower contact 130 may be electrically connected to the substrate 110 . For example, when the substrate 110 includes a transistor (not shown), the lower contact 130 may be electrically connected to a drain region of the transistor. The lower contact 130 is at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). may include

The insulating structure 140 may be provided on the lower insulating layer 120 . The insulating structure 140 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous. The upper surface of the insulating structure 140 may have a smaller roughness than the upper surface of the protrusion 154 , which will be described later.

The lower electrode 150 may vertically penetrate the insulating structure 140 . The lower electrode 150 may be electrically connected to the lower contact 130 . For example, as shown in FIG. 1A , the lower surface of the lower electrode 150 may be in contact with the upper surface of the lower contact 130 . As another example, a conductive pad (not shown) may be further provided between the lower electrode 150 and the lower contact 130 to electrically connect the lower electrode 150 and the lower contact 130 through the conductive pad. The lower electrode 150 may include a bottom part 152 and a protrusion part 154 . The bottom portion 152 may be a bottom portion of the lower electrode 150 and may have a plate shape, and the protrusion 154 may be disposed from the top surface of the bottom portion 152 toward the opposite direction of the substrate 110 (that is, to be described later). It may be a protruding portion (toward the magnetic tunnel junction pattern 160 ). The upper surface of the protrusion 154 may be coplanar with the upper surface of the insulating structure 140 . The width of the upper surface of the protrusion 154 may be smaller than the width of the upper surface of the bottom part 152 . Furthermore, in some embodiments, an area of a lower surface of the protrusion 154 may be smaller than an area of an upper surface of the bottom portion 152 . The lower electrode 150 may include at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include, and may be polycrystalline.

According to an embodiment, as shown in FIGS. 1A and 1B , the lower electrode 150 may have a hollow cylinder shape with a closed bottom. In this case, the insulating structure 140 may include a first insulating pattern 142 and a second insulating pattern 144 . The first insulating pattern 142 is disposed on the lower insulating layer 120 and may have an opening OP exposing the lower contact 130 . The lower electrode 150 may conformally cover a sidewall and a bottom surface of the opening OP. A portion of the lower electrode 150 that covers the bottom surface of the opening OP may correspond to the bottom portion 152 , and a portion that covers the sidewall of the opening OP may correspond to the protrusion 154 . The second insulating pattern 144 may fill the hollow (or the opening OP). The lower electrode 150 may not extend onto the upper surface of the first insulating pattern 142 and the upper surface of the second insulating pattern 144 . Furthermore, the uppermost surface of the lower electrode 150 (ie, the upper surface of the protrusion 154 ) may be coplanar with the upper surface of the first insulating pattern 142 and the upper surface of the second insulating pattern 144 . At least one of the first insulating pattern and the second insulating pattern may be amorphous.

The magnetic tunnel junction pattern 160 may be provided on the lower electrode 150 . The magnetic tunnel junction pattern 160 may contact the top surface of the insulating structure 140 and the top surface of the protrusion 154 at the same time, but may be spaced apart from the bottom part 152 . A contact area between the magnetic tunnel junction pattern 160 and the top surface of the insulating structure 140 may be larger than an area between the magnetic tunnel junction pattern 160 and the top surface of the protrusion 154 .

The root-mean-square roughness of the upper surface of the insulating structure 140 and the upper surface of the lower electrode 150 in contact with the magnetic tunnel junction pattern 160 may be about 0.01 nm to about 1 nm.

The magnetic tunnel junction pattern 160 may include a first magnetic pattern 162 , a tunnel barrier pattern 164 , and a second magnetic pattern 166 that are sequentially stacked. The first magnetic pattern 162 , the tunnel barrier pattern 164 , and the second magnetic pattern 166 may each have a specific crystal structure. The material and data storage principle of the magnetic tunnel junction pattern 160 will be described in more detail below with reference to FIGS. 20 and 21 .

According to some embodiments, the magnetic tunnel junction pattern 160 may further include an additional lower electrode (not shown) on a lower surface thereof. An additional lower electrode (not shown) may be one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include at least one. Alternatively, according to other embodiments, the magnetic tunnel junction pattern 160 may not include an additional lower electrode (not shown).

An upper electrode 180 , an upper contact 182 , and a bit line 184 may be sequentially provided on the magnetic tunnel junction pattern 160 . Top electrode 180, top contact 182, and bit line 184 may be formed of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal. (eg, titanium or tantalum).

The upper insulating layer 170 may be provided between the insulating structure 140 and the bit line 184 to cover side surfaces of the magnetic tunnel junction pattern 160 , the upper electrode 180 , and the upper contact 182 . The upper insulating layer 170 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

In general, the crystallinity of the magnetic tunnel junction pattern 160 may be affected by the roughness of the lower film quality in contact with the magnetic tunnel junction pattern 160 and the crystallinity of the lower film quality. That is, as the roughness increases or the contact area with the lower layer having crystallinity increases, the crystallinity of the magnetic tunnel junction pattern 160 may be inhibited.

According to the magnetic memory device 100 , the magnetic tunnel junction pattern 160 may be formed in contact with the upper surface of the insulating structure 140 more than the upper surface of the lower electrode 150 . The roughness of the upper surface of the insulating structure 140 may be smaller than the roughness of the upper surface of the lower electrode 150 . Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 having a large contact area with the insulating structure 140 having a relatively small roughness may be improved. Also, the insulating structure 140 may be amorphous while the lower electrode 150 may be polycrystalline. Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 having a large contact area with the amorphous insulating structure 140 may be further improved.

Furthermore, according to the magnetic memory device 100 , the contact area between the magnetic tunnel junction pattern 160 and the lower electrode 150 is reduced, so that the contact resistance between the magnetic tunnel junction pattern 160 and the lower electrode 150 can be increased. there is. Accordingly, when a write current flows through the magnetic tunnel junction pattern 160 , a large amount of Joule's heat may be generated. As a result, the temperature of the magnetic tunnel junction pattern 160 is increased, so that the magnetization of the free layer included in the magnetic tunnel junction pattern 160 can be easily switched.

2A is a cross-sectional view illustrating a magnetic memory device according to a second embodiment of the present invention. 2B is a perspective view of a lower electrode included in a magnetic memory device according to a second exemplary embodiment of the present invention.

2A and 2B , the magnetic memory device 101 includes a substrate 110 , a lower insulating layer 120 , a lower contact 130 , an insulating structure 140 , a lower electrode 150 , and a magnetic tunnel junction pattern 160 . ), an upper insulating layer 170 , and an upper electrode 180 .

The substrate 110 , the lower insulating layer 120 , and the lower contact 130 are a substrate (refer to 110 in FIG. 1A ) included in the magnetic memory device (refer to 100 in FIG. 1A ) according to the first embodiment of the present invention. 1 may be substantially the same as the lower insulating layer (refer to 120 of FIG. 1A ) and the lower contact (refer to 130 of FIG. 1A ). For simplicity of description, descriptions of the substrate 110 , the lower insulating layer 120 , and the lower contact 130 will be omitted.

The insulating structure 140 may be provided on the lower insulating layer 120 . The insulating structure 140 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous. The upper surface of the insulating structure 140 may have a smaller roughness than the upper surface of the protrusion 154 , which will be described later.

The lower electrode 150 may vertically penetrate the insulating structure 140 . The lower electrode 150 may be electrically connected to the lower contact 130 . For example, as shown in FIG. 2A , the lower surface of the lower electrode 150 may be in contact with the upper surface of the lower contact 130 . As another example, a conductive pad (not shown) may be further provided between the lower electrode 150 and the lower contact 130 to electrically connect the lower electrode 150 and the lower contact 130 through the conductive pad. The lower electrode 150 may include a bottom part 152 and a protrusion part 154 . The bottom portion 152 may be a bottom portion of the lower electrode 150 and may have a plate shape, and the protrusion 154 may be directed from the top surface of the bottom portion 152 toward the opposite direction of the substrate 110 (ie, a magnetic field to be described later). It may be a protruding portion (toward the tunnel junction pattern 160 ). The upper surface of the protrusion 154 may be coplanar with the upper surface of the insulating structure 140 . The width of the upper surface of the protrusion 154 may be smaller than the width of the upper surface of the bottom part 152 . Furthermore, in some embodiments, an area of a lower surface of the protrusion 154 may be smaller than an area of an upper surface of the bottom portion 152 . The lower electrode 150 may include at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include, and may be polycrystalline.

According to an embodiment, as shown in FIGS. 2A and 2B , the vertical cross-section of the lower electrode 150 may be L-shaped. A horizontal portion of the L-shaped lower electrode 150 may correspond to the bottom portion 152 , and a vertical portion of the L-shaped lower electrode 150 may correspond to the protrusion 154 . In this case, the insulating structure 140 may cover the sidewall of the lower electrode 150 and expose the uppermost surface of the lower electrode 150 (ie, the upper surface of the protrusion 154 ). The uppermost surface of the lower electrode 150 may be coplanar with the upper surface of the insulating structure 140 .

The magnetic tunnel junction pattern 160 , the upper insulating layer 170 , the upper electrode 180 , the upper contact 182 , and the bit line 184 are formed in the magnetic memory device 100 in FIG. 1A according to the first embodiment of the present invention. reference) included in the upper insulating layer (see 170 in FIG. 1A ), the upper electrode (see 180 in FIG. 1A ), the upper contact (see 182 in FIG. 1A ), and the bit line (see 184 in FIG. 1A ). can For simplicity of description, descriptions of the magnetic tunnel junction pattern 160 , the upper insulating layer 170 , the upper electrode 180 , the upper contact 182 , and the bit line 184 will be omitted.

According to the magnetic memory device 101 , the magnetic tunnel junction pattern 160 may be formed in contact with the upper surface of the insulating structure 140 more than the upper surface of the lower electrode 150 . The roughness of the upper surface of the insulating structure 140 may be smaller than the roughness of the upper surface of the lower electrode 150 . Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be improved. In addition, the insulating structure 140 may be amorphous, while the lower electrode 150 may be polycrystalline. Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be further improved.

Furthermore, according to the magnetic memory device 101, the contact area between the magnetic tunnel junction pattern 160 and the lower electrode 150 is reduced, so that the contact resistance between the magnetic tunnel junction pattern 160 and the lower electrode 150 can be increased. there is. Accordingly, when a write current flows through the magnetic tunnel junction pattern 160 , a large amount of Joule's heat may be generated. As a result, the temperature of the magnetic tunnel junction pattern 160 is increased, so that the magnetization of the free layer included in the magnetic tunnel junction pattern 160 can be easily switched.

3A to 8A are plan views illustrating a method of manufacturing a magnetic memory device according to a first exemplary embodiment of the present invention. 3B to 8B are cross-sectional views taken along line I-I' of FIGS. 3A to 8A, respectively. The same reference numerals are provided to substantially the same components as those of the magnetic memory device according to the first embodiment of the present invention, and overlapping descriptions may be omitted for simplicity of description.

3A and 3B , the first lower insulating layer 120 and the lower contact 130 penetrating the first lower insulating layer 120 may be formed on the substrate 110 . Forming the lower contact 130 includes forming the first lower insulating layer 120 having the contact hole CH on the substrate 110 , and forming a preliminary lower contact (not shown) filling the contact hole CH. and planarizing the first lower insulating layer 120 and the preliminary lower contact. According to an example, as illustrated, the top surface of the substrate 110 may be exposed through the contact hole CH, but is not limited thereto.

4A and 4B , a second lower insulating layer 141 having an opening OP may be formed on the first lower insulating layer 120 . The upper surface of the lower contact 130 may be exposed by the opening OP. The second lower insulating layer 141 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous.

5A and 5B , a conductive layer 151 and a third lower insulating layer 143 may be formed.

The conductive layer 151 may be formed to conformally cover the bottom surface and sidewalls of the opening OP. The conductive layer 151 may be formed to extend onto the upper surface of the second lower insulating layer 141 . The conductive layer 151 is at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include, and may be polycrystalline.

The third lower insulating layer 143 may be formed on the conductive layer 151 to fill the opening OP. The third lower insulating layer 143 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous. The third lower insulating layer 143 may be formed by atomic layer deposition (ALD).

6A and 6B , at least until the conductive layer (refer to 151 of FIGS. 5A and 5B ) covering the sidewall of the opening OP is exposed (eg, up to the reference level RL shown in FIG. 5B )) By performing the planarization process, the lower electrode 150 , the first insulating pattern 142 , and the second insulating pattern 144 may be formed. The first insulating pattern 142 and the second insulating pattern 144 may form the insulating structure 140 together. Removal of the conductive layer (refer to 151 in FIG. 5B ), the second lower insulating layer (refer to 141 in FIG. 5B ), and the third lower insulating layer (refer to 143 in FIG. 5B ) is a chemical mechanical polishing (CMP) process. can be performed by The upper surface of the lower electrode 150 , the upper surface of the first insulating pattern 142 , and the upper surface of the second insulating pattern 144 may be coplanar. The upper surface of the first insulating pattern 142 or the upper surface of the second insulating pattern 144 may have a smaller roughness than the upper surface of the lower electrode 150 .

The lower electrode 150 may be formed from a conductive layer (refer to 151 of FIG. 5B ). A portion of the conductive layer (refer to 151 of FIG. 5B ) extending to the upper surface of the second lower insulating layer (refer to 141 of FIG. 5B ) may be removed. Accordingly, the lower electrode 150 may be a conductive layer portion 152 covering a bottom surface of the opening OP and a conductive layer portion 154 covering a sidewall of the opening OP. For example, the lower electrode 150 may have a hollow cylinder shape with a closed bottom.

The first insulating pattern 142 may be formed from the second lower insulating layer (refer to 141 of FIG. 5B ). Accordingly, the first insulating pattern 142 may have an opening OP, and the lower electrode 150 may be located in the opening OP.

The second insulating pattern 144 may be formed from the third lower insulating layer (refer to 143 of FIG. 5B ). The second insulating pattern 144 may be limited to the inside of the opening OP. For example, when the lower electrode 150 has a hollow cylinder shape with a closed lower portion, the second insulating pattern 144 may fill the hollow.

7A and 7B , magnetic tunnel junction layers 161 and a conductive layer 181 may be sequentially formed on the insulating structure 140 . Forming the magnetic tunnel junction layers 161 may include sequentially forming the first magnetic layer 163 , the tunnel barrier layer 165 , and the second magnetic layer 167 on the insulating structure 140 . The conductive layer 181 may include at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). may include According to some embodiments, an additional conductive layer (not shown) may be formed before forming the magnetic tunnel junction layers 161 . An additional conductive layer (not shown) may be one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include at least one. Alternatively, according to other embodiments, forming an additional conductive layer (not shown) may be omitted.

Referring to FIGS. 8A and 8B , the magnetic tunnel junction pattern 160 and the upper electrode 180 may be formed by patterning the magnetic tunnel junction layers (see 161 of FIG. 7B ) and the conductive layer (see 181 of FIG. 7B ). . For example, after the upper electrode 180 is first formed, the magnetic tunnel junction pattern 160 may be formed by patterning the magnetic tunnel junction layers (refer to 161 of FIG. 7B ) using the upper electrode 180 as an etch mask. there is. When an additional conductive layer (not shown) is formed, the additional conductive layer (not shown) may be patterned together when the magnetic tunnel junction layers (refer to 161 of FIG. 7B ) are patterned. Accordingly, an additional lower electrode (not shown) may be formed.

The magnetic tunnel junction pattern 160 may contact at least a portion of the second insulating pattern 144 and at least a portion of the lower electrode 150 at the same time. In some embodiments, the magnetic tunnel junction pattern 160 may also contact a portion of the first insulating pattern 142 adjacent to the lower electrode 150 . A contact area between the magnetic tunnel junction pattern 160 and the top surface of the insulating structure 140 may be larger than an area between the magnetic tunnel junction pattern 160 and the top surface of the protrusion 154 .

The root-mean-square roughness of the upper surface of the insulating structure 140 and the upper surface of the lower electrode 150 in contact with the magnetic tunnel junction pattern 160 may be about 0.01 nm to about 1 nm. The magnetic tunnel junction pattern 160 may include a first magnetic pattern 162 , a tunnel barrier pattern 164 , and a second magnetic pattern 166 that are sequentially stacked. The first magnetic pattern 162 , the tunnel barrier pattern 164 , and the second magnetic pattern 166 may each have a specific crystal structure. The crystallinity of the magnetic tunnel junction pattern 160 may be affected by a film in contact with the magnetic tunnel junction pattern 160 . For example, the crystallinity of the magnetic tunnel junction pattern 160 may be improved as the roughness of the layer decreases. As another example, the crystallinity of the magnetic tunnel junction pattern 160 may be improved when the layer is amorphous rather than crystalline. The material and data storage principle of the magnetic tunnel junction pattern 160 will be described in more detail below with reference to FIGS. 20 and 21 .

According to the method of manufacturing the magnetic memory device 100 of the present invention, the magnetic tunnel junction pattern 160 may be formed in contact with the upper surface of the insulating structure 140 more than the upper surface of the lower electrode 150 . The roughness of the upper surface of the insulating structure 140 may be smaller than the roughness of the upper surface of the lower electrode 150 . Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be improved. In addition, the insulating structure 140 may be amorphous, while the lower electrode 150 may be polycrystalline. Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be further improved.

When the magnetic tunnel junction pattern 160 is formed, misalignment may occur between the magnetic tunnel junction pattern 160 and the lower electrode 150 , so that a portion of the lower electrode 150 may be exposed. According to the method of manufacturing the magnetic memory device of the present invention, even if the misalignment as described above occurs, the exposed area of the upper surface of the lower electrode 150 may be small. Accordingly, a phenomenon in which the magnetic patterns 162 and 166 of the magnetic tunnel junction pattern 160 are short-circuited due to partial redeposition of the lower electrode 150 may be reduced.

Referring back to FIGS. 1A and 1B , an upper insulating layer 170 , an upper contact 182 , and a bit line 184 may be formed.

The upper insulating layer 170 may be formed to cover the insulating structure 140 on which the magnetic tunnel junction pattern 160 is formed. The upper insulating layer 170 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The upper contact 182 may be formed to pass through the upper insulating layer 170 to be electrically connected to the upper electrode 180 . The bit line 184 is formed on the upper insulating layer 170 and may be electrically connected to the upper contact 182 . Top contact 182 and bit line 184 may be formed of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride) or a transition metal (eg, titanium or tantalum)).

9A to 19A are plan views illustrating a method of manufacturing a magnetic memory device according to a second exemplary embodiment of the present invention. 9B to 19B are cross-sectional views taken along line II′ of FIGS. 9A to 19A, respectively. The same reference numerals are provided to substantially the same components as those of the magnetic memory device according to the second embodiment of the present invention, and overlapping descriptions may be omitted for simplicity of description.

9A and 9B , the first lower insulating layer 120 and a pair of lower contacts 130 penetrating the first lower insulating layer 120 may be formed on the substrate 110 . The pair of lower contacts 130 may be disposed along the first direction D1 and may be spaced apart from each other. Forming the lower contacts 130 includes forming the first lower insulating layer 120 having contact holes CH on the substrate 110 , and preliminary lower contacts (not shown) filling the contact holes CH. and planarizing the first lower insulating layer 120 and the preliminary lower contacts. According to an example, as illustrated, the top surface of the substrate 110 may be exposed through the contact holes CH, but is not limited thereto.

10A and 10B , a second lower insulating layer 141 having a trench TR may be formed on the first lower insulating layer 120 . At least a portion of a top surface of each of the lower contacts 130 may be exposed by the trench TR. The trench TR may extend in a second direction D2 crossing the first direction D1 . The second lower insulating layer 141 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous.

11A and 11B , the conductive layer 155 may be formed to conformally cover the bottom surface and sidewalls of the trench TR. The conductive layer 155 may extend on the upper surface of the second lower insulating layer 141 . The conductive layer 155 may be in contact with upper surfaces of the lower contacts 130 exposed by the trench TR. The conductive layer 155 may include at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include, and may be polycrystalline.

12A and 12B , a conductive pattern 156 extending in the first direction D1 may be formed by patterning the conductive layer (refer to 155 of FIGS. 11A and 11B ). The conductive pattern 156 may be in contact with the top surface of the pair of lower contacts 130 exposed by the trench TR. In other words, the conductive pattern 156 may extend in the first direction D1 and may be formed to vertically overlap the pair of lower contacts 130 .

13A and 13B , a third lower insulating layer 143 may be formed to conformally cover the upper surface of the structure described with reference to FIGS. 12A and 12B . The third lower insulating layer 143 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous.

14A and 14B , a pair of spacers SP covering a portion of the conductive layer 156 on the sidewall of the trench TR by etching a portion of the third lower insulating layer (see 143 of FIGS. 13A and 13B ) can be formed. For example, forming the spacers SP may include performing anisotropic etching on the entire surface of the third lower insulating layer (refer to 143 of FIGS. 13A and 13B ). Accordingly, a pair of spacers SP may be formed on the sidewall of the trench TR. Each of the spacers SP may extend in the second direction D2 along the sidewall of the trench TR.

15A and 15B , a pair of preliminary lower electrodes 157 may be formed by etching the conductive pattern (refer to 156 of FIGS. 14A and 14B ) using the spacer SP as an etch mask. The preliminary lower electrodes 157 may be formed to be spaced apart from each other on the lower contacts 130 , respectively, and may have an L-shaped cross-section facing each other.

16A and 16B , a fourth lower insulating layer 145 covering the upper surface of the structure described with reference to FIGS. 15A and 15B may be formed. The fourth lower insulating layer 145 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and may be amorphous.

Referring to FIGS. 17A and 17B , a planarization process is performed until at least the preliminary lower electrode (refer to 157 of FIG. 16B ) is exposed (eg, up to the reference level RL shown in FIG. 16B ) to obtain the first insulation A pattern 142 , second insulating patterns 144 , a third insulating pattern 146 , and lower electrodes 150 may be formed. The first insulating pattern 142 , the second insulating patterns 144 , and the third insulating pattern 146 may form the insulating structure 140 together. Removal of the second lower insulating layer (see 141 of FIG. 16B ), the spacers (see SP of FIG. 16B ), the fourth lower insulating layer (see 145 of FIG. 16B ), and preliminary lower electrodes (see 157 of FIG. 16B ) is It may be performed by a chemical mechanical polishing (CMP) process. The upper surface of the lower electrode 150 , the upper surface of the first insulating pattern 142 , the upper surface of the second insulating patterns 144 , and the upper surface of the third insulating pattern 146 may be coplanar. The top surface of the first insulating pattern 142 , the top surface of the second insulating patterns 144 , or the top surface of the third insulating pattern 146 may have a smaller roughness than the top surfaces of the lower electrodes 150 .

The lower electrodes 150 may be formed from preliminary lower electrodes (refer to 157 of FIG. 16B ). Accordingly, each of the lower electrodes 150 includes a bottom portion 152 covering the bottom surface of the trench TR and a protrusion 154 extending from the top surface of the bottom portion 152 along the sidewall of the trench TR. may include In other words, the lower electrodes 150 may have an L-shaped cross-section facing each other and spaced apart from each other.

The first insulating pattern 142 may be formed from the second lower insulating layer (refer to 141 of FIG. 16B ). Accordingly, the first insulating pattern 142 may have the trench TR, and the lower electrodes 150 may be located in the trench TR.

The second insulating patterns 144 may be formed from spacers (see SP of FIG. 16B ). The second insulating patterns 144 may be on a portion of the bottom portion 152 of the lower electrodes 150 in which the protrusion 154 is not formed.

The third insulating pattern 146 may be formed from the fourth lower insulating layer (refer to 145 of FIG. 16B ). The third insulating pattern 146 may be between the second insulating patterns 144 .

18A and 18B , magnetic tunnel junction layers 161 and a conductive layer 181 may be sequentially formed on the insulating structure 140 . Forming the magnetic tunnel junction layers 161 may include sequentially forming the first magnetic layer 163 , the tunnel barrier layer 165 , and the second magnetic layer 167 on the insulating structure 140 . The conductive layer 181 may include at least one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). may include According to some embodiments, an additional conductive layer (not shown) may be formed before forming the magnetic tunnel junction layers 161 . An additional conductive layer (not shown) may be one of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride), or a transition metal (eg, titanium or tantalum). It may include at least one. Alternatively, according to other embodiments, forming an additional conductive layer (not shown) may be omitted.

19A and 19B , the magnetic tunnel junction pattern 160 and the upper electrode 180 may be formed by patterning the magnetic tunnel junction layers (see 161 of FIG. 18B ) and the conductive layer (see 181 of FIG. 18 ). . For example, after the upper electrode 180 is first formed, the magnetic tunnel junction pattern 160 may be formed by patterning the magnetic tunnel junction layers (refer to 161 of FIG. 18B ) using the upper electrode 180 as an etch mask. there is. When an additional conductive layer (not shown) is formed, the additional conductive layer (not shown) may be patterned together when the magnetic tunnel junction layers (refer to 161 of FIG. 7B ) are patterned. Accordingly, an additional lower electrode (not shown) may be formed.

The magnetic tunnel junction pattern 160 may contact at least a part of the first insulating pattern 142 , at least a part of the second insulating pattern 144 , and at least a part of the lower electrode 150 at the same time. In some embodiments, the magnetic tunnel junction pattern 160 may also contact a portion of the third insulating pattern 146 . A contact area between the magnetic tunnel junction pattern 160 and the top surface of the insulating structure 140 may be larger than an area between the magnetic tunnel junction pattern 160 and the top surface of the protrusion 154 .

The root-mean-square roughness of the upper surface of the insulating structure 140 and the upper surface of the lower electrode 150 in contact with the magnetic tunnel junction pattern 160 may be about 0.01 nm to about 1 nm.

The magnetic tunnel junction pattern 160 may include a first magnetic pattern 162 , a tunnel barrier pattern 164 , and a second magnetic pattern 166 that are sequentially stacked. The first magnetic pattern 162 , the tunnel barrier pattern 164 , and the second magnetic pattern 166 may each have a specific crystal structure. The crystallinity of the magnetic tunnel junction pattern 160 may be affected by a film in contact with the magnetic tunnel junction pattern 160 . For example, the crystallinity of the magnetic tunnel junction pattern 160 may be improved as the roughness of the layer decreases. As another example, the crystallinity of the magnetic tunnel junction pattern 160 may be improved when the layer is amorphous than when the layer is crystalline. The material and data storage principle of the magnetic tunnel junction pattern 160 will be described in more detail below with reference to FIGS. 20 and 21 .

According to the method of manufacturing the magnetic memory device 101 of the present invention, the magnetic tunnel junction pattern 160 may be formed in contact with the upper surface of the insulating structure 140 more than the upper surface of the lower electrode 150 . The roughness of the upper surface of the insulating structure 140 may be smaller than the roughness of the upper surface of the lower electrode 150 . Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be improved. In addition, the insulating structure 140 may be amorphous, while the lower electrode 150 may be polycrystalline. Accordingly, the crystallinity of the magnetic tunnel junction pattern 160 may be further improved.

When the magnetic tunnel junction pattern 160 is formed, misalignment may occur between the magnetic tunnel junction pattern 160 and the lower electrode 150 , so that a portion of the lower electrode 150 may be exposed. According to the method of manufacturing the magnetic memory device of the present invention, even if the misalignment as described above occurs, the exposed area of the upper surface of the lower electrode 150 may be small. Accordingly, a phenomenon in which the magnetic patterns 162 and 166 of the magnetic tunnel junction pattern 160 are short-circuited due to partial redeposition of the lower electrode 150 may be reduced.

Referring back to FIGS. 2A and 2B , an upper insulating layer 170 , an upper contact 182 , and a bit line 184 may be formed.

The upper insulating layer 170 may be formed to cover the insulating structure 140 on which the magnetic tunnel junction pattern 160 is formed. The upper insulating layer 170 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

The upper contact 182 may be formed to pass through the upper insulating layer 170 to be electrically connected to the upper electrode 180 . The bit line 184 is formed on the upper insulating layer 170 and may be electrically connected to the upper contact 182 . Top contact 182 and bit line 184 may be formed of a metal (eg, tungsten, copper, or aluminum), a conductive metal nitride (eg, titanium nitride or tantalum nitride) or a transition metal (eg, titanium or tantalum)).

20 is a conceptual diagram illustrating a magnetic tunnel junction pattern according to an embodiment of the present invention. The magnetic tunnel junction pattern 160 according to the present embodiment may include a first magnetic pattern 162 , a tunnel barrier pattern 164 , and a second magnetic pattern 166 . One of the first and second magnetic patterns 162 and 166 may be a free layer of a magnetic tunnel junction (MTJ) and the other may be a pinned layer of a magnetic tunnel junction. Hereinafter, the first magnetic pattern 162 as a pinned layer and the second magnetic pattern 166 as a free layer will be described for simplicity of explanation. On the contrary, the first magnetic pattern 162 is a free layer and the second magnetic pattern (166) may be a fixed layer. The electrical resistance of the magnetic tunnel junction pattern 160 may depend on the magnetization directions of the free layer and the pinned layer. For example, the electrical resistance of the magnetic tunnel junction pattern 160 may be much greater when the magnetization directions of the free layer and the pinned layer are antiparallel than when they are parallel. As a result, the electrical resistance of the magnetic tunnel junction pattern 160 can be adjusted by changing the magnetization direction of the free layer, which can be used as a data storage principle in the magnetic memory device according to the present invention.

In an embodiment, the first magnetic pattern 162 and the second magnetic pattern 166 may be magnetic layers for forming a horizontal magnetization structure in which a magnetization direction is substantially parallel to a top surface of the tunnel barrier pattern 164 . In this embodiment, the first magnetic pattern 162 may include a layer including an anti-ferromagnetic material and a layer including a ferromagnetic material. The layer including the antiferromagnetic material may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. In an embodiment, the layer including the antiferromagnetic material may include at least one selected from among rare metals. The rare metal may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), or silver (Ag). The layer including the ferromagnetic material includes at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. can do.

The second magnetic pattern 166 may include a material having a changeable magnetization direction. The second magnetic pattern 166 may include a ferromagnetic material. For example, the second magnetic pattern 166 may be selected from among FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12. It may include at least one selected.

The second magnetic pattern 166 may be formed of a plurality of layers. For example, it may include a plurality of layers including a ferromagnetic material and a layer including a non-magnetic material interposed between the layers. In this case, the layers including the ferromagnetic material and the layer including the nonmagnetic material may constitute a synthetic antiferromagnetic layer. The synthetic antiferromagnetic layer may reduce the critical current density of the magnetic memory device and improve thermal stability.

The tunnel barrier pattern 164 is an oxide of magnesium (Mg), an oxide of titanium (Ti), aluminum (Al), an oxide of magnesium-zinc (MgZn), an oxide of magnesium-boron (MgB), and a nitride of titanium (Ti). and at least one of a nitride of vanadium (V). For example, the tunnel barrier pattern 164 may be a single layer of magnesium oxide (MgO). Alternatively, the tunnel barrier pattern 164 may include a plurality of layers. The tunnel barrier pattern 164 may be formed by chemical vapor deposition.

21 is a conceptual diagram for explaining a magnetic tunnel junction pattern according to another embodiment of the present invention. In this embodiment, the first magnetic pattern 162 and the second magnetic pattern 166 may have a perpendicular magnetization structure in which a magnetization direction is substantially perpendicular to a top surface of the tunnel barrier pattern 164 . In this embodiment, the first magnetic pattern 162 and the second magnetic pattern 166 are a material having an L1 ₀ crystal structure, a material having a dense hexagonal lattice, and an amorphous Rare-Earth Transition Metal (RE-TM) alloy. may include at least one of For example, the first magnetic pattern 162 and the second magnetic pattern 166 may be at least one of a material having an L1 ₀ crystal structure including Fe50Pt50, Fe50Pd50, Co50Pt50, Co50Pd50, and Fe50Ni50. In contrast, the first magnetic pattern 162 and the second magnetic pattern 166 have a dense hexagonal lattice of 10 to 45 at. A cobalt-platinum (CoPt) disordered alloy having a platinum (Pt) content of % or a Co3Pt ordered alloy may be included. In contrast, the first magnetic pattern 162 and the second magnetic pattern 166 include at least one selected from iron (Fe), cobalt (Co), and nickel (Ni) and rare earth metals terbium (Tb) and dysprosium (Dy). And it may include at least one selected from an amorphous RE-TM alloy containing at least one of gadolinium (Gd).

The first magnetic pattern 162 and the second magnetic pattern 166 may include a material having an interface perpendicular magnetic anisotropy. Interfacial perpendicular magnetic anisotropy refers to a phenomenon in which a magnetic layer having intrinsic horizontal magnetization characteristics has a perpendicular magnetization direction due to the influence from the interface with another layer adjacent thereto. Here, the “intrinsic horizontal magnetization characteristic” refers to a characteristic in which the magnetic layer has a magnetization direction parallel to its widest surface when there is no external factor. For example, when a magnetic layer having intrinsic horizontal magnetization characteristics is formed on a substrate and there is no external factor, the magnetization direction of the magnetic layer may be substantially parallel to a top surface of the substrate.

For example, the first magnetic pattern 162 and the second magnetic pattern 166 may include at least one of cobalt (Co), iron (Fe), and nickel (Ni). The first magnetic pattern 162 and the second magnetic pattern 166 may include boron (B), zinc (Zn), aluminum (Al), titanium (Ti), ruthenium (Ru), tantalum (Ta), and silicon (Si). , silver (Ag), gold (Au), copper (Cu), carbon (C), and may further include at least one of a non-magnetic material including nitrogen (N). For example, the first magnetic pattern 162 and the second magnetic pattern 166 may include CoFe or NiFe, but may further include boron (B). In addition, in order to lower the saturation magnetization amount of the first magnetic pattern 162 and the second magnetic pattern 166 , the first magnetic pattern 162 and the second magnetic pattern 166 may be formed of titanium (Ti) or aluminum (Al). ), silicon (Si), magnesium (Mg), tantalum (Ta), and may further include at least one of silicon (Si). The first magnetic pattern 162 and the second magnetic pattern 166 may be formed by sputtering or PECVD.

22 is a cross-sectional view illustrating a general magnetic memory device. Referring to FIG. 22 , in the general magnetic memory device 10 , the magnetic tunnel junction pattern 16 may be directly disposed on the lower contact 13 . In such a general magnetic memory device 10, the root mean square roughness of the upper surface of the lower film quality (lower contact 13 and lower insulating film 12) in contact with the magnetic tunnel junction pattern 16 may be about 1 nm to about 3 nm. there is. Accordingly, in the magnetic memory device (see 100 of FIG. 1A and 101 of FIG. 2A ) according to embodiments of the present invention, the roughness of the lower layer in contact with the magnetic tunnel junction pattern (see 160 of FIGS. 1A and 2A ) is a general magnetic memory. smaller than in element 10 . This is the magnetic tunnel junction pattern (see 160 of FIGS. 1A and 2A) and the lower electrode (see FIGS. 1A and 2A) in the magnetic memory device (see 100 in FIG. 1A and 101 in FIG. 2A) according to embodiments of the present invention. 150) is smaller than a contact area between the magnetic tunnel junction pattern 16 and the lower contact 13 in the general magnetic memory device 10 . Accordingly, the magnetic tunnel junction pattern (see 160 of FIGS. 1A and 2A ) included in the magnetic memory device according to the embodiments of the present invention has improved crystallinity compared to the magnetic tunnel junction pattern 16 included in the general magnetic memory device. can have

23 is a block diagram illustrating an example of electronic systems including magnetic memory devices according to embodiments of the present invention.

Referring to FIG. 23 , an electronic system 1100 according to an embodiment of the present invention includes a controller 1110 , an input/output device 1120 , I/O, a memory device 1130 , an interface 1140 , and a bus. (1150, bus). The controller 1110 , the input/output device 1120 , the memory device 1130 , and/or the interface 1140 may be coupled to each other through the bus 1150 . The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing a function similar thereto. The input/output device 1120 may include a keypad, a keyboard, and a display device. The memory device 1130 may store data and/or instructions. The memory device 1130 may include at least one of the magnetic memory devices disclosed in the above-described embodiments. The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be wired or wireless. For example, the interface 1140 may include an antenna or a wired/wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and/or an SRAM device as a motion memory device for improving the operation of the controller 1110 .

The electronic system 1100 includes a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player ( digital music player), memory card, or any electronic product capable of transmitting and/or receiving information in a wireless environment.

24 is a block diagram illustrating an example of memory cards including magnetic memory devices according to embodiments of the present invention.

Referring to FIG. 24 , a memory card 1200 according to an exemplary embodiment includes a storage device 1210 . The memory device 1210 may include at least one of the magnetic memory devices according to the above-described embodiments. The memory card 1200 may include a memory controller 1220 that controls data exchange between a host and the storage device 1210 .

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory card. Also, the memory controller 1220 may include an SRAM 1221 (SRAM) used as an operation memory of the processing unit 1222 . In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225 . The host interface 1223 may include a data exchange protocol between the memory card 1200 and the host. The memory interface 1225 may connect the memory controller 1220 and the memory device 1210 . Furthermore, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 may detect and correct an error in data read from the memory device 1210 . Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) that can replace the hard disk of the computer system.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can implement the present invention in other specific forms without changing its technical spirit or essential features. You can understand that there is Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (10)

a lower insulating film on the substrate;
an insulating structure on the lower insulating layer;
a lower contact penetrating the lower insulating layer;
a lower electrode passing through the insulating structure and electrically connected to the lower contact; and
a magnetic tunnel junction pattern in contact with at least a portion of an upper surface of the insulating structure and at least a portion of an upper surface of the lower electrode;
The lower electrode includes a bottom and a protrusion protruding from an upper surface of the bottom toward the magnetic tunnel junction pattern,
At least a portion of the upper surface of the bottom portion is in contact with the insulating structure,
The root-mean-square roughness of the upper surface of the insulating structure and the upper surface of the lower electrode in contact with the magnetic tunnel junction pattern is 0.01 nm to 1 nm,
The insulating structure is amorphous,
and the lower electrode is polycrystalline.
According to claim 1,
A contact area between the magnetic tunnel junction pattern and a top surface of the insulating structure is greater than a contact area between the magnetic tunnel junction pattern and a top surface of the lower electrode.
According to claim 1,
The bottom portion is a magnetic memory device spaced apart from the magnetic tunnel junction pattern.
delete According to claim 1,
A magnetic memory device wherein a roughness of an upper surface of the insulating structure is smaller than a roughness of an upper surface of the protrusion.
According to claim 1,
An upper surface of the protrusion is coplanar with an upper surface of the insulating structure.
a lower insulating film on the substrate;
a lower contact penetrating the lower insulating layer;
a first insulating pattern disposed on the lower insulating layer and having an opening exposing the lower contact;
a lower electrode conformally covering a sidewall and a bottom surface of the opening;
a second insulating pattern filling the opening; and
a magnetic tunnel junction pattern in contact with at least a portion of an upper surface of the lower electrode, at least a portion of an upper surface of the first insulating pattern, and at least a portion of an upper surface of the second insulating pattern;
The root-mean-square roughness of the upper surface of the lower electrode in contact with the magnetic tunnel junction pattern, the upper surface of the first insulating pattern, and the upper surface of the second insulating pattern is 0.01 nm to 1 nm,
At least one of the first insulating pattern and the second insulating pattern is amorphous,
and the lower electrode is polycrystalline.
8. The method of claim 7,
Define an insulating structure including the first insulating pattern and the second insulating pattern,
A contact area between the magnetic tunnel junction pattern and a top surface of the insulating structure is greater than a contact area between the magnetic tunnel junction pattern and a top surface of the lower electrode.
delete 8. The method of claim 7,
The roughness of the upper surface of the first insulating pattern and the roughness of the upper surface of the second insulating pattern are smaller than the roughness of the upper surface of the lower electrode.

Images