KR102372891B1 - Integrated circuit including standard cells overlapping each other and method for generating layout thereof - Google Patents

Abstract

According to an exemplary embodiment of the present disclosure, an integrated circuit including a plurality of standard cells, each of the plurality of standard cells, includes a front end of line (FEOL) region including at least one gate line extending in a first horizontal direction. and a back end of line (BEOL) region on the FEOL region, wherein the BEOL region of the first standard cell as one of the plurality of standard cells does not vertically overlap with the FEOL region of the first standard cell and does not overlap the first It may include an eaves (eaves) portion protruding in a second horizontal direction perpendicular to the horizontal direction.

Description

INTEGRATED CIRCUIT INCLUDING STANDARD CELLS OVERLAPPING EACH OTHER AND METHOD FOR GENERATING LAYOUT THEREOF

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit including a standard cell and a method of generating a layout thereof.

As semiconductor processes are miniaturized, the size of a standard cell included in an integrated circuit may also decrease. Due to the reduced size of the standard cell, the influence between adjacent standard cells may be increased, and in order to prevent this, a structure for separating the standard cells, for example, a diffusion break, may be inserted between the standard cells. . Also, a standard cell may contain unnecessary space in certain layers depending on its structure. This wasted space may limit the increase in the degree of integration of the integrated circuit by offsetting the reduction in the size of the standard cell.

The technical idea of the present disclosure relates to an integrated circuit including standard cells, and provides an integrated circuit including overlapping standard cells and a method of generating a layout thereof.

In order to achieve the above object, according to an aspect of the technical concept of the present disclosure, an integrated circuit including a plurality of standard cells, each of the plurality of standard cells, includes at least one gate line extending in a first horizontal direction. It may include a front end of line (FEOL) region including the FEOL region and a back end of line (BEOL) region on the FEOL region, wherein the BEOL region of the first standard cell as one of the plurality of standard cells includes: It may include an eaves portion, which does not overlap the area in a vertical direction and protrudes in a second horizontal direction perpendicular to the first horizontal direction.

According to an aspect of the present disclosure, an integrated circuit including a plurality of first standard cells, the plurality of first standard cells, includes a first FEOL including at least one gate line extending in a first horizontal direction ( front end of line) region and a first BEOL region on the first FEOL region, and may be continuously disposed in a second horizontal direction perpendicular to the first horizontal direction, wherein the first BEOL region includes a second horizontal direction It may be vertically overlapped with at least a portion of the first FEOL region of another first standard cell adjacent to .

A computer implemented method of generating a layout of an integrated circuit according to an aspect of the present disclosure includes a front end of line (FEOL) region including at least one gate line extending in a first horizontal direction and a BEOL on the FEOL region (back end of line) may include accessing a standard cell library defining a plurality of standard cells each including a region, and arranging a standard cell based on the standard cell library, In the step, the eaves of the BEOL region protruding in the second horizontal direction perpendicular to the first horizontal direction in the first standard cell and the step portion of the FEOL region protruding in the opposite direction to the second horizontal direction in the second standard cell are vertical It may include disposing a second standard cell adjacent to the first standard cell in a second horizontal direction so as to overlap in the direction.

According to an aspect of the present disclosure, a computer implemented method for generating a standard cell library defining a plurality of standard cells for generating a layout of an integrated circuit includes at least one gate line extending in a first horizontal direction. and a first FEOL region having double diffusion breaks respectively extending in a first horizontal direction at opposite ends in a second horizontal direction perpendicular to the first horizontal direction, and a first BEOL on the first FEOL region Receiving an input library defining a first standard cell including a region, and a single diffusion break each extending in a first horizontal direction at opposite ends of the first standard cell and providing the same function as the first standard cell generating an output library defining a second standard cell including a second FEOL region formed thereon, and a second BEOL region on the second FEOL region, the output library comprising: An eaves portion of the second BEOL region and a step portion of the second FEOL region protruding in a direction opposite to the second horizontal direction may be defined.

According to an exemplary embodiment of the present disclosure, an integrated circuit may have improved space efficiency by standard cells each having portions overlapping each other.

According to an exemplary embodiment of the present disclosure, an integrated circuit may include a standard cell having an efficient structure and improved performance by separating a boundary by diffusion break and a boundary for routing from the standard cell.

The standard cell according to the exemplary embodiment of the present disclosure may be easily generated from the verified standard cell, and accordingly, the integrated circuit may have improved reliability, and the development period of the integrated circuit may be shortened.

Effects obtainable in exemplary embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are exemplary of the present disclosure from the description of exemplary embodiments of the present disclosure below. Embodiments can be clearly derived and understood by those of ordinary skill in the art. That is, unintended effects of carrying out the exemplary embodiments of the present disclosure may also be derived by those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

The drawings attached to this specification may not fit to scale for convenience of illustration, and components may be exaggerated or reduced.
1 is a diagram illustrating standard cells according to an exemplary embodiment of the present disclosure.
2A to 2E are diagrams illustrating some of standard cells included in an integrated circuit according to exemplary embodiments of the present disclosure.
3 is a diagram schematically illustrating a part of an integrated circuit according to an exemplary embodiment of the present disclosure.
4 is a flowchart illustrating a method of manufacturing an integrated circuit including a plurality of standard cells according to an exemplary embodiment of the present disclosure.
5A and 5B are diagrams illustrating examples of standard cells defined by the standard cell library of FIG. 4 according to an exemplary embodiment of the present disclosure.
6 is a diagram illustrating examples of standard cells defined by the standard cell library of FIG. 4 according to an exemplary embodiment of the present disclosure.
7 is a diagram illustrating an example of a standard cell defined by a standard cell library according to an exemplary embodiment of the present disclosure.
8A and 8B show examples of a method for generating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
9A-9C show examples of a method for generating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
10A and 10B show examples of a method of generating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
11A and 11B show examples of a method of generating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
12 is a flowchart illustrating a method of generating a standard cell library including standard cells having directionality according to an exemplary embodiment of the present disclosure.
13A and 13B show an example of a method of generating a standard cell having directionality according to an exemplary embodiment of the present disclosure.
14 is a flowchart illustrating a method of generating a standard cell having directionality according to an exemplary embodiment of the present disclosure.
15A and 15B show an example of a method for generating a standard cell having directionality according to an exemplary embodiment of the present disclosure.
16A and 16B show an example of a method for generating a standard cell having directionality according to an exemplary embodiment of the present disclosure.
17A and 17B show an example of a method for generating a standard cell having directionality according to an exemplary embodiment of the present disclosure.
18 is a diagram illustrating a method of verifying an integrated circuit including standard cells having directionality according to an exemplary embodiment of the present disclosure.
19 is a block diagram illustrating a system on a chip (SoC) according to an exemplary embodiment of the present disclosure.
20 is a block diagram illustrating a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

1 is a diagram illustrating standard cells according to an exemplary embodiment of the present disclosure. Specifically, the standard cells C11, C12, and C13 are inverters having an input pin A and an output pin Y, and first to third on a plane formed by the X and Y axes in the upper part of FIG. 1 . A top view of the standard cells C11 to C13 is shown, and side views of the first to third standard cells C11 to C13 viewed in the Y-axis direction are shown in the lower part of FIG. 1 . In this specification, a plane consisting of the X-axis and Y-axis may be referred to as a horizontal plane, and a component disposed in the +Z direction relative to other components may be referred to as being above other components, and relative to other components. As such, a component arranged in the -Z direction may be referred to as being under another component. Also, the area of a specific object may refer to a space occupied by a plane parallel to a horizontal plane.

A standard cell is a unit of layout included in an integrated circuit, and the integrated circuit may include a plurality of various standard cells. The standard cells may have a structure conforming to a predetermined standard. For example, as shown in Figure 1, the first to third standard cells (C11 to C13) may have a constant height, that is, a constant length in the Y-axis direction, are spaced apart from each other in the Y-axis direction in parallel X It may include a pair of power rails VDD and GND extending in the axial direction and to which power voltages are respectively applied. In addition, the first to third standard cells C11 to C13 may include at least one gate line extending in the Y-axis direction (or in the first horizontal direction), and in the X-axis direction (or in the second horizontal direction). It may include at least one active region extending and a fin. In some embodiments, the active region may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs or InP, and a conductive region, such as a well doped with an impurity, an impurity It may also include doped structures. The gate line may include a work function metal-containing layer and a gap-fill metal layer. For example, the work function metal-containing layer may include at least one metal of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd, The metal film may be made of a W film or an Al film. In some embodiments, the gate lines may include a stacked structure of TiAlC/TiN/W, a stacked structure of TiN/TaN/TiAlC/TiN/W, or a stacked structure of TiN/TaN/TiN/TiAlC/TiN/W. there is. Although fins on the active region are not shown in the drawings for convenience of illustration, exemplary embodiments of the present disclosure may be applied to standard cells including flat transistors as well as standard cells including FinFETs. The point will be understood.

Referring to FIG. 1 , first to third standard cells C11 to C13 have a structure for reducing mutual influence with other adjacent standard cells when disposed in an integrated circuit, and include a diffusion break (DB). may include A diffusion break may separate a diffusion region between standard cells adjacent to each other. For example, as shown in FIG. 1 , when the first to third standard cells C11 , C12 , and C13 include a FinFET formed by at least one fin, the diffusion break DB ) may separate fins between adjacent standard cells. Also, unlike shown in FIG. 1 , when the standard cell includes a planner transistor, the diffusion break DB diffuses between the standard cells adjacent to each other by removing at least a portion of the diffusion region and/or the active region. areas can be separated.

The diffusion break DB may include a double diffusion break (DDB) and a single diffusion break (SDB) according to a structure. For example, the double diffusion break (DDB) may be formed under two gate lines adjacent to each other or a series of three or more gate lines, and has a width of about 1 CPP (contacted poly pitch) or more, that is, the X-axis direction. It may extend in the Y-axis direction while having a length. The single diffusion break SDB may be formed under one gate line or in a region in which one gate line is removed, and may extend in the Y-axis direction. Accordingly, the double diffusion break (DDB) may separate adjacent standard cells by 1 CPP or more, while the single diffusion break (SDB) may allow adjacent standard cells to be sequentially disposed.

As shown in FIG. 1 , the first to third standard cells C11 to C13 are FEOL regions FR11 , FR12 , FR13 formed by a front end of line (FEOL) process and a back end of line (BEOL). ) may include BEOL regions BR11 , BR12 , and BR13 formed by the process, and the BEOL regions BR11 , BR12 , and BR13 may be on the FEOL regions FR11 , FR12 , and FR13 . For example, the FEOL region of a standard cell may include a substrate, an active region, a fin, a contact, and a transistor, a diffusion break, etc. may be formed therein. In addition, the BEOL region of the standard cell may include a via and a metal layer, and an input pin, an output pin, and an interconnect for an internal signal of the standard cell may be formed in the BEOL region of the standard cell. The contact connected to the gate line and the fins may be classified as being formed by a middle of line (MOL) process that is different from the FEOL process and the BEOL process, but it is assumed herein that the contact is included in the FEOL region. do. In addition, in the drawings of the present specification, the via V0 connecting the contact and the pattern of the first metal layer M1 is shown on the pattern of the first metal layer M1 for convenience of illustration, but the via V0 is the contact and Note that it is disposed between the first metal layers M1.

The double diffusion brake (DDB) is advantageous in terms of manufacturing an integrated circuit by solving some issues in the semiconductor process, while providing lower space efficiency compared to the single diffusion brake (SDB). In addition, the single diffusion brake (SDB) may provide high space efficiency compared to the double diffusion brake (DDB), while generating some issues in the semiconductor process or may provide relatively deteriorated performance of the standard cell. For example, as shown in FIG. 1 , the first standard cell C11 has a width of 1/2 CPP at both ends facing in the X-axis direction to form double diffusion breaks DDBs with the standard cells adjacent to each other. may include DDB regions DR11a and DR11b extending in the Y-axis direction. In addition, the second standard cell C12 has a single diffusion break SDB extending in the Y-axis direction from the position of the gate line at both ends facing the X-axis direction to form single diffusion breaks SDB with the standard cells adjacent to each other. ) regions SR12a and SR12b. Accordingly, the first standard cell C11 may have a width of 3 CPP (ie, a length in the X-axis direction), while the second standard cell C12 may have a width of 2 CPP.

As shown in FIG. 1 , in the case of the second standard cell C12 , the output pin Y may be moved in the -X direction rather than the first standard cell C11 , and accordingly, the input pin A is also It can be moved in the -X direction. In order to connect the input pin and the gate line, the contact (or gate contact) CB12 may extend in the X-axis direction and may be referred to as an offset contact. As shown in FIG. 1 , the contact CB12 may have a specific length in the Y-axis direction, and accordingly, fins around the contact CB12 and the contact (or active) connected to the fins. In order to secure a distance between the contacts), the number of fins on the active region may be reduced compared to that of the first standard cell C11 . That is, the first standard cell C11 may include a total of six fins F11 to F16 on the active region, while the second standard cell C12 includes a total of four fins F11, F12, and F15 on the active region. , F16) may be included. Due to the reduced number of fins, the second standard cell C12 may have different characteristics from the first standard cell C11 .

According to an exemplary embodiment of the present disclosure, the standard cell may include an eaves portion of the BEOL region protruding in the X-axis direction and/or a step portion of the FEOL region protruding in the X-axis direction. For example, the third standard cell C13 of FIG. 1 may include the eaves portion ┏ of the BEOL region BR13 and may include the step portion ┛ of the FEOL region FR13. The eaves portion ┏ and the step portion ┛ of the third standard cell C13 may have the same length D in the X-axis direction. Accordingly, the third standard cell C13 has the BEOL region BR13 including the same patterns as the first standard cell C11 including the double diffusion break (DDB) regions DR11a and DR11b while having a single diffusion It may include single diffusion break SDB regions SR13a and SR13b for the break SDB.

In some embodiments, the eaves portion of the standard cell may include the first metal layer M1 and the layers thereon. That is, in the following exemplary embodiments of the present disclosure, the BEOL region including the via (V0) and the layers thereon includes a protruding eaves portion, but the exemplary embodiments of the present disclosure are not limited thereto. No, the eaves portion may include the first metal layer M1 and layers thereon, and the via V0 may be disposed within a planar boundary of the FEOL region, and may be included in the step portion in some embodiments .

As will be described later with reference to FIG. 2A and the like, the eaves ┏ of the third standard cell C13 may overlap with the step portion of the adjacent standard cell in the Z-axis direction (or in the vertical direction), and arranged in this way The standard cells may have substantially the same characteristics as a standard cell (eg, the first standard cell C11 ) including a double diffusion break (DDB) region while providing improved space efficiency. That is, standard cells may have an orientation according to a direction in which the eaves and step portions protrude, and standard cells having the same orientation may be sequentially disposed. In addition, since the third standard cell C13 can be easily derived from the first standard cell C11 as shown in FIG. 1 , it is developed at the beginning of the operation of the semiconductor process as will be described later with reference to FIG. 12 and the like. Standard cells supporting the single diffusion break (SDB) may be easily generated from the verified standard cells for the double diffusion break (DDB).

2A to 2E are diagrams illustrating some of standard cells included in an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, FIGS. 2A to 2E show examples of cross-sections in which standard cells are cut in a plane formed along the X and Z axes in an integrated circuit, and as described above with reference to FIG. 1 , '┏' and '┓' are The eave part of the BEOL area is indicated, and '┛' and '┗' indicate the step portion of the FEOL region.

Referring to FIG. 2A , in some embodiments, standard cells may be arranged such that the eaves portion of the standard cell overlaps the step portion of the adjacent standard cell in the Z-axis direction (or the vertical direction). For example, as shown in Figure 2a, the eaves portion (┏) of the first standard cell (C21a) may overlap with the step portion (┛) of the second standard cell (C22a) in the Z-axis direction, The eaves portion ┏ of the second standard cell C22a may overlap the step portion ┛ of the third standard cell C23a in the Z-axis direction. As shown in FIG. 2A , in order to arrange a series of standard cells, each of the standard cells may include an eaves portion ┏ and a step portion ┛ protruding in opposite directions to each other. For example, the first to third standard cells C21a to C23a may include eaves portions ┏ protruding in the +X direction and step portions ┛ protruding in the -X direction. In this specification, standard cells (eg, C21a to C23a) having a eaves portion projecting in the +X direction and a step portion projecting in the -X direction may be referred to as having a +X direction, while projecting in the -X direction A standard cell (eg, C23b in FIG. 2B ) having a raised eaves portion and a step portion protruding in the +X direction may be referred to as having a -X direction.

In some embodiments, a single diffusion break (SDB) may be formed between FEOL regions of standard cells arranged according to the +X direction. For example, as shown in FIG. 2A , a single diffusion break SDB may be formed between the FEOL regions of the first and second standard cells C21a and C22a, and the single diffusion break SDB is connected to the Y-axis direction can be extended. Further, in some embodiments, an active region and/or a fin of adjacent standard cells without a diffusion break may be connected, such as between the FEOL regions of the second and third standard cells C22a and C23a. In the drawings below, the illustration of a single diffusion break (SDB) is omitted at the boundary of a standard cell or between FEOL areas of adjacent standard cells, but a single diffusion break (SDB) is formed at the boundary of FEOL areas of adjacent standard cells Note that it may be

Referring to FIG. 2B , in some embodiments, a standard cell for switching directions may be disposed between standard cells having different directions. For example, as shown in FIG. 2B , a second standard cell C22b may be disposed between a first standard cell C21b having a +X direction and a third standard cell C23b having a -X direction. there is. The second standard cell C22b may include step portions ┛ and ┗ respectively protruding in the -X direction and the +X direction, and the step portions ┛ and ┗ of the second standard cell C22b are The eaves parts ┏ and ┓ of the first and third standard cells C21b and C23b may overlap each other in the Z-axis direction. Accordingly, the direction of the standard cells in the second standard cell C22b may be switched. In the present specification, a standard cell that switches the direction of standard cells, such as the second standard cell C22b, may be referred to as having a ±X direction, and in particular, may be referred to as a convergence cell. In some embodiments, the second standard cell C22b may provide an output signal by processing the input signal like the third standard cell C53 of FIG. 5B, and the fourth and fifth standard cells (C53) of FIG. 5B ( It may be a filler cell, such as C54 and C55).

Referring to FIG. 2C , in some embodiments, a double diffusion break DDB may be formed at a point where the directions of standard cells are switched. For example, as shown in FIG. 2c , the eaves parts (┏, ┓) of the first standard cell C21c having the +X direction and the second standard cell C22c having the -X direction are adjacent to each other. The first and second standard cells C21c and C22c may be disposed. Accordingly, double diffusion is performed in the empty space under the eaves portions ┏ and ┓ of the first and second standard cells C21c and C22c, that is, between the FEOL regions of the first and second standard cells C21c and C22c. A brake DB21c may be disposed. Although the BEOL regions of the first and second standard cells C21c and C22c are shown to be in contact with each other in FIG. 2C , in some embodiments, the BEOL regions of the standard cells having different orientations have a double diffusion interval between the FEOL regions. They may be spaced apart from each other so as to be the width of the brake DDB (eg, 1 CPP).

Referring to FIG. 2D , in some embodiments standard cells may be arranged such that standard cells each having step portions protruding in different directions abut. For example, as shown in FIG. 2D, the step portions ┗ and ┛ of the first standard cell C21d having the -X direction and the second standard cell C22d having the +X direction are adjacent to each other. The first and second standard cells C21d and C22d may be disposed. Accordingly, the empty space above the step portions ┗ and ┛ of the FEOL regions of the first and second standard cells C21d and C22d, that is, between the BEOL regions of the first and second standard cells C21d and C22d. (B21d) may occur, and the space B21d of the BEOL region may include patterns connecting the power rails of the first and second standard cells C21d and C22d.

Referring to FIG. 2E , similar to the example of FIG. 2B , in some embodiments, a standard cell for switching a direction may be disposed between standard cells having different directions. For example, as shown in FIG. 2E , a second standard cell C22e may be disposed between a first standard cell C21e having a -X direction and a third standard cell C23e having a +X direction. there is. The second standard cell C22e may include eaves portions ┓ and ┏ respectively protruding in the -X direction and the +X direction, and the eaves portions ┓ and ┏ of the second standard cell C22e are The first and third standard cells C21e and C23e may overlap the step portions ┗ and ┛ in the Z-axis direction, respectively. Accordingly, the direction of the standard cell may be switched in the second standard cell C22e, and the second standard cell C22e may be referred to as having a ±X direction, and in particular may be referred to as a divergence cell. there is. Similar to the second standard cell C22b of FIG. 2B , the second standard cell C22e of FIG. 2E may also provide an output signal by processing an input signal, or may be a filler cell.

3 is a diagram schematically illustrating a portion of an integrated circuit 30 according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1 , the integrated circuit 30 may include a plurality of standard cells, and the standard cells may have a constant height, that is, a length in the Y-axis direction. As will be described later with reference to FIG. 3 , the integrated circuit 30 may include a plurality of standard cells sequentially arranged with the same directionality, thereby preventing performance degradation in the standard cell and providing improved space efficiency. can do.

In some embodiments, the integrated circuit 30 may include standard cells arranged in series with the same orientation. For example, as shown in FIG. 3 , the standard cells disposed in the first row R31 may have a +X direction (→), and a eaves protruding in the +X direction and protruding in the -X direction. It may include a step portion. Accordingly, in the first row R31 , the BEOL region (ie, the eaves portion) of one standard cell may overlap the FEOL region (ie, the step portion) of another standard cell adjacent in the +X direction in the Z-axis direction. . Similarly, the standard cells arranged in the third row R33 may have a -X direction (←), and may include an eaves portion protruding in the -X direction and a step portion protruding in the +X direction. Accordingly, in the third row R33 , the BEOL region (ie, the eaves portion) of one standard cell may overlap the FEOL region (ie, the step portion) of another standard cell adjacent in the -X direction in the Z-axis direction.

In some embodiments, integrated circuit 30 may include standard cells with different orientations in one row. For example, as shown in FIG. 3 , the standard cells arranged in the second row R32 are a series of standard cells having -X directionality (←) and a series of standard cells having +X directionality (→). may include At a point X31 where standard cells having different orientations meet, the integrated circuit 30 may include a standard cell that switches orientation (eg, C22e in FIG. 2E ), and connects the power rails of the standard cells adjacent to each other. It may include patterns. Similarly, standard cells having -X directionality (←) may be disposed between standard cells having +X directionality (→) in the fourth row R34 .

4 is a flowchart illustrating a method of manufacturing an integrated circuit including a plurality of standard cells according to an exemplary embodiment of the present disclosure.

The standard cell library D42 may include information about a plurality of standard cells, such as function information, characteristic information, and layout information. As shown in FIG. 4 , the standard cell library D42 includes a first group D42_1 including standard cells having a +X direction, a second group D42_2 including standard cells having a -X direction, and A third group D42_3 including standard cells having ±X direction may be defined.

In operation S410 , a logic synthesis operation for generating the netlist data D43 from the RTL data D41 may be performed. For example, a semiconductor design tool (eg, a logic synthesis tool) refers to a standard cell library D42 from RTL data D41 written as VHDL (VHSIC Hardware Description Language) and HDL (Hardware Description Language) such as Verilog to perform logic By performing the synthesis, it is possible to generate the bitstream or netlist data D43 including the netlist. The standard cell library D42 may define a plurality of standard cells having different directions while providing the same function, or may define a plurality of standard cells having the same function and direction but different boundary structures. Accordingly, the standard cells may have different characteristics while providing the same function, and the standard cell library D42 may include information about the characteristics of the standard cell. Standard cells can be incorporated into integrated circuits by referring to such information during logic synthesis.

In operation S420 , a Place & Routing (P&R) operation for generating the layout data D44 from the netlist data D43 may be performed. As shown in Figure 4, the arrangement and routing step (S420) may include a plurality of steps (S421, S422, S423).

In step S421, an operation of arranging standard cells may be performed. For example, a semiconductor design tool (eg, a P&R tool) may refer to the standard cell library D42 from the netlist data D41 to arrange a plurality of standard cells. As described above, the standard cells may have a directionality, and the semiconductor design tool may place the standard cells based on the directionality of the standard cell. For example, the semiconductor design tool may arrange the standard cell so that the FEOL area and the BEOL area of the standard cells adjacent to each other vertically overlap based on the directionality of the standard cell. In addition, after arranging standard cells according to the boundary structure of the standard cells defined by the standard cell library D42 , a diffusion break, for example, a double diffusion break or a single diffusion break, may be disposed between the standard cells.

In step S422, an operation of creating interconnections may be performed. The interconnect may electrically connect an output pin and an input pin of a standard cell, and may include, for example, at least one via and at least one conductive pattern. By creating interconnections the standard cells can be routed, for example interconnections are created for connecting the power rails of the first and second standard cells C21d, C22d in the space B21d of the BEOL area in FIG. 2d . can be

In operation S423, an operation of generating the layout data D44 may be performed. The layout data D44 may have a format such as, for example, GDSII, and may include geometric information of standard cells and interconnections.

In operation S430, optical proximity correction (OPC) may be performed. OPC may refer to an operation for forming a pattern of a desired shape by correcting a distortion phenomenon such as refraction caused by characteristics of light in photolithography included in a semiconductor process for manufacturing an integrated circuit, and layout data By applying OPC to (D44), the pattern on the mask can be determined. In some embodiments, the layout of the integrated circuit may be limitedly modified in step S430. For example, at least one step included in examples of a method of generating a layout of an integrated circuit described below with reference to FIGS. 8A-11B , may be included in step S420 in some embodiments, and in some embodiments It may be included in step S430. The limited deformation of the integrated circuit in operation S430 is a post-processing for optimizing the structure of the integrated circuit, and may be referred to as design posishing.

In operation S440, an operation of manufacturing a mask may be performed. For example, by applying OPC to the layout data D44, patterns on a mask may be defined to form patterns formed on a plurality of layers, and at least one mask (or at least one mask for forming patterns of each of the plurality of layers) , a photomask) can be fabricated.

In step S450, an operation of fabricating an integrated circuit may be performed. For example, an integrated circuit may be manufactured by patterning a plurality of layers using the at least one mask manufactured in operation S440 . 11A , step S450 may include steps S451 and S452.

In step S451, a front-end-of-line (FEOL) process may be performed. FEOL may refer to a process of forming individual devices, such as transistors, capacitors, resistors, etc., on a substrate in an integrated circuit manufacturing process. For example, FEOL includes the steps of planarization and cleaning of a wafer, forming a trench, forming a well, forming a gate line, a source and and forming a drain. A portion formed by the FEOL process herein may be referred to as a FEOL region, and may include, for example, an active region, a diffusion region, a gate line, a contact, and the like.

In step S452, a back-end-of-line (BEOL) process may be performed. BEOL may refer to a process of interconnecting individual devices, such as transistors, capacitors, resistors, and the like, in an integrated circuit manufacturing process. For example, BEOL may include silicidation of the gate, source and drain regions, adding a dielectric, planarizing, forming a hole, adding a metal layer, forming a via, passivation ( passivation) forming a layer, and the like. In the present specification, a portion formed by the BEOL process may be referred to as a BEOL region, and may include, for example, vias, metal layer patterns, and the like. The integrated circuit can then be packaged in a semiconductor package and used as a component in a variety of applications.

5A and 5B are diagrams illustrating examples of standard cells defined by the standard cell library D42 of FIG. 4 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 5A shows standard cells included in each of the first and second groups D42_1 and D42_2 of the standard cell library D42, and FIG. 5B is a third group D42_3 of the standard cell library D42. Indicates the included standard cell. As described above with reference to FIG. 4 , the first to third groups D42_1 to D42_3 may include standard cells each having a +X direction, a -X direction, and a ±X direction. Hereinafter, FIGS. 5A and 5B will be described with reference to FIG. 4 .

Referring to FIG. 5A , the standard cell library D42 may define standard cells that provide the same inverter function and have different directions. For example, as shown in FIG. 5A , the first and second standard cells C51 and C52 serve the same function as an inverter with an input pin A and an output pin Y, while providing different orientations. can have That is, the first standard cell C51 may be included in the first group D42_1 of the standard cell library D42, and the eaves ┏ and the FEOL area FR51 protruding in the +X direction from the BEOL area BR51. ) may include a step portion (┛) protruding in the -X direction. In addition, the second standard cell C52 may be included in the second group D42_2 of the standard cell library D42, and the eave portion ┓ and the FEOL region FR52 protruding in the -X direction from the BEOL region BF52. ) may include a step portion (┗) protruding in the +X direction.

The standard cell library D42 may define standard cells that provide the same function but have different structures as the same functional group, and the standard cells included in one and the same functional group may have different directions in some embodiments. may have different boundary structures in some embodiments, as described below with reference to FIG. 6, and may have a different pin arrangement in some embodiments, as described below with reference to FIG. 10B there is. In some embodiments, standard cells included in the same functional group and having different orientations may be symmetric to each other. For example, as shown in FIG. 5A , the first and second standard cells C51 and C52 may be in a symmetrical relationship with each other about an axis parallel to the Y-axis.

Referring to FIG. 5B , the standard cell library D42 may define standard cells included in the third group D42_3. For example, the third standard cell C53 may be an inverter having a higher driving strength than the first and second standard cells C51 and C52 of FIG. 5A . The fourth and fifth standard cells C54 and C55 are filler cells, and may be disposed in a space remaining after standard cells having a unique function, for example, generating an output signal by processing an input signal, are disposed. . As shown in FIG. 5B , in the ±X-direction standard cells in which the FEOL region has a larger area than the BEOL region, the number of input pins and output pins is relatively small compared to the number of gate lines. There may be fewer patterns of the metal layer in the standard cell. For example, standard cells of the ±X direction in which the FEOL region has a larger area than the BEOL region may include a functional cell or a non-function cell having a relatively high driving capability. Although in FIG. 5B , similar to the second standard cell C22b of FIG. 2B , standard cells in which the area of the FEOL region is larger than the area of the BEOL region are illustrated, the third group D42_3 is the second standard cell of FIG. 2E . It will be understood that standard cells in which the area of the BEOL region is larger than that of the FEOL region may also be included, such as (C22e) and the seventh standard cell (C97) of FIG. 9C .

6 is a diagram illustrating examples of standard cells defined by the standard cell library D42 of FIG. 4 according to an exemplary embodiment of the present disclosure. As described above with reference to FIGS. 5A and 5B , the standard cell library D42 may define standard cells that provide the same function but are included in the same functional group having a different structure.

Referring to FIG. 6 , the standard cell library D42 may define standard cells that provide the same function but have different boundary structures. For example, the first to third standard cells C61 to C63, as shown in the plan view shown in the upper part of Fig. 6, the input pins (A, B, C, D) and the output pin (Y) The branch may provide the same function as a standard cell, while each may have different boundary structures, as shown in the side view shown in the lower part of FIG. 6 .

The first to third standard cells (C61 to C63) are the eave portions (┏) protruding in the +X direction in the BEOL regions (BR61, BR62, BR63) and -X in the FEOL regions (FR61, FR62, FR63) may include step portions ┛ protruding in the direction and thus may have the same directionality, i.e. +X directionality, while each having different boundary structures in the FEOL regions FR61, FR62, FR63 . That is, the first standard cell C61 has a boundary structure such that the FEOL region FR61 is connected to the FEOL region of another standard cell adjacent in the +X direction, that is, the active region and the fins are interconnected ( That is, it may have a no-diffusion brake). The second standard cell C62 has a double diffusion break (DDB) area DR62 such that the FEOL area FR62 is separated from the FEOL area of another standard cell adjacent in the +X direction by a double diffusion break DDB. may be included at one end of the FEOL region FR62. The third standard cell C63 is a single diffusion break (SDB) area (SR63) such that the FEOL area (FR63) is separated from the FEOL area of another standard cell adjacent in the +X direction by a single diffusion break (SDB). may be included at one end of the FEOL region (FR63). Accordingly, when arranging the standard cells in step S421 of FIG. 4 , an appropriate standard cell among the standard cells of the same functional group defined in the standard cell library D42 is based on the boundary structures of the standard cells disposed adjacent to each other. can be selected. Although FIG. 6 shows only three standard cells (C61 to C63) having different boundary structures, different boundary structures (eg, no-diffusion break, double diffusion break (DDB), single diffusion break (DDB), at both ends of the FEOL region are shown. It will be understood that additional standard cells are possible depending on the combinations of SDB)).

7 is a diagram illustrating an example of a standard cell defined by a standard cell library according to an exemplary embodiment of the present disclosure.

According to exemplary embodiments of the present disclosure, the standard cell library may define the directionality of the standard cell in various ways. In some embodiments, the standard cell library may define shapes of the BEOL region and the FEOL region of the standard cell according to a direction. For example, the standard cell library may differently define the boundary of the BEOL region and the FEOL region of the standard cell on a plane by defining the shapes of the eaves part and the step part. In some embodiments, the standard cell library may define a standard cell having directionality using a virtual layer. For example, as shown in FIG. 7 , the standard cell library equally defines the boundary of the BEOL region BR71 and the FEOL region FR71 of the first standard cell C71 on a plane, and the BEOL region ( BR71) and portions to be removed in the FEOL region FR71 may be represented as marking layers ML71 and ML72. In the process of disposing the standard cells (eg, S421 of FIG. 4 ), the marking layers ML71 and ML72 may be recognized by the P&R tool, and the directionality of the standard cells may be recognized. Hereinafter, examples of an operation of generating a layout of an integrated circuit with reference to a standard cell library defining standard cells will be described with reference to the drawings.

8A is a flowchart illustrating an example of a method for generating a layout of an integrated circuit including standard cells disposed adjacent to each other with different orientations according to an exemplary embodiment of the present disclosure, and FIG. 8B is a method according to the method of FIG. 8A An example of the generated layout is shown. As will be described later, according to an exemplary embodiment of the present disclosure, standard cells having different directions may be disposed adjacent to each other and the boundary structure of the standard cells may be changed.

Referring to FIG. 8A , in step S81, an operation of arranging standard cells so that the eaves of the standard cells are in contact may be performed. For example, as shown on the left side of FIG. 8B , SDB regions ( SDB regions for forming a single diffusion break (SDB) at one ends of the FEOL regions FR81 and FR82 with +X directionality and -X directionality, respectively) The first and second standard cells C81 and C82, including SR81 and SR82, may be disposed adjacently. The BEOL regions BR81 and BR82 of the first and second standard cells C81 and C82 may be in contact with each other, and thus a space may be generated between the FEOL regions FR81 and FR82.

Referring back to FIG. 8A , in step S82 , an operation of removing the SDB regions facing each other and disposing the double diffusion break DDB may be performed. For example, as shown on the right side of FIG. 8B , the SDB regions SR81 and SR82 at one end of the FEOL regions FR81 and FR82 of the first and second standard cells C81 and C82 are to be removed. Also, a double diffusion break (DDB) DB80 may be disposed between the FEOL regions FR81 and FR82. Accordingly, while not affecting the performance of the first and second standard cells C81 and C82, a double diffusion brake (DDB) (DB80) advantageous in semiconductor processing compared to the single diffusion brake (SDB) can be generated. there is. 8B , the removal of the SDB regions SR81 and SR82 and the arrangement of the double diffusion break (DDB) DB80 are performed after the first and second standard cells C81 and C82 are disposed (eg, , in a P&R process), or in a layout of an integrated circuit in which routing is completed (eg, in a design polishing process). That is, step S82 of FIG. 8A may be included in step S420 of FIG. 4 in some embodiments, and may be included in step S430 of FIG. 4 in some embodiments.

9A shows examples including a power tap on one side as standard cells defined by a standard cell library according to an exemplary embodiment of the present disclosure, and FIG. 9B illustrates a different type according to an exemplary embodiment of the present disclosure. It is a flowchart illustrating an example of a method of generating a layout of an integrated circuit including a structure in which standard cells disposed adjacent to each other with directionality are merged, and FIG. 9C shows an example of a layout generated according to the method of FIG. 9A . As will be described later, according to an exemplary embodiment of the present disclosure, standard cells having different orientations are disposed adjacent to each other, and parts of the standard cells are merged to provide improved space efficiency.

Referring to FIG. 9A , the standard cell library may define standard cells in which a power tap is disposed on one side. For example, as shown in FIG. 9B , the first to fourth standard cells C91 to C94 may have a +X direction, and power taps PT91a, PT91b, PT92a, PT92b, PT93a, PT93b, PT94a, PT94b). The power tap may refer to a pattern that provides a path for supplying a power supply voltage to a standard cell. For example, a power tap may include a contact coupled to the source of a transistor included in a standard cell, and may deliver a positive or negative supply voltage to the transistor. The first to fourth standard cells C91 to C94 may include contacts and vias that are adjacent to the step portion and deliver a positive supply voltage and a negative supply voltage to the transistors. Although FIG. 9A shows standard cells having +X directionality, the standard cell library includes standard cells having -X directionality and including a power tap adjacent to a step portion, for example, first to fourth standard cells C91 to C94. Standard cells that are symmetric about an axis parallel to the Y axis can be defined. Also, in FIG. 9A , the power taps PT91a, PT91b, PT92a, PT92b, PT93a, PT93b, PT94a, and PT94b are disposed adjacent to the step portion of the standard cell, but in some embodiments, the step portion may include at least a portion of the power tap. may include As will be described later, since the standard cells adjacent to each other are merged, the power tap may be shared by the standard cells, and the area of the standard cells may be reduced. Accordingly, in some embodiments, standard cells having directionality may be designed to have a power tap disposed on one side, and details thereof will be described later with reference to FIGS. 17A and 17B .

Referring to FIG. 9B , in step S91, an operation of arranging standard cells so that power taps of the standard cells are adjacent to each other may be performed. For example, as shown in the left side of FIG. 9C , the fifth and sixth standard cells C95 and C96 each having different directions and including power taps PT95a, PT95b, PT96a, PT96b adjacent to the step portion, respectively. ) may be disposed adjacent to each other. While the FEOL regions FR95 and FR96 of the fifth and sixth standard cells C95 and C96 are in contact with each other, a space may be generated between the BEOL regions BR95 and BR96.

Referring back to FIG. 9B , an operation of merging standard cells so that the standard cells share a power tap may be performed in step S92 . For example, as shown on the right side of FIG. 9C , the fifth and sixth standard cells C95 and C96 are merged to share the power taps PT97a and PT97b, thereby creating a seventh standard cell C97. there is. Accordingly, the length (X92) in the X-axis direction of the seventh standard cell (C97) is smaller than the length (X91) in the X-axis direction occupied when the fifth and sixth standard cells (C95, C96) are disposed adjacent to each other. and, as a result, the space efficiency of the integrated circuit may be improved. The merging operation of the standard cells, shown in FIG. 9C , may be performed after the fifth and sixth standard cells C95 and C96 are disposed (eg, in the P&R process), and in the layout of the integrated circuit in which routing is completed. It may be performed (eg, in a design polishing process). That is, step S92 of FIG. 9B may be included in step S420 of FIG. 4 in some embodiments, and may be included in step S430 of FIG. 4 in some embodiments.

10A is a flowchart illustrating an example of a method for generating a layout of an integrated circuit in which standard cells having different pin assignments are selectively disposed according to an exemplary embodiment of the present disclosure, and FIG. 10B is a different pin arrangement; An example of standard cells with an arrangement is shown. As will be described later, according to an exemplary embodiment of the present disclosure, an appropriate standard cell may be selected and placed among standard cells having different pin arrangements to be advantageous for routing. In some embodiments, steps S101 and S102 of FIG. 10A may be included in step S420 of FIG. 4 .

Referring to FIG. 10A , in step S101, a step of obtaining standard cells having the same function and direction and having different pin arrangements may be performed. For example, as shown in FIG. 10B , the first and second standard cells C101 and C102 may have the same +X direction as an inverter having an input pin A and an output pin Y, while , can have a different arrangement of the input pin (A) and the output pin (Y). When standard cells having the same directionality are consecutively arranged, routing congestion may occur due to positions of input pins and output pins of the standard cells. Accordingly, the standard cell library may define standard cells having different pin arrangements while having the same function and directionality, and standard cells having different pin arrangements may be obtained from the standard cell library. In some embodiments, for different pin placements, the standard cell library may define standard cells whose FEOL regions are mutually symmetric about an axis parallel to the Y axis. In this case, the pin arrangement of the standard cells may also be symmetric about an axis parallel to the Y axis.

Referring back to FIG. 10A , an operation of selecting and arranging one standard cell among standard cells based on routing may be performed in step S102. For example, as shown in FIG. 10B , the first standard cell C101 may be advantageous when an output signal of a standard cell disposed adjacently in the -X direction is applied to the input pin A, while the second standard cell C101 The standard cell C102 may be advantageous when a standard cell disposed adjacent in the -X direction receives an output signal output through the output pin Y. Accordingly, routing congestion may be reduced, a time required for generating a layout of the integrated circuit may be shortened, and performance of the integrated circuit may be improved due to a simple routing structure.

11A is a flowchart illustrating an example of a method of generating a layout of an integrated circuit by transforming a standard cell according to an exemplary embodiment of the present disclosure, and FIG. 11B shows an example of a layout generated according to the method of FIG. 11A . As will be described later, according to an exemplary embodiment of the present disclosure, the direction of the standard cell may be changed in the P&R process.

Referring to FIG. 11A , an operation of acquiring a standard cell having a specific directionality may be performed in step S111. In some embodiments, the standard cell library may not define a standard cell having a directionality while providing the same function but not defining a standard cell having a different directionality. For example, as shown in FIG. 11B , the standard cell library selects a first standard cell (C111) having -X direction as AOI22 having input pins (A0, A1, B0, B1) and an output pin (Y). can be defined

Referring back to FIG. 11A , an operation of flipping and arranging the standard cell obtained based on the boundary of the standard cell disposed in step S112 may be performed. For example, when a standard cell disposed adjacent to the left or right side of the first standard cell C111 in FIG. 11B has +X directionality, similarly as described above with reference to FIGS. 2C and 2D , space may occur can Accordingly, in the P&R process (eg, step S420 of FIG. 4 ), by flipping the first standard cell C111, the first standard cell C111 and the second standard cell symmetric about an axis parallel to the Y-axis direction ( C112 may be generated, and the second standard cell C112 may be disposed adjacent to the standard cell having the +X direction. In some embodiments, different from the standard cell library D42 of FIG. 4 , when a standard cell library defining only standard cells having one direction is used, the standard cell is selected according to the direction of the standard cell in the P&R process. An operation of flipping and disposing may be performed.

12 is a flowchart illustrating a method of generating a standard cell library including standard cells having directionality according to an exemplary embodiment of the present disclosure. As described above with reference to FIG. 1 , the double diffusion break (DDB) can solve some issues in the semiconductor process, so standard cells supporting the double diffusion break (DDB) can be developed at the initial stage of operation of the semiconductor process and After , standard cells supporting a single diffusion break (SDB) may be developed as issues in the semiconductor process are gradually resolved. As will be described later, when standard cells supporting single diffusion break (SDB) have directionality, standard cells supporting single diffusion break (SDB) can be easily generated from standard cells supporting double diffusion break (DDB). can In some embodiments, the method of FIG. 12 may be performed by a computing system including a processor and a memory (eg, 200 of FIG. 20 ).

In step S121, an operation of obtaining the input standard cell library D121 may be performed. The input standard cell library D121 may include information D121_1 on standard cells supporting the double diffusion break DDB. In some embodiments, the input standard cell library D121 may be stored in a computer-readable storage medium or may be received through a communication channel.

In operation S122, an operation of generating a standard cell having a single diffusion break (SDB) and directionality may be performed. As described above with reference to FIG. 1 , in some embodiments, a standard cell having a directionality may have patterns of the same BEOL region as a cell supporting a double diffusion break (DDB), so that a standard cell having a directionality can be easily can be created Examples of step S122 will be described later with reference to FIGS. 13A to 17B .

In step S123, an operation of generating the output standard cell library D122 may be performed. The output standard cell library D122 may include information D122_1 on standard cells supporting the single diffusion break SDB and having directionality. As described above with reference to FIG. 4 , the output standard cell library D122 may be referenced to create a layout of an integrated circuit, or to verify an integrated circuit as described below with reference to FIG. 18 .

13A is a flowchart illustrating a method of generating a standard cell having directionality according to an exemplary embodiment of the present disclosure, and FIG. 13B illustrates an example of a standard cell generated according to the method of FIG. 13A . In some embodiments, steps S131 and S132 of FIG. 13A may be included in step S122 of FIG. 12 .

Referring to FIG. 13A , in step S131, an operation of removing 1/2 CPP from both ends of the FEOL region may be performed. For example, as shown in FIG. 13B , the first standard cell C131 supporting the double diffusion break DDB has double diffusion break (DDB) regions DR131a for the double diffusion break DDB at both ends. DR131b). Since the DDB regions DR131a and DR131b may have a width of 1/2 CPP (ie, a length in the X-axis direction) at one end of the first standard cell C131, the FEOL region of the first standard cell C131 The DDB regions DR131a and DR131b of the first standard cell C131 may be removed by removing 1/2 CPP from both ends of the . Accordingly, the FEOL region of the first standard cell C131 may have a length in the X-axis direction of 3 CPP, while the FEOL region of the second standard cell C132 may have a length in the X-axis direction of 2 CPP.

Referring back to FIG. 13A , in step S132 , an operation of removing a total of 1 CPP from both ends of the BEOL region may be performed. For example, as shown in FIG. 13B , after the DDB regions DR131a and DR131b of the first standard cell C131 are removed, the output pin Y in the BEOL region of the first standard cell C131 is It can protrude in the +X direction. Accordingly, the BEOL region including the output pin Y protruding in the +X direction is removed by a total of 1 CPP from both ends of the BEOL region, thereby generating the second standard cell C132 having the +X direction. Accordingly, the second standard cell C132 may have a length in the X-axis direction of 2 CPP and include a BEOL region shifted in the +X direction from the FEOL region. That is, the second standard cell C132 may include patterns of the same BEOL region as the first standard cell C131 . In some embodiments, as shown in FIG. 13B , SDB regions SR132a and SR132b extending in the Y-axis direction from both ends of the FEOL region of the second standard cell C132 may be added.

14 is a flowchart illustrating a method of generating a standard cell having directionality according to an exemplary embodiment of the present disclosure. A standard cell having a different direction may be generated from a standard cell having a specific direction.

In step S141, an operation of obtaining a standard cell having a specific directionality may be performed. For example, a standard cell having +X directionality (eg, C132 of FIG. 13B ) may be generated by the method of FIG. 13A , and standard cells having +X directionality may be obtained.

In step S142, an operation of flipping the obtained standard cell may be performed. For example, when the second standard cell C132 of FIG. 13b having the +X direction is obtained, the second standard cell C132 and the second standard cell C132 are symmetrical about an axis parallel to the Y axis. A standard cell that provides the same function and has -X directionality can be generated.

15A is a flowchart illustrating a method for generating a standard cell having directionality according to an exemplary embodiment of the present disclosure, and FIG. 15B shows an example of a standard cell generated according to the method of FIG. 15A . In some embodiments, steps S151 and S152 of FIG. 15A may be included in step S122 of FIG. 12 .

Referring to FIG. 15A , in step S151, an operation of acquiring a standard cell in which the BEOL region cannot be removed may be performed at both ends of the standard cell. For example, as shown in FIG. 15B , the FEOL region FR151 of the first standard cell C151 can be removed by 1/2 CPP at both ends by removing the DDB regions, while the BEOL region BR151 is Due to the input pin (A) and output pin (Y) it cannot be removed by a total of 1 CPP at both ends.

Referring back to FIG. 15A , an operation of shifting the boundary of the FEOL region may be performed in step S152. For example, as shown in FIG. 15B , the boundary of the FEOL region FR151 of the first standard cell C151 may be shifted by 1/2 CPP in the -X direction, and accordingly, the second standard cell C152 may be shifted by 1/2 CPP. Silver may have a FEOL region FR152 that has the same length in the X-axis direction as the FEOL region FR151 of the first standard cell C151 and extends from the gate line in the X-axis direction. Accordingly, the BEOL region BR152 of the second standard cell C152 may include an eaves region ┏ protruding in the +X direction, and the FEOL region FR152 may include a step region ┛ protruding in the -X direction. there is. In some embodiments, the BEOL region BR151 as well as the FEOL region FR151 of the first standard cell C151 may be shifted, and as shown in FIG. 15B , the second standard cell C152 is the first The BEOL region BF151 of the standard cell C151 may include the BEOL region BR152 shifted in the +X-axis direction.

16A is a flowchart illustrating a method for generating a standard cell having directionality according to an exemplary embodiment of the present disclosure, and FIG. 16B shows an example of a standard cell generated according to the method of FIG. 16A . In some embodiments, steps S161 and S162 of FIG. 16A may be included in step S122 of FIG. 12 .

Referring to FIG. 16A , in step S161, an operation of acquiring a standard cell including a removable pattern from both ends of the BEOL region may be performed. For example, as shown in FIG. 16B , the pattern M161 of the metal layer of the first standard cell C161 may include a portion P161 extending from the via V161 in the -X direction. The portion P161 of the pattern M161 of the metal layer may be removable because it is not electrically connected to other patterns except for the pattern M161 and the via V161 electrically connecting the contact. Similarly, the portion P162 of the pattern M161 of the metal layer may also be removable.

Referring back to FIG. 16A , in step S162 , an operation of removing at least a portion of the pattern and reducing the BEOL region may be performed. For example, as in the second standard cell C162 of FIG. 16B , the removable portion P161 of the pattern M161 of the metal layer of the first standard cell C161 may be removed, and thus, the second standard cell C161 may be removed. The cell C162 may include a BEOL region having a reduced length in the X-axis direction compared to the first standard cell C161. Accordingly, similar to as described above with reference to FIGS. 13A and 13B , the FEOL region of the second standard cell C162 may be generated by removing the DDB regions of the first standard cell C161, and as a result, the second The standard cell C162 may have +X directionality.

17A is a flowchart illustrating a method of generating a standard cell having directionality according to an exemplary embodiment of the present disclosure, and FIG. 17B illustrates an example of a standard cell generated according to the method of FIG. 17A . In some embodiments, steps S171 and S172 of FIG. 17A may be included in step S122 of FIG. 12 .

Referring to FIG. 17A , in step S171 , an operation of moving or generating a power tap for transmitting a power voltage to be adjacent to a step portion may be performed. As described above with reference to FIG. 15B , the second standard cell C152 of FIG. 15B may be generated by shifting the boundary of the FEOL region of the first standard cell C151 . At this time, the power tap may be disposed adjacent to the portion extended by shifting the FEOL region, that is, the step portion ┛ of the FEOL region, or the power tap may be disposed such that at least a portion of the power tap is included in the step portion ┛. there is. For example, as shown in FIG. 17B , the power taps PT171 and PT172 are generated adjacent to the step portion ┛ of the second standard cell C152 of FIG. 15B , thereby generating the first standard cell C171 of FIG. 17B . ) can be created.

Referring back to FIG. 17A , in step S172, an operation of modifying the pattern so that the function of the standard cell is invariant may be performed. For example, the input pin A electrically connected to the gate line GL171 may be affected due to the power taps PT171 and PT172 added in the first standard cell C171 of FIG. 17B . Accordingly, a gate cut CT171 for removing the gate line GL171 may be generated like the second standard cell C172, and accordingly, as described above with reference to FIGS. 9A to 9C , The second standard cell C172 may have a structure capable of sharing a power tap with an adjacent standard cell, and may contribute to improved space efficiency of the integrated circuit.

18 is a diagram illustrating a method ( S180 ) of verifying an integrated circuit including standard cells having directivity according to an exemplary embodiment of the present disclosure. In some embodiments, the method of FIG. 18 may be performed in a computing system including a processor and memory (eg, 200 of FIG. 20 ).

The method S180 of verifying the integrated circuit may include a plurality of steps S181 to S183, and result data ( D184) can be created. As described above with reference to FIG. 4 , the netlist data D181 may include a netlist of an integrated circuit that is generated through an operation such as logic synthesis and describes standard cells and a connection relationship between the standard cells. Also, the layout data D182 may be generated by arranging and routing standard cells with reference to the standard cell library D183 from the netlist data D181, and may indicate the layout of the integrated circuit. The standard cell library D183 includes a first group D183_1 including standard cells having a +X direction, a second group D183_2 including standard cells having a -X direction, and standard cells having a ±X direction. and a third group D183_3. Standard cells included in the same functional group may have different characteristics according to directions, and the first to third groups D183_1 to D183_3 may define information on characteristics of standard cells, respectively.

In step S181, a design rule check (DRC) may be performed. The design rule may be defined based on a semiconductor process, for example, a minimum width of a pattern and a minimum separation distance between patterns may be defined. With reference to the first to third groups D183_1 to D183_3 included in the standard cell library D183, it may be verified whether the layout of the integrated circuit defined by the layout data D182 complies with the design rule. When a portion that does not comply with the design rule is detected, result data D184 including the coordinates of the detected portion, the non-compliant design rule, and an error may be generated.

In step S182, layout versus schematic (LVS) may be performed. LVS may refer to an operation of verifying whether the integrated circuit defined by the netlist data D181 and the integrated circuit defined by the layout data D182 match. For example, it may be verified whether standard cells and nodes included in the netlist data D181 exist in a layout defined by the layout data D182. LVS may be performed with reference to the first to third groups D183_1 to D183_3 included in the standard cell library D183, and a portion that does not match between the netlist data D181 and the layout data D182 Result data D184 including information on may be generated.

In step S183, parasitic extraction (PEX) may be performed. PEX may refer to an operation of extracting parasitics from the layout of the integrated circuit defined by the layout data D182 in order to simulate the performance of the integrated circuit, for example, operating speed, power consumption, and the like. For example, the resistance and capacitance of the interconnect forming the node may be extracted from the layout data D182, and an equivalent circuit of the interconnect including the extracted resistance and capacitance may be generated. With reference to the first to third groups D183_1 to D183_3 included in the standard cell library D183, parasitics may be extracted from the layout data D182, and the result including information on the extracted parasitics Data D184 may be generated.

19 is a block diagram illustrating a system on chip (SoC) 190 according to an exemplary embodiment of the present disclosure. The SoC 190 is a semiconductor device and may include an integrated circuit according to an exemplary embodiment of the present disclosure. The SoC 190 implements complex functional blocks such as intellectual property (IP) that perform various functions in a single chip, and standard cells according to exemplary embodiments of the present disclosure include each functional block of the SoC 120 . may be included, thereby achieving an SoC 120 that provides improved space efficiency and proven performance.

Referring to FIG. 19 , the SoC 190 includes a modem 192 , a display controller 193 , a memory 194 , an external memory controller 195 , a central processing unit (CPU) 196 , a transaction unit 197 , It may include a PMIC 198 and a graphic processing unit (GPU) 199 , and respective functional blocks of the SoC 190 may communicate with each other through a system bus 191 .

The CPU 196 , which can generally control the operation of the SoC 190 , can control the operation of the other functional blocks 192 , 193 , 194 , 195 , 197 , 198 , and 199 . The modem 192 may demodulate a signal received from the outside of the SoC 190 or may modulate a signal generated inside the SoC 190 and transmit it to the outside. The external memory controller 195 may control an operation of transmitting and receiving data from an external memory device connected to the SoC 190 . For example, programs and/or data stored in the external memory device may be provided to the CPU 196 or the GPU 199 under the control of the external memory controller 195 . The GPU 199 may execute program instructions related to graphic processing. The GPU 199 may receive graphic data through the external memory controller 195 , and may transmit graphic data processed by the GPU 199 to the outside of the SoC 190 through the external memory controller 195 . The transaction unit 197 may monitor data transactions of each functional block, and the PMIC 198 may control power supplied to each functional block according to the control of the transaction unit 197 . The display controller 193 may transmit data generated inside the SoC 190 to the display by controlling a display (or display device) external to the SoC 190 .

The memory 194 is a non-volatile memory, such as a non-volatile memory (EEPROM) such as a Electrically Erasable Programmable Read-Only Memory, flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM). ), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), etc., and may include DRAM (Dynamic Random Access Memory) as a volatile memory , SRAM (Static Random Access Memory), mobile DRAM, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power DDR) SDRAM, GDDR (Graphic DDR) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc. may include

20 is a block diagram illustrating a computing system 200 including a memory for storing a program according to an exemplary embodiment of the present disclosure. A method of manufacturing an integrated circuit (eg, the method of FIG. 4 ), a method of generating a layout of an integrated circuit (eg, S420 of FIG. 4 ), a method of generating a standard cell library, according to exemplary embodiments of the present disclosure At least some of the steps included in (eg, the method of FIG. 12 ) may be performed in the computing system 200 .

The computing system 200 may be a stationary computing system, such as a desktop computer, workstation, server, or the like, or a portable computing system, such as a laptop computer. As shown in FIG. 20 , the computing system 200 includes a processor 210 , input/output devices 220 , a network interface 230 , a random access memory (RAM) 240 , and a read only memory (ROM) 250 . ) and a storage device 260 . The processor 210 , the input/output devices 220 , the network interface 230 , the RAM 240 , the ROM 250 , and the storage device 260 may be connected to the bus 270 , and may be connected to each other via the bus 270 . can communicate

The processor 210 may be referred to as a processing unit, and may be any instruction set (eg, a micro-processor), an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU). at least one core capable of running IA-32 (Intel Architecture-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 210 may access memory, ie, RAM 240 or ROM 250 , via bus 270 , and execute instructions stored in RAM 240 or ROM 250 .

The RAM 240 may store a program 241 or at least a portion thereof for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure, and the program 241 causes the processor 210 to manufacture the integrated circuit. At least some of the steps included in the method for generating a layout of the integrated circuit, the method for generating a standard cell library (eg, the method of FIG. 12 ) may be performed. That is, the program 241 may include a plurality of instructions executable by the processor 210 , and the plurality of instructions included in the program 241 causes the processor 210 to, for example, include the instructions included in the above-described flowcharts. at least some of the steps may be performed.

The storage device 260 may not lose stored data even if the power supplied to the computing system 200 is cut off. For example, the storage device 260 may include a non-volatile memory device or a storage medium such as a magnetic tape, an optical disk, or a magnetic disk. Also, the storage device 260 may be removable from the computing system 200 . The storage device 260 may store the program 241 according to an exemplary embodiment of the present disclosure, and before the program 241 is executed by the processor 210 , the program 241 or At least a portion of it may be loaded into RAM 240 . Alternatively, the storage device 260 may store a file written in a programming language, and the program 241 generated by a compiler or the like from the file or at least a part thereof may be loaded into the RAM 240 . In addition, as shown in FIG. 20 , the storage device 260 may store a database 261 , and the database 261 includes information necessary for designing an integrated circuit, for example, the standard cell library D42 of FIG. 4 , FIG. 12 may include at least a portion of the input standard cell library (D121) and the output standard cell library (D122).

The storage device 260 may store data to be processed by the processor 210 or data processed by the processor 210 . That is, the processor 210 may generate data by processing data stored in the storage device 260 according to the program 241 , and may store the generated data in the storage device 260 . For example, the storage device 260 may store the RTL data D41 , the netlist data D43 and/or the layout data D44 of FIG. 4 , and the netlist data D181 of FIG. 18 , the layout Data D182 and/or result data D184 may be stored.

The input/output devices 220 may include an input device such as a keyboard and a pointing device, and may include an output device such as a display device and a printer. For example, the user may trigger execution of the program 241 by the processor 210 through the input/output devices 220 , and RTL data D41 and/or netlist data D43 of FIG. 4 . may be input, and the layout data D44 of FIG. 4 may be checked.

Network interface 230 may provide access to a network external to computing system 200 . For example, a network may include a number of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

An integrated circuit comprising a plurality of standard cells, comprising:
Each of the plurality of standard cells includes a front end of line (FEOL) region including at least one gate line extending in a first horizontal direction and a back end of line (BEOL) region on the FEOL region,
The BEOL area of the first standard cell as one of the plurality of standard cells does not vertically overlap with the FEOL area of the first standard cell and protrudes in a second horizontal direction perpendicular to the first horizontal direction, the eaves ( eaves) portion. The method according to claim 1,
The plurality of standard cells further include a second standard cell adjacent to the first standard cell in the second horizontal direction,
The FEOL region of the second standard cell is vertically overlapped with the eaves of the first standard cell and protrudes in a direction opposite to the second horizontal direction, characterized in that it includes a first step portion integrated circuit. 3. The method according to claim 2,
and a single diffusion break extending in the first horizontal direction between a FEOL region of the first standard cell and a FEOL region of the second standard cell. 3. The method according to claim 2,
The BEOL region of the second standard cell does not vertically overlap with the FEOL region of the second standard cell and protrudes in the second horizontal direction, including an eaves portion,
and the eaves portion of the second standard cell has the same length in the second horizontal direction as the first step portion of the second standard cell. 3. The method according to claim 2,
The FEOL region of the second standard cell further includes a second step portion that does not vertically overlap with the BEOL region of the second standard cell and protrudes in the second horizontal direction,
and the second step portion of the second standard cell has the same length in the second horizontal direction as the first step portion of the second standard cell. The method according to claim 1,
The plurality of standard cells further include a third standard cell adjacent to the first standard cell in the second horizontal direction,
The BEOL region of the third standard cell does not vertically overlap with the FEOL region of the third standard cell but protrudes in a direction opposite to the second horizontal direction, the integrated circuit comprising an eaves portion. 7. The method of claim 6,
A double diffusion break extending in the first horizontal direction between the FEOL area of the first standard cell and the FEOL area of the third standard cell and vertically overlapping with the eaves portions of the first and third standard cells (double diffusion break). The method according to claim 1,
The FEOL region of the first standard cell includes a step portion that does not vertically overlap with the BEOL region of the first standard cell and protrudes in a direction opposite to the second horizontal direction,
and the step portion of the first standard cell has the same length in the second horizontal direction as the eaves portion of the first standard cell. 9. The method of claim 8,
The plurality of standard cells further include a fourth standard cell adjacent to the first standard cell in a direction opposite to the second horizontal direction,
The FEOL region of the fourth standard cell includes a step portion that does not vertically overlap with the BEOL region of the fourth standard cell and protrudes in the second horizontal direction. 10. The method of claim 9,
and a single diffusion brake extending in the first horizontal direction between FEOL regions of the first and fourth standard cells. 9. The method of claim 8,
and at least one pattern extending in the second horizontal direction between the BEOL regions of the first and fourth standard cells and connecting power lines of the first and second standard cells. 9. The method of claim 8,
The plurality of standard cells further include a fifth standard cell adjacent to the first standard cell in a direction opposite to the second horizontal direction,
The BEOL region of the fifth standard cell does not vertically overlap with the FEOL region of the fifth standard cell, but protrudes in the second horizontal direction and the second horizontal direction opposite to the second horizontal direction. comprising first and second eaves portions having a length;
and the first eaves portion of the fifth standard cell vertically overlaps with the step portion of the first standard cell. 9. The method of claim 8,
The FEOL region of the first standard cell further includes at least one transistor and at least one contact for transferring a power supply voltage to the at least one transistor;
and said at least one contact is adjacent to a step portion of said first standard cell. The method according to claim 1,
The plurality of standard cells provide the same function as the first standard cell and project the BEOL region in the opposite direction to the second horizontal direction by symmetry of the first standard cell about an axis parallel to the first horizontal direction. The integrated circuit further comprising a sixth standard cell comprising an eaves portion of The method according to claim 1,
The plurality of standard cells further include a seventh standard cell including a FEOL region and a BEOL region stacked identically to the same size as the first standard cell and having a different pin arrangement from the first standard cell. 16. The method of claim 15,
and the seventh standard cell includes a FEOL region in which the FEOL region of the first standard cell is symmetrical about an axis parallel to the first horizontal direction. An integrated circuit comprising a plurality of standard cells, comprising:
Each of the plurality of standard cells includes a front end of line (FEOL) region including at least one gate line extending in a first horizontal direction and a back end of line (BEOL) region on the FEOL region,
The plurality of standard cells include a first standard cell and a second standard cell continuously arranged in a second horizontal direction perpendicular to the first horizontal direction,
The BEOL region of the first standard cell vertically overlaps with at least a portion of the FEOL region of the second standard cell. A computer-implemented method of generating a layout of an integrated circuit, comprising:
A standard cell library defining a plurality of standard cells each including a front end of line (FEOL) region including at least one gate line extending in a first horizontal direction and a back end of line (BEOL) region on the FEOL region access to; and
Placing standard cells based on the standard cell library,
The arranging of the standard cell includes the eaves of the BEOL region protruding in a second horizontal direction perpendicular to the first horizontal direction from the first standard cell and the second standard cell projecting in the opposite direction to the second horizontal direction. and arranging the second standard cell adjacent to the first standard cell in the second horizontal direction so that the step portion of the FEOL region is vertically overlapped. 19. The method of claim 18,
The disposing of the second standard cell may include flipping a standard cell that provides the same function as the second standard cell and includes a step portion of the second horizontally protruding FEOL region. A computer implemented method comprising generating a cell. A computer-implemented method for creating a standard cell library defining a plurality of standard cells for creating a layout of an integrated circuit, the method comprising:
Double diffusion breaks including at least one gate line extending in a first horizontal direction and extending in the first horizontal direction at both ends opposite to each other in a second horizontal direction perpendicular to the first horizontal direction receiving an input library defining a first standard cell including the formed first FEOL region and a first BEOL region on the first FEOL region; and
A second FEOL region providing the same function as the first standard cell and having single diffusion breaks respectively extending in the first horizontal direction at opposite ends of the second horizontal direction, and a second on the second FEOL region generating an output library defining a second standard cell comprising a BEOL region;
The output library defines an eaves portion of the second BEOL region protruding in the second horizontal direction and a step portion of the second FEOL region protruding in a direction opposite to the second horizontal direction. method.

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