KR102351337B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an OLED display device, and when the pixel (P) is driven in the PM mode, only the initialization voltage (Vinti) input to the initialization voltage (Vinit) supply line is controlled to drive or not to drive the OLED, In addition, an OLED display device capable of variously controlling the emission of OLEDs is provided.

Description

OLED display device {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE}

The present invention relates to an organic light emitting diode (OLED) display device.

A plurality of pixels constituting an OLED display device driven in an active matrix (hereinafter referred to as AM) method includes an OLED each comprising an anode, a cathode, and an organic light emitting layer between the anode and cathode, and a pixel driving device that independently drives the OLED circuit is provided. The pixel driving circuit mainly includes a switching thin film transistor (hereinafter, TFT), a capacitor, and a driving TFT. The switching TFT charges the data voltage to the capacitor in response to the scan pulse, and the driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted by the OLED.

Such an OLED display device is a self-emission type display device, and unlike a liquid crystal display device, it does not require a separate light source, so it can be manufactured in a lightweight and thin form. In addition, OLED display devices are not only advantageous in terms of power consumption due to low voltage driving, but also have excellent color realization, response speed, viewing angle, and contrast ratio (CR). is being applied as

In manufacturing an OLED display having the above advantages, spots or patterns are generated on the screen, bright spots or dark spots are generated, or an afterimage is generated. Alternatively, the OLED display device may not light up at all.

When such various defects occur in the OLED display device, an attempt is made to solve the defects by identifying the cause of the defect and analyzing it. In order to identify the cause of the defect, a process of recognizing which of the various components constituting the OLED display device has the cause of the defect must first be performed.

However, since components constituting the OLED display device are very diverse, it is not easy to determine which component specifically has the defect. For example, the manufacturing process of an OLED display device can be largely divided into a TFT process for manufacturing a pixel driving circuit for each pixel and an OLED process for manufacturing an OLED independently driven by a pixel driving circuit for each pixel. However, it is not easy to know in which process the cause of the defect occurred by visually checking the defective OLED display device.

The present invention is to solve the above problems, and in an OLED display device driven by the AM method, when a defect occurs in the OLED display device, whether the component having the cause of the defect is in the pixel driving circuit or the OLED It is an object of the present invention to provide an OLED display device capable of recognizing whether or not

The present invention can provide an OLED display with improved image quality by compensating for a characteristic deviation of a driving TFT and compensating for a voltage drop of a high potential voltage, thereby reducing a luminance deviation between pixels.

The present invention can provide an OLED display in which the luminance of the OLED is improved by relatively reducing the capacitance ratio of the first capacitor by including the second capacitor connected in series to the first capacitor.

The present invention can provide an OLED display that compensates for variations in mobility of driving TFTs between pixels.

The present invention can provide an OLED display device capable of discriminating whether a defect is caused by a pixel driving circuit or an OLED when a defect occurs in the OLED display device.

The present invention can provide an OLED display capable of driving in PM mode by mounting a Drive-IC designed to output an initialization voltage greater than zero to an initialization voltage supply line of the OLED display device.

The present invention provides a drive-IC designed to vary and output the initialization voltage so that the initialization voltage supplied to the initialization voltage supply line of the OLED display can be either a negative value or a positive value. It is possible to provide an OLED display device capable of driving in mode.

The present invention provides an OLED display device capable of identifying a component causing a corresponding defect without performing a destructive analysis by driving the OLED display device in a PM (Passive Matrix) mode when a defect occurs in the OLED display device can do.

According to the present invention, when a defect occurs in an OLED display device, it is possible to provide an OLED display device in which failure analysis efficiency is increased by simply and repeatedly performing failure analysis with the OLED display device.

The present invention can provide an OLED display device capable of inputting an initialization voltage that is optimized for each pixel emitting the same color among a plurality of pixels included in the OLED display device.

The present invention can provide an OLED display capable of adjusting luminance, color coordinates or color temperature when driving in PM mode by separately inputting an initialization voltage for each pixel emitting the same color among a plurality of pixels included in the OLED display device. have.

The present invention provides an OLED display device in which an initialization voltage amplifier of a low-capacity Drive-IC can be used by dividing the initialization voltage value for each set of pixels emitting the same color, thereby reducing the amplifier load and reducing the stabilization period can do.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram of an OLED display device according to an embodiment of the present invention.
FIG. 2 is a driving timing diagram of the pixel P shown in FIG. 1 in an AM mode.
3, 4A, and 4B are circuit diagrams of the pixel P shown in FIG. 1 .
FIG. 5 is a circuit diagram of the pixel P shown in FIG. 1 , and is a driving concept diagram in a PM mode.
6 is a configuration diagram of an initialization voltage supply line and a pad in an OLED display device according to an embodiment of the present invention;

Hereinafter, an OLED display device and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an OLED display device according to an embodiment of the present invention.

The OLED display shown in FIG. 1 includes a display panel 2 in which a plurality of gate lines GL and gate lines GL cross each other to define each pixel P, and a display panel 2 that drives the plurality of gate lines GL. The gate driver 4, the data driver 6 driving the plurality of data lines DL, and the image data RGB input from the outside are arranged and supplied to the data driver 6, and the gate control signal GCS ) and a timing controller 8 for controlling the gate driver 4 and the data driver 6 by outputting the data control signal DCS.

Each pixel P includes an OLED and a pixel driving circuit for independently driving the OLED including a driving TFT DT for supplying a driving current to the OLED. The pixel driving circuit is configured to compensate the characteristic deviation of the driving TFT (DT) and compensate for the voltage drop of the high potential voltage (VDD), that is, by including the compensation circuit, it is possible to reduce the luminance deviation between the respective pixels (P). have.

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL that intersect each other, and a plurality of pixels P are provided in the intersection regions of the GL and DL. Each pixel P includes an OLED and a pixel driving circuit. The gate line GL, the data line DL, the high potential voltage VDD supply line, the low potential voltage VSS supply line, and the initialization voltage Vinit supply line are connected.

The gate driver 4 supplies a plurality of gate signals to the plurality of gate lines GL according to the plurality of gate control signals GCS provided from the timing controller 8 . More specifically, the gate driver 4 includes a timing controller 8 , a level shifter connected between the plurality of gate lines GL of the display panel 2 , and a GIP driving circuit.

At this time, the GIP driving circuit includes a scan driver controlling various scan signals SCAN1 and SCAN2 and an initialization voltage Vint of each pixel P and a light emission signal EM of each pixel P. It includes a light emission control unit (Inverter) for controlling the.

The level shifter level-shifts the transistor-transistor-logic (TTL) logic level voltages of the 4-phase or 5-phase gate shift clocks input from the timing controller 8 to a gate high voltage VGH and a gate low voltage VGL. In the present invention, the TFT may be configured as a P-type or an N-type. Hereinafter, for convenience of explanation, the TFT will be described as an N-type. Accordingly, the gate high voltage VGH is a voltage higher than the threshold voltage of the TFT and is a gate-on voltage that turns on the TFT, and the gate low voltage VGL is a voltage lower than the threshold voltage of the TFT and turns the TFT off. is the off voltage. And, in describing the pulse-shaped signal, a state of the gate high voltage VGH is defined as a “high state” and a state of the gate low voltage VGL is defined as a “low state”.

The scan controller outputs various scan signals SCAN1 and SCAN2 to each gate line GL while shifting the gate start pulse according to the gate shift clocks. The light emission control unit outputs the light emission signal EM through the light emission control line. The various scan signals SCAN1 and SCAN2 and the emission signal EM may be calculated through gate shift clocks and a start voltage.

The GIP driving circuit is directly formed on the lower substrate of the display panel 2 in a GIP (Gate Drive-IC In Panel) method. The GIP driving circuit may be connected between the gate lines GL of the display panel 2 and the timing controller 8 in a TAB method. In the GIP method, the level shifter may be mounted on a PCB, and the GIP driving circuit may be formed on a lower substrate of the display panel 2 .

The high potential voltage VDD has a relatively higher voltage than the low potential voltage VSS. The low potential voltage VSS may be a ground voltage.

The initialization voltage Vinit may have a voltage lower than the OLED driving voltage of each pixel or a voltage higher than the OLED driving voltage of each pixel.

The data driver 6 converts digital image data RGB input from the timing controller 8 according to a plurality of data control signals DCS provided from the timing controller 8 to a data voltage Vdata using a reference gamma voltage. convert Then, the converted data voltage Vdata is supplied to the plurality of data lines DL.

The timing controller 8 aligns image data RGB input from the outside according to the size and resolution of the display panel 2 and supplies it to the data driver 6 . The timing controller 8 uses a plurality of synchronization signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. of gate and data control signals (GCS, DCS) are generated. And by supplying the generated plurality of gate and data control signals GCS and DCS to the gate driver 4 and the data driver 6, respectively, the gate driver 4 and the data driver 6 are controlled.

Hereinafter, the pixel P included in the OLED display according to an embodiment of the present invention will be described in more detail.

First, a pixel driving circuit capable of driving an OLED display device according to an embodiment of the present invention in AM mode will be described with reference to FIGS. 3, 4A and 4B .

In this case, the AM mode is a mode in which the OLED receives a driving current through the high potential voltage (VDD) supply line of the pixel driving circuit and the driving TFT DT when the pixel P emits light. When the pixel P is driven in the AM mode, the initialization voltage Vinit may have a voltage lower than the OLED driving voltage, and the high potential voltage VDD may have a voltage higher than the OLED driving voltage.

Referring to FIG. 3 , the pixel P may include an OLED, four TFTs including a driving TFT DT, and a pixel driving circuit including two capacitors to drive the OLED. Specifically, the pixel driving circuit of FIG. 3 is a so-called 4T2C, and may include a driving TFT DT, first to third TFTs T1 to T3, and first and second capacitors C1 and C2.

The driving TFT (DT) is connected in series between the high potential voltage (VDD) supply line and the low potential voltage (VSS) supply line together with the OLED, and supplies a current for driving the OLED to the OLED in the light emission period t4 .

The first TFT T1 is turned on or turned off according to the first scan signal SCAN1 , and when turned on, the first node N1 connected to the data line DL and the gate of the driving TFT DT connect to each other The first TFT T1 supplies the reference voltage Vref provided from the data line DL to the first node N1 in the initialization period t1 and the sampling period t2 . In the programming period t3 , the data voltage Vdata provided from the data line DL is supplied to the first node N1 .

The second TFT (T2) is turned on or turned off according to the second scan signal (SCAN2), and at turn-on, a second node ( N2) are connected to each other. The second TFT T2 supplies the initialization voltage Vinit provided from the initialization voltage Vinit supply line to the second node N2 in the initialization period t1 .

The third TFT T3 is turned on or turned off according to the emission signal EM, and when turned on, supplies the high potential voltage VDD to the drain of the driving TFT DT. The third TFT T3 supplies the high potential voltage VDD provided from the high potential voltage VDD supply line to the drain of the driving TFT DT in the sampling period t2 and the light emission period t4 .

The first capacitor C1 is connected between the first and second nodes N1 and N2. The first capacitor C1 stores the threshold voltage Vth of the driving TFT DT in the sampling period t2 .

The second capacitor C2 is connected between the initialization voltage Vinit supply line and the second node N2 . The second capacitor C2 is connected in series with the first capacitor C1 to relatively reduce the capacitance ratio of the first capacitor C1 to the data voltage applied to the first node N1 in the programming period t3. It plays a role in improving the luminance of OLED compared to (Vdata). Meanwhile, the second capacitor C2 may be connected between the high potential voltage VDD supply line and the second node N2 as shown in FIG. 4A . Also, as shown in FIG. 4B , it may be connected between the low potential voltage (VSS) supply line and the second node N2.

Next, a method of driving the pixel P when the OLED display device according to an exemplary embodiment is driven in the AM mode will be described with reference to FIGS. 2 and 3 .

In the OLED display device according to the embodiment of the present invention, when the pixel P is driven in the AM mode, the pixel P is basically The operation is divided into an initialization period t1, a sampling period t2, a programming period t3, and a light emission period t4.

In the initialization period t1, the gate node (which becomes the first node N1 in Fig. 3) and the source node (which becomes the second node N2 in Fig. 3) of the driving TFT DT of the pixel P, This is a period in which a voltage difference greater than the threshold voltage of the driving TFT DT is made. That is, it is a period in which the gate-source voltage difference Vgs of the driving TFT DT is greater than the threshold voltage of the driving TFT DT. For example, in the pixel P driven by the pixel driving circuit according to the circuit diagram of FIG. 3 , in the initialization period t1 , when the first scan signal SCAN1 is output in a high state, the second scan signal ( SCAN2) may be output in a high state and then output in a low state, and the emission signal EM may be output in a low state.

The sampling period t2 is a period for sensing or sampling the threshold voltage of the driving TFT DT of the pixel P. For example, in the pixel P driven by the pixel driving circuit according to the circuit diagram of FIG. 3 , in the sampling period t2 , both the first scan signal SCAN1 and the emission signal EM are output to a high state. and at the same time may be a period in which the second scan signal SCAN2 is output in a low state.

The programming period t3 is a period in which data is written into the capacitor of the pixel P. For example, in the pixel P driven by the pixel driving circuit according to the circuit diagram of FIG. 3 , in the programming period t3 , the first scan signal SCAN1 is output to a high state, and at the same time, the second scan signal ( SCAN2) and the emission signal EM are both output in a low state, and the data voltage Vdata is input to the data line DL.

As a period between the programming period t3 and the light emission period t4, there may be a holding period. For example, in the pixel P driven by the pixel driving circuit according to the circuit diagram of FIG. 3 , the holding period includes all of the first scan signal SCAN1 , the second scan signal SCAN2 , and the emission signal EM together. It may be a period in which the low state is output. Without the holding period, the programming period t3 may directly proceed to the light emission period t4 .

The light emission period t4 is a period in which the OLED receives current and emits light in response to data written in the capacitor of the pixel P. For example, in the pixel P driven by the pixel driving circuit according to the circuit diagram of FIG. 3 , in the emission period t4 , the emission signal EM is output in a high state, and the first and second scan signals are simultaneously output. (SCAN1, SCAN2) may be a period in which both are output to a low state.

FIG. 2 is a driving timing diagram of the pixel P shown in FIG. 1 in an AM mode.

First, in the initialization period t1 , the first TFT T1 and the second TFT T2 are turned on. Then, the reference voltage Vref provided from the data drive 6 to the data line DL is supplied to the first node N1 through the first TFT T1 and provided as the initialization voltage Vinit supply line. The initialization voltage Vinit is supplied to the second node N2 to initialize the pixel P.

Subsequently, in the sampling period t2 , the first TFT ( T1 ) and the third TFT ( T3 ) are turned on. That is, in the sampling period t2 as in the initialization period t1, the reference voltage Vref is continuously supplied to the data line DL, the second TFT T2 is turned off, and the third TFT T3 is turned off. is turned on, and the first node N1 maintains the reference voltage Vref. In addition, current flows in the source direction with the drain floating at the high potential voltage VDD in the driving TFT DT, and is turned off when the voltage of the source becomes “Vref-Vth”. Here, "Vth" represents the threshold voltage of the driving TFT DT.

Subsequently, in the programming period t3 , the first TFT T1 is turned on. Then, the data voltage Vdata provided from the data drive 6 to the data line DL is supplied to the first node N1 through the first TFT T1 .

Then, as a coupling phenomenon occurs according to voltage distribution by the series cap of the first capacitor C1 and the second capacitor C2, the voltage of the second node N2 is "Vref-Vth+C'(Vdata) -Vref)". Here, "C" represents "C1/(C1+C2+Coled)". "Coled" refers to the capacitance of the OLED. In the present invention, by providing the second capacitor C2 connected in series to the first capacitor C1, the capacitance ratio of the first capacitor C1 is relatively reduced, and in the programming period t3, the first node N1 is The luminance of the OLED is improved compared to the applied data voltage (Vdata).

Subsequently, in the light emission period t4 , the third TFT T3 is turned on. Then, the high potential voltage VDD is applied to the drain of the driving TFT DT through the third TFT T3 , and the driving TFT DT supplies a driving current to the OLED. At this time, the expression of the driving current supplied to the OLED from the driving TFT DT becomes "K(Vdata-Vref-C'(Vdata-Vref)) ² ". Looking at the above equation, it can be seen that the influence of the threshold voltage Vth and the high potential voltage VDD of the driving TFT DT is excluded from the driving current of the OLED. Accordingly, in the pixel P of the present invention, by compensating for the characteristic deviation of the driving TFT and the voltage drop of the high potential voltage VDD, the luminance deviation between the pixels P can be reduced. Meanwhile, according to the present invention, the variation in mobility of the driving TFT DT may be compensated for by adjusting a rise time during which the emission signal EM changes from a low state to a high state at the start of the emission period t4 .

When the OLED display device according to the embodiment of the present invention generally displays an image, it is necessary to compensate for the fluctuation of the threshold voltage of the driving TFT DT individually for each pixel P, so that it is basically driven in the AM mode. do.

As a result of driving the OLED display device according to the embodiment of the present invention in AM mode, if it is determined that a defect has occurred in image display, try driving the OLED display device in PM (Passive Matrix) mode.

The PM mode is a mode in which the OLED receives the driving current from the initialization voltage Vinit supply line of the pixel driving circuit and the second TFT when the pixel P emits light. Accordingly, when the pixel P is driven in the PM mode, the initialization voltage Vinit may have a voltage higher than the OLED driving voltage. Also, when the pixel P is driven in the PM mode, no current may flow in the driving TFT DT.

If, as a result of driving the OLED display device according to the embodiment of the present invention in PM mode, it is determined that the same or similar defect as when driving in AM mode occurs in image display, the cause of the defect is included It can be concluded that the components present are present in the OLED, not the pixel driving circuit.

If, as a result of driving the OLED display device according to the embodiment of the present invention in PM mode, the same or similar defect as when driving in AM mode is not found in image display, the cause of the defect is included It can be concluded that the element is present in the pixel driving circuit, not in the OLED.

That is, by driving the OLED display device according to the embodiment of the present invention in the PM mode, it is possible to distinguish which component is the cause of the defect.

The OLED display according to the embodiment of the present invention may be driven in the PM mode by using the pixel driving circuit shown in FIGS. 3, 4A, and 4B that can be driven in the AM mode as it is.

In the AM mode, as the OLED display displays an image in a cascade driving method in units of lines constituting one frame of the display panel 2, the pixels in FIGS. 3, 4A and 4B The driving circuit is driven so as to follow the driving timing diagram as in FIG.

On the other hand, in the PM mode, as the OLED display displays an image in such a way that all of the plurality of pixels P constituting the frame are simultaneously driven in units of one frame of the display panel 2, FIGS. 3, 4A and The pixel driving circuit in FIG. 4B does not perform a division operation according to the initialization period t1 to the light emission period t4.

In the AM mode, the current for driving the OLED of the pixel P is supplied from the high potential voltage (VDD) supply line, whereas in the PM mode, the current for driving the OLED of the pixel P is supplied from the initialization voltage (Vinit) supply line. will become

In the AM mode, since the OLED needs to be initialized with the initialization voltage Vinit, the voltage input to the initialization voltage Vinit supply line of the pixel P is less than 0, whereas in the PM mode, the OLED is driven with the initialization voltage Vinit. Therefore, the voltage input to the initialization voltage Vinit supply line of the pixel P is greater than the OLED driving voltage and is a positive value.

Hereinafter, a method of driving the pixel P when the OLED display device according to an embodiment of the present invention is driven in the PM mode will be described with reference to FIG. 5 .

The first scan signal SCAN1 is output in a high state, and the first TFT T1 is turned on according to the first scan signal SCAN1 . When the first TFT T1 is turned on, the data line DL and the first node N1 connected to the gate of the driving TFT DT are connected to each other. In the PM mode driving, in order to always output the first scan signal SCAN1 to the pixel driving circuit in a high state, for example, there is no gate low voltage VGL, but only the gate high voltage VGH in the scan controller. can be entered. Accordingly, the first scan signal SCAN1 output from the GIP driving circuit may always be output in a high state in the PM mode driving.

The second scan signal SCAN2 is output to a high state, and the second TFT T2 is turned on according to the second scan signal SCAN2 . The second TFT T2 connects the initialization voltage Vinit supply line and the second node N2 connected to the source of the driving TFT DT during turn-on to each other. The second TFT T2 supplies the initialization voltage Vinit provided from the initialization voltage Vinit supply line to the second node N2 . In the PM mode driving, in order to always output the second scan signal SCAN2 to the pixel driving circuit in a high state, for example, there is no gate low voltage VGL but only the gate high voltage VGH in the scan controller. can be entered. Accordingly, the second scan signal SCAN2 output from the GIP driving circuit may always be output in a high state in the PM mode driving.

The light emission signal EM is output in a low state, and the third TFT T3 is turned off according to the light emission signal EM. When the third TFT T3 is turned off, the high potential voltage VDD provided from the high potential voltage VDD supply line is not supplied to the drain of the driving TFT DT. In the PM mode driving, in order to always output the emission signal EM to the pixel driving circuit in a low state, for example, there is no emission high voltage VEH and only the emission low voltage VEL is applied to the emission control unit. can be entered. Accordingly, the light emitting signal EM output from the GIP driving circuit may always be output in a low state in the PM mode driving.

In the PM mode driving, the data line DL does not play a role in controlling the emission of the pixel P. Accordingly, a predetermined voltage value may be supplied to the data line DL. Alternatively, the data line DL may be floating.

In the PM mode driving, the high potential voltage (VDD) supply line does not serve to supply a voltage for driving the OLED of the pixel (P). Accordingly, a predetermined voltage value to the extent that no current flows in the driving TFT DT may be continuously supplied to the high potential voltage VDD supply line. Alternatively, the high potential voltage (VDD) supply line may be floated or grounded.

In the PM mode driving, the driving TFT DT does not play a role in controlling whether the OLED of the pixel P emits light. Accordingly, a voltage corresponding to the threshold voltage of the driving TFT is not stored in the first and second capacitors C1 and C2 , and a predetermined potential difference continues to exist across the first capacitor C1 .

In the PM mode driving, a current for driving the OLED may be supplied from an initialization voltage (Vinit) supply line. That is, since the OLED must be driven by the initialization voltage Vinit supplied to the initialization voltage Vinit supply line, the initialization voltage Vinit has at least a greater value than the OLED driving voltage. For example, the initialization voltage Vinit may be 5V.

In summary, in the OLED display device according to the embodiment of the present invention, when the pixel P is driven in the AM mode, the current driving the OLED is supplied from the high potential voltage (VDD) supply line, whereas the current driving the OLED is supplied in the PM mode. In the case of driving, the current for driving the OLED is supplied from the initialization voltage (Vinit) supply line.

In addition, in the OLED display device according to the embodiment of the present invention, when the pixel P is driven in the AM mode, the data voltage Vdata supplied from the data line DL is controlled to control the emission of the OLED. will do However, when the pixel P is driven in the PM mode, the initialization voltage Vinit supplied from the initialization voltage Vinit supply line is controlled to control the emission of the OLED. In other words, when it is desired to adjust luminance, color coordinates, or color temperature by controlling the light emission of the OLED in each pixel P, when the pixel P is driven in the AM mode, the data voltage is used to control the light emission of the OLED. On the other hand, when the pixel A is driven in the PM mode, it is necessary to control the initialization voltage Vinit in order to control the emission of the OLED.

That is, in the OLED display device according to the embodiment of the present invention, when the pixel P is driven in the PM mode, only the initialization voltage Vinti input to the initialization voltage Vinit supply line is controlled to drive the OLED or It may not be driven, and it is possible to control the emission of OLED in various ways.

In the OLED display device according to the embodiment of the present invention, the initialization voltage input from the initialization voltage (Vinit) supply line to the pixel P has a lower value than the OLED driving voltage when driving in the AM mode and in the PM mode. When driving, it has a higher value than the OLED driving voltage, so it initializes the OLED in AM mode and drives the OLED in PM mode.

In this way, it is possible to separate the initialization voltage (Vinit) supply line for each group of pixels (P) emitting the same type of color. Referring to FIG. 6 , an initialization voltage (Vinit) supply line and an initialization voltage pad (Vinit Pad) will be described in the case where the display panel 2 includes a red pixel, a green pixel, and a blue pixel.

All pixels P included in the display panel 2 may each correspond to any one of a red pixel, a green pixel, and a blue pixel. In this case, the red initialization voltage supply line R-Vinit Line shared by the red pixel group may be connected to the red initialization voltage pad R-Vinit Pad. Also, a green initialization voltage supply line (G-Vinit Line) shared by the group of green pixels may be connected to the green initialization voltage pad (G-Vinit Pad). Also, the blue initialization voltage supply line R-Vinit Line shared by the blue pixel group may be connected to the blue initialization voltage pad R-Vinit Pad. At this time, the red initialization voltage supply line (R-Vinit Line), the green initialization voltage supply line (G-Vinit Line), and the blue initialization voltage supply line (R-Vinit Line) are separated from each other, and the red initialization voltage pad (R -Vinit Pad), green initialization voltage pad (G-Vinit Pad), and blue initialization voltage pad (R-Vinit Pad) are separated from each other. That is, the red initialization voltage supply line (R-Vinit Line), the green initialization voltage supply line (G-Vinit Line), and the blue initialization voltage supply line (R-Vinit Line) do not share the initialization voltage pad with each other.

Accordingly, the red pixel group may receive the same red initialization voltage R-Vinit, respectively. Also, the green pixel group may receive the same green initialization voltage R-Vinit, respectively. In addition, each group of blue pixels may receive the same blue initialization voltage R-Vinit.

As the OLEDs of the pixels P of different colors are formed of different materials, the OLED driving voltages of the pixels P of different colors have different values. Accordingly, when the OLED display device according to the embodiment of the present invention is driven in the AM mode, it is possible to supply the initialization voltage Vinit of different values to the pixels P of different colors. The driving conditions can be further optimized.

In addition, when the OLED display device according to the embodiment of the present invention is driven in AM mode, a plurality of initialization voltage amplifiers of the Drive-IC are provided in order to supply initialization voltages (Vinit) of different values to each pixel group of different colors. should be used, it is possible to use the initialization voltage amplifier of Drive-IC with low capacity, and accordingly, the load applied to each amplifier is lowered and the stabilization period is shortened.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

SYNC: sync signals
DCLK: dot clock
DE: data enable signal
Hsync: horizontal sync signal
Vsync: vertical sync signal
GCS: gate control signal
DCS: data control signal
RGB: image data
8: Timing Controller
4: gate driver
6: Data driver
2: Display panel
P: pixel
GL: gate line
DL: data line
VDD: high potential voltage
VSS: low potential voltage
Vinit: initialization voltage
Vdata: data voltage
Vref: reference voltage
SCAN1: first scan signal
SCAN2: second scan signal
EM: luminescence signal
t1: initialization period
t2: sampling period
t3: programming period
t4: luminescence period
DT: driving TFT
T1: first TFT
T2: second TFT
T3: third TFT
C1: first capacitor
C2: second capacitor
N1: first node
N2: second node

Claims (14)

Including a plurality of pixels driven in either an AM mode (Active Matrix Mode) in which a plurality of pixels are sequentially driven cascade in line units and a PM mode (Passive Matrix Mode) in which all of the plurality of pixels are simultaneously driven,
Each of the plurality of pixels includes an OLED and a pixel driving circuit,
The pixel driving circuit comprises:
a driving TFT for supplying a driving current to the OLED; and
a second TFT for supplying an initialization voltage to the driving TFT according to a second scan signal; including,
In the AM mode, the initialization voltage is lower than the driving voltage of the OLED, so that the gate-source voltage difference (Vgs) of the driving TFT is greater than the threshold voltage of the driving TFT;
In the PM mode, the initialization voltage is higher than the driving voltage of the OLED, and a positive bias is applied to the OLEDs provided in all of the plurality of pixels, so that all of the normal OLEDs among the OLEDs provided in all of the plurality of pixels are driven. Device.
According to claim 1,
The pixel driving circuit comprises:
a first TFT connecting a data line and a gate electrode of the driving TFT to each other according to a first scan signal;
a third TFT connecting the driving TFT and the high potential voltage supply line to each other according to the light emitting signal; and
a first capacitor connected between a source electrode and a gate electrode of the driving TFT; Further comprising, an OLED display device.
3. The method of claim 2,
The pixel driving circuit comprises:
and a second capacitor connected between the source electrode of the driving TFT and an initialization voltage supply line.
3. The method of claim 2,
The pixel driving circuit comprises:
and a second capacitor connected between the source electrode of the driving TFT and the high potential voltage supply line.
3. The method of claim 2,
The pixel driving circuit comprises:
and a second capacitor connected between the source electrode of the driving TFT and the low potential voltage supply line.
3. The method of claim 2,
In the PM mode,
The second scan signal is output to a high state,
The light emitting signal is output in a low state.
7. The method of claim 6,
In the PM mode,
and the first scan signal is output in a high state.
3. The method of claim 2,
In the PM mode,
wherein the data line is floating.
3. The method of claim 2,
In the PM mode,
and the high potential voltage supply line is grounded or floated.
delete 3. The method of claim 2,
and a gate driver outputting the first scan signal, the second scan signal, the emission signal, and the initialization voltage.
12. The method of claim 11,
The plurality of pixels are composed of a red pixel, a green pixel, and a blue pixel,
The initialization voltage supply line for supplying the initialization voltage includes a red initialization voltage supply line, a green initialization voltage supply line, and a blue initialization voltage supply line, which are separated from each other;
the red initialization voltage supply line is connected to the red pixel;
the green initialization voltage supply line is connected to the green pixel;
and the blue initialization voltage supply line is connected to the blue pixel.
13. The method of claim 12,
The red initialization voltage supply line is connected to the red initialization voltage pad,
the green initialization voltage supply line is connected to the green initialization voltage pad;
The blue initialization voltage supply line is connected to the blue initialization voltage pad.
14. The method of claim 13,
The gate driver is
supplying a red initialization voltage to the red initialization voltage pad;
supplying a green initialization voltage to the green initialization voltage pad;
and supplying a blue initialization voltage to the blue initialization voltage pad.

Images