KR102334811B1 - Thin film transistor substrate - Google Patents

Abstract

The present invention provides an insulating substrate having a dummy area and a display area; a signal line formed in the dummy region on the insulating substrate; a switching element positioned in the display area on the insulating substrate; a color filter layer positioned in the display area on the insulating substrate, exposing a portion of the switching element through one or more contact holes; and a dummy color filter layer positioned in the dummy region on the insulating substrate and exposing a portion of the signal line through one or more dummy contact holes, wherein the one or more dummy contact holes formed in the dummy color filter layer and the color filter layer are formed The at least one contact hole relates to a thin film transistor substrate formed at the same position in a plan view.

Description

Thin film transistor substrate {THIN FILM TRANSISTOR SUBSTRATE}

The present invention relates to a thin film transistor substrate.

A liquid crystal display device is one of the most widely used flat panel display devices at present. It consists of two display panels having electrodes and a liquid crystal layer interposed therebetween. A display device that controls the amount of transmitted light.

Among the liquid crystal display devices, currently mainly used is a structure in which an electric field generating electrode is provided on two display panels, respectively. Among them, a plurality of thin film transistors and pixel electrodes are arranged in a matrix on one display panel (hereinafter referred to as a 'thin film transistor display panel'), and red, green, and A structure in which a blue color filter is formed and a common electrode is covered over its front surface is the mainstream.

However, in such a liquid crystal display, since the pixel electrode and the color filter are formed on different display panels, it is difficult to accurately align the pixel electrode and the color filter, and thus an alignment error may occur.

To solve this problem, a color filter on array (CoA) structure in which a color filter and a pixel electrode are formed on the same display panel has been proposed. In the COA structure, a color filter and a light blocking member called a black matrix are formed on the same display panel as the pixel electrode.

In the manufacturing process of the liquid crystal display, a structure is formed by performing exposure and development processes. In this case, a dummy region may be generated during the formation process when the exposure and development processes are performed. For example, when a divided exposure process is performed to form a color filter in the liquid crystal display, dummy regions including dummy pixels are generated on the left and right sides of the panel of the liquid crystal display.

The present invention has been devised to solve the above problems, and it is an object of the present invention to provide a thin film transistor substrate that provides a panoramic and large panel by securing a panel region by utilizing a dummy region generated in the manufacturing process of the thin film transistor substrate There is this.

According to an exemplary embodiment of the present invention, there is provided a thin film transistor substrate comprising: an insulating substrate having a dummy area and a display area; a signal line formed in the dummy region on the insulating substrate; a switching element positioned in the display area on the insulating substrate; a color filter layer positioned in the display area on the insulating substrate, exposing a portion of the switching element through one or more contact holes; and a dummy color filter layer positioned in the dummy region on the insulating substrate and exposing a portion of the signal line through one or more dummy contact holes, wherein the one or more dummy contact holes formed in the dummy color filter layer and the color filter layer are formed The one or more contact holes are formed at the same position in a plan view.

The dummy area according to an embodiment of the present invention includes vertical dummy areas positioned on left and right sides of the display area, and the vertical dummy area includes a plurality of dummy pixels in which different dummy color filters are formed, which are arranged in at least one column. may include

The display area according to an embodiment of the present invention includes a plurality of display pixels including the color filter layer in which the switching element and the one or more contact holes are formed, wherein the display pixels are formed on the color filter layer, The display device may further include a pixel electrode contacting a portion of the switching element through the one or more contact holes formed in the color filter layer.

In this case, the display pixel may include: an upper display panel facing the insulating substrate; a liquid crystal layer positioned between the insulating substrate and the upper display panel; and a common electrode positioned on the liquid crystal layer in the upper panel.

Also, the dummy region may not include at least one of the thin film transistor, the pixel electrode, and the common electrode included in the display pixel.

In another embodiment, a portion of the storage electrode line among the signal lines may be bridged to the pixel electrode through the one or more dummy contact holes in the dummy region on the insulating substrate.

In another embodiment, an open short (OS) pad is positioned under the dummy color filter in the dummy region on the insulating substrate, and the OS pad is bridged using the one or more dummy contact holes formed in the dummy color filter. can be performed.

In this case, the OS pad may be bridged through one or more dummy contact holes formed in the dummy color filter layer of the first dummy pixel in which the OS pad is positioned.

The OS pad may be bridge-connected through one or more dummy contact holes formed in the dummy color filter layer of a second dummy pixel adjacent to the first dummy pixel in which the OS pad is positioned.

Alternatively, two or more OS pads may be positioned under the dummy color filter layer of the first dummy pixel according to the number of dummy contact holes formed in the dummy color filter layer of the second dummy pixel.

Also, according to another embodiment of the present invention, the dummy color filter layer may be implemented to expose a portion of the diode through the one or more dummy contact holes.

According to an embodiment of the present invention, the thin film transistor substrate including panoramic and large panels can be provided by securing the panel area by utilizing the dummy area generated during the thin film transistor substrate manufacturing process.

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention.
2 is a detailed layout view of a display pixel PX among a thin film transistor substrate according to an exemplary embodiment of the present invention.
3 is a plan view illustrating a thin film transistor substrate according to an embodiment of the present invention.
4 is a cross-sectional view illustrating the thin film transistor substrate shown in FIG. 3 taken along line IV-IV.
5 is a cross-sectional view schematically illustrating a cross-section of the thin film transistor substrate shown in FIG. 3 taken along a line V-V.
6 is a diagram illustrating another example of a thin film transistor substrate including a dummy pixel according to an embodiment of the present invention.
7 is a diagram illustrating another example of a thin film transistor substrate including a dummy pixel according to an embodiment of the present invention.

With reference to the accompanying drawings, the embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. However, the present invention may be embodied in several different forms and is not limited to the embodiments described herein.

In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. Throughout the specification, like reference numerals are assigned to similar parts. When a part, such as a layer, film, region, plate, etc., is “on” another part, it includes not only cases where it is “directly on” another part, but also cases where there is another part in between. Conversely, when we say that a part is "just above" another part, we mean that there is no other part in the middle.

1 is a pixel layout diagram of a thin film transistor substrate according to an embodiment of the present invention.

1 shows a layout view of the entire thin film transistor substrate. A liquid crystal display according to an embodiment of the present invention includes a thin film transistor array panel, a common electrode panel facing the same, and a liquid crystal layer between the two display panels, and pixels are arranged in a matrix direction on the thin film transistor array panel. The thin film transistor array panel is based on an insulating substrate.

A plurality of gate lines and a plurality of data lines are sequentially formed on the insulating substrate. The gate lines G1, G2, ..., Gm transmit a gate signal and mainly extend in the horizontal direction, and the data lines D1, D2, ..., Dn transmit a data signal and mainly extend in the vertical direction. , G2, …, Gm). In addition, a light blocking member (not shown) is formed on the gate lines G1, G2, ..., Gm and the data lines D1, D2, ..., Dn, and a color is formed in the pixel area partitioned by the light blocking member (not shown). A filter (not shown) is formed and constitutes a pixel.

The pixel is divided into a display pixel PX that displays an image and a dummy pixel that does not display an image. The display pixel PX is located inside the display area 500 , and the dummy pixel is located on at least one side of the outside of the display area 500 .

In the embodiment of FIG. 1 , the dummy pixels are formed outside the display area 500 , but they may be located on only one side of the display area 500 .

A dummy pixel is located in the dummy area 510 . The dummy area 510 may be formed in one or more of the upper and lower, left and right areas of the display area 500 , and thus various dummy areas may be formed according to embodiments.

The dummy region 510 shown in FIG. 1 may include a plurality of dummy pixels arranged in at least one column, and according to an embodiment, is composed of dummy pixels in two or more rows or two or more columns. . For example, if the liquid crystal display device is a device that provides ultra-large panoramic pixels of 100 inches or more, as a divided exposure process is performed in the process of forming a color filter of the liquid crystal display device, vertical dummy regions on the left and right sides of the display region 500 A plurality of columns of dummy pixels may be generated at 510 .

The display pixel PX positioned in the display area 500 includes a thin film transistor, a pixel electrode, a common electrode, and a liquid crystal layer positioned in a space between the thin film transistor array panel and the common electrode display panel. The thin film transistor is formed on an insulating substrate, and is insulated from each other and connected to a crossing gate line and a data line. The other terminal of the thin film transistor is connected to the pixel electrode. A color filter and a light blocking member may be positioned between the thin film transistor and the pixel electrode. The light blocking member may also be positioned between adjacent pixels. Meanwhile, the color filter and the light blocking member may be formed below the pixel electrode and above the thin film transistor.

Since a dummy pixel is not a pixel displaying an image, various embodiments of the structure may exist. That is, the dummy pixel may not include at least one of a thin film transistor, a pixel electrode, a common electrode, and a liquid crystal layer included in the display pixel PX.

Meanwhile, the color filter and the light blocking member may be formed below the pixel electrode and above the thin film transistor. A dummy pixel may be formed in the same way as the layered structure of the display pixel PX, but it may have a structure in which at least one component is deleted. This is because the dummy pixel does not display the actual image.

Hereinafter, the structure of the display pixel PX according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 and 3 .

2 is a detailed layout view of a display pixel PX among a thin film transistor substrate according to an exemplary embodiment of the present invention.

A thin film transistor substrate of a display device includes a plurality of pixels and a plurality of signal lines. The signal line may include a gate line, a data line, a divided reference voltage line, a storage electrode line, and the like.

Referring to FIG. 2 , one pixel of the thin film transistor substrate may include a plurality of pixel electrodes and a plurality of switching elements Q1 and Q2 .

For example, in the case of a liquid crystal display, a plurality of domains having different alignment directions of liquid crystals may be formed in one pixel to realize a wide viewing angle. To form a plurality of domains, a plurality of pixel electrodes 191a and 191b may be formed in one pixel.

The switching elements Q1 and Q2 are elements such as thin film transistors, and may be connected to at least one of a corresponding signal line, the pixel electrodes 191a and 191b, and input/output terminals of the switching elements Q1 and Q2, respectively. The switching elements Q1 and Q2 may be turned on/off according to a signal applied to a signal line. A corresponding voltage may be applied to the pixel electrodes 191a and 191b according to the operation of the switching elements Q1 and Q2 .

In this case, the input or output terminals of the switching elements Q1 and Q2 and the pixel electrodes 191a and 191b may be formed on different layers. For example, when the switching elements Q1 and Q2 are formed of thin film transistors, the layer on which the drain of the switching elements Q1 and Q2 is formed and the layer on which the pixel electrodes 191a and 191b are formed may be formed of different layers. have. In addition, a color filter layer, a passivation layer, etc. may be formed between the layer in which the drain of the switching elements Q1 and Q2 is formed and the layer in which the pixel electrodes 191a and 191b are formed.

Accordingly, the switching elements Q1 and Q2 may be connected to a pixel electrode or the like through contact holes 185a and 185b. In order to connect the pixel electrode and the input/output terminals of the switching elements Q1 and Q2, contact holes 185a and 185b are formed in a layer formed on the upper portion of the switching elements Q1 and Q2, so that the contact holes 185a and 185b are formed. A pixel electrode is directly connected to an input terminal or an output terminal of the switching elements Q1 and Q2 exposed through the pixel electrode.

In this case, the color filter layer may be formed such that contact holes 185a and 185b exposing the input and output terminals of the switching elements Q1 and Q2 are provided. In order to form the color filter layer, an exposure process and a developing process may be performed. Various methods can be used as a process method for forming the color filter layer. For example, in the case of a liquid crystal display device that provides super-large panoramic pixels of 100 inches or more, the color filter of the liquid crystal display device can be formed using a divided exposure process. . When the divided exposure process is used, one or more dummy pixels may be additionally generated outside the display area in which the display pixels are located.

3 is a plan view illustrating a thin film transistor substrate according to an embodiment of the present invention.

3 , a color filter may be formed in a plurality of pixels including a display pixel and a dummy pixel to express at least one primary color among red, green, and blue.

In addition, at least one contact hole may be formed in each pixel. The contact hole may be formed by being surrounded by color filter layers corresponding to at least two or more primary colors.

For example, at least one contact hole 185a and 185b may be formed in the pixels 191a and 191b of the display area. In addition, at least one dummy contact hole 186a, 186b, 186c, 186d, 186e, 186f, 186g, 186h, 186i, 186j) may be formed. A storage electrode line 131 is formed at an edge of the dummy area.

As described above, the at least one contact hole 185a , 185b formed in the pixels 191a and 191b of the display area is configured such that the switching elements Q1 and Q2 are connected to the pixel electrode or the like through the contact holes 185a and 185b. do.

On the other hand, at least one dummy contact hole 186a, 186b, 186c, 186d, 186e, 186f, 186g, 186h formed in the dummy pixels 192a, 192b, 192c, 192d, 192e, 192f, 192g, 192h, 192i, 192j , 186i, 186j) may be used for other purposes than those for switching elements and pixel electrodes. For example, the dummy contact holes 186a, 186b, 186c, 186d, 186e, 186f, 186g, 186h, 186i, and 186j are bridged between the storage electrode line 131 formed at the edge of the dummy pixel and the pixel electrode 191 in the display area. It can be used as a path or as a diode connection path.

Hereinafter, the structure of the thin film transistor substrate including the display pixel and the dummy pixel shown in FIG. 3 will be described with reference to FIGS. 4 and 5 .

4 is a cross-sectional view illustrating a cross-section of the thin film transistor substrate shown in FIG. 3 taken along line IV-IV, and FIG. 5 is a schematic cross-sectional view of the thin film transistor substrate shown in FIG. 3 taken along line V-V. A cross-sectional view is shown.

3 and 4 , in the display area, the thin film transistor substrate includes a plurality of gate lines 121 , a plurality of step-down gate lines 123 , and a storage electrode line (not shown) on the insulating substrate 110 . A plurality of gate conductors including

The gate line 121 and the step-down gate line 123 mainly extend in a horizontal direction and transmit a gate signal. The storage electrode line (not shown) is for transmitting a predetermined voltage such as the common voltage Vcom. The storage electrode line (not shown) mainly extends in a horizontal direction, but a storage electrode protruding upward and downward, a pair of vertical portions extending substantially vertically downward from the gate line 121 , and a horizontal portion connecting the ends of the pair of vertical portions and the transverse portion includes a capacitive electrode 126 extending downward.

A gate insulating layer 140 is formed on the gate conductors 121 , 123 , and 126 .

A plurality of linear semiconductors 154 and 157 that may be made of amorphous or crystalline silicon are formed on the gate insulating layer 140 . A plurality of linear ohmic contact members 164 and 167 are formed on the linear semiconductor 154 .

Data conduction including a plurality of data lines and a plurality of drain electrodes 175 that transmit a data signal on the ohmic contact members 164 and 167 and mainly extend in a vertical direction to intersect the gate lines 121 and 123 . body is formed.

A data line (not shown) transmits a data signal and mainly extends in a vertical direction to cross the gate line 121 and the step-down gate line 123 . Each data line (not shown) includes a plurality of source electrodes (not shown).

The gate electrode, the source electrode, and the drain electrode form one thin film transistor Q1 and Q2 together with the island semiconductor, and a channel of the thin film transistor is formed in each semiconductor between each source electrode and each drain electrode.

The linear semiconductor including the semiconductors 154 and 157 includes the data conductors 175 and 177 and the ohmic contact members 164 and 167 thereunder except for the channel region between the source electrode and the drain electrode 175 and 177 . has substantially the same planar shape as That is, in the linear semiconductor 151 including the semiconductor 154 , there is an exposed portion between the source electrode and the drain electrode 175 and not covered by the data conductor 175 .

A lower passivation layer 180p, which may be made of an inorganic insulating material such as silicon nitride or silicon oxide, is formed on the data conductors 175 and 177 and the exposed portion of the semiconductor 154 .

A color filter 230 is positioned on the lower passivation layer 180p. The color filter 230 is located in most areas except where a plurality of thin film transistors are located, and each color filter 230 can display one of primary colors such as three primary colors of red, green, and blue. have.

A light blocking member 220 is positioned on an area where the color filter 230 is not positioned and a portion of the color filter 230 . The light blocking member 220 is also referred to as a black matrix and prevents light leakage. The light blocking member 220 extends along the gate line 121 and the pressure-reducing gate line 123 and extends upward and downward, and a height of a portion of the light blocking member 220 may be lower than the height of the color filter 230 .

An upper passivation layer 180q is formed on the color filter 230 and the light blocking member 220 . The upper passivation layer 180q prevents the color filter 230 and the light blocking member 220 from lifting up, and suppresses contamination of the liquid crystal layer 3 by an organic material such as a solvent flowing from the color filter 230 to the screen. Prevents defects such as afterimages that may occur during operation.

A plurality of contact holes 185a and 185b exposing a wide end of the drain electrode 175 are formed in the lower passivation layer 180p, the light blocking member 220 and the upper passivation layer 180q. Color filters corresponding to at least two primary colors may be formed around the plurality of contact holes 185a and 185b.

A plurality of pixel electrodes 191 are formed on the upper passivation layer 180q.

The plurality of pixel electrodes 191 are physically and electrically connected to the drain electrode 175 through the contact holes 185a and 185b, respectively, and may receive a data voltage from the drain electrode 175 .

The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 of the upper panel 200 to determine the direction of liquid crystal molecules in the liquid crystal layer 3 between the two electrodes 191 and 270 . . The luminance of the light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules determined as described above.

The upper panel 200 includes an insulating substrate 210 and a common electrode 270 made of transparent glass or plastic.

Next, a structure of a thin film transistor substrate including a dummy pixel formed in a dummy region will be described with reference to FIGS. 3 and 5 .

Referring back to FIG. 3 , any of the dummy contact holes 186a, 186b, 186e, 186f, 186g, 186h of the dummy contact holes 186a, 186b, 186c, 186d, 186e, 186f, 186g, 186h, 186i, 186j. may be selected to be used as a bridge connection path for the storage electrode line 131 or a bridge connection path for a diode.

A cut surface of a dummy pixel including a first dummy contact hole 186g and a second dummy contact hole 186h among the dummy contact holes 186a, 186b, 186e, 186f, 186g, and 186h used as a bridge connection path is shown in FIG. 5 can be shown.

Referring to FIG. 5 , at least one dummy contact hole 186g and 186h is also formed in the dummy pixels 192g and 192h formed on the insulating substrate 110 in the dummy region. In this case, the at least one dummy contact hole 186g and 186h may be used as a bridge or a diode bridge of the storage electrode line 131 .

For example, in the case of the first dummy contact hole 186g , the linear semiconductor 154 , the linear ohmic contact member 164 , and the drain electrode 175 are disposed on the insulating substrate 110 at the position where the first dummy contact hole 186g is formed. ) are sequentially stacked data conductors. In addition, a gate line 123 is formed on the insulating substrate 110 at a position where the second dummy contact hole 186h is formed.

A dummy color filter 231 is formed on the insulating substrate, the gate line 123 , and the data conductor. The dummy color filter 231 may display one of primary colors, such as three primary colors of red, green, and blue.

A dummy pixel electrode 192 is formed on the gate line 123 and the drain electrode 175 exposed through the dummy color filter 231 and the dummy contact holes 186g and 186h.

Accordingly, the dummy contact holes 186g and 186h may serve as a bridge for the storage electrode line 131 formed outside the dummy region or may be used as a contact hole for diode connection.

Furthermore, the dummy contact hole according to an embodiment of the present invention may be used as a bridge contact hole for an OS (Open Short) pad.

6 and 7 are diagrams illustrating another example of a thin film transistor substrate including a dummy pixel according to an embodiment of the present invention.

Referring to FIG. 6 , one or more open short (OS) pads 193a and 193b may be disposed in some of the at least one dummy pixel 192a, 192b, 192c, 192d, 192e, and 192f. In this case, the dummy contact holes 186c, 186d, 186e, and 186f formed in the dummy pixels 192c, 192d, 192e, and 192f in which the OS pads 193a and 193b are disposed are connected to the contact hole bridges of the OS pads 193a and 193b, respectively. can be used as That is, the first OS pad 193a may be disposed under the first dummy pixels 192c and 192d using the dummy contact holes 186c and 186d of the first dummy pixels 192c and 192d as a bridge. Also, the second OS pad 193b may be disposed under the second dummy pixels 192e and 192f by using the dummy contact holes 186e and 186f of the second dummy pixels 192e and 192f as a bridge.

The form in which the OS pads 193a and 193b are disposed may be implemented such that one or more OS pads are disposed under different dummy pixels, as shown in FIG. 6 .

Alternatively, as shown in FIG. 7 , one or more OS pads 193a , 193b , and 193c may be disposed in one pixel 192c and 192d. In this case, the one or more dummy contact holes 186a , 186b , and 186c formed in one dummy pixel may be used as a bridge connection path of the OS pads 193a , 193b , and 193c, respectively, and when the bridge is connected, one dummy contact hole is available. That is, the first dummy pixel 192e, using the plurality of OS pads 193a , 193b , and 193c as a bridge by using each of the plurality of dummy contact holes 186d , 186e , and 186f formed in the first dummy pixels 192e and 192f as a bridge. 192f) may be disposed below the second dummy pixels 192c and 192d.

6 and 7 are provided to explain an embodiment in which OS pads are bridged using dummy contact holes, but the present invention is not limited thereto, and the OS pads may vary depending on the position and number of dummy contact holes formed in one pixel. Various forms of connection can be implemented.

Furthermore, referring to FIG. 3 , in the substrate on which the dummy pixel is formed, the region A for opening the light blocking member on the lower metal layer may be separately designed to enable UV irradiation.

Accordingly, the above detailed description should not be construed as restrictive in all respects but as exemplary. The scope of the present invention should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of the present invention are included in the scope of the present invention.

Q1, Q2: switching element (thin film transistor)
110, 210: substrate 121, 123: gate line
140: gate insulating film 154: semiconductor
163, 165: ohmic contact member 175: drain electrode
180p, 180q: protective film 185a, 185b: contact hole
186a to 186j: dummy contact holes
191a, 191b: display pixels 192a to 192j: dummy pixels
220: light blocking member 230: color filter

Claims (13)

an insulating substrate having a dummy area including dummy pixels and a display area including display pixels;
a signal line formed in the dummy region on the insulating substrate;
a switching element positioned on the display pixel on the insulating substrate;
a color filter layer positioned in the display area on the insulating substrate; and
a dummy color filter layer positioned in the dummy region on the insulating substrate;
the dummy pixel includes a first dummy contact hole and a second dummy contact hole formed in the dummy color filter layer;
the display pixel includes a first contact hole and a second contact hole formed in the color filter layer;
wherein the first dummy contact hole, the second dummy contact hole, the first contact hole, and the second contact hole are aligned in a line in a plan view.
thin film transistor substrate. According to claim 1,
The dummy area is
and a vertical dummy area positioned on the left and right of the display area;
The vertical dummy region includes a plurality of dummy pixels in which different dummy color filters are formed. 3. The method of claim 2,
The display pixel may further include a pixel electrode formed on the color filter layer and contacting a portion of the switching element through the first contact hole or the second contact hole. 4. The method of claim 3,
The display pixel is
an upper display panel facing the insulating substrate;
a liquid crystal layer positioned between the insulating substrate and the upper display panel; and
The thin film transistor substrate further comprising a common electrode positioned on the liquid crystal layer in the upper panel. 5. The method of claim 4,
The dummy pixel is
The thin film transistor substrate which does not include at least one of the switching element included in the display pixel, the pixel electrode, and the common electrode. 6. The method of claim 5,
and bridge-connecting a portion of the storage electrode line among the signal lines to the pixel electrode through the first dummy contact hole or the second dummy contact hole in the dummy region. 6. The method of claim 5,
An open short (OS) pad is positioned under the dummy color filter layer in the dummy area;
and bridge connection of the OS pad is performed using the first dummy contact hole or the second dummy contact hole. 8. The method of claim 7,
and the OS pad is bridge-connected through the first dummy contact hole or the second dummy contact hole formed in the dummy color filter layer of a first dummy pixel in which the OS pad is positioned. 8. The method of claim 7,
and the OS pad is bridge-connected through the first dummy contact hole or the second dummy contact hole formed in the dummy color filter layer of a second dummy pixel adjacent to the first dummy pixel in which the OS pad is located. . 10. The method of claim 9,
Two or more of the OS pads are located under the dummy color filter layer of the first dummy pixel according to the number of first dummy contact holes or the second dummy contact holes formed in the dummy color filter layer of the second dummy pixel. thin film transistor substrate. delete In claim 1,
a first conductor positioned in the dummy region on the insulating substrate; and
and a second conductor positioned in the dummy region on the insulating substrate and positioned in a layer different from the first conductor,
thin film transistor substrate. In claim 12,
Further comprising a dummy electrode positioned on the dummy color filter layer,
wherein the dummy electrode contacts the first conductor through the first dummy contact hole and contacts the second conductor through the second dummy contact hole.

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