KR102320950B1 - Pressure sensing memory transistor - Google Patents

Abstract

A pressure detection memory transistor according to this embodiment includes: a substrate, source and drain electrodes positioned on the substrate, a semiconductor layer positioned over the source and drain electrodes, and a ferroelectric layer positioned over the semiconductor layer and a gate structure disposed over the ferroelectric and deformed according to pressure, wherein the pressure detecting memory transistor detects and stores the applied pressure.

Description

PRESSURE SENSING MEMORY TRANSISTOR

The present technology relates to a pressure sensing memory transistor.

The tactile sensor according to the prior art stores tactile information by physically connecting two elements of the tactile sensor and the semiconductor memory in order to store the detected pressure.

Since the tactile sensor of the prior art combines the tactile sensor and the semiconductor memory as described above, it becomes an obstacle to use in wearable devices such as being mounted on the human body due to its large volume, and has disadvantages in that the manufacturing cost increases.

One of the problems to be solved by the present technology is to provide a tactile sensor capable of reducing the volume and manufacturing cost in order to solve the disadvantages of the tactile sensor of the prior art.

A pressure detection memory transistor according to this embodiment includes: a substrate, source and drain electrodes positioned on the substrate, a semiconductor layer positioned over the source and drain electrodes, and a ferroelectric layer positioned over the semiconductor layer and a gate structure disposed over the ferroelectric and deformed according to pressure, wherein the pressure detecting memory transistor detects and stores the applied pressure.

The pressure detection memory according to this embodiment includes: a substrate, source and drain electrodes positioned on the substrate, a semiconductor layer positioned over the source and drain electrodes, a ferroelectric layer positioned over the semiconductor layer, and and a gate structure disposed on the ferroelectric and deformed according to pressure, the pressure detection memory changes electrical resistance between the source electrode and the drain electrode according to the pressure applied to the gate structure, and the pressure detection memory is formed according to the pressure applied to the gate structure. electrical resistance is maintained.

The pressure detection memory transistor according to this embodiment functions as a non-volatile memory that stores a value corresponding to the applied pressure. Accordingly, an advantage is provided that miniaturization is possible and manufacturing cost is reduced.

1 is an exploded perspective view of a pressure detection memory transistor according to the present embodiment.
2(a) and 2(b) are plan views illustrating an embodiment of a source electrode and a drain electrode.
3 is a diagram illustrating an embodiment of a gate structure.
4A to 4C are diagrams for explaining that the pressure detection memory transistor detects and stores the pressure.
5 (a) and 5 (b) are diagrams for explaining the detection and storage of a pressure F2 greater than the pressure F1.
6(a) and 6(b) are diagrams schematically illustrating initialization of a pressure sensing element.
7 is a diagram illustrating changes in pressure, gate voltage, and drain current provided through a gate structure of a pressure detection memory transistor.
8 is a diagram illustrating a retention time of a value stored in a pressure detection memory transistor.
9 is a diagram illustrating a result of performing a reliability check.
FIG. 10(a) is a view showing the results of forming the present embodiment using a polyimide flexible substrate and performing a bending test.

Hereinafter, an outline of the pressure detection memory transistor according to the present embodiment will be described with reference to the accompanying drawings. 1 is an exploded perspective view of a pressure detection memory transistor 10 according to the present embodiment. Referring to FIG. 1 , the pressure detection memory transistor 10 according to the present embodiment includes a substrate sub, a source electrode 110 and a drain electrode 120 positioned on the substrate sub, and a source electrode 110 . ) and the drain electrode 120, the semiconductor layer 200 positioned on the upper part, the ferroelectric layer 300 positioned on the semiconductor layer 200, and the ferroelectric layer 300 positioned on the upper part and deformed according to the pressure The structure 400 includes the gate structure 400 and the contact area with the ferroelectric layer 300 increases as the applied pressure increases.

The substrate sub has insulation, and the components of the pressure detection memory transistor 10 according to the present embodiment are formed. In an embodiment, the substrate (sub) is a rigid substrate, and may be a silicon substrate, a silicon oxide film substrate, a glass substrate, and a synthetic resin substrate such as polycarbonate. As another example, the substrate (sub) is a flexible substrate, and may be a substrate having any one material of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyetherimide (PEI). can

The rigid substrate is suitable for implementing rigid devices such as, for example, a tactile sensor and a pressure sensor, and the flexible substrate is a wearable device such as a patch mounted on the human body and an electronic skin (e-skin). ) is suitable for implementing However, this is only an embodiment, and a wearable device may be implemented using a rigid substrate, and it is of course possible to implement a rigid device using a flexible substrate.

A source electrode 110 and a drain electrode 120 are positioned on a substrate sub. For example, the source electrode 110 and the drain electrode 120 have good conductivity such as gold, chrome, copper, aluminum, nickel, platinum, etc. It may be a metal material. As another example, the source electrode 110 and the drain electrode 120 may be formed of a conductive material such as ITO or PEDOT:PSS.

2A and 2B are plan views illustrating an embodiment of the source electrode 110 and the drain electrode 120 illustrated in FIG. 1 . Referring to FIGS. 1 and 2A , the source electrode 110 and the drain electrode 120 may each include a plurality of fingers f, and the plurality of fingers f are interdigitated with each other. is the form According to the illustrated embodiment, in the transistor forming the pressure detection memory transistor 10 according to the present embodiment, the channel width of the source electrode 110 and the drain electrode 120 is increased to increase the channel width of the source electrode 110 and the drain electrode. The amount of current flowing between the electrodes 120 may be increased. 2B is a plan view of another embodiment of the source electrode 110 and the drain electrode 120 . According to the illustrated embodiment, the source electrode 110 and the drain electrode 120 may be bar-shaped electrodes, and the size of the transistor may be reduced.

Referring back to FIG. 1 , the semiconductor layer 200 is formed on the source electrode 110 and the drain electrode 120 . The semiconductor layer 200 may be either a P-type semiconductor in which holes are a majority carrier or an N-type semiconductor in which electrons are majority carriers. The semiconductor layer 200 may be made of an existing semiconductor such as an organic semiconductor, an inorganic semiconductor, a silicon-based semiconductor, or a compound semiconductor as a main material.

In an embodiment, the semiconductor layer 200 may be formed by doping a silicon-based semiconductor or a compound semiconductor with an n-type dopant or a p-type dopant in an intrinsic semiconductor layer. In addition, the semiconductor layer 200 is a nitride semiconductor such as aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), an oxide semiconductor such as IGZO, HfZO, ITZO, MoS ₂ , WSe ₂ Two-dimensional material ( two dimensional material).

Organic semiconductors are p-type semiconductors such as P3HT (poly(3-hexylthiophene-2,5-diyl), P8BT (Poly(9,9-dioctylfluorene-alt-benzothiadiazole)), MEH-PPV (Poly[2-methoxy-5- (2-ethylhexyloxy)-1,4-phenylenevinylene]), PTAA (Poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]) may be an organic material.

The n-type organic semiconductor is P(NDI2OD-T2)(poly(N,N'-bis-2-octyldodecylnaphtalene-1,4,5,6-bis-dicarboximide-2,6-diyl-alt-5,52,2bitiophene) )), N2300 ((C ₅₄ H ₇₂ N _2O4 S ₂ )n), Poly(benzimidazobenzophenanthroline), Poly(2,5-di(3,7-dimethyloctyloxy)cyanooterephthalylidene), and the like. The organic semiconductor layer may be formed by using a method such as spin coating or dip coating to form the semiconductor layer 200 .

The organic semiconductor may be a small molecule semiconductor, for example, may be P-type pentacene, and may be deposited by evaporation.

A ferroelectric layer 300 is positioned on the semiconductor layer 200 . Ferroelectrics are materials that undergo spontaneous polarization even when no electric field is provided, and refer to materials whose direction of polarization can be switched by an external electric field. In the ferroelectric layer 300 , a dipole is formed by spontaneous polarization, and when a voltage greater than or equal to a coercive voltage is applied, the direction of the dipole is switched.

In one embodiment, the ferroelectric layer 300 may be P(VDF-TrFE) (poly(vinylidenefluoride-co-trifluoroethylene), PZT, BaTiO ₃ , PbTiO _{3 It} may be an inorganic material having ferroelectric properties such as PVDF, It may be an organic material having ferroelectric properties such as polytrifluoroethylene or odd-numbered nylon.

As the pressure applied from the upper portion of the gate structure 400 increases, the contact area with the ferroelectric layer 300 increases. In an embodiment, the gate structure 400 includes a gate elastic body 410 and a conductive material 420 (refer to FIG. 4 ) coating the gate elastic body 410 . In an embodiment, the gate voltage applied to the gate structure 400 may be applied to the conductive material 420 coating the gate elastic body 410 .

The gate elastic body 410 may be formed of a material having elasticity that is deformed when a pressure F is applied from the upper portion and is restored to an original state when the pressure F is removed. For example, the gate elastic body 410 may be formed of an elastic material such as PDMS or rubber. By finely adjusting the elastic modulus of the gate elastic body 410 , an input pressure detectable by the pressure detection memory transistor may be controlled.

The gate elastic body 410 may be coated with a conductive material 420 (refer to FIG. 4 ). For example, the conductive material may be a conductive polymer such as PEDOT:PSS, poly(thiophene)s (PT), poly(p-phenylene sulfide) (PPS), and polyanilines (PANI). As another example, the conductive material may be any one of a conductive metal thin film such as gold, copper, or aluminum.

3 is a diagram illustrating an embodiment of a gate structure 400 . The gate structure 400 may have a hemisphere shape as illustrated in FIG. 1 . As illustrated in FIG. 3(a), the gate structure 400a is a triangular pyramid or tetrahedron, and as illustrated in FIG. 3(b), the gate structure 400b is a quadrangular pyramid, FIG. 3(c) ), the gate structure 400c may have a pyramid shape such as a pentagonal pyramid. However, these are only examples, and it is sufficient that the gate structure 400 has a shape in which the contact area with the ferroelectric layer 300 located below increases when a pressure is applied. In the embodiment illustrated in FIGS. 3A to 3C , the gate structures 400a , 400b , and 400c may be coated with a conductive material 420 (see FIG. 4 ).

Hereinafter, the operation of the pressure detection memory transistor according to the present embodiment will be described with reference to FIGS. 4 to 6 . The illustrated example includes a hemisphere-shaped gate electrode 400, a P (VDF-TrFE) ferroelectric layer 300, a P-type polymer semiconductor P3HT, and a pressure detection memory transistor device formed of a silicon oxide substrate (sub). exemplify

4A to 4C are diagrams for explaining a process in which the pressure detection memory transistor detects a pressure. Referring to FIG. 4A , the ferroelectric layer 300 is spontaneously dielectric polarized to form dipoles. Even if no voltage is applied to the gate structure 400 , the direction of the dipoles is maintained by dielectric polarization regardless of the pressure applied to the gate electrode 400 . Since a channel is not formed in the semiconductor layer 200 , the source electrode 110 and the drain electrode 120 are electrically blocked.

4(b) shows a state in which a pressure F1 is applied in a state in which the gate structure 400 has a negative polarity and a gate voltage (Vg, Vg < -Vco) equal to or less than the coercive voltage (Vco) is provided. It is a diagram schematically showing. Referring to Fig. 4(b), a gate voltage Vg equal to or less than the coercive voltage of negative polarity and a pressure F1 are applied to the gate structure 400. As the pressure F1 is applied, the gate structure 400 is 400 is deformed to increase the contact area with the ferroelectric layer 300 .

The conductive material 420 coated on the gate structure 400 and the ferroelectric layer 300 come into contact with each other to provide a gate voltage Vg to the ferroelectric layer 300 . In the ferroelectric layer 300, the dipoles are switched by the provided gate voltage Vg to change the polarization direction (refer to the solid circle).

As the dipoles rotate and the polarization direction is changed, the same effect as that a negative voltage is applied to the semiconductor layer 200 occurs, and holes that are majority carriers are accumulated in the P-type semiconductor layer 200 therefrom (accumulated) to form a channel as shown by the broken line. Accordingly, the source electrode 110 and the drain electrode 120 are electrically connected.

The pressure detection memory transistor according to the present embodiment operates similarly even when an N-type semiconductor layer is used. When the gate structure 400 has a positive polarity and a pressure is applied in a state where a coercive voltage (Vg, Vg > +Vco) greater than or equal to the coercive voltage is applied, the gate structure 400 is coated with conductivity The material 420 and the ferroelectric layer 300 come into contact to provide a gate voltage Vg to the ferroelectric layer 300. The ferroelectric layer 300 is polarized by switching the dipoles by the provided gate voltage Vg. In this case, the − and poles of the dipole are positioned on the surface where the ferroelectric layer 300 contacts the gate structure 400 , and the dipole is positioned on the surface where the ferroelectric layer 300 contacts the semiconductor layer 200 . + pole is located.

As the polarization directions of the dipoles change, the same effect as when a positive voltage is applied to the semiconductor layer 200 occurs, and from this, electrons, which are majority carriers, are accumulated in the N-type semiconductor layer to form a channel. . Accordingly, the source electrode and the drain electrode are electrically connected.

Hereinafter, only an embodiment using the P-type semiconductor layer will be described for concise and clear explanation. However, these are merely examples and are not intended to limit the scope of the present invention.

FIG. 4C is a diagram schematically illustrating a pressure detection memory transistor in a state in which the gate structure 400 is removed or a voltage is not applied to the gate structure 400 . Referring to FIG. 4C , the dipole does not rotate again and the polarization direction is maintained even when the gate structure 400 is removed or a voltage is not provided due to the characteristics of the ferroelectric. Accordingly, in the semiconductor layer 200 , holes are accumulated by the dipole and the channel is maintained.

FIG. 5A is a diagram schematically illustrating a state of a pressure detecting element when a pressure F2 greater than a pressure F1 is applied to the gate structure 400 . Referring to FIG. 5A , when a pressure F2 greater than the pressure F1 is applied to the gate structure 400 , the contact area is larger than the contact area between the gate structure 400 and the ferroelectric layer 300 when the pressure F1 is applied. increases

When the pressure F2 is applied, the number of dipoles rotating in the ferroelectric layer 300 increases compared to when the pressure F1 is applied, and accordingly, the number of carriers accumulated in the semiconductor layer 200 also increases. Accordingly, the resistance of the channel formed between the source electrode 110 and the drain electrode 120 is reduced.

The pressure detection memory transistor according to the present embodiment has a feature of sensing a pressure and storing the sensing result as a resistance value of a channel. Accordingly, the source electrode 110 and the drain electrode when the pressure F2 is applied compared to the electrical resistance value between the source electrode 110 and the drain electrode 120 when the pressure F1 (see Fig. 4(b)) is applied. The electrical resistance value between (120) decreases.

Furthermore, since the dipoles in the ferroelectric layer 300 remain rotated even when the gate structure 400 is removed as shown in FIG. 5B , channels in which holes are accumulated are maintained in the semiconductor layer 200 . Accordingly, an electrical resistance value between the source electrode 110 and the drain electrode 120 corresponding to the given pressure F2 is maintained.

The pressure detecting element according to the present embodiment has the characteristics of a nonvolatile memory that detects the level of applied pressure and does not lose a written value even when power is removed. Unlike the prior art pressure detection device in which a sensor for detecting a pressure and a memory are electrically connected, the pressure detection memory transistor of this embodiment detects the level of the applied pressure and stores the detected value even when the power is removed. The advantage of being able to implement the characteristics of a single device is provided.

6A is a diagram schematically illustrating initialization of a pressure sensing element. Referring to FIG. 6A , in order to disperse carriers formed in all areas between the source electrode 110 and the drain electrode 120 , the entire area between the source electrode 110 and the drain electrode 120 may be covered. F3, which is a pressure greater than F, is provided.

In order to restore the dipoles back to their original state while providing the pressure F3, the gate structure 400 has a positive polarity and provides a gate voltage (Vg, Vg>Vco) equal to or greater than the coercive voltage (Vco). The polarities of the dipoles in the ferroelectric layer 300 are rotated so that - poles face the gate structure 400 , and the + poles of the dipoles contact the semiconductor layer 200 . Accordingly, the same effect as that a positive voltage is applied to the P-type semiconductor layer 200 is provided, so that the accumulated holes are dispersed into the semiconductor layer 200 and disappear. Since the holes forming the channel between the source electrode 110 and the drain electrode 120 disappear, the blocked state is maintained as in the initial state, and all values of the sensed pressure are erased.

Referring to FIG. 6( b ), even when the gate structure is removed or 0 V is applied to the gate voltage, the dipoles of the ferroelectric layer 300 maintain their previous state due to the characteristics of the ferroelectric, and from this, the carrier also in the semiconductor layer 200 . Since they do not accumulate, the initial state is maintained.

It can be seen that the pressure detection memory transistor according to the present embodiment detects and stores the pressure provided to the gate structure as described above, and functions as a memory capable of erasing the stored value if necessary.

From these characteristics, the pressure detecting memory transistor 10 according to the present embodiment includes a tactile sensor that can be mounted on the human body, a patch that can be mounted on the skin, and an electronic skin (e-skin) that can detect the sense of touch. It can be used as a wearable device of

evaluation

Hereinafter, an embodiment of the pressure detection memory transistor according to the present embodiment and an operation thereof will be described. The source electrode and the drain electrode are gold electrodes with a thickness of 30 nm, and were fabricated in the form of interdigitating each of four fingers. The semiconductor layer was formed of a P-type P3HT polymer semiconductor. A ferroelectric layer was formed of P (VDF-TrFE), the gate elastic body was formed of hemispherical PDMS, and a conductive polymer PEDOT: PSS was coated.

7 is a diagram illustrating changes in pressure, gate voltage, and drain current provided through a gate structure of a pressure detection memory transistor. In FIG. 7 , blue is 40 kPa, red is 20 kPa, green is 5 kPa, pink is 1 kPa, yellow is 0.5 kPa, purple is 0.1 kPa, and black is a state in which no pressure is applied. Referring to FIG. 7 , when the gate voltage (Vg < -Vco) having a negative polarity and less than the coercive voltage is provided, the amount of current flowing through the drain electrode and the source electrode increases as the pressure applied to the gate structure increases. can be checked

In addition, when a gate voltage (Vg>Vco) equal to or greater than the coercive voltage of the positive polarity is provided, the dipoles formed in the dielectric layer are switched. Accordingly, the majority carriers accumulated in the semiconductor layer are dispersed, the channel is deleted, and the drain electrode and the source electrode are blocked, and the amount of current flowing through the drain electrode and the source electrode is reduced.

8 is a diagram illustrating a retention time of a value stored in a pressure detection memory transistor. The pressure for each color in FIG. 8 is the same as in FIG. 7 . Referring to FIG. 8 , it shows that the value of the current flowing through the drain electrode and the source electrode is maintained up to approximately 20,000 seconds from the state in which the pressure of 40 kPa is applied to the state in which the pressure is not applied, which indicates that majority carriers are accumulated between the semiconductor layers. This results from the fact that the formed channel is maintained for at least 20,000 seconds. Accordingly, it can be confirmed that the pressure detection memory transistor according to the present embodiment functions as a memory for storing the detected pressure.

9 is a diagram illustrating a result of performing a reliability check. Reliability check provides a gate voltage of -60 V, which is below the coercive voltage of negative polarity, 0.5 kPa (purple), 1 kPa (orange), 1.5 kPa (pink), 10 kPa (green), 20 kPa (red), respectively. , 40 kPa (blue) pressure was applied to perform sensing, and +60 V, which is a voltage higher than the coercive voltage of positive polarity, was provided as a gate voltage, and a pressure of 40 kPa was provided to perform one cycle of erasing 50 times. was done by Referring to FIG. 9 , it can be seen that the detection, storage, and erasure processes are performed without deterioration even though the process of providing different pressures and erasing them is performed 50 times.

FIG. 10(a) is a view formed by laminating a source electrode and a drain electrode, a semiconductor layer, and a ferroelectric layer 300 on a polyimide flexible substrate, and is a photograph showing bending. 10( b ) shows a state in which 40 kPa (blue), 5 kPa (red), 0.1 kPa (green) and a pressure are applied when 0 V as a gate voltage and ??5 V as a drain-source voltage are provided in a bent state It is a diagram showing the result of detecting the current between the drain and the source in As shown, it can be seen that the memory characteristics are maintained in the flat state and even in the most sharply bent state with a radius of curvature of 5 mm.

Furthermore, referring to the graph showing the current variation with respect to the number of bending shown in FIG. 10( c ), it can be seen that the memory exhibits stable memory characteristics even when bending is performed 1000 times with a radius of curvature of 6 mm.

The pressure detection memory transistor according to the present embodiment has the advantage of detecting the magnitude of the applied pressure as well as the presence or absence of the pressure, and has the characteristic of a non-volatile memory for storing the detected pressure. Accordingly, an advantage of being suitable for implementing a wearable device such as a patch mounted on the skin of a human body or an electronic skin (e-skin) is provided.

Although it has been described with reference to the embodiment shown in the drawings in order to help the understanding of the present invention, this is an embodiment for implementation, it is merely an example, and those of ordinary skill in the art have various modifications and equivalents therefrom. It will be appreciated that other embodiments are possible. Accordingly, the true technical protection scope of the present invention should be defined by the appended claims.

110: source electrode 120: drain electrode
200: semiconductor layer 300: ferroelectric layer
400, 400a, 400b, 400c: gate structure 410: gate elastic body
420: conductive material

Claims (33)

A pressure detection memory transistor comprising:
Board;
a source electrode and a drain electrode positioned on the substrate;
a semiconductor layer disposed on the source electrode and the drain electrode;
a ferroelectric layer positioned on the semiconductor layer; and
and a gate structure that is positioned on the ferroelectric layer and deformed according to pressure,
The pressure detection memory transistor detects and stores the magnitude of the provided pressure,
The gate structure includes a conductive material coating a surface,
a voltage is provided through the conductive material such that polarization directions of dipoles formed in the ferroelectric layer corresponding to a contact area between the gate structure and the ferroelectric layer that are deformed according to the pressure are switched. delete According to claim 1,
The conductive material is
PEDOT: A pressure sensing memory transistor that is a conductive polymer material including any one of PSS, PT (poly(thiophene)s), PPS (poly(p-phenylene sulfide)), and PANI (polyanilines). According to claim 1,
The conductive material is
A pressure-sensitive memory transistor that is a thin film of conductive metal. According to claim 1,
The semiconductor layer is
A pressure sensing memory transistor comprising any one of a silicon-based semiconductor, a nitride semiconductor, an oxide semiconductor, a compound semiconductor, a two-dimensional material, and an organic semiconductor. 6. The method of claim 5,
The silicon-based semiconductor is a pressure detection memory transistor formed by doping a silicon intrinsic semiconductor with any one of an n-type dopant and a p-type dopant. 6. The method of claim 5,
The nitride semiconductor is
A pressure detection memory transistor comprising any one of aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). 6. The method of claim 5,
The oxide semiconductor is
A pressure detection memory transistor that is any one of GZO, HfZO, and ITZO. 6. The method of claim 5,
The two-dimensional material is
A pressure detection memory transistor of any one of MoS2 and WSe2. 6. The method of claim 5,
The organic semiconductor is
P3HT(poly(3-hexylthiophene-2,5-diyl), P8BT(Poly(9,9-dioctylfluorene-alt-benzothiadiazole)), MEH-PPV(Poly[2-methoxy-5-(2-ethylhexyloxy)-1 ,4-phenylenevinylene]), PTAA(Poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]), P(NDI2OD-T2)(poly(N,N'-bis-2-octyldodecylnaphtalene- 1,4,5,6-bis-dicarboximide-2,6-diyl-alt-5,52,2bithiophene)), N2300((C54H72N2O4S2)n), Poly(benzimidazobenzophenanthroline), Poly(2,5-di(3) ,7-dimethyloctyloxy)cyanoterephthalylidene) and pentacene (Pentacene), the pressure sensing memory transistor. According to claim 1,
The ferroelectric layer is
Pressure sensing memory transistors in any one of PVDF-TrFE, PZT, BaTiO3, PbTiO3, PVDF, polytrifluoroethylene, and odd-numbered nylon. According to claim 1,
The source electrode and the drain electrode are
each having a plurality of fingers,
wherein the fingers are interdigitated with each other. According to claim 1,
The gate structure is
A pressure detection memory transistor having any one of a hemisphere, a pyramid, and a polyhedron. According to claim 1,
The substrate is a flexible substrate, the pressure detection memory transistor. According to claim 1,
The gate structure is
A pressure detection memory transistor in which a contact area with the ferroelectric layer increases as the applied pressure increases. According to claim 1,
The pressure detection memory transistor is a pressure detection memory transistor included in the wearable device. a pressure detection memory, the pressure detection memory comprising:
Board;
a source electrode and a drain electrode positioned on the substrate;
a semiconductor layer disposed on the source electrode and the drain electrode;
a ferroelectric layer positioned on the semiconductor layer; and
and a gate structure positioned on the ferroelectric layer and deformed according to pressure,
In the pressure detection memory, the electrical resistance between the source electrode and the drain electrode changes according to the pressure applied to the gate structure,
The pressure detection memory maintains the electrical resistance formed according to the provided pressure,
The gate structure includes a conductive material coating a surface,
a voltage is provided through the conductive material such that polarization directions of dipoles formed in the ferroelectric layer corresponding to a contact area between the gate structure and the ferroelectric layer that are deformed according to the pressure are switched. 18. The method of claim 17,
The pressure sensitive transistor comprises:
Pressure detection memory that functions as non-volatile memory. delete 18. The method of claim 17,
The conductive material is
PEDOT: A pressure detection memory that is a conductive polymer material including any one of PSS, PT (poly(thiophene)s), PPS (poly(p-phenylene sulfide)), and PANI (polyanilines). 18. The method of claim 17,
The conductive material is
A pressure-sensitive memory that is a thin film of conductive metal. 18. The method of claim 17,
The semiconductor layer is
A pressure detection memory that is any one of a silicon-based semiconductor, a nitride semiconductor, an oxide semiconductor, a compound semiconductor, a two-dimensional material, and an organic semiconductor. 23. The method of claim 22,
The silicon-based semiconductor is a pressure detection memory formed by doping a silicon intrinsic semiconductor with any one of an n-type dopant and a p-type dopant. 23. The method of claim 22,
The nitride semiconductor is
A pressure detection memory made of any one of aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). 23. The method of claim 22,
The oxide semiconductor is
Pressure detection memory in any one of GZO, HfZO, and ITZO. 23. The method of claim 22,
The two-dimensional material is
MoS2 or WSe2 pressure detection memory. 23. The method of claim 22,
The organic semiconductor is
P3HT(poly(3-hexylthiophene-2,5-diyl), P8BT(Poly(9,9-dioctylfluorene-alt-benzothiadiazole)), MEH-PPV(Poly[2-methoxy-5-(2-ethylhexyloxy)-1 ,4-phenylenevinylene]), PTAA(Poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]), P(NDI2OD-T2)(poly(N,N'-bis-2-octyldodecylnaphtalene- 1,4,5,6-bis-dicarboximide-2,6-diyl-alt-5,52,2bithiophene)), N2300((C54H72N2O4S2)n), Poly(benzimidazobenzophenanthroline), Poly(2,5-di(3) ,7-dimethyloctyloxy)cyanoterephthalylidene) and pentacene (Pentacene), a pressure detection memory. 18. The method of claim 17,
The ferroelectric layer is
Pressure detection memory in any of PVDF-TrFE, PZT, BaTiO3, PbTiO3, PVDF, polytrifluoroethylene and odd-numbered nylon. 18. The method of claim 17,
The source electrode and the drain electrode are
each having a plurality of fingers,
wherein the fingers are interdigitated with each other. 18. The method of claim 17,
The gate structure is
A pressure detection memory having a shape of any one of a hemisphere, a pyramid, and a polyhedron. 18. The method of claim 17,
The pressure detection memory is
Pressure detection memory, which is non-volatile memory. 18. The method of claim 17,
wherein the substrate is a flexible substrate. 18. The method of claim 17,
The pressure detection memory is a pressure detection memory included in the wearable device.

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