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KR102305952B1 - Semiconductor device package based flip chip bonding - Google Patents

Semiconductor device package based flip chip bonding Download PDF

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KR102305952B1
KR102305952B1 KR1020200041126A KR20200041126A KR102305952B1 KR 102305952 B1 KR102305952 B1 KR 102305952B1 KR 1020200041126 A KR1020200041126 A KR 1020200041126A KR 20200041126 A KR20200041126 A KR 20200041126A KR 102305952 B1 KR102305952 B1 KR 102305952B1
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chip
bump
terminal
semiconductor device
device package
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한규진
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주식회사 코스텍시스
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Priority to PCT/KR2020/007876 priority patent/WO2021201336A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

플립 칩 본딩 기반 반도체 디바이스 패키지가 개시된다. 히트싱크는, 신호단자, 상면에 반도체 칩이 부착되는 패들, 및 패들 및 신호단자 사이를 절연시키는 절연체를 포함하고, 리드는, 몸체, 몸체로부터 돌출되어 형성되며 반도체 칩에 접착되기 위한 칩 범프, 칩 범프 보다 외측에서 몸체로부터 돌출되어 형성되며 신호단자에 접착되기 위한 터미널 범프, 및 몸체 내부에 실장되어 칩 범프 및 터미널 범프와 연결되는 인터커넥터를 포함할 수 있다.A flip chip bonding based semiconductor device package is disclosed. The heat sink includes a signal terminal, a paddle to which a semiconductor chip is attached to an upper surface, and an insulator insulating between the paddle and the signal terminal, and the lead includes a body, a chip bump formed to protrude from the body and adhered to the semiconductor chip; It may include a terminal bump that is formed to protrude from the body outside the chip bump and is attached to the signal terminal, and an interconnector that is mounted inside the body and is connected to the chip bump and the terminal bump.

Description

플립 칩 본딩 기반 반도체 디바이스 패키지{SEMICONDUCTOR DEVICE PACKAGE BASED FLIP CHIP BONDING}Flip-chip bonding-based semiconductor device package {SEMICONDUCTOR DEVICE PACKAGE BASED FLIP CHIP BONDING}

본 발명은 반도체 디바이스 패키지에 관한 것으로, 보다 상세하게는, 내부에 반도체 칩 실장되도록 패키징하는 플립 칩 본딩 기반 반도체 디바이스 패키지에 관한 것이다.The present invention relates to a semiconductor device package, and more particularly, to a flip-chip bonding-based semiconductor device package packaged so that a semiconductor chip is mounted therein.

반도체 디바이스는 기판이나 전자기기의 구성품으로서 필요한 위치에 장착되기 위해 그에 맞는 모양으로 전기적인 패키징이 이루어져야 한다. 패키징은 상호배선, 전력공급, 방열 그리고 반도체 디바이스 보호 등의 기능 및 역할을 한다. 이러한 패키징으로 세라믹 패키지 및 플랫 노리드(Flat No-leads) 패키징이 있다.A semiconductor device must be electrically packaged in a shape suitable for being mounted at a required position as a component of a substrate or electronic device. Packaging has functions and roles such as interconnection, power supply, heat dissipation, and protection of semiconductor devices. Such packaging includes ceramic packages and flat no-leads packaging.

세라믹 패키지는 플랜지, 리드(lead), 세라믹 절연부로 구성되며, 플랜지의 중앙에 반도체 디바이스가 실장될 공간부를 갖게 세라믹 절연부가 부착되며, 절연부 위에 리드(lead)가 부착되는 구조를 갖는다. 여기서, 플랜지는 히트싱크 등으로, 리드(lead)는 리드 프레임(lead frame) 등으로 명명되기도 한다.The ceramic package includes a flange, a lead, and a ceramic insulating part, and has a structure in which the ceramic insulating part is attached to have a space in which a semiconductor device is mounted in the center of the flange, and a lead is attached to the insulating part. Here, the flange may be referred to as a heat sink or the like, and the lead may be referred to as a lead frame or the like.

플랫 노리드(Flat No-leads) 패키지는 표면 실장을 위한 집적 핀들을 갖는 집적 회로 패키지의 한 유형을 의미하며, 듀얼-플랫 노리드(DFN: dual-flat no-leads) 및 쿼드-플랫 노리드(QFN: quad-flat no-leads)를 포함한다. 플랫 노리드는 종종 마이크로 리드프레임(micro lead frames)이라고 지칭되며 고방열 플라스틱 큐에프엔 패키지는 캡슐화된 IC 부품과 인쇄 회로 기판(PCB) 등의 외부 회로 사이에 물리적 및 전기적 연결을 제공한다.Flat no-leads package refers to a type of integrated circuit package that has integrated pins for surface mounting, dual-flat no-leads (DFN) and quad-flat no-leads. (QFN: quad-flat no-leads). Flat Norleads are often referred to as micro lead frames and high heat dissipation plastic QFN packages provide the physical and electrical connections between encapsulated IC components and external circuitry such as printed circuit boards (PCBs).

도 1은 종래의 와이어 본딩 방식의 반도체 디바이스 패키지를 도시한 사시도이고, 도 2는 종래의 와이어 본딩 방식의 반도체 디바이스 패키지를 도시한 단면도이다.1 is a perspective view illustrating a semiconductor device package of a conventional wire bonding method, and FIG. 2 is a cross-sectional view illustrating a semiconductor device package of a conventional wire bonding method.

도 1 및 도 2를 참조하면, 종래의 반도체 디바이스 패키지는 본딩 와이어(5)를 통해 신호단자(7)와 반도체 칩(20)의 전극이 연결되는 구조를 가지고 있었다. 또한, 종래의 반도체 디바이스 패키지는 반도체 칩(20)의 하부가 패들(6)과 연결되고 상부는 빈공간상에 위치하고 있어서, 하부 방향(B)에 의해 방열되는 특성을 가지고 있다.1 and 2 , a conventional semiconductor device package has a structure in which a signal terminal 7 and an electrode of a semiconductor chip 20 are connected through a bonding wire 5 . In addition, the conventional semiconductor device package has a characteristic that the lower portion of the semiconductor chip 20 is connected to the paddle 6 and the upper portion is located in an empty space, so that heat is dissipated in the lower direction (B).

도 3은 종래의 세라믹 패키지를 도시한 단면도이다.3 is a cross-sectional view illustrating a conventional ceramic package.

도 3을 참조하면, 본딩 와이어(5)는 도 3에 도시된 세라믹 패키지에서와 같이, 세라믹 패키지에서도 사용되고 있다. 여기서 도 2에 도시된 신호단자(7)는 세라믹 패키지의 리드(lead)(8)일 수 있고, 패들(6)은 세라믹 패키지의 플랜지(4)일 수 있다.Referring to FIG. 3 , the bonding wire 5 is used in a ceramic package as in the ceramic package shown in FIG. 3 . Here, the signal terminal 7 shown in FIG. 2 may be a lead 8 of a ceramic package, and the paddle 6 may be a flange 4 of the ceramic package.

도 4는 종래의 플랫 노리드 패키지를 도시한 단면도이다.4 is a cross-sectional view illustrating a conventional flat no-lead package.

도 4를 참조하면, 본딩 와이어(5)는 도 4에 도시된 플랫 노리드 패키지에서와 같이, 플랫 노리드 패키지에서도 사용되고 있다. 여기서, 도 2에 도시된 신호단자(7)은 플랫 노리드 패키지의 입출력터미널(I/O Terminal)(9)일 수 있다.Referring to FIG. 4 , the bonding wire 5 is used in a flat no lead package as in the flat no lead package shown in FIG. 4 . Here, the signal terminal 7 shown in FIG. 2 may be an input/output terminal 9 of a flat no-lead package.

본딩 와이어(5)는 와이어 사용 및 그 길이로 인해, 감쇠 및 경로 손실이 근본적으로 발생하고, 그로 인해 신호 손실(signal loss)이 발생할 수밖에 없는 문제점이 있다. 특히, 최대 동작 주파수가 20GHz 이상인 경우에는, 본딩 와이어 기반 반도체 디바이스 패키지는 RF 특성 손실이 3db 이상되어 Ka 밴드에 부적합한 문제점을 가지고 있다.The bonding wire 5 has a problem in that, due to the use of the wire and its length, attenuation and path loss are fundamentally generated, thereby inevitably causing signal loss. In particular, when the maximum operating frequency is 20 GHz or more, the bonding wire-based semiconductor device package has an RF characteristic loss of 3 db or more, which is unsuitable for the Ka band.

본 발명이 해결하고자 하는 과제는, 신호단자와 반도체 칩의 전극 사이의 접속 길이를 감소시켜 신호의 경로 손실을 줄이고, 신호단자와 반도체 칩의 전극 사이의 신호 전달시에 발생하는 감쇠를 없애, 최대 동작 주파수가 40KHz 이상에서도 RF 특성 손실이 없어 Ka 밴드에서 최적화된 고주파 전력 증폭기용으로 사용이 가능한 반도체 디바이스 패키지를 제공하는데 있다.The problem to be solved by the present invention is to reduce the signal path loss by reducing the connection length between the signal terminal and the electrode of the semiconductor chip, eliminate the attenuation that occurs during signal transmission between the signal terminal and the electrode of the semiconductor chip, It is to provide a semiconductor device package that can be used for a high frequency power amplifier optimized in the Ka band because there is no RF characteristic loss even at an operating frequency of 40KHz or higher.

본 발명이 해결하고자 하는 다른 과제는, 신호단자와 반도체 칩이 동일 평면에 위치할 수 있는 반도체 디바이스 패키지를 제공하는데 있다.Another object of the present invention is to provide a semiconductor device package in which a signal terminal and a semiconductor chip can be positioned on the same plane.

본 발명이 해결하고자 하는 또 다른 과제는, 방열성이 보다 우수한 반도체 디바이스 패키지를 제공하는데 있다.Another problem to be solved by the present invention is to provide a semiconductor device package having better heat dissipation properties.

본 발명이 해결하고자 하는 또 다른 과제는, 제조공정이 단순화되고 자동화가 가능하여 생산효율이 향상되고 생산비용을 절감될 수 있는 반도체 디바이스 패키지를 제공하는데 있다.Another object of the present invention is to provide a semiconductor device package capable of improving production efficiency and reducing production costs by simplifying and automating the manufacturing process.

상기 해결하고자 하는 과제를 달성하기 위한, 본 발명에 따른 반도체 디바이스 패키지는, 반도체 칩이 부착되는 히트싱크 및 상기 히트싱크의 상부를 덮는 리드(Lid)를 포함하는 반도체 디바이스 패키지에 있어서, 상기 히트싱크는, 신호단자, 상면에 상기 반도체 칩이 부착되는 패들, 및 상기 패들 및 상기 신호단자 사이를 절연체를 포함하고, 상기 리드는, 몸체, 상기 몸체로부터 돌출되어 형성되며 상기 반도체 칩에 접착되기 위한 칩 범프, 상기 칩 범프 보다 외측에서 상기 몸체로부터 돌출되어 형성되며 상기 신호단자에 접착되기 위한 터미널 범프, 및 상기 몸체 내부에 실장되어 상기 칩 범프 및 상기 터미널 범프와 연결되는 인터커넥터를 포함할 수 있다. 상기 칩 범프는, 전도성 접착제로 상기 반도체 칩의 전극에 접착될 수 있다. 상기 터미널 범프는, 전도성 접착제로 상기 신호단자에 접착될 수 있다.In order to achieve the above object, the semiconductor device package according to the present invention is a semiconductor device package comprising a heat sink to which a semiconductor chip is attached and a lid (Lid) covering an upper portion of the heat sink, the heat sink includes a signal terminal, a paddle to which the semiconductor chip is attached to an upper surface, and an insulator between the paddle and the signal terminal, wherein the lead is formed to protrude from the body and the chip is attached to the semiconductor chip It may include a bump, a terminal bump formed to protrude from the body outside the chip bump and to be adhered to the signal terminal, and an interconnector mounted inside the body to be connected to the chip bump and the terminal bump. The chip bump may be adhered to the electrode of the semiconductor chip with a conductive adhesive. The terminal bump may be adhered to the signal terminal with a conductive adhesive.

상기 리드는, 상기 몸체 경계에서 하부로 절곡되게 형성되어, 상기 몸체 및 상기 히트싱크 사이에 공간부를 형성하는 벽부를 더 포함할 수 있다. 상기 벽부는, 비전도성 접착제로 상기 신호단자 또는 상기 절연체에 접착되어, 상기 공간부를 밀폐할 수 있다.The lead may further include a wall portion formed to be bent downward at the body boundary and forming a space portion between the body and the heat sink. The wall portion may be attached to the signal terminal or the insulator with a non-conductive adhesive to seal the space portion.

상기 반도체 칩은, 상기 칩 범프, 상기 인터커넥터 및 상기 터미널 범프를 통해 상기 신호단자와 전기적으로 연결될 수 있다.The semiconductor chip may be electrically connected to the signal terminal through the chip bump, the interconnector, and the terminal bump.

상기 칩 범프, 상기 인터커넥터 및 상기 터미널 범프는 구리 소재로 형성될 수 있고, 상기 리드는 플라스틱 소재 또는 액정고분자로 형성될 수 있다.The chip bump, the interconnector, and the terminal bump may be formed of a copper material, and the lead may be formed of a plastic material or a liquid crystal polymer.

상기 신호단자 상부는, 상기 반도체 칩의 상부와 동일한 평면에 위치할 수 있다. 또한, 상기 신호단자의 높이는, 상기 패드 및 상기 반도체 칩의 높이의 합과 대응할 수 있다.An upper portion of the signal terminal may be positioned on the same plane as an upper portion of the semiconductor chip. In addition, the height of the signal terminal may correspond to the sum of the heights of the pad and the semiconductor chip.

상기 벽부, 상기 칩 범프 및 상기 터미널 범프는 서로 대응하는 높이를 가질 수 있다.The wall portion, the chip bump, and the terminal bump may have heights corresponding to each other.

신호단자는 세라믹 패키지의 리드(Lead) 또는 플랫 노리드 패키지의 입출력터미널(I/O Terminal)일 수 있다. 패들은 세라믹 패키지의 플랜지 또는 플랫 노리드 패키지의 패들일 수 있다.The signal terminal may be a lead of a ceramic package or an I/O terminal of a flat nor lead package. The paddle may be a flange of a ceramic package or a paddle of a flat norid package.

본 발명에 따른 반도체 디바이스 패키지에 의하면, 리드(Lid)를 통해 반도체 디바이스 패키지의 신호단자와 반도체 칩의 전극 사이가 연결됨으로써, 본딩 와이어를 이용하여 신호단자와 반도체 칩의 전극 사이를 연결하는 것보다 접속 경로를 감소시킬 수 있고, 본딩 와이어 보다 낮은 인덕턴스로 신호의 감쇠를 없앨 수 있으며, 경로 손실 및 감쇠가 없어짐에 따라 최대 동작 주파수가 40KHz 이상에서도 RF 특성 손실이 없어 Ka 밴드에서 최적화된 고주파 전력 증폭기용으로도 사용이 가능한 반도체 디바이스 패키지를 제공할 수 있고,According to the semiconductor device package according to the present invention, since the signal terminal of the semiconductor device package and the electrode of the semiconductor chip are connected through a lead, it is better than connecting between the signal terminal and the electrode of the semiconductor chip using a bonding wire. High frequency power amplifier optimized in Ka band because connection path can be reduced, signal attenuation can be eliminated with inductance lower than bonding wire It is possible to provide a semiconductor device package that can be used for

리드(Lid)가 히트싱크 및 반도체 칩에 동시에 결합됨으로써, 신호단자의 상부와 반도체 칩의 상부가 동일한 평면에 위치할 수 있으며,As the lead is coupled to the heat sink and the semiconductor chip at the same time, the upper part of the signal terminal and the upper part of the semiconductor chip may be positioned on the same plane,

반도체 칩이 히트싱크 뿐만 아니라 리드를 통해서도 방열될 수 있음으로써, 반도체 칩이 상하부로 방열이 가능하여 방열성이 보다 우수하고,Since the semiconductor chip can be dissipated not only through the heat sink but also through the lead, the semiconductor chip can dissipate heat from the top and bottom, so that the heat dissipation is better,

반도체 칩과 본딩 와이어 결합을 위한 별도의 공간을 마련할 필요가 없고 본딩 와이어 결합 공정이 별도로 요구되지 않음으로써, 제조공정이 단순화되고 자동화가 가능하여, 생산시간이 단축되며 생산효율이 향상되고 생산원가를 절감시킬 수 있는 효과가 있다.Since there is no need to prepare a separate space for bonding the semiconductor chip and the bonding wire, and the bonding wire bonding process is not required, the manufacturing process is simplified and automated, so the production time is shortened, the production efficiency is improved, and the production cost is not required. has the effect of reducing

도 1은 종래의 와이어 본딩 방식의 반도체 디바이스 패키지를 도시한 사시도이다.
도 2은 종래의 와이어 본딩 방식의 반도체 디바이스 패키지를 도시한 단면도이다.
도 3은 종래의 세라믹 패키지를 도시한 단면도이다.
도 4는 종래의 플랫 노리드 패키지를 도시한 단면도이다.
도 5는 본 발명에 따른 바람직한 일실시예의 리드(lid)를 도시한 단면도이다.
도 6은 본 발명에 따른 바람직한 일실시예의 히트싱크를 도시한 사시도이다.
도 7은 본 발명에 따른 바람직한 일실시예의 히트싱크를 도시한 단면도이다.
도 8은 본 발명에 따른 바람직한 일실시예의 반도체 디바이스 패키지를 도시한 단면도이다.
도 9는 본 발명에 따른 바람직한 일실시예의 반도체 디바이스 패키지의 방열 특성을 설명하기 위한 도면이다.1 is a perspective view illustrating a conventional wire bonding method of a semiconductor device package.
2 is a cross-sectional view illustrating a semiconductor device package of a conventional wire bonding method.
3 is a cross-sectional view illustrating a conventional ceramic package.
4 is a cross-sectional view illustrating a conventional flat no-lead package.
5 is a cross-sectional view showing a lid of a preferred embodiment according to the present invention.
6 is a perspective view showing a heat sink of a preferred embodiment according to the present invention.
7 is a cross-sectional view showing a heat sink of a preferred embodiment according to the present invention.
8 is a cross-sectional view illustrating a semiconductor device package according to a preferred embodiment of the present invention.
9 is a view for explaining the heat dissipation characteristics of a semiconductor device package according to a preferred embodiment of the present invention.

이하에서 첨부된 도면들을 참조하여 본 발명에 따른 플립 칩 본딩 기반 반도체 디바이스 패키지에 대해 상세하게 설명한다. 이때 도면에 도시되고 또 이것에 의해서 설명되는 본 발명의 구성과 작용은 적어도 하나의 실시예로서 설명되는 것이며, 이것에 의해서 본 발명의 기술적 사상과 그 핵심 구성 및 작용이 제한되지는 않는다.Hereinafter, a flip-chip bonding-based semiconductor device package according to the present invention will be described in detail with reference to the accompanying drawings. At this time, the configuration and operation of the present invention shown in the drawings and described by it is described as at least one embodiment, and the technical idea of the present invention and its core configuration and operation are not limited thereby.

본 발명에서 사용되는 용어는 본 발명에서의 기능을 고려하면서 가능한 현재 널리 사용되는 일반적인 용어를 선택하였으나, 이는 당해 기술분야에 종사하는 기술자의 의도 또는 관례 또는 새로운 기술의 출현 등에 따라 달라질 수 있다. 또한, 특정한 경우는 출원인이 임의로 선정한 용어도 있으며, 이 경우 해당되는 발명의 설명 부분에서 상세히 그 의미를 기재할 것이다. 따라서 본 발명에서 사용되는 용어는 단순한 용어의 명칭이 아닌 그 용어가 가지는 의미와 본 발명의 전반에 걸친 내용을 토대로 정의되어야 함을 밝혀 두고자 한다.The terms used in the present invention have been selected as currently widely used general terms as possible while considering the functions in the present invention, but these may vary depending on the intention or custom of a person skilled in the art or the advent of new technology. In addition, in a specific case, there is a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the corresponding invention. Therefore, it is intended to clarify that the terms used in the present invention should be defined based on the meaning of the term and the overall contents of the present invention, rather than the simple name of the term.

도 5는 본 발명에 따른 바람직한 일실시예의 리드(lid)를 도시한 단면도이다.5 is a cross-sectional view showing a lid of a preferred embodiment according to the present invention.

도 5를 참조하면, 본 발명에 따른 리드(200)는 몸체(210), 칩 범프(220 내지 220-4), 터미널 범프(230, 230-2), 인터커넥터(240 내지 240-4), 및 벽부(250)를 포함할 수 있다. 칩 범프(220), 터미널 범프(230) 및 인터커넥터(240)는 구리 소재로 형성될 수 있다. 그리고 몸체(210) 및 벽부(250)는 플라스틱 소재로 형성될 수 있고, 바람직하게는 액정고분자(LCP: Liquid Crystal Polymer)로 형성될 수 있다.5, the lead 200 according to the present invention includes a body 210, chip bumps 220 to 220-4, terminal bumps 230 and 230-2, interconnectors 240 to 240-4, and a wall part 250 . The chip bump 220 , the terminal bump 230 , and the interconnector 240 may be formed of a copper material. In addition, the body 210 and the wall part 250 may be formed of a plastic material, and preferably, may be formed of a liquid crystal polymer (LCP).

칩 범프(220)는 몸체(210)로부터 돌출되어 형성될 수 있고, 터미널 범프(230)보다 상대적으로 몸체(210)의 중심부 지점에 위치할 수 있다.The chip bump 220 may be formed to protrude from the body 210 , and may be located at a central point of the body 210 relative to the terminal bump 230 .

터미널 범프(230)는 몸체(210)로부터 돌출되어 형성될 수 있고, 칩 범프(220)보다 상대적으로 몸체(210)의 외곽 지점에 돌출되어 형성될 수 있다. The terminal bump 230 may be formed to protrude from the body 210 , and may be formed to protrude at an outer point of the body 210 relative to the chip bump 220 .

인터커넥터(240)는 몸체(210)에 실장되어 칩 범프(220) 및 터미널 범프(230)와 연결될 수 있다. 인터커넥터(240)는 몸체(210) 내부에 삽입되게 위치할 수 있고, 몸체(210) 상에 마이크로 스트립(Microstrip)으로 부착될 수 있다.The interconnector 240 may be mounted on the body 210 to be connected to the chip bump 220 and the terminal bump 230 . The interconnector 240 may be positioned to be inserted into the body 210 , and may be attached to the body 210 by a microstrip.

일부 실시예로, 칩 범프(220), 터미널 범프(230) 및 인터커넥터(240)는 단일한 구리 소재가 일체형으로 가공되어 형성될 수 있고, 일체형으로 몸체(210)에 부착될 수 있다.In some embodiments, the chip bump 220 , the terminal bump 230 , and the interconnector 240 may be formed by processing a single copper material integrally, and may be integrally attached to the body 210 .

일부 실시예로, 인터커넥터(240-4)에 하나의 칩 범프(220-4) 및 하나의 터미널 범프(230-2)과 연결될 수 있고, 칩 범프(220-4)는 터미널 범프(230-2) 보다 상대적으로 몸체(210)의 중심 지점에 위치할 수 있다.In some embodiments, one chip bump 220-4 and one terminal bump 230-2 may be connected to the interconnector 240-4, and the chip bump 220-4 may be connected to the terminal bump 230- 2) It may be relatively located at the center point of the body 210 .

벽부(250)는 몸체(210) 경계에서 하부로 절곡되게 형성될 수 있다. 벽부(250)는 칩 범프(220) 및 터미널 범프(230)와 서로 대응하는 높이를 가질 수 있다. 바람직하게, 벽부(250), 칩 범프(220) 및 터미널 범프(230)의 하부는 같은 평면상에 위치할 수 있다.The wall part 250 may be formed to be bent downward at the boundary of the body 210 . The wall part 250 may have a height corresponding to the chip bump 220 and the terminal bump 230 . Preferably, the lower portions of the wall portion 250 , the chip bump 220 , and the terminal bump 230 may be located on the same plane.

도 6은 본 발명에 따른 바람직한 일실시예의 히트싱크를 도시한 사시도이고, 도 7은 본 발명에 따른 바람직한 일실시예의 히트싱크를 도시한 단면도이다.6 is a perspective view illustrating a heat sink according to a preferred embodiment according to the present invention, and FIG. 7 is a cross-sectional view illustrating a heat sink according to a preferred embodiment according to the present invention.

도 6 및 도 7를 참조하면, 본 발명에 따른 히트싱크(100)는 패들(paddle)(110), 입출력터미널(I/O Terminal)(120, 120-2) 및 절연체(130)를 포함할 수 있다. 여기서, 절연체(130)는 플라스틱 소재 또는 액정고분자(LCP: Liquid Crystal Polymer)일 수 있다.6 and 7 , the heat sink 100 according to the present invention may include a paddle 110 , input/output terminals 120 and 120-2 and an insulator 130 . can Here, the insulator 130 may be a plastic material or a liquid crystal polymer (LCP).

패들(100)은 상면에 반도체 칩(20)이 부착될 수 있으며, 입출력터미널(120)에 의해, 패들(100) 상부에는 반도체 칩(20)이 실장되기 위한 공간부가 형성될 수 있다. 패들(100)은 금속 소재로 형성될 수 있다. 예를 들어, 패들(100)은 구리(Cu) 또는 구리(Cu) 복합소재로 형성될 수 있다. 여기서 구리(Cu) 복합소재는 sCMC, CMC, CPC, CuMO 및 CuW를 중 적어도 하나를 포함할 수 있다. 바람직하게 패들(100)은 무산소동 소재로 형성될 수 있다. 일부 실시예로, 패들(100)은 0.02mm 내지 1.5mm의 두께를 가질 수 있다. 바람직하게 패들(100)은 0.5mm 이상의 두께를 가질 수 있다.A semiconductor chip 20 may be attached to the upper surface of the paddle 100 , and a space for mounting the semiconductor chip 20 may be formed on the paddle 100 by the input/output terminal 120 . The paddle 100 may be formed of a metal material. For example, the paddle 100 may be formed of copper (Cu) or a copper (Cu) composite material. Here, the copper (Cu) composite material may include at least one of sCMC, CMC, CPC, CuMO, and CuW. Preferably, the paddle 100 may be formed of an oxygen-free copper material. In some embodiments, the paddle 100 may have a thickness of 0.02 mm to 1.5 mm. Preferably, the paddle 100 may have a thickness of 0.5 mm or more.

입출력터미널(120)은 패들(100)로부터 절연체(130)에 의해 절연되게 배치되며, 패들(100)과 함께 히트싱크(100)의 하면층을 형성할 수 있다. 입출력터미널(120)은, 패들(100)의 높이보다 높을 수 있고, 바람직하게 패들(100) 및 반도체 칩(20)의 합과 동일한 높이를 가질 수 있다. 입출력터미널(120)의 상부는 반도체 칩(20)의 상부와 같은 평면상에 위치할 수 있다.The input/output terminal 120 is disposed to be insulated from the paddle 100 by the insulator 130 , and may form a lower surface layer of the heat sink 100 together with the paddle 100 . The input/output terminal 120 may be higher than the height of the paddle 100 , and preferably may have a height equal to the sum of the paddle 100 and the semiconductor chip 20 . The upper portion of the input/output terminal 120 may be positioned on the same plane as the upper portion of the semiconductor chip 20 .

입출력터미널(120)은 패들(100)과 동일한 소재로 형성될 수 있고, 이에 따라 히트싱크(100)의 하면층이 금속으로만 형성될 수 있어, 열전도율이 높아, 본 발명에 따른 히트싱크(100)는 방열특성이 우수한 효과가 있다. 일예로, 입출력터미널(120)은 구리(Cu) 또는 구리(Cu) 복합소재로 형성될 수 있다. 바람직하게 입출력터미널(120)은 무산소동 소재로 형성될 수 있다.The input/output terminal 120 may be formed of the same material as the paddle 100 , and accordingly, the lower surface layer of the heat sink 100 may be formed of only metal, and thus the thermal conductivity is high, and the heat sink 100 according to the present invention ) has excellent heat dissipation properties. For example, the input/output terminal 120 may be formed of copper (Cu) or a copper (Cu) composite material. Preferably, the input/output terminal 120 may be formed of an oxygen-free copper material.

도 8은 본 발명에 따른 바람직한 일실시예의 반도체 디바이스 패키지를 도시한 단면도이다.8 is a cross-sectional view illustrating a semiconductor device package according to a preferred embodiment of the present invention.

도 8을 참조하면, 본 발명에 따른 반도체 디바이스 패키지(10)는 히트싱크(300) 및 리드(400)를 포함할 수 있다. 여기서 히트싱크(300) 및 리드(400)는 플립 칩 본딩(Flip Chip Bonding)으로 접합될 수 있다. 히트싱크(300) 및 리드(400)가 플립 칩 본딩(Flip Chip Bonding)으로 접합된다는 점에서, 본 발명에 따른 반도체 디바이스 패키지(10)는 플립 칩 본딩(Flip Chip Bonding) 기반 반도체 디바이스 패키지이며, 플립 칩 본딩(Flip Chip Bonding) 기반 반도체 디바이스 패키지는 히트싱크(300) 및 리드(400)가 플립 칩 본딩(Flip Chip Bonding)으로 접합되는 반도체 디바이스 패키지를 의미할 수 있다.Referring to FIG. 8 , the semiconductor device package 10 according to the present invention may include a heat sink 300 and a lead 400 . Here, the heat sink 300 and the lead 400 may be joined by flip chip bonding. In that the heat sink 300 and the lead 400 are joined by flip chip bonding, the semiconductor device package 10 according to the present invention is a flip chip bonding based semiconductor device package, The flip chip bonding-based semiconductor device package may refer to a semiconductor device package in which the heat sink 300 and the lead 400 are joined by flip chip bonding.

히트싱크(300)는 패들(paddle)(310), 신호단자(320, 320-2) 및 절연체(330)를 포함할 수 있다. 여기서, 절연체(330, 330-2)는 플라스틱 소재 또는 액정고분자(LCP: Liquid Crystal Polymer)일 수 있다.The heat sink 300 may include a paddle 310 , signal terminals 320 and 320 - 2 and an insulator 330 . Here, the insulators 330 and 330 - 2 may be made of a plastic material or liquid crystal polymer (LCP).

일부 실시예로, 히트싱크(400)는 도 7에 도시된 히트싱크(100)일 수 있다. 패들(310), 신호단자(320) 및 절연체(330)는 각각 도 7에 도시된 패들(110), 입출력터미널(120) 및 절연체(130)와 대응할 수 있다. In some embodiments, the heat sink 400 may be the heat sink 100 illustrated in FIG. 7 . The paddle 310 , the signal terminal 320 , and the insulator 330 may correspond to the paddle 110 , the input/output terminal 120 and the insulator 130 shown in FIG. 7 , respectively.

일부 실시예로, 히트싱크(400)는 도 3에 도시된 세라믹 패키지의 히트싱크일 수 있다. 이러한 경우에는, 신호단자(320)는 도 3에 도시된 세라믹 패키지의 리드(lead)(8)일 수 있고, 패들(310)은 도 3에 도시된 세라믹 패키지의 플랜지(4)일 수 있다. 여기서, 도 3에 도시된 바와 달리, 리드(320)의 상부는, 플랜지(310) 상면에 부착된 반도체 칩(20)의 상부와 동일한 평면에 위치하게 형성될 수 있다.In some embodiments, the heat sink 400 may be a heat sink of the ceramic package illustrated in FIG. 3 . In this case, the signal terminal 320 may be a lead 8 of the ceramic package shown in FIG. 3 , and the paddle 310 may be a flange 4 of the ceramic package shown in FIG. 3 . Here, unlike shown in FIG. 3 , the upper portion of the lead 320 may be formed to be positioned on the same plane as the upper portion of the semiconductor chip 20 attached to the upper surface of the flange 310 .

리드(400)는 몸체(410), 칩 범프(420), 터미널 범프(430), 인터커넥터(440), 및 벽부(450)를 포함할 수 있다. 리드(400)는 도 5에 도시된 리드(200)일 수 있다. 즉 몸체(410), 칩 범프(420), 터미널 범프(430), 인터커넥터(440), 및 벽부(450)는 각각 도 5에 도시된 몸체(210), 칩 범프(220), 터미널 범프(230), 인터커넥터(240), 및 벽부(250)와 대응할 수 있다.The lead 400 may include a body 410 , a chip bump 420 , a terminal bump 430 , an interconnector 440 , and a wall portion 450 . The lead 400 may be the lead 200 shown in FIG. 5 . That is, the body 410, the chip bump 420, the terminal bump 430, the interconnector 440, and the wall portion 450 are the body 210, the chip bump 220, the terminal bump shown in FIG. 5, respectively. 230 , the interconnector 240 , and the wall portion 250 may correspond to each other.

터미널 범프(430)는 신호단자(320)에 접착될 수 있다. 터미널 범프(430)는 전도성 접착제(105)로 신호단자(320)에 접착될 수 있다. The terminal bump 430 may be attached to the signal terminal 320 . The terminal bump 430 may be adhered to the signal terminal 320 with a conductive adhesive 105 .

칩 범프(420)는 반도체 칩(20)의 전극에 접착될 수 있다. 여기서, 칩 범프(420)는 전도성 접착제로 반도체 칩(20)의 전극에 접착될 수 있다. 일부 실시예로, 칩 범프(430)는 터미널 범프(420)와 동일한 전도성 접착제(105)로 반도체 칩(20)의 전극에 접착될 수 있다.The chip bump 420 may be adhered to the electrode of the semiconductor chip 20 . Here, the chip bump 420 may be adhered to the electrode of the semiconductor chip 20 with a conductive adhesive. In some embodiments, the chip bump 430 may be adhered to the electrode of the semiconductor chip 20 with the same conductive adhesive 105 as the terminal bump 420 .

벽부(450)는 몸체(410) 및 히트싱크(300) 사이에 공간부(103)을 형성할 수 있다. 또한 벽부(450)는 비전도성 접착제(107)로 신호단자(320) 또는 절연체(330)에 접착되어, 공간부(103)를 밀폐할 수 있다. The wall part 450 may form a space part 103 between the body 410 and the heat sink 300 . In addition, the wall portion 450 may be attached to the signal terminal 320 or the insulator 330 with a non-conductive adhesive 107 to seal the space portion 103 .

반도체 칩(20)은 칩 범프(420), 인터커넥터(440) 및 터미널 범프(430)를 통해 신호단자(320)와 전기적을 연결될 수 있다. 이에 따라, 본 발명에 따른 반도체 디바이스 패키지(10)는, 도 1 및 도 2에 도시된 바와 같이 본딩 와이어(5)를 이용하는 반도체 디바이스 패키지에 비해, 본딩 와이어(5)로 인한 감쇠가 없고 본딩 와이어(5)어 보다 더 짧은 길이로 반도체 칩(20)의 전극과 신호단자(320)와의 연결이 가능하여 접속 길이(Interconnection Length)를 감소시킬 수 있고, 본딩 와이어 보다 낮은 인덕턴스 및 감소된 접속 길이로 인해 경로 손실 및 감쇠를 없애 신호 손실을 감소시킬 수 있음으로써, 고주파 삽입손실이 -0.5db@28GHz로 절대량이 낮고(본딩 와이어(5)의 반도체 디바이스 패키지는 고주파 삽입손실이 -3db@28GHz로 절대량 높음), 최대 동작 주파수가 40KHz 이상에서도 RF 특성 손실이 없어 Ka 밴드에서 최적화된 고주파 대역 전력 증폭기용 반도체 디바이스 패키지를 저비용으로 제공할 수 있는 효과가 있다.The semiconductor chip 20 may be electrically connected to the signal terminal 320 through the chip bump 420 , the interconnector 440 , and the terminal bump 430 . Accordingly, the semiconductor device package 10 according to the present invention has no attenuation due to the bonding wire 5 and has no bonding wire compared to the semiconductor device package using the bonding wire 5 as shown in FIGS. 1 and 2 . (5) It is possible to connect the electrode of the semiconductor chip 20 and the signal terminal 320 with a shorter length than that, thereby reducing the interconnection length, and with a lower inductance and reduced connection length than the bonding wire. Because it is possible to reduce signal loss by eliminating path loss and attenuation, the high-frequency insertion loss is -0.5db@28GHz, which is a low absolute amount (the semiconductor device package of the bonding wire 5 has an absolute high-frequency insertion loss of -3db@28GHz) High), there is no RF characteristic loss even at a maximum operating frequency of 40KHz or higher, so it is possible to provide a semiconductor device package for a high frequency band power amplifier optimized in the Ka band at low cost.

또한, 본 발명에 따른 반도체 디바이스 패키지(10)는, 본딩 와이어(5)를 접착하는 공정이 요구되지 않음으로써, 리드(400)를 히트싱크(300)에 접촉하는 하나의 공정 작업으로 반도체 칩(20)과 신호단자(320)의 전기적 연결을 이룰 수 있어, 공정이 단순화되고 원 타임(one time) 공정이 가능하고, 이에 따라 제조 설비가 저렴해 지며 공정 자동화가가 가능함으로써, 생산성이 향상되고, 생산단가를 감소시켜 고효율 저비용의 반도체 디바이스 패키지를 제공할 수 있다.In addition, since the semiconductor device package 10 according to the present invention does not require a process for bonding the bonding wire 5, the semiconductor chip ( 20) and the signal terminal 320 can be electrically connected, so the process is simplified and a one-time process is possible. , it is possible to provide a high-efficiency and low-cost semiconductor device package by reducing the production cost.

도 9는 본 발명에 따른 바람직한 일실시예의 반도체 디바이스 패키지의 방열 특성을 설명하기 위한 도면이다.9 is a view for explaining the heat dissipation characteristics of a semiconductor device package according to a preferred embodiment of the present invention.

도 9를 참조하면, 본 발명에 따른 반도체 디바이스 패키지(10)는 반도체 칩(20)이 히트싱크(300) 및 리드(400)와 접촉되어 있어, 히트싱크(300) 뿐만 아니라 리드(400)를 통해서도 방열될 수 있음으로써, 반도체 칩(20)이 하부(B) 및 상부(T) 양방향으로 방열이 가능하여 방열성이 보다 우수한 효과가 있다.Referring to FIG. 9 , in the semiconductor device package 10 according to the present invention, the semiconductor chip 20 is in contact with the heat sink 300 and the lead 400 , so that not only the heat sink 300 but also the lead 400 are provided. By being able to dissipate heat through the semiconductor chip 20, heat dissipation is possible in both the lower (B) and upper (T) directions, so that the heat dissipation property is more excellent.

또한 리드(400)가 히트싱크(300) 및 반도체 칩(200)에 동시에 결합됨으로써, 신호단자(320)의 상부와 반도체 칩(20)의 상부가 동일한 평면에 위치할 수 있어, 접속 길이(Interconnection Lengh)를 감소시킬 수 있는 효과가 있다. In addition, since the lead 400 is simultaneously coupled to the heat sink 300 and the semiconductor chip 200 , the upper portion of the signal terminal 320 and the upper portion of the semiconductor chip 20 may be located on the same plane, so that the interconnection length (Interconnection) Lengh) can be reduced.

이상에서 본 발명의 바람직한 실시예에 대해 도시하고 설명하였으나, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변형 실시가 가능한 것은 물론이고, 그와 같은 변경은 청구범위 기재의 범위 내에 있게 된다.Although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific preferred embodiments described above, and in the technical field to which the present invention belongs, without departing from the gist of the present invention as claimed in the claims Any person skilled in the art can make various modifications, of course, and such modifications are within the scope of the claims.

반도체 디바이스 패키지 10
히트싱크 300
리드 400
Semiconductor device package 10
heatsink 300
lead 400

Claims (8)

반도체 칩이 부착되는 히트싱크 및 상기 히트싱크의 상부를 덮는 리드(Lid)를 포함하는 반도체 디바이스 패키지에 있어서,
상기 히트싱크는,
신호단자, 상면에 상기 반도체 칩이 부착되는 패들, 및 상기 패들 및 상기 신호단자 사이를 절연시키는 절연체를 포함하고,
상기 리드는,
몸체, 상기 몸체로부터 돌출되어 형성되며 상기 반도체 칩에 접착되기 위한 칩 범프, 상기 칩 범프 보다 외측에서 상기 몸체로부터 돌출되어 형성되며 상기 신호단자에 접착되기 위한 터미널 범프, 및 상기 몸체 내부에 실장되어 상기 칩 범프 및 상기 터미널 범프와 연결되는 인터커넥터를 포함하고,
상기 리드는 상기 히트싱크의 상부를 덮어 밀폐된 공간을 형성하고, 상기 반도체 칩은 상기 공간 내부에 위치하는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.A semiconductor device package comprising: a heat sink to which a semiconductor chip is attached; and a lid (Lid) covering an upper portion of the heat sink,
The heat sink is
a signal terminal, a paddle to which the semiconductor chip is attached to an upper surface, and an insulator insulating between the paddle and the signal terminal;
The lead is
a body, a chip bump formed to protrude from the body and adhered to the semiconductor chip, a terminal bump formed to protrude from the body outside the chip bump and adhered to the signal terminal, and a terminal bump mounted inside the body a chip bump and an interconnect connected to the terminal bump;
The lid covers an upper portion of the heat sink to form a sealed space, and the semiconductor chip is positioned inside the space. 제 1항에 있어서,
상기 칩 범프 또는 상기 터미널 범프는,
전도성 접착제로 상기 반도체 칩의 전극에 접착되는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.The method of claim 1,
The chip bump or the terminal bump,
A flip-chip bonding-based semiconductor device package, characterized in that it is adhered to the electrode of the semiconductor chip with a conductive adhesive. 제 1항 또는 제 2항에 있어서,
상기 리드는,
상기 몸체 경계에서 하부로 절곡되게 형성되어, 상기 몸체 및 상기 히트싱크 사이에 공간부를 형성하는 벽부를 더 포함하고,
상기 벽부는,
비전도성 접착제로 상기 신호단자 또는 상기 절연체에 접착되어, 상기 공간부를 밀폐하는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.3. The method of claim 1 or 2,
The lead is
It is formed to be bent downward at the boundary of the body, further comprising a wall portion forming a space between the body and the heat sink,
The wall part,
A flip-chip bonding-based semiconductor device package, characterized in that it is adhered to the signal terminal or the insulator with a non-conductive adhesive to seal the space. 제 1항에 있어서,
상기 반도체 칩은,
상기 칩 범프, 상기 인터커넥터 및 상기 터미널 범프를 통해 상기 신호단자와 전기적을 연결되는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.The method of claim 1,
The semiconductor chip is
The flip chip bonding-based semiconductor device package of claim 1, wherein the chip bump, the interconnector, and the terminal bump are electrically connected to the signal terminal. 제 1항에 있어서,
상기 칩 범프, 상기 인터커넥터 및 상기 터미널 범프는 구리 소재로 형성되는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.The method of claim 1,
The flip chip bonding-based semiconductor device package, wherein the chip bump, the interconnector, and the terminal bump are formed of a copper material. 제 1항에 있어서,
상기 신호단자는,
리드(Lead) 또는 입출력터미널(I/O Terminal)인 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.The method of claim 1,
The signal terminal is
A flip-chip bonding-based semiconductor device package, characterized in that it is a lead or an input/output terminal (I/O terminal). 제 1항 또는 제 2항에 있어서,
상기 신호단자 상부는,
상기 반도체 칩의 상부와 동일한 평면에 위치하는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.3. The method of claim 1 or 2,
The upper part of the signal terminal,
A flip-chip bonding-based semiconductor device package, characterized in that it is positioned on the same plane as an upper portion of the semiconductor chip. 제 3항에 있어서,
상기 벽부, 상기 칩 범프 및 상기 터미널 범프는 서로 대응하는 높이를 갖는 것을 특징으로 하는 플립 칩 본딩 기반 반도체 디바이스 패키지.
4. The method of claim 3,
The flip-chip bonding-based semiconductor device package, wherein the wall portion, the chip bump, and the terminal bump have heights corresponding to each other.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068329A (en) * 1998-08-24 2000-03-03 Mitsubishi Electric Corp Semiconductor integrated device
KR20020001211A (en) * 2000-06-27 2002-01-09 윤종용 Printed circuit board having semiconductor chip package located in window
KR20040036270A (en) * 2002-10-24 2004-04-30 엘지이노텍 주식회사 Semiconductor device package and method for manufacturing semiconductor device packaging
KR20100070292A (en) * 2008-12-17 2010-06-25 페어차일드 세미컨덕터 코포레이션 Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same
US20160300874A1 (en) * 2012-07-11 2016-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for CIS Flip-Chip Bonding and Methods for Forming the Same
KR20200005882A (en) * 2018-07-09 2020-01-17 주식회사 코스텍시스 Seiconductor device package having humidity barrier function

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI225693B (en) * 2003-04-23 2004-12-21 Advanced Semiconductor Eng Multi-chips package
US8653635B2 (en) * 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
US8581416B2 (en) * 2011-12-15 2013-11-12 Semiconductor Components Industries, Llc Method of forming a semiconductor device and leadframe therefor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068329A (en) * 1998-08-24 2000-03-03 Mitsubishi Electric Corp Semiconductor integrated device
KR20020001211A (en) * 2000-06-27 2002-01-09 윤종용 Printed circuit board having semiconductor chip package located in window
KR20040036270A (en) * 2002-10-24 2004-04-30 엘지이노텍 주식회사 Semiconductor device package and method for manufacturing semiconductor device packaging
KR20100070292A (en) * 2008-12-17 2010-06-25 페어차일드 세미컨덕터 코포레이션 Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same
US20160300874A1 (en) * 2012-07-11 2016-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure for CIS Flip-Chip Bonding and Methods for Forming the Same
KR20200005882A (en) * 2018-07-09 2020-01-17 주식회사 코스텍시스 Seiconductor device package having humidity barrier function

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