KR102289927B1 - Pixel driving circuit having less contacting point - Google Patents

Abstract

Disclosed is a pixel driving circuit with less external contacts. A conventional digital driving pixel required two contacts (Vcc, GND) related to power, a contact (row signal, column signal) for inputting two signals for digital driving, a contact (Mode selection) for inputting a set value required for driving pixels, and a contact (reset) for maintaining video data for one frame to implement a cycle function during PWM operation, and inputting a reset signal to delete previous video data before inputting new video data. However, as the number of contacts increases, the efficiency of transfer (pick & place) decreases in a manufacturing process. Accordingly, according to the present specification, the pixel driving circuit can be digitally operated through a combination of a row signal and a column signal even when the number of contacts is reduced. The pixel driving circuit comprises: a setting register unit; a first switching unit for outputting a signal, input from a first low-frequency filter, to the setting register unit or a pixel internal memory unit; and a second switching unit for outputting a signal, input from a signal sensing unit, to the setting register unit or the pixel internal memory unit.

Description

Pixel driving circuit with reduced number of contacts {PIXEL DRIVING CIRCUIT HAVING LESS CONTACTING POINT}

The present invention relates to a display device, and more particularly, to an operation of a pixel driving circuit having a reduced number of contacts compared to the prior art.

The content described in this section merely provides background information for the embodiments described herein and does not necessarily constitute prior art.

Various types of display devices, such as a liquid crystal display device, a plasma display device, and an organic light emitting display device, are being used. Recently, a display device used in a smart watch or VR (Virtual Reality), AR (Augmented Reality), MR (Mixed Reality) device is small and high resolution is required, a display using a micro light emitting diode (μLED) Interest in the device is growing. In addition, micro LEDs are being commercialized in large display devices.

On the other hand, when a large display device using a micro LED is driven in a passive matrix method, a large amount of power is required, which is not suitable as a driving method of a next-generation display device. Accordingly, an active matrix method with a relatively low power consumption is more suitable for a next-generation display device.

1 is a circuit diagram schematically illustrating the structure of a general pixel.

Referring to FIG. 1 , a pixel 10 including three light emitting devices R, G, and B and a pixel driving circuit 11 for driving the light emitting devices can be seen. Pixels driven by an active matrix method are generally digitally driven using PWM (Pulse Width Modulation) technology. Accordingly, in the pixel 10, two contacts (Vcc, GND) related to power required for driving the pixel and a contact (Row signal, column signal) for inputting two signals for digital driving are essential. Additionally, video data is maintained for one frame to implement the cycle function during PWM driving and mode selection for inputting a set value required for driving a pixel, and before inputting new video data. In order to clear previous video data, a contact point (Reset) for inputting a reset signal is required.

Meanwhile, in order to manufacture an active matrix type display device, a method using a conventional TFT backplane and a method of configuring a pixel driving circuit on a semiconductor wafer and attaching a micro LED are possible. In particular, when configuring a pixel driving circuit on a semiconductor wafer, it is necessary to minimize the number of contacts required to improve the efficiency of pick & place. However, as shown in FIG. 1 , a plurality of contacts increases the difficulty in the pick & place process due to an increase in the number of pins, causes a problem of increasing the size of the pixel driving circuit, and reduces price competitiveness.

Republic of Korea Patent Publication No. 10-2017-0111788

An object of the present specification is to provide a pixel driving circuit in which the number of external contacts is reduced.

The present specification is not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A pixel driving circuit according to the present specification for solving the above problems includes: a setting register unit having a plurality of memory cells for storing a setting value related to driving a pixel; a pixel-embedded memory unit having a plurality of memory cells for storing video data; a signal sensing unit having a row signal input terminal and a column signal input terminal; a first low-frequency filter for outputting a signal having a frequency lower than a preset first cut-off frequency for the signal input from the signal detecting unit; a second low-frequency filter for outputting a signal having a frequency lower than a preset second cut-off frequency from the signal inputted from the signal sensing unit to the pixel embedded memory unit; a first switching unit outputting the signal input from the first low frequency filter to the setting register unit or the pixel embedded memory unit; and a second switching unit for outputting the signal input from the signal sensing unit to the setting register unit or the pixel embedded memory unit.

The setting register unit according to an embodiment of the present specification may include: a plurality of setting data memory cells for storing setting values related to driving of pixels; and one flag memory cell for storing the mode value.

The setting register unit according to an embodiment of the present specification may output the mode value stored in the flag memory cell to the first switching unit and the second switching unit. At this time, the first switching unit outputs the signal input from the first low-frequency filter to the setting register unit when the mode value is the first mode, and from the first low-frequency filter when the mode value is the second mode. The input signal may be output to the pixel embedded memory unit. In addition, the second switching unit outputs the signal input from the signal sensing unit to the setting register unit when the mode value is the first mode, and receives the signal input from the signal sensing unit when the mode value is the second mode output to the pixel-embedded memory unit.

According to one embodiment of the present specification, the signal output from the first switching unit is input to the data terminal of the setting register unit and the data terminal of the pixel embedded memory unit, and the signal output from the second switching unit is the setting register It may be input to a negative clock terminal and a clock terminal of the pixel embedded memory unit.

The pixel embedded memory unit according to an embodiment of the present specification may include: a plurality of video data memory cells for storing video data; and one flag memory cell for storing the mode flag.

The pixel embedded memory unit according to an embodiment of the present specification may output the mode value stored in the flag memory cell to the signal sensing unit. In this case, the signal detector may output the column signal when the mode value is the third mode, and output the row signal when the mode value is the fourth mode.

According to an exemplary embodiment of the present specification, the signal output from the second low frequency filter may be input to a reset terminal for deleting data stored in the pixel embedded memory unit.

According to an embodiment of the present specification, an initial driving signal may be input to a reset terminal for deleting data stored in the setting register unit.

The pixel embedded memory unit according to an embodiment of the present specification may further include a plurality of PWM termination memory cells for terminating PWM driving of each light emitting device.

According to an embodiment of the present specification, each PWM termination memory cell may be located adjacent to the least significant bit (LSB) of video data of each light emitting device.

A pixel driving circuit according to the present specification includes: a pixel driving circuit; and a plurality of light emitting devices.

A pixel circuit according to the present specification includes: a display panel in which a plurality of pixel circuits are arranged; a scan driving circuit for outputting a row signal through a plurality of scan lines connected to row signal input terminals of pixel circuits arranged in a row direction; and a data driving circuit for outputting column signals through a plurality of data lines connected to column signal input terminals of pixel circuits arranged in a column direction.

According to an embodiment of the present specification, the raw signal may include a first scan signal for inputting a set value related to pixel driving, a second scan signal for inputting video data, and a clock signal for PWM driving.

The scan driving circuit according to an embodiment of the present specification outputs a first scan signal first for each scan line once after an initial driving signal is generated, and is associated with each frame to provide the second scan signal and the clock signal A low signal including repeatedly may be output.

The scan driving circuit according to an embodiment of the present specification may output a low signal in which M clock signals are repeated for each second scan signal according to an M-cycling operation mode.

According to an embodiment of the present specification, the column signal may include a set value data signal related to driving a pixel, a video data reset signal having a length exceeding a preset reference time, and a video data signal related to a plurality of light emitting devices. have.

The data driving circuit according to an embodiment of the present specification outputs the set value data signal once for each data line after an initial driving signal is generated, and is associated with each frame to include the video data reset signal and the It is possible to output a column signal repeatedly including a video data signal.

According to an embodiment of the present specification, the most significant bit (MSB) of the set value data signal may be a mode value, and the remaining bits may be a set value.

According to an embodiment of the present specification, the most significant bit (MSB) of the video data signal may be a mode value, and the remaining bits may be video data values related to grayscales of a plurality of light emitting devices.

According to an embodiment of the present specification, the video data value is a signal having a frequency lower than the cut-off frequency of the first low-frequency filter and a signal having a frequency higher than the cut-off frequency of the first low-frequency filter within the preset reference time. may include.

Other specific details of the invention are included in the detailed description and drawings.

According to one aspect of the present specification, since the number of external contacts of the pixel driving circuit is reduced, the efficiency of a process of constructing the pixel driving circuit on a semiconductor wafer and transferring (Pick & Place) may be improved.

According to another aspect of the present specification, as the number of external pixels of the pixel driving circuit is gradually reduced, the difficulty of the transfer process is lowered, and the size of the pixel driving circuit is reduced, thereby improving price competitiveness.

Effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

1 is a circuit diagram schematically illustrating the structure of a general pixel.
2 is a block diagram schematically illustrating a configuration of a display device according to the present specification.
3 is a block diagram schematically illustrating the configuration of a pixel driving circuit according to the present specification.
4 is a block diagram schematically illustrating a configuration of a setting register unit according to an embodiment of the present specification.
5 is a block diagram schematically illustrating the configuration of a pixel embedded memory unit ( ) according to an embodiment of the present specification.
6 is a timing reference diagram of a row signal and a column signal according to the present specification.
7 is an operation reference diagram in mode 1.
8 is a reference diagram for operation in mode 2;
9 is a reference diagram for operation in mode 3;
10 is a reference diagram for operation in mode 4.
11 is a reference diagram for an operation sequence of Modes 1 to 4 according to the present specification.
12 is a reference diagram of video data and a video data reset signal according to an embodiment of the present specification.
13 is a reference diagram in which a memory cell according to the present specification stores data '1' and '0'.
14 is a reference diagram of a PWM terminated memory cell according to the present specification.
15 is a reference diagram for a cycling operation.

Advantages and features of the invention disclosed herein, and methods for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments allow the disclosure of the present specification to be complete, and those of ordinary skill in the art to which this specification belongs. It is provided to fully inform those skilled in the art (hereinafter 'those skilled in the art') the scope of the present specification, and the scope of the present specification is only defined by the scope of the claims.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the scope of the present specification. As used herein, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and/or “comprising” does not exclude the presence or addition of one or more other components in addition to the stated components.

Like reference numerals refer to like elements throughout, and "and/or" includes each and every combination of one or more of the recited elements. Although "first", "second", etc. are used to describe various elements, these elements are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first component mentioned below may be the second component within the spirit of the present invention.

This specification describes embodiments using elements of logic circuits and electronic circuits. For convenience of understanding, data '1' corresponds to logic high and '0' corresponds to logic low. However, the reverse case is also possible, and embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a configuration of a display device according to the present specification.

Referring to FIG. 2 , the display apparatus 100 according to the present specification may include a display panel 110 , a scan driving circuit 120 , a data driving circuit 130 , and a controller 140 .

The display panel 110 may include a plurality of pixel circuits (pixels, PX) according to the present specification. The plurality of pixel circuits PX may be arranged in a matrix form m X n (m, n is a natural number). However, the pattern in which the plurality of pixels are arranged may be arranged in various patterns according to embodiments, such as a zigzag type.

The display panel 110 is a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), It may be implemented as one of AMD (Actuated Mirror Device), GLV (Grating Light Valve), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), and other types of flat panel displays or flexible displays It may be implemented as a display. In this specification, the LED display panel will be described as an example.

Each pixel circuit PX may include a plurality of light emitting devices. The light emitting device may be a light emitting diode (LED). The light emitting diode may be a micro LED having a size of 80 μm or less. One pixel circuit PX may output various colors through a plurality of light emitting devices having different colors. For example, one pixel circuit PX may include a light emitting device composed of red, green, and blue colors. As another example, if a white light emitting device may be further included, the white light emitting device may replace any one of the red, green, and blue light emitting devices. Each light emitting element included in one pixel circuit PX is called a 'sub pixel'.

Each pixel circuit PX may include a pixel driving circuit for driving a plurality of sub-pixels. The pixel driving circuit turns on or turns off the sub-pixels according to a row signal output from the scan driving circuit 120 and/or a column signal control signal output from the data driving circuit 130 . action can be driven. The pixel driving circuit may include at least one thin film transistor and at least one capacitor. The pixel driving circuit may be implemented by a stacked structure on a semiconductor wafer.

The display panel 110 may include scan lines SL ₁ to SL _m arranged in a row direction and data lines DL ₁ to DL _n arranged in a column direction. Pixel circuits PX may be positioned at intersections of the scan lines SL ₁ to SL _m and the data lines DL ₁ to DL _{n .} Each pixel circuit PX may be connected to any one scan line SL _k and any one data line DL _{k .} The scan lines SL ₁ to SL _m may be connected to the scan driving circuit 120 , and the data lines DL ₁ to DL _n may be connected to the data driving circuit 130 .

The scan driving circuit 120 may output a row signal through _{a plurality of scan lines SL 1} to SL _m connected to the row signal input terminals of the pixel circuits arranged in the row direction. have. Preferably, the scan driving circuit 120 may sequentially output a low signal to _{the scan lines SL 1} to SL _{m .} For example, pixels connected to the first scan line SL ₁ may be driven during the first scan driving period, and pixels connected to the second scan line SL ₂ may be driven during the second scan driving period. The operation of the scan driving circuit 120 according to the present specification will be described in more detail later.

The data driving circuit 130 may output a column signal through a plurality of data lines DL ₁ to DL _{n connected to column signal input terminals of pixel circuits arranged in a column direction.} have. The column signal includes data related to gradation for each pixel circuit. Although one data line is connected to a plurality of pixel circuits in the longitudinal direction, the column signal may be input only to the pixel circuit connected to the scan line selected by the scan driving circuit 120 . The operation of the data driving circuit 130 according to the present specification will be described in more detail later.

The control unit 140 may output a control signal to execute the operations of the scan driving circuit 120 and the data driving circuit 130 . The controller 140 may output a control signal corresponding to image data corresponding to one image frame to the scan driving circuit 120 and the data driving circuit 130 , respectively.

3 is a block diagram schematically illustrating the configuration of a pixel driving circuit according to the present specification.

Referring to FIG. 3 , the pixel driving circuit 200 according to the present specification includes a signal sensing unit 210 , a first low frequency filter 220 , a second low frequency filter 230 , a first switching unit 240 , and a second It may include a switching unit 250 , a setting register unit 260 , and a pixel embedded memory unit 270 .

The signal detection unit 210 receives a row signal input terminal to which a row signal output from the scan driving circuit 120 is input and a column signal output from the data driving circuit 130 is input. It may have a column signal input terminal that is A row signal or a column signal input to the signal detection unit 210 is output to the first low frequency filter 220 , the second low frequency filter 230 , and the second switching unit 250 . can be Which one of a row signal or a column signal input to the signal sensing unit 210 is output may vary depending on an operation mode. In order to control the signal output according to the operation mode, the signal sensing unit 210 may be configured using a logic circuit element and a multiplexer, as shown in FIG. 3 .

The first low-frequency filter 220 outputs a signal having a frequency lower than a preset first cut-off frequency in the signal input from the signal detecting unit 210 to the first switching unit 240 (Low Pass). filter).

The second low-frequency filter 230 outputs a signal having a lower frequency than a preset second cut-off frequency in the signal input from the signal sensing unit 210 to the pixel embedded memory unit 270 (Low Pass). filter).

The first cut-off frequency may have a higher frequency value (Hz) than the second cut-off frequency. Conversely, the second cutoff frequency may have a lower frequency value (Hz) than the first cutoff frequency. Accordingly, a signal having a relatively long logic high retention time may pass through the second low-frequency filter 230 , and a short signal having a logic high retention time relatively short. ) may not pass through the second low-frequency filter 230 and only pass through the first low-frequency filter 220 . The first cut-off frequency and the second cut-off frequency can be designed at the level of a person skilled in the art according to a difference in the retention time of a logic high to be set.

The first switching unit 240 may output a signal input from the first low frequency filter 220 to the setting register unit 260 or the pixel embedded memory unit 270 . The second switching unit 250 may output the signal input from the signal sensing unit 210 to the setting register unit 260 or the pixel embedded memory unit 270 . Each of the first switching unit 240 and the second switching unit 250 may be implemented as a demultiplexer (DeMux).

The setting register unit 260 may have a plurality of memory cells for storing setting values related to pixel driving. The setting register unit 260 may include a plurality of setting data memory cells for storing setting values related to pixel driving and one flag memory cell for storing mode values.

4 is a block diagram schematically illustrating a configuration of a setting register unit according to an embodiment of the present specification.

Referring to FIG. 4 , a plurality of setting data memory cells 261 and one flag memory cell 262 can be identified. The size of the set data memory cell 261 may vary according to the size of a set value such as 19 bits or 12 bits. The flag memory cell 262 of the setting register unit 260 may store a value corresponding to the first mode or the second mode according to the present specification.

The setting register unit 260 may output the mode value stored in the flag memory cell 262 to the first switching unit 240 and the second switching unit 250 . In this case, the signal output to the first switching unit 240 and the second switching unit 250 is a selection signal (DeMUX Select) for selecting the output terminals of the first switching unit 240 and the second switching unit 250 . signal) can be In this specification, when the mode value stored in the flag memory cell 262 is '0', it is called a 'first mode', and when the mode value stored in the flag memory cell 262 is '1', it is called a 'second mode'. would.

The first switching unit 240 may output the signal (data_s) input from the first low-frequency filter 220 to the setting register unit 260 when the mode value is the first mode. The first switching unit 240 may output the signal data_s input from the first low frequency filter 220 to the embedded pixel memory unit 270 when the mode value is the second mode. In this case, the signal output from the first switching unit 240 may be input to the data terminal data_s0 of the setting register unit 260 and the data terminal data_s1 of the pixel embedded memory unit 270 .

The second switching unit 250 may output the signal clock_s input from the signal sensing unit 210 to the setting register unit 260 when the mode value is the first mode. The second switching unit 250 may output the signal clock_s input from the signal sensing unit 210 to the embedded pixel memory unit 270 when the mode value is the second mode. In this case, the signal output from the second switching unit 250 may be input to the clock terminal clock_s0 of the setting register unit 260 and the clock terminal clock_s1 of the pixel embedded memory unit 270 .

The pixel embedded memory unit 270 may have a plurality of memory cells for storing video data. The pixel embedded memory unit 270 may include a plurality of video data memory cells for storing video data and one flag memory cell for storing a mode flag.

5 is a block diagram schematically illustrating the configuration of the pixel embedded memory unit 270 according to an embodiment of the present specification.

Referring to FIG. 5 , a plurality of video data memory cells 271 and one flag memory cell 272 can be identified. The video data memory cell 271 may be further divided into a plurality of memory cells 271-R, 271-G, and 271-B respectively corresponding to the plurality of light emitting devices R, G, and B. The size of the memory cell 271 may vary according to the size of video data, that is, the size of grayscale (eg, 11 bits). The flag memory cell 272 of the pixel embedded memory unit 270 may store a value corresponding to the third mode or the fourth mode according to the present specification.

The pixel embedded memory unit 270 may output the mode value stored in the flag memory cell 272 to the signal sensing unit 210 . In this case, the signal output to the signal sensing unit 210 may be a MUX Select Signal for selecting an input terminal of the multiplexer MUX included in the signal sensing unit 210 . In this specification, when the mode value stored in the flag memory cell 272 is '0', it is called a 'third mode', and when the mode value stored in the flag memory cell 272 is '1', it is called a 'fourth mode'. would.

Referring back to FIG. 3 , the signal detecting unit 210 outputs the column signal when the mode value is the third mode, and the row signal when the mode value is the fourth mode. ) can be printed. Characteristics of the column signal and the row signal for the above operation will be described in more detail later.

Meanwhile, in the present specification, a memory cell means a circuit device for storing 1-bit data, and the memory cell according to the present specification may be implemented using various memory devices known to those skilled in the art. In this specification, an example in which a memory cell is implemented using a flip-flop (FF) is presented, but the pixel driving circuit according to the present specification is not limited to the above example.

The signal output from the second low frequency filter 230 may be input to a reset terminal for deleting data stored in the pixel embedded memory unit 270 . To this end, a flip-flop DFF for converting a signal data_l having a long logic high into a pulse signal clear may be connected to an output terminal of the second low frequency filter 230 .

Meanwhile, an initial driving signal (Power On Reset, POR) may be input to a reset terminal (reset) for deleting data stored in the setting register unit 260 . The initial driving signal POR may be a signal input together when power is supplied to operate the display device.

Hereinafter, the configuration and timing of the row signal and the column signal will be described. The row signal is a signal output from the scan driving circuit 120 according to the present specification, and the column signal is a signal output from the data driving circuit 130 according to the present specification. Output timings of the row signal and the column signal may be controlled by the controller 140 according to the present specification.

6 is a timing reference diagram of a row signal and a column signal according to the present specification.

Referring to FIG. 6 , first, the POR signal may be input together when power is supplied and may be continuously maintained in a logic high state. In addition, the frame sync signal V_sync of the screen may be periodically output according to a preset interval. The row signal and the column signal may be input to the pixel driving circuit 200 according to an output timing of the frame sync signal V_sync. Meanwhile, the first frame section is a frame section for mode 1 according to the present specification. Thereafter, the frame period is a frame period for modes 2 to 4. The frame sections for the modes 2 to 4 may be repeatedly maintained.

The timing of the signal shown in FIG. 6 is the column signal Col. 1 and the row signal Row 1 input to the pixel driving circuit arranged at the 1x1 position among the plurality of pixel circuits arranged on the display panel. The remaining pixel driving circuits differ only in input timing according to their arrangement positions, and the configuration of each row signal and each column signal is the same.

The row signal may include a first scan signal for inputting a set value related to pixel driving, a second scan signal for video data input, and a clock signal for PWM driving. The scan driving circuit 120 outputs a first scan signal once for each scan line after the initial driving signal POR is generated, and repeats the second scan signal and the clock signal in connection with each frame A low signal can be output.

The column signal may include a set value data signal related to driving a pixel, a video data reset signal having a length exceeding a preset reference time, and a video data signal related to a plurality of light emitting devices. The data driving circuit 130 first outputs the set value data signal once for each data line after the initial driving signal POR is generated, and outputs the video data reset signal and the video data signal in connection with each frame. A column signal including repetition can be output. In this case, the most significant bit (MSB) of the set value data signal may be a mode value, and the remaining bits may be a set value. The most significant bit MSB of the video data signal may be a mode value, and the remaining bits may be video data values related to grayscales of the plurality of light emitting devices.

Hereinafter, the order in which the pixel driving circuit 200 according to the present specification operates according to the above-described row signal and column signal, that is, the order in which modes 1 to 4 operate will be described. A path through which a signal input in each mode is output will be described below with reference to FIGS. 7 to 10 . Since the pixel driving circuit 200 shown in FIGS. 7 to 10 is the same as the pixel driving circuit 200 shown in FIG. 3 , a repetitive description of each configuration will be omitted.

7 is an operation reference diagram in mode 1.

Referring to FIG. 7 , first, an initial driving signal POR is input to a reset terminal of the setting register unit 260 . Accordingly, data stored in all memory cells included in the setting register unit 260 is deleted, and the initial value is reset to “0”. The mode value stored in the flag memory cell 262 of the setting register unit 260 is also reset to '0', and the mode value '0' is applied to the first switching unit 240 and the second switching unit 250 . is output This sets the mode 1 state.

After the initial driving signal is generated, the first scan signal output from the scan driving circuit 120 is input to the row signal input terminal, and the set value data signal output from the data driving circuit 130 is input to the column signal input terminal. is input In FIG. 7 , a set value data signal indicated by a mode value of '1' in the largest digit MSB and 'R' as a set value in the remaining bits is displayed.

The set value data signal passes through the signal detection unit 210 , the first low-frequency filter 220 and the first switching unit 240 while the first scan signal maintains a logic high. It is input to the data terminal (data_s0) of the setting register unit 260. In addition, the set value data signal passed through the second switching unit 250 in the signal sensing unit 210 is input to the clock terminal clock_s0 of the setting register unit 260 to operate as a clock signal. Accordingly, the set value data is stored in the memory cells 261 and 262 of the setting register unit 260 .

8 is a reference diagram for operation in mode 2;

Referring to FIG. 8 , the mode value '1' is stored in the flag memory cell 262 of the setting register unit 260 . The mode value '1' is output to the first switching unit 240 and the second switching unit 250, and is changed from the mode 1 to the mode 2 state.

The second scan signal output from the scan driving circuit 120 is input to the row signal input terminal, and the video data reset signal output from the data driving circuit 130 is input to the column signal input terminal.

12 is a reference diagram of video data and a video data reset signal according to an embodiment of the present specification.

Referring to FIG. 12 , video data 'H' and 'L' displayed in a preset time period T may be checked. And it is possible to check the video data reset signal (video data clear) displayed in the time period 'n' times longer than the time period 1T for distinguishing 1 bit of the video data (data 'H', data 'L'). have. That is, the video data reset signal (video data clear) is a signal having a length (eg, n=7) that exceeds a preset reference time, and is relatively relative to the video data signals (data 'H' and data 'L'). can have low frequency characteristics. And the second cutoff frequency of the second low frequency filter 230 has a frequency value that passes the video data clear signal and blocks the video data data 'H' and data 'L'. is set to Accordingly, the video data reset signal may pass through the second low frequency filter 230 .

Referring back to FIG. 8 , the video data reset signal passes through the signal detecting unit 210 and the second low-frequency filter 230 while the second scan signal maintains a logic high level to the pixel. It is input to a reset terminal (reset) of the built-in memory unit 270 . As a result, data stored in all memory cells included in the pixel embedded memory unit 270 is deleted, and the initial value is reset to “0”.

9 is a reference diagram for operation in mode 3;

Referring to FIG. 9 , the mode value '0' is stored in the flag memory cell 272 of the pixel embedded memory unit 270 . The mode value '0' is output to the multiplexer (MUX) included in the signal sensing unit 210, and is changed from the mode 2 to the mode 3 state.

The second scan signal output from the scan driving circuit 120 is continuously input to the row signal input terminal, and the video data signal output from the data driving circuit 130 is input to the column signal input terminal.

As described above with reference to FIG. 12 , the video data signal is cut off by the second low frequency filter 230 . On the other hand, the first low-frequency filter 220 is set to a cutoff frequency value through which the video data signal can pass. Accordingly, the video data signal passes through the signal detection unit 210 , the first low-frequency filter 220 , and the first switching unit 240 while the second scan signal maintains a logic high level. It is input to the data terminal data_s1 of the pixel embedded memory unit 270 . In addition, the video data signal passing through the second switching unit 250 in the signal sensing unit 210 is input to the clock terminal clock_s1 of the pixel embedded memory unit 270 and operates as a clock signal. Accordingly, the video data is stored in the memory cells 271 and 272 of the pixel embedded memory unit 270 .

13 is a reference diagram in which a memory cell according to the present specification stores data '1' and '0'.

12 and 13 together, the video data value according to the present specification is a signal having a lower frequency than the cut-off frequency of the first low-frequency filter 220 within the preset reference time T and the first low-frequency It may include a signal having a higher frequency than the cutoff frequency of the filter 220 . That is, the data '1' has a relatively long retention time (A) of the logic high to have a lower frequency than the cut-off frequency of the first low-frequency filter 220, and the data '0' is the first low-frequency filter 220 . The holding time C of the logic high may be relatively short to have a higher frequency than the cut-off frequency of . 13 shows a signal waveform after the video data signal having the above characteristics passes through the first low-frequency filter 220 . Both '1' and '0' of the video data signal before passing through the first low frequency filter 220 have a logic high, but after passing through the first low frequency filter 220 , the video data signal has a logic low ('0'). ) and logic high ('1'). Accordingly, video data may be stored as '1' and '0' in the memory cells 271 and 272 of the pixel embedded memory unit 270 . Meanwhile, the signal passing through the second switching unit 250 without passing through the first low-frequency filter 220 in the signal sensing unit 210 may operate as a clock signal because the pulse is input as it is without being deformed.

10 is a reference diagram for operation in mode 4.

Referring to FIG. 10 , the mode value '1' is stored in the flag memory cell 272 of the pixel embedded memory unit 270 . The mode value '1' is output to the multiplexer MUX included in the signal sensing unit 210 and is changed from mode 3 to mode 4.

A clock signal for PWM driving output from the scan driving circuit 120 is input to the low signal input terminal. Video data signals for other pixel driving circuits arranged in the column direction are input to the column signal input terminal, but the multiplexer MUX included in the signal detection unit 210 is set to output only the signal input from the row signal input terminal Thus, the signal input to the column signal input terminal has no effect in mode 4.

In the scan driving circuit 120 , the clock signal may be composed of a pulse signal having a relatively high frequency characteristic compared to the video data signal, and may be blocked by the first low frequency filter 220 . Accordingly, the clock signal may pass through the signal sensing unit 210 and the second switching unit 250 and may be input to the clock terminal Clock_S1 of the embedded pixel memory unit 270 . Thereafter, the pixel embedded memory unit 270 may perform an operation for PWM driving of the light emitting device LED according to the timing of the clock signal with the video data stored in the memory cell 272 .

11 is a reference diagram for an operation sequence of Modes 1 to 4 according to the present specification.

Referring to FIG. 11 , the first mode 1 operates, and the mode 2, mode 3, and mode 4 operate sequentially. Thereafter, modes 2 to 4 are repeatedly executed according to the video frame. As described with reference to FIGS. 8 to 10 , the repeated execution of modes 2 to 4 may be repeatedly executed according to characteristics of a row signal and a column signal.

Meanwhile, depending on the operation setting of the display device, there may be a case in which PWM driving is performed once and a case in which PWM driving is repeatedly performed twice or more during one frame. In this specification, an operation mode in which PWM driving is repeatedly performed M times will be referred to as an 'M-cycling operation mode'. When the conventional PWM driving is performed only once, the PWM driving can be terminated regardless of the value of the least significant bit LSB of the grayscale data by resetting all shift registers. On the other hand, in the M-cycling operation mode, the shift registers are all reset after M times of PWM driving. However, when the value of the least significant bit (LSB) of the grayscale data is '1', the light emitting element (LED) is continuously turned on until the most significant bit (MSB) of the grayscale data for the next PWM driving is input. problems may arise. Therefore, each PMW driving needs to be finished after outputting the last grayscale data.

According to an embodiment of the present specification, the pixel embedded memory unit 270 may further include a plurality of PWM termination memory cells for terminating PWM driving of each light emitting device.

With reference to FIG. 5 again, the configuration of the pixel embedded memory unit 270 according to the present specification will be described in more detail. The pixel embedded memory unit 270 according to the present specification may include K shift registers corresponding to the number of light emitting devices (LEDs). 5 shows three shift registers 271-R, 271-G, and 271-B corresponding to RGB. As described above, each shift register 271 includes L video data memory cells for storing video data of each light emitting device, that is, grayscale data. 5 is an example in which grayscale data of each light emitting device is 11 bits. In addition, each shift register 271 may further include one PWM termination memory cell for terminating PWM driving of the light emitting device.

The PWM termination memory cell may be located adjacent to a memory cell storing the least significant bit (LSB) or the most significant bit (MSB) among grayscale data of each light emitting device.

14 is a reference diagram of a PWM terminated memory cell according to the present specification.

Referring to FIG. 14 , one PWM end memory cell and four video data memory cells can be identified. In the example shown in FIG. 14, it is shown that one PWM termination memory cell is positioned next to the memory cell storing the least significant bit (LSB) among grayscale data. And an example of input data is also shown. When the grayscale data of the light emitting device LED is '0101', a '0' of 1 bit is further added to input '0101 0 '. In addition, when the grayscale data of the light emitting device LED is '1010', '0' of 1 bit is further added to input '1010 0 '.

Referring again to FIG. 5 , the remaining components shown in the pixel embedded memory unit 270 according to the present specification will be described.

The pixel-embedded memory unit 270 includes K output switching elements connected to one end of each shift register 271 and outputting stored data to the corresponding light emitting elements, and one end and the other end of each shift register 271 . It may further include K cycling switching elements connected therebetween to re-input data output from the one end to the other end. In the example shown in FIG. 5 , 'K=3'.

The flag memory cell 272 may output the stored mode value as a selection signal to the K output switching devices and the K cycling switching devices. Accordingly, when '1' is stored as the mode value in the flag memory cell 272, the cycling operation mode may be operated by the output switching element and the cycling switching element.

Meanwhile, in the cycling operation mode, the video data signal output by the data driving circuit 130 may include L-bit grayscale data and 1-bit '0' data corresponding to the grayscale of each light emitting device as PWM end data. . In this case, the PWM end data is located adjacent to the least significant bit (LSB) or the most significant bit (MSB) among the grayscale data of each light emitting device.

Meanwhile, in the cycling operation mode, the scan driving circuit 120 may output a low signal in which M clock signals are repeated for each second scan signal according to the M-cycling operation mode.

15 is a reference diagram for a cycling operation.

Referring to FIG. 15 , it is an example of operating at 50% on-duty using 6-bit PWM.

The scan driving circuit 120 , the data driving circuit 130 and the controller 140 according to the present specification are a processor known in the art to which the present invention pertains to execute signal output, calculation and various control logic, ASIC (application- specific integrated circuit), other chipsets, logic circuits, registers, communication modems, data processing devices, and the like. In addition, when the above-described control logic is implemented in software, the scan driving circuit 120 , the data driving circuit 130 , and the controller 140 may be implemented as a set of program modules. In this case, the program module may be stored in the memory device and executed by the processor.

The computer program is C/C++, C#, JAVA, Python that can be read by a processor (CPU) of the computer through a device interface of the computer in order for the computer to read the program and execute the methods implemented as a program , may include code coded in a computer language such as machine language. Such code may include functional code related to functions defining functions necessary for executing the methods, etc. can do. In addition, the code may further include additional information necessary for the processor of the computer to execute the functions or code related to memory reference for which location (address address) in the internal or external memory of the computer should be referenced. have. In addition, when the processor of the computer needs to communicate with any other computer or server located remotely in order to execute the functions, the code uses the communication module of the computer to determine how to communicate with any other computer or server remotely. It may further include a communication-related code for whether to communicate and what information or media to transmit and receive during communication.

The storage medium is not a medium that stores data for a short moment, such as a register, a cache, a memory, etc., but a medium that stores data semi-permanently and can be read by a device. Specifically, examples of the storage medium include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage device. That is, the program may be stored in various recording media on various servers accessible by the computer or in various recording media on the computer of the user. In addition, the medium may be distributed in a computer system connected by a network, and a computer readable code may be stored in a distributed manner.

In the above, the embodiments of the present specification have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which this specification belongs can realize that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: display device
110: display panel 120: scan driving circuit
130: data driving circuit 140: control unit
200: pixel driving circuit 210: signal detection unit
220: first low-frequency filter 230: second low-frequency filter
240: first switching unit 250: second switching unit
260: setting register unit 270: pixel built-in memory unit

Claims (20)

a setting register unit having a plurality of memory cells for storing setting values related to pixel driving;
a pixel-embedded memory unit having a plurality of memory cells for storing video data;
a signal sensing unit having a row signal input terminal and a column signal input terminal;
a first low-frequency filter for outputting a signal having a frequency lower than a preset first cut-off frequency for the signal input from the signal detecting unit;
a second low-frequency filter for outputting a signal having a frequency lower than a preset second cut-off frequency from the signal inputted from the signal sensing unit to the pixel embedded memory unit;
a first switching unit outputting the signal input from the first low frequency filter to the setting register unit or the pixel embedded memory unit; and
and a second switching unit for outputting the signal input from the signal sensing unit to the setting register unit or the pixel embedded memory unit. The method according to claim 1,
The setting register unit,
a plurality of set data memory cells for storing set values related to pixel driving; and
A pixel driving circuit comprising a; one flag memory cell for storing a mode value. 3. The method according to claim 2,
The setting register unit outputs the mode value stored in the flag memory cell to the first switching unit and the second switching unit,
The first switching unit,
When the mode value is the first mode, the signal input from the first low-frequency filter is output to the setting register unit, and when the mode value is the second mode, the signal input from the first low-frequency filter is transferred to the pixel embedded memory output to the department,
The second switching unit,
When the mode value is the first mode, the signal input from the signal detection unit is output to the setting register unit, and when the mode value is the second mode, the signal input from the signal detection unit is applied to the pixel built-in memory unit. Output, pixel driving circuit. 4. The method according to claim 3,
The signal output from the first switching unit is input to the data terminal of the setting register unit and the data terminal of the pixel embedded memory unit,
The signal output from the second switching unit is input to a clock terminal of the setting register unit and a clock terminal of the pixel embedded memory unit. The method according to claim 1,
The pixel built-in memory unit,
a plurality of video data memory cells for storing video data; and
A pixel driving circuit comprising a; one flag memory cell for storing a mode flag. 6. The method of claim 5,
the pixel-embedded memory unit outputs the mode value stored in the flag memory cell to the signal sensing unit;
The signal detection unit,
outputting the column signal when the mode value is a third mode,
and outputting the low signal when the mode value is a fourth mode. The method according to claim 1,
and the signal output from the second low-frequency filter is input to a reset terminal for erasing data stored in the pixel embedded memory unit. The method according to claim 1,
A pixel driving circuit in which an initial driving signal is input to a reset terminal for deleting data stored in the setting register unit. 6. The method of claim 5,
The pixel built-in memory unit,
A pixel driving circuit further comprising a; a plurality of PWM termination memory cells for terminating PWM driving of each light emitting device. 10. The method of claim 9,
Each PWM termination memory cell is located adjacent to the least significant bit (LSB) of the video data of each light emitting device, the pixel driving circuit. A pixel driving circuit according to any one of claims 1 to 10; and
A pixel circuit comprising a plurality of light emitting elements. a display panel in which a plurality of pixel circuits according to claim 11 are arranged;
a scan driving circuit for outputting a row signal through a plurality of scan lines connected to row signal input terminals of pixel circuits arranged in a row direction; and
A display device comprising a; a data driving circuit for outputting a column signal through a plurality of data lines connected to the column signal input terminals of the pixel circuits arranged in the column direction. 13. The method of claim 12,
The low signal is
A display device comprising: a first scan signal for inputting a set value related to pixel driving; a second scan signal for inputting video data; and a clock signal for PWM driving. 14. The method of claim 13,
The scan driving circuit is
A display apparatus for outputting a first scan signal once for each scan line after an initial driving signal is generated, and outputting a row signal repeatedly including the second scan signal and the clock signal in association with each frame. 14. The method of claim 13,
The scan driving circuit is
A display apparatus for outputting a low signal in which M clock signals are repeated for every one second scan signal according to an M-cycling operation mode. 13. The method of claim 12,
The column signal is
A display device comprising: a set value data signal related to driving a pixel; a video data reset signal having a length exceeding a preset reference time; and a video data signal related to a plurality of light emitting elements. 17. The method of claim 16,
The data driving circuit is
After the initial driving signal is generated, the set value data signal is first output once for each data line, and a column signal including the video data reset signal and the video data signal is repeatedly outputted in connection with each frame. Device. 17. The method of claim 16,
The most significant bit (MSB) of the set value data signal is a mode value, and the remaining bits are set values. 17. The method of claim 16,
The most significant bit (MSB) of the video data signal is a mode value, and the remaining bits are video data values related to grayscales of a plurality of light emitting devices. 20. The method of claim 19,
The video data value is within the preset reference time.
A display device comprising a signal having a frequency lower than the cut-off frequency of the first low-frequency filter and a signal having a frequency higher than the cut-off frequency of the first low-frequency filter.

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