KR102259845B1 - Apparatus and method for image compensation - Google Patents

Abstract

An image compensation apparatus according to an embodiment, comprising: a signal output unit for outputting light as a plurality of electrical signals; a plurality of NOT gates receiving the plurality of electrical signals; a plurality of OR gates performing an OR operation on the output signals of the plurality of NOT gates; A plurality of D-Flip-flops using the final output signals of the plurality of OR gates as clock signals, receiving the plurality of electrical signals, and generating output signals of the plurality of electrical signals with respect to the clock signals flop); and an image data acquisition unit configured to acquire image data based on output signals generated by the plurality of di flip-flops, wherein, when the clock signal is “0”, the di-flip-flop sets the clock signal to “0”. When the previous clock signal in the case of " is "1", the output signal of the D flip-flop may be transmitted to the image data acquisition unit to compensate the output signal.

Description

Image Compensation Apparatus and Method {APPARATUS AND METHOD FOR IMAGE COMPENSATION}

The present invention relates to an image compensation apparatus and an image compensation method.

In general, an image sensor (eg, may be a CMOS image sensor) is composed of a plurality of transistors, photodiodes, and capacitors, and may output light as an electrical signal.

In this case, the photodiode of the image sensor operates in the visible light region, and the photodiode has radiation (eg, alpha, beta) having higher energy than visible light (which may be energy having a shorter wavelength than visible light). , gamma, and neutron), the image sensor may output an error signal instead of a normal signal.

Accordingly, due to an error signal of the image sensor, error pixels such as white spots or red green blue (RGB) occurring in an image may be generated in a camera that acquires an image using the image sensor.

As one example, after the previous Fukushima nuclear accident, a robot (Scorpion) was deployed to reconnaissance the accident situation. At this time, due to the error signal of the image sensor in the radiation environment, an error pixel was generated in the image acquired by the camera mounted on the robot.

On the other hand, in the case of electronic circuits or other systems, radiation shielding is possible with lead, etc., but in the case of an image sensor, an image can be taken only when exposed to the outside. Accordingly, an image sensor capable of image correction is required to obtain a normal image even in a radiation environment.

Korean Patent Laid-Open Publication No. 10-2010-0087639 (published on Aug. 5, 2010)

SUMMARY OF THE INVENTION An object of the present invention is to provide an image compensation apparatus and an image compensation method.

In addition, obtaining an image obtained by compensating for an erroneous pixel (which may be a white point in the image) in a radiation environment through such an apparatus and method may be included in the problem to be solved by the present invention.

However, the problems to be solved of the present invention are not limited to those mentioned above, and other problems to be solved that are not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the following description. will be.

An image compensation apparatus according to an embodiment includes a signal output unit for outputting light as a plurality of electrical signals; a plurality of NOT gates receiving the plurality of electrical signals; a plurality of OR gates performing an OR operation on the output signals of the plurality of NOT gates; A plurality of D-Flip-flops using the final output signals of the plurality of OR gates as clock signals, receiving the plurality of electrical signals, and generating output signals of the plurality of electrical signals with respect to the clock signals flop); and an image data acquisition unit configured to acquire image data based on output signals generated by the plurality of di flip-flops, wherein, when the clock signal is “0”, the di-flip-flop sets the clock signal to “0”. When the previous clock signal in the case of " is "1", the output signal of the D flip-flop may be transmitted to the image data acquisition unit to compensate the output signal.

In addition, when the signal output unit receives light having a wavelength less than a specific reference and outputs the plurality of electrical signals, all of the plurality of electrical signals are output as “1”, and all of the plurality of electrical signals are “ When output is 1", the final output signal of the plurality of OR gates may output "0".

In addition, the light having a wavelength less than or equal to the specific reference may include radiation.

The signal output unit may include: a first transistor receiving a voltage; a photodiode connected to the first transistor and receiving the voltage and the light to generate photocharges; a capacitor connected to the photodiode; a second transistor connected to a node between the first transistor and the photodiode and receiving a voltage lower than the voltage; a third transistor receiving an output signal of the second transistor; an amplifier amplifying the output signal of the third transistor; and an analog-to-digital converter converting the signal amplified by the amplifier into a digital signal.

An image compensation method according to an embodiment comprises the steps of outputting light as a plurality of electrical signals, performing a NOT operation on the plurality of electrical signals, and performing an OR operation on the plurality of signals on which the NOT operation is performed; generating an output signal of the electrical signal with respect to the clock signal by using the final output signal on which the OR operation is performed as a clock signal, receiving the plurality of electrical signals, and image data based on the output signal; and generating the output signal, when the clock signal is "0", the output signal when the previous clock signal is "1" when the clock signal is "0" can be used

In addition, in the outputting of the plurality of electrical signals, when light having a wavelength less than a specific reference is received and output as the plurality of electrical signals, all of the plurality of electrical signals are output as “1”, and the plurality of When all of the electrical signals of "1" are output, "0" may be output as the final output signal on which the OR operation is performed.

In addition, the light having a wavelength less than or equal to the specific reference may include radiation.

According to an embodiment, when an error occurs in the image data (for example, it may be an error pixel such as a white dot in the image data), the image compensation apparatus may compensate the image in which the error occurred by using the data before the error occurred. can Accordingly, an image (or image) of higher quality than a low-quality image (or image) taken in the existing radiation environment can be obtained.

In addition, the image compensation apparatus and image compensation method according to an embodiment may be used in various radiation environments, such as a nuclear accident robot, a nuclear power plant CCTV, and a nuclear inspection.

1 is a circuit diagram of an image compensator according to an exemplary embodiment.
2 is a spectrum according to a wavelength of light according to an exemplary embodiment.
3A and 3B are views comparing before and after irradiating radiation with respect to an image output through an image sensor according to an exemplary embodiment.
4 is a diagram for describing an output pulse signal of an image compensation apparatus according to an exemplary embodiment.
5 is an exemplary flowchart of a procedure of an image compensation method in one embodiment.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

In describing the embodiments of the present invention, if it is determined that a detailed description of a well-known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the terms to be described later are terms defined in consideration of functions in an embodiment of the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification.

1 is a diagram illustrating a circuit diagram of an image compensation apparatus 100 according to an embodiment of the present invention. Referring to FIG. 1 , an image compensation apparatus 100 according to an exemplary embodiment includes a signal output unit 20 , a plurality of NOT gates 43 , a plurality of OR gates 45 , and a plurality of D-Flip-flops. -Flop, 47) and an image data acquisition unit 60 may be included. In addition, the image compensation apparatus 100 may include a CMOS image sensor, but is not limited thereto. In addition, since the image compensation apparatus 100 of FIG. 1 is only an embodiment of the present invention, the spirit of the present invention is not interpreted as being limited by FIG. 1 .

In this case, according to an embodiment, the image compensation apparatus 100 may not include at least one of the components shown in FIG. 1 and/or may additionally include a configuration not shown in FIG. 1 . In addition, each of the components included in the image compensation apparatus 100 may be implemented in the form of a software module or a hardware module, or a combination of a software module and a hardware module, for example, a computer or a smart device, etc. can be electrically connected.

The signal output unit 20 includes a plurality of transistors 21 , 24 , 25 , a photo diode 22 , a capacitor 23 , an amplifier 26 and an analog-to-digital converter (ADC, Analog Digital Converter, 27) may include, and may output light as a plurality of electrical signals.

As an embodiment, the plurality of transistors 21 , 24 , and 25 may include a first transistor 21 , a second transistor 23 , and a third transistor 25 , but the present invention is not limited thereto. It is also possible

The first transistor 21 may receive power and may be connected to the photodiode 22 .

The second transistor 24 may be connected to a node (not shown) between the first transistor 21 and the photodiode 22 . In this case, the second transistor 24 may receive lower power than the first transistor 21 .

The third transistor 25 may be connected to the second transistor 24 , and may receive an output signal of the second transistor 24 .

The photodiode 22 is connected to the first transistor 21 , and may generate photocharges by receiving power and light passing through the first transistor 21 .

The photodiode 22 operates in the visible light region, and the magnitude of the voltage reduced by the photodiode 22 may vary depending on the energy of the light or the wavelength of the light.

More specifically, the above-described energy of light may be calculated as in Equation 1 below.

는 빛의 파장이고, c는 빛의 속도이다.where, Energy of Photon is the energy of light, h is the Planck constant,

is the wavelength of light and c is the speed of light.

The capacitor 23 may be connected to the photodiode 22 so that the power supplied to the photodiode 22 is maintained.

The amplifier 26 may receive the output signal of the third transistor 25 and amplify it.

The analog-to-digital converter (ADC, 27) may receive the amplified signal of the amplifier 26 and convert it into a plurality of digital (electrical) signals (MSB_in, MSB-1_in, MSB-2_in, MSB-3_in ... LSB_in). .

Each of the plurality of NOT gates 43 receives the digital signals MSB_in, MSB-1_in, MSB-2_in, MSB-3_in … LSB_in from the analog-to-digital converter 27 and receives the NOT operation (X ₁ , X ₂ , X _{3 )} , X ₄ ) can be done.

Meanwhile, the plurality of NOT gates 43 may be provided as many as the number of digital signals output from the analog-to-digital converter 27 , but is not limited thereto.

The plurality of OR gates 45 may perform an OR operation on _{the output signals X 1} , X ₂ , X ₃ , and X _{4 of the plurality of NOT gates 43 .}

In one embodiment, the OR gates 45a and 45b among the plurality of OR gates 45 are output signals X ₁ , X ₂ , X ₃ , X _{4 of the plurality of NOT gates 43 as shown in FIG. 1 .} ), and the OR gate 45c performs an OR operation on the values (Y ₁ , Y ₂ ) on which the OR operation is performed, so that the output signals of the plurality of NOT gates 43 (X ₁ , A final output signal CLK may be generated by performing a predetermined OR operation on X ₂ , X ₃ , and X _{4 .}

The plurality of di flip-flops D-Flip-Flop 47 transmits the output signal CLK of the OR gate 45c among the plurality of OR gates 45 to the output signal CLK of the plurality of di flip-flops D-Flip-Flop 47 . It can be used as a clock signal.

In addition, the plurality of D flip-flops (D-Flip-Flop, 47) receives a plurality of digital signals (MSB_in, MSB-1_in, MSB-2_in, MSB-3_in ... LSB_in) from the analog-to-digital converter 27, Output signals MSB_out, MSB-1_out, MSB-2_out, MSB-3_out ... LSB_out of a plurality of digital signals with respect to the clock signal CLK may be generated.

Furthermore, the plurality of D flip-flops (D-Flip-Flop, 47) are output signals (MSB_out, MSB-1_out, MSB-2_out, MSB) of the plurality of digital signals corresponding to the clock signal when the clock signal is “1”. After generating -3_out … LSB_out), it can be stored in a plurality of D-Flip-Flops (D-Flip-Flops, 47). In this case, the plurality of D flip-flops (D-Flip-Flops) 47 are output signals when the previous clock signal is “1” when the clock signal is “0” (eg, when the clock signal is “0”). output signals stored in the plurality of D flip-flops 47) may be used, but the present invention is not limited thereto.

Meanwhile, the plurality of D-Flip-Flops 47 corresponds to the plurality of digital signals MSB_in, MSB-1_in, MSB-2_in, MSB-3_in … LSB_in output from the analog-to-digital converter 27 . It may be provided in any number, but is not limited thereto.

The image data acquisition unit 60 may acquire image data based on output signals of the plurality of D-Flip-Flops 47 .

Hereinafter, a case in which radiation is incident on the image compensating apparatus will be described in detail with reference to FIGS. 2 and 3A and 3B .

2 is a view showing a spectrum according to a wavelength of light, and FIGS. 3A and 3B are views comparing an image output through an image sensor according to an embodiment of the present invention before and after irradiation with radiation.

Referring to FIG. 2 , when compared with the lights in the spectrum according to the wavelength of light shown in FIG. 2 , the light of the visible light 300 corresponds to light having a relatively short wavelength and a high frequency.

However, compared with the visible light 300 , the light of the radiation 310 has a shorter wavelength than visible light and a higher frequency than visible light.

3A is a view before irradiating radiation to an image through an image sensor. Referring to FIG. 3A , before irradiating the image sensor with radiation (for example, it may be a case of irradiating visible light), an error pixel is generated in the image A normal image that does not appear may be output.

However, when radiation is irradiated to the image sensor as shown in FIG. 3B , radiation having a shorter wavelength and higher frequency than visible light is irradiated to the image sensor, and the image sensor outputs a high bit value due to radiation having higher energy than visible light. will do

In addition, due to the output of a high bit value, error pixels outputting white spots or bright RGB (Red Green BLUE), etc. are generated in the image output through the image sensor, so that the image cannot be properly checked.

In contrast, the image compensation apparatus 100 according to an embodiment outputs a high bit from the analog-to-digital converter 27 (eg, the analog-to-digital converter 27 may have all digital signals of “1”). ), as “0” is input to the clock signals of the plurality of di flip-flops (D-Flip-Flop, 47), the previous clock signal stored in the plurality of di flip-flops (D-Flip-Flop, 47) An output signal when is "1" can be used.

Accordingly, the image compensating apparatus 100 according to an embodiment transfers the data in which an error has occurred (the output signal of the plurality of di flip-flops 47 when the clock signal of the plurality of di-flip-flops 47 is “0”). data (output signals of the plurality of di flip-flops 47 when the clock signal is “1” in the plurality of di-flip-flops 47) can be compensated.

4 is a diagram for explaining an output pulse signal of the image compensation apparatus 100 according to an exemplary embodiment. In addition, FIG. 4 relates to an output pulse signal of the image compensation apparatus 100 of FIG. 1 .

Referring to FIG. 4 , MSB, MSB-1, MSB-2, and MSB-3 shown in FIG. 4 are a plurality of digital signals output from the analog-to-digital converter 27 , and X ₁ , X _{2 ,} X _{3 ,} X ₄ are output signals of the plurality of NOT gates 43 , Y ₁ , Y ₂ are output signals of the plurality of OR gates 45 , and CLK are final output signals of the plurality of OR gates 45 .

Referring to FIG. 4 , a plurality of digital signals MSB, MSB-1, MSB-2, and MSB-3 output from the analog-to-digital converter 27 are “1”, “1”, “1”, In the case of "0", a plurality of digital signals are output as "0", "0", "0", and "1" respectively through the plurality of NOT gates 43 (X ₁ , X _{2 ,} X _{3 ,} X _{4 )} ) can be

At this time, the output signals (X ₁ , X _{2 ,} X _{3 ,} X ₄ ) of the plurality of NOT gates 43 “0”, “0”, “0”, and “1” are input to the plurality of OR gates 45 . In this case, among the output signals of the plurality of NOT gates 43, “0” and “0” are input (X ₁ , X ₂ ), and “0”, “1” are input (X ₃ , X _{4 )} ) can be

In addition, the plurality of OR gates 45 may output “0” for “0” and “0” (Y ₁ ), and output “1” for “0” and “1” (Y ₂ ). have.

Finally, the final output signal of the plurality of OR gates 45 is output (CLK) of "1" by ORing "0" and "1", and the final output signal CLK of the plurality of OR gates 45 is used as clock signals of the plurality of D-Flip-Flops 47, and in this case, the clock signals of the plurality of D-Flip-Flops 47 may be “1”.

On the other hand, when all of the plurality of digital signals MSB, MSB-1, MSB-2, and MSB-3 output from the analog-to-digital converter 27 are “1”, through the plurality of NOT gates 43 A plurality of digital signals MSB, MSB-1, MSB-2, and MSB-3 may be output as “0”, “0”, “0”, and “0”, respectively.

In addition, when all of the plurality of digital signals MSB, MSB-1, MSB-2, and MSB-3 output from the analog-to-digital converter 27 are “1”, the bits for the plurality of digital signals are the most The high case may be, for example, a case in which a radiation signal is incident, but is not limited thereto.

At this time, the output signals (X ₁ , X _2, X _3, X ₄ ) "0", "0", "0", and "0" of the plurality of NOT gates 43 are input to the plurality of OR gates 45 In this case, among the output signals of the plurality of NOT gates 43 , “0” and “0” are input (X ₁ , X ₂ ), and “0”, “0” are input (X ₃ , X _{4 )} ) can be

Also, the plurality of OR gates 45 may output “0” for “0” and “0” (Y _{1 ,} Y ₂ ), respectively.

Finally, the final output signal of the plurality of OR gates 45 performs an OR operation on “0” and “0” to output “0” (CLK), and the final output signal CLK of the plurality of OR gates 45 ) is used as clock signals of the plurality of D-Flip-Flops 47, and in this case, the clock signals of the plurality of D-Flip-Flops 47 may be “0”.

5 is an exemplary flowchart of a procedure of an image compensation method according to an embodiment. The image compensation method illustrated in FIG. 5 may be performed by the image compensation apparatus 100 illustrated in FIG. 1 . In addition, the image compensation method shown in FIG. 5 is merely exemplary.

Referring to FIG. 5 , first, the signal output unit 20 may output light as a plurality of electrical signals (step S10 ).

In this case, the plurality of NOT gates 43 may receive a plurality of electrical signals MSB_in, MSB-1_in, MSB-2_in, MSB-3_in ... LSB_in from the signal output unit 20 and perform a NOT operation (step S20).

The plurality of OR gates 45 may perform an OR operation on _{the output signals X 1} , X _{2 ,} X ₃ , and X _{4 of the plurality of NOT gates 43 (step S30 ).}

The plurality of D flip-flops D-Flip-Flop 47 uses the final output signal CLK, which has been subjected to the OR operation in the plurality of OR gates 45 , as a clock signal, and receives a plurality of signals from the signal output unit 20 . By receiving the electrical signal, output signals MSB_out, MSB-1_out, MSB-2_out, MSB-3_out ... LSB_out of the clock signal CLK may be generated (step S40).

At this time, when the clock signal of the plurality of D-Flip-Flops 47 is “1”, an output signal of an electrical signal corresponding to the clock signal is generated, and the plurality of D-Flip-Flops (D-Flip-Flop) is generated. , 47) may store the generated output signal. In addition, the plurality of D-Flip-Flops 47 may call a stored output signal when the clock signal is “0”.

Finally, the image data acquisition unit 60 may acquire image data based on output signals of a plurality of D-Flip-Flops 47 (step S50).

As described above, according to an exemplary embodiment, when an error occurs in image data (for example, it may be an error pixel such as a white dot in the image data), the image compensation apparatus uses the data before the error occurs to generate an error. Since the generated image is compensated, it is possible to obtain an image (or image) of higher quality than a low-quality image (or image) taken in the existing radiation environment.

In addition, the image compensation apparatus and image compensation method according to an embodiment may be used in various radiation environments, such as a nuclear accident robot, a nuclear power plant CCTV, and a nuclear inspection.

The above description is merely illustrative of the technical idea of the present invention, and various modifications and variations will be possible without departing from the essential quality of the present invention by those skilled in the art to which the present invention pertains. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

20: signal output unit
43: multiple NOT gates
45: multiple OR gates
47: Multiple D-Flip-Flops
60: image data acquisition unit
100: image compensation device

Claims (9)

a signal output unit for outputting light as a plurality of electrical signals;
a plurality of NOT gates receiving the plurality of electrical signals;
a plurality of OR gates performing an OR operation on the output signals of the plurality of NOT gates;
A plurality of D-Flip-flops using the final output signals of the plurality of OR gates as clock signals, receiving the plurality of electrical signals, and generating output signals of the plurality of electrical signals with respect to the clock signals flop); and
and an image data acquisition unit configured to acquire first image data based on a first output signal generated by the plurality of D flip-flops at a first time,
The D flip-flop is
When the clock signal is a preset value, a second output signal generated at a second time point earlier than the first time point stored in the D flip-flop is transferred to the image data acquisition unit,
The image data acquisition unit,
Compensating for the first image data including the erroneous pixel by using second image data obtained based on the second output signal when the obtained first image data includes an erroneous pixel
image compensation device. The method of claim 1,
The D flip-flop is
When the clock signal is “0”, when the previous clock signal when the clock signal is “0” is “1”, the output signal of the di-flip-flop is transferred to the image data acquisition unit;
The signal output unit,
When light having a wavelength less than a specific reference is input and output as the plurality of electrical signals, all of the plurality of electrical signals are output as “1”,
When all of the plurality of electrical signals are output as "1",
The final output signal of the plurality of OR gates is "0" is output
image compensation device. 3. The method of claim 2,
Light having a wavelength less than the specific standard,
containing radiation
image compensation device. The method of claim 1,
The signal output unit,
a first transistor receiving a voltage;
a photodiode connected to the first transistor and receiving the voltage and the light to generate photocharges;
a capacitor connected to the photodiode;
a second transistor connected to a node between the first transistor and the photodiode and receiving a voltage lower than the voltage;
a third transistor receiving an output signal of the second transistor;
an amplifier amplifying the output signal of the third transistor; and
An analog-to-digital converter for converting the amplified signal from the amplifier into a digital signal
image compensation device. outputting light as a plurality of electrical signals;
NOT calculating the plurality of electrical signals;
ORing a plurality of signals on which the NOT operation has been performed;
generating an output signal of the electrical signal with respect to the clock signal by using the final output signal on which the OR operation is performed as a clock signal and receiving the plurality of electrical signals;
In the step of generating the output signal, comprising the step of obtaining first image data based on the first output signal generated at a first time,
The step of generating the output signal comprises:
When the clock signal is a preset value, a second output signal generated at a second point in time earlier than the first point stored in the step of generating the output signal is transferred to the step of acquiring the image data,
The step of obtaining the image data includes:
Compensating for the first image data including the erroneous pixel by using second image data obtained based on the second output signal when the obtained first image data includes an erroneous pixel
Image compensation method. 6. The method of claim 5,
The step of generating the output signal comprises:
When the clock signal is “0”, the output signal when the previous clock signal when the clock signal is “0” is “1” is transferred to the step of acquiring the image data,
The step of outputting the plurality of electrical signals,
When light having a wavelength less than a specific reference is input and output as the plurality of electrical signals, all of the plurality of electrical signals are output as “1”,
When all of the plurality of electrical signals are output as "1",
The final output signal on which the OR operation is performed is "0"
Image compensation method. 7. The method of claim 6,
Light having a wavelength less than the specific standard,
containing radiation
Image compensation method. The method of claim 1,
The D flip-flop is
When the clock signal is “0”, when the previous clock signal when the clock signal is “0” is “1”, the output signal of the di-flip-flop is transferred to the image data acquisition unit;
The image data is
An erroneous pixel is included in the image data obtained when the clock signal input from the image data obtaining unit to the D flip-flop is “0” and is obtained based on an output signal,
When the clock signal input from the image data acquisition unit to the D flip-flop is “1”, the image data obtained when the output signal is obtained does not include the erroneous pixel.
image compensation device. 6. The method of claim 5,
The step of generating the output signal comprises:
When the clock signal is “0”, the output signal when the previous clock signal when the clock signal is “0” is “1” is transferred to the step of acquiring the image data,
The image data is
In the step of obtaining the image data, the image data obtained when the clock signal is obtained based on an output signal generated when the clock signal is “0” includes an erroneous pixel,
In the step of acquiring the image data, the image data acquired when the clock signal is acquired based on an output signal generated when the clock signal is “1” does not include the erroneous pixel.
Image compensation method.

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