KR102255588B1 - Liquid Crystal Display - Google Patents

Abstract

The display device according to the present invention includes a display panel, a timing controller, a shift register, a level shifter, and a selection output unit. The timing controller generates a gate timing control signal that controls the output timing of the gate pulse. The shift register generates a gate output using a gate timing control signal. The level shifter shifts and outputs the voltage level of the gate output. The selection output unit selectively connects at least two or more output terminals of the level shifter to generate a gate pulse by summing signals of the connected level shifter output terminals.

Description

Display device {Liquid Crystal Display}

The present invention relates to a display device.

Display devices are applied to various information devices and office devices as a transmission medium for visual information. Cathode Ray Tubes or CRTs, which are the most widely used display devices, have a problem in that they are large in weight and volume. Many types of flat panel displays that can overcome the limitations of such a cathode ray tube have been developed. Flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode device (OLED). Etc.

In a flat panel display, data lines and gate lines are disposed to cross each other, and pixels are disposed in a matrix form. A video data voltage to be displayed is supplied to the data lines, and a gate pulse is sequentially supplied to the gate lines. A video data voltage is supplied to pixels of a display line to which a gate pulse is supplied, and all display lines are sequentially scanned by the gate pulse to display video data.

In recent years, as the size of the panel increases, the length of the gate line increases, and accordingly, the delay phenomenon of the gate pulse is increasing. When the delay of the gate line increases, the time to charge the data voltage decreases, and eventually the operation of charging the data voltage becomes unstable.

This phenomenon is more pronounced in a high-resolution display device in which the time to scan one gate line is shortened or a display device operating at high speed. Accordingly, there is a need for a display device capable of improving the delay phenomenon of the gate pulse so as to be suitable for high-resolution or high-speed driving.

The present invention is to provide a display device capable of improving a delay phenomenon of a gate pulse.

The display device according to the present invention includes a display panel, a timing controller, a shift register, a level shifter, and a selection output unit. The timing controller generates a gate timing control signal that controls the output timing of the gate pulse. The shift register generates a gate output using a gate timing control signal. The level shifter shifts and outputs the voltage level of the gate output. The selection output unit selectively connects at least two or more output terminals of the level shifter to generate a gate pulse by summing signals of the connected level shifter output terminals.

The present invention can improve the delay of the gate pulse by generating a gate pulse by summing two or more gate outputs.

1 is a view showing a display device according to an embodiment of the present invention.
2 is a diagram illustrating a pixel of a display device.
3 and 4 are diagrams showing the configuration of a gate drive IC according to an embodiment of the present invention.
Fig. 5 is a diagram showing the timing of input and output signals of the gate drive IC.
6 is an equivalent circuit diagram of an output stage of a level shifter according to a comparative example.
7 is an equivalent circuit diagram of an output stage of a level shifter according to an embodiment of the present invention.
8 is a diagram showing a profile of a gate pulse according to a comparative example.
9 is a view showing a profile of a gate pulse according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a diagram showing a display device according to the present invention, and FIG. 2 is a diagram showing an example of a pixel of the present invention.

Referring to FIG. 1, a display device according to the present invention includes a display panel 100, a timing controller 200, a data driving circuit 300, and a gate driving circuit 33. The data driving circuit 300 includes a plurality of source ICs. The gate driving circuit 33 includes a plurality of gate ICs 400.

The display panel 100 includes a plurality of pixels P, and displays an image based on a gray scale displayed by each of the pixels P. The pixels P receive a scan signal SCAN and a sense signal SENSE, respectively, through a scan line SL and a sense line SEL arranged in a horizontal direction. In addition, the pixels P receive the data voltage Vdata through the data line DL connected to the data driver 120.

Each of the pixels P includes an organic light emitting diode OLED, a driving transistor DT, first and sensing transistors ST1 and ST2, and a storage capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multi-layered organic compound layer is formed between the anode electrode and the cathode electrode of an organic light-emitting diode (OLED). The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the ground terminal VSS.

The driving transistor DT controls the driving current Ioled flowing through the organic light emitting diode OLED according to the gate-source voltage Vgs. The storage capacitor Cst is connected between the gate node N1 and the source node N2 to maintain the data voltage provided from the data line DL for one frame. The scan transistor ST1 is switched according to the scan signal SCAN to control the potential of the gate electrode of the driving transistor DT. The sense transistor ST2 is switched according to the sense signal SENSE to control the potential of the source electrode of the driving transistor DT.

The timing controller 200 receives timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), a data enable signal DE, and a clock signal CLK, and receives the data driving circuit 300 and the gate driving circuit 33. Generates control signals for controlling the operation timing of ). These control signals include a gate timing control signal and a data timing control signal. In addition, the timing controller 200 supplies digital video data RGB to the data driving circuit 300.

The gate timing control signal generated by the timing controller 200 includes a gate start pulse (GSP), a gate shift clock signal (Gate Shift Clock, GSC), and a gate output enable signal (Gate Output Enable, GOE).

The gate start pulse GSP is applied to the gate drive IC 400 and indicates a start line at which the scan starts so that the first gate pulse is generated. The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate ICs 400 shift the gate start pulse GSP at the rising edge of the gate shift clock signal GSC. The gate output enable signal GOE is commonly input to each gate drive IC 400. The gate drive IC 400 outputs a gate pulse during a low logic period of the gate output enable signal GOE, that is, a period from immediately after the falling time of the pulse to immediately before the rising time of the next pulse.

The data timing control signal generated by the timing controller 200 includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal. (Source Output Enable, SOE), etc. are included. The source start pulse SSP indicates a start pixel in a line on which data is to be displayed. The source sampling clock SSC instructs a latch operation of data in the data driving circuit 300 based on a rising or falling edge.

Each of the source ICs of the data driving circuit 300 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 300 latches the digital video data RGB under the control of the timing controller 200.

3 and 4 are diagrams showing the configuration of the gate drive IC 400 of the present invention.

3 and 4, the gate drive IC 400 of the present invention includes a shift register 410, a level shifter 420, and an output selector 430. 4 shows only the first to third level shifters 420-1, 420-2, and 420-3 among m level shifters.

The shift register 410 sequentially shifts the gate start pulse (GSP) according to the gate shift clock (GSC) using a plurality of dependently connected flip-flops, so that the first to m-th gate outputs (Gout1 to Goutm) are obtained. Generate. The first to mth gate outputs Gout1 to Goutm are input to the first to mth level shifters 420-1 to 420-m, respectively.

The level shifter 420 shifts the voltage level of the gate output Gout of the shift register 410 to a gate high voltage. The first level shifter 420-1 receives the first gate output Gout1 and shifts the voltage level of the first gate output Gout1 to a gate high voltage. ) Is received and the voltage level of the m-th gate output Goutm is shifted to a gate high voltage. To this end, the level shifter 420 includes first and second transistors Tp and Tn. The first transistor Tp includes a gate electrode receiving the gate output Gout of the shift resistor 410, a first electrode connected to a gate high voltage VGH power source, and a second electrode connected to the output terminal N1. do. The second transistor Tn includes a gate electrode receiving a gate output of the shift resistor, a first electrode connected to the gate low voltage VGL power source, and a second electrode connected to the output terminal N1.

The output selector 430 includes a gate switch element SW and a select switch element SEL.

The gate switch element SW is positioned between the output terminal of the level shifter 420 and the gate line, and selectively connects the level shifter 420 and the gate line. For example, the first gate switch device SW1 selectively connects the output terminal of the first level shifter 420-1 and the first gate line. The first gate switch device SW1 operates in response to a first gate switch signal.

The selection switch element SEL is located between the output terminals of each of the adjacent level shifters, and selectively connects the output terminals of the adjacent level shifters 420. For example, the first selection switch element SEL1 selectively connects the first output terminal N1 of the first level shifter 420-1 and the second output terminal N2 of the second level shifter 420-2, The (m-1)th selection switch element selectively connects the output terminal of the (m-1)th level shifter and the output terminal of the mth level shifter. The first selection switch element SEL1 operates in response to the first selection switch signal, and the (m-1)th selection switch element operates in response to the (m-1)th selection switch signal.

5 is a diagram showing input and output signals of the level shifter 420 and the output selector 430 according to the present invention.

During the first period T1, the shift register 410 outputs the first gate output Gout1 to the first level shifter 420-1, and outputs the second gate output Gout2 to the second level shifter 420- 2). The first level shifter 420-1 shifts the voltage level of the first gate output Gout1 and outputs it to the first output terminal N1. The second level shifter 420-2 shifts the voltage level of the second gate output Gout2 and outputs it to the second output terminal N2.

During the first period T1, the first selection switch signal SSEL1 is input to the first selection switch element SEL1. The first selection switch element SEL1 is turned on by the first selection switch signal SSEL1, and the first output terminal N1 and the second level shifter 420-2 of the first level shifter 420-1 The second output terminal N2 of is connected. During the first period T1, the first gate switch signal SSW1 is input to the first gate switch element SW1. The first gate switch device SW1 is turned on by the first gate switch signal SSW1, and the second to mth gate switch devices SW1 to SWm maintain a turn-off state.

Since the first output terminal N1 of the first level shifter 420-1 and the second output terminal N2 of the second level shifter 420-2 are connected by the first selection switch element SEL1, the first Outputs of the level shifter 420-1 and the second level shifter 420-2 are simultaneously provided to the first gate line. The first gate line simultaneously receives output voltages from the first level shifter 420-1 and the second level shifter 420-2. Accordingly, the time for the first gate pulse G1 provided to the first gate line to reach the gate high voltage is reduced.

During the second period T2, the shift register 410 provides the second gate output Gout2 to the second level shifter 420-2 and the third gate output Gout3 to the third level shifter Gou3. Provided with. During the second period T2, the second gate switch device SW2 is turned on by the second gate switch signal SSW2, and the first gate switch device SW1 is turned off. In addition, during the second period T2, the second selection switch element SEL2 is turned on by the second selection switch signal SSEL2. During the second period T2, the second gate line receives output voltages from the second level shifter 420-2 and the third level shifter 420-3 at the same time, so that the second gate pulse G2 is The time to reach the high voltage VGH is reduced.

6 is a diagram illustrating an equivalent circuit of an output stage of a level shifter according to a comparative example in which a gate pulse is output using one level shifter. And Figure 7 is a diagram showing the equivalent circuit of the first and second output terminals (N1, N2) according to an embodiment of the present invention.

As shown in FIGS. 6 and 7, the output terminal of the level shifter according to the present invention provides twice as much current to the gate pulse as compared to the output terminal of a general level shifter. Since the amount of change in voltage is proportional to the amount of change in current, the amount of change in the voltage level of the gate pulse provided to the gate line during the same period changes at a rate twice as fast as when outputting one level shifter. That is, the gate pulse of the present invention can shorten the time during which the voltage level of the gate pulse swings from a low potential to a high gate voltage. Therefore, it is possible to reduce the degree of delay of the gate pulse provided to a pixel located far from the level shifter.

8 is a diagram showing a comparative example in which one level shifter output is used as a gate pulse. 9 is a diagram showing a waveform of a gate pulse according to an embodiment of the present invention.

As shown in FIG. 8, according to the comparative example, the degree of delay of the gate pulse is very small in a region close to the level shifter that outputs the gate pulse, and the delay of the gate pulse increases in a region far from the level shifter. Therefore, in a region far from the level shifter, the time point at which the gate high voltage VGH is reached is delayed by't' time.

In contrast, the gate pulse according to the present invention, as shown in FIG. 9, is delayed by a time't1' when the gate pulse reaches the gate high voltage VGH even at a point far from the level shifter. That is, the present invention can reduce the time to reach the gate high voltage VGH by Δt compared to the comparative example.

In addition, the gate pulse according to the present invention can reduce the discharge time to the gate low voltage VGL as compared to the comparative example.

The above-described embodiment of the present invention has been described for outputting a gate pulse by summing the outputs of two level shifters. The technical idea of the present invention is to generate gate pulses using outputs of a plurality of level shifters, and the number of level shifter outputs added to generate the gate pulses may be set to three or more.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 200: timing controller
300: source drive IC 400: gate drive IC
410: serial-to-parallel converter 420: DAC
430: output circuit

Claims (4)

A display panel in which gate lines receiving gate pulses are arranged;
A timing controller generating a gate timing control signal for controlling an output timing of the gate pulse;
A shift register generating a gate output using the gate timing control signal;
A level shifter for shifting and outputting the voltage level of the gate output; And
And a selection output unit that selectively connects at least two output terminals of the level shifter to generate a gate pulse by summing signals of the connected level shifter output terminals,
The selection output unit
A gate switch element positioned between an output terminal of the level shifter and a gate line; And
Includes a selection switch element positioned between the output terminals of each of the adjacent level shifters,
The display device connects the output terminals of the level shifters while the selection switch element is turned on.
delete The method of claim 1,
The selection output unit
A first gate switch element positioned between the output terminal of the first level shifter and the first gate line;
A second gate switch element positioned between the output terminal of the second level shifter and the second gate line; And
And a first selection switch element connecting the output terminal of the first level shifter and the output terminal of the second level shifter,
While the first selection switch element is turned on, one of the first gate switch element and the second gate switch element is turned on.
The method of claim 3,
The level shifter is
A first transistor including a gate electrode receiving the gate output of the shift resistor, a first electrode connected to a gate high voltage source, and a second electrode connected to the output terminal; And
A display device including a second transistor including a gate electrode receiving the gate output of the shift resistor, a first electrode connected to a gate low voltage source, and a second electrode connected to the output terminal.

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