KR102228084B1 - Pixel using low-voltage transistor and Micro Display comprising the Pixel - Google Patents

Abstract

The present invention relates to a pixel circuit and a test circuit composed of a low voltage transistor included in a micro display device. The micro-display device of the present invention includes a display area including a plurality of pixels and a power supply unit for applying power through a first power line and a second power line connected to the plurality of pixels, each of the plurality of pixels A light emitting device including an electrode and a second electrode, the first electrode connected to the first power line, the drain terminal connected to the second electrode of the light emitting device, and maintaining a turn-on state by a bias voltage applied to the gate terminal, and the source The voltage control transistor for controlling the voltage applied to the terminal, the driving transistor with the drain terminal connected to the source terminal of the voltage control transistor, and the drain terminal connected to the second power line, the source terminal connected to the source terminal of the voltage control transistor, It includes an inspection transistor to test for defects.

Description

Pixel using low-voltage transistor and micro display comprising the same

The present invention relates to a pixel circuit and a test circuit composed of a low voltage transistor included in a micro display device.

Recently, excellent display device characteristics are required for VR (Virtual Reality), AR (Augmented Reality), and MR (Mixed Reality) technologies. In particular, the development of micro LED on Silicon or AMOLED on Silicon is increasing, and in particular, there is an increasing demand for minimizing the pixel size for high resolution implementation. Accordingly, it is necessary to implement a circuit driven in a small pixel-sized area, and a new technology development capable of miniaturization is required.

Conventionally, testing for a large number of sub-pixels (FHD case: 1920*1080*RGB = 6,220,800) is impossible in the equipment and environment, and since an additional test circuit was required, it had no choice but to affect the pixel size minimization. Actually.

In particular, high voltage transistors used in conventional circuits require a certain space to satisfy breakdown voltage even if a fine process is applied, and thus, high resolution implementation is limited.

The present invention is in accordance with the above-described necessity, and an object of the present invention is to provide a display device including a miniaturization circuit suitable for realization of a high-resolution display device.

However, these problems are exemplary, and the scope of the present invention is not limited thereby.

According to an embodiment of the present invention, a micro-display device includes: a display area including a plurality of pixels; And a power supply for applying power through a first power line and a second power line connected to the plurality of pixels, wherein each of the plurality of pixels includes a first electrode and a second electrode, and the first A light emitting device having an electrode connected to the first power line; A voltage control transistor having a drain terminal connected to the second electrode of the light emitting device, maintaining a turned-on state by a bias voltage applied to a gate terminal, and controlling a voltage applied to a source terminal; A driving transistor having a drain terminal connected to the source terminal of the voltage control transistor; And a test transistor having a drain terminal connected to the second power line, a source terminal connected to the source terminal of the voltage control transistor, and testing a defect of the pixel.

In addition, a power voltage applied through the first power line may be higher than a power voltage applied through the second power line.

In addition, the driving transistor may operate in a triode region.

In addition, the voltage control transistor, the driving transistor, and the test transistor may be transistors driven with a low voltage.

Other aspects, features, and advantages other than those described above will become apparent from the detailed contents, claims, and drawings for carrying out the following invention.

According to an embodiment of the present invention made as described above, the pixel circuit of the present invention can be implemented with a low voltage transistor, and thus, a micro display device having a minimum size suitable for high resolution can be implemented.

In addition, since the pixel circuit of the present invention uses a low voltage transistor as a driving transistor, it is possible to secure an optimum mismatch characteristic in the same size.

Of course, the scope of the present invention is not limited by these effects.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.
2 is a diagram illustrating a pixel circuit included in a conventional display device.
3 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.
4 is an example of a pixel of the display device illustrated in FIG. 3.
5 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.
6 is an example of a pixel of the display device illustrated in FIG. 5.
7 is a diagram illustrating a safe operating area (SOA) of a bias transistor used according to an embodiment of the present invention.

Since the present invention can apply various transformations and have various embodiments, specific embodiments are illustrated in the drawings and will be described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when describing with reference to the drawings, the same or corresponding constituent elements are assigned the same reference numerals, and redundant descriptions thereof will be omitted. .

In the following embodiments, terms such as first and second are used for the purpose of distinguishing one constituent element from other constituent elements rather than a limiting meaning. In addition, in the following embodiments, expressions in the singular include plural expressions unless the context clearly indicates otherwise.

In the following embodiments, when X and Y are connected, X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. I can. Here, X and Y may be objects (eg, devices, devices, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship indicated in the drawings or detailed description, and may include anything other than the connection relationship indicated in the drawing or detailed description.

When X and Y are electrically connected, for example, an element (e.g., a switch, a transistor, a capacitor element, an inductor, a resistance element, a diode, etc.) that enables the electrical connection of X and Y, It may include a case of connecting one or more between X and Y.

In the following embodiments, "ON" used in connection with the device state may refer to an activated state of the device, and "OFF" may refer to an inactive state of the device. "On" used in connection with a signal received by the device may refer to a signal that activates the device, and "off" may refer to a signal that disables the device. The device can be activated by a high voltage or a low voltage. For example, a P-type transistor is activated by a low voltage, and an N-type transistor is activated by a high voltage. Therefore, it should be understood that the "on" voltage for the P-type and N-type transistors is at opposite (low vs. high) voltage levels.

In the following embodiments, terms such as include or have means that the features or elements described in the specification are present, and do not preclude the possibility of adding one or more other features or components in advance.

1 is a schematic diagram illustrating a manufacturing process of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device 30 according to an exemplary embodiment may include a light emitting device array 10 and a driving circuit board 20. The light emitting device array 10 may be coupled to the driving circuit board 20. The display device 30 may be a micro display device.

The light emitting device array 10 may include a plurality of light emitting devices. The light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. At least one light emitting device array 10 may be manufactured by growing a plurality of light emitting diodes on a semiconductor wafer. Accordingly, the display device 30 can be manufactured by combining the light emitting device array 10 with the driving circuit board 20 without the need to individually transfer the light emitting diodes to the driving circuit board 20.

Pixel circuits corresponding to each of the light emitting diodes on the light emitting device array 10 may be arranged on the driving circuit board 20. The light emitting diodes on the light emitting device array 10 and the pixel circuits on the driving circuit board 20 may be electrically connected to each other to form a pixel.

2 is a diagram illustrating a pixel circuit included in a conventional display device.

Referring to FIG. 2, in a conventional pixel circuit, a high voltage transistor must be used because the voltage of the first transistor T1 is not limited by a bias. For the same reason, a high voltage transistor must be used for not only the first transistor T1 but also the second transistor T2 and the third transistor T3.

In the case of a high voltage transistor used in a conventional pixel circuit, even if a fine process is applied, a space of a certain size or more is required to satisfy the withstand voltage. Accordingly, there is a disadvantage in that there is a limitation in manufacturing a micro display device having a high resolution.

In the present invention, as shown in FIGS. 3 to 6, a bias transistor BT for limiting a voltage by applying a bias to a conventional pixel circuit is added.

Specifically, FIG. 3 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the display device 30A of the present invention may include a pixel unit 110 and at least one driving unit.

The pixel unit 110 may be disposed in a display area displaying an image. The pixel unit 110 may include a plurality of pixels PX arranged in various patterns such as a predetermined pattern, for example, a matrix type, a zigzag type, or the like. The pixel PX emits one color and, for example, may emit one color of red, blue, green, and white. The pixel PX may emit colors other than red, blue, green, and white.

The pixel PX may include a light emitting device. The light emitting device may be a self-luminous device. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may emit light with a single peak wavelength or may emit a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The pixel circuit may be implemented by a semiconductor stacked structure on a substrate.

In the pixel unit 110, a scan line SL1 to SLn for applying a scan signal to the pixels PX, a light emission control line EL1 to ELn for applying a light emission control signal to the pixels PX, and pixels PX Data lines DL1 to DLm for applying a data signal to the device may be included.

Each of the scan lines SL1 to SLn and the emission control lines EL1 to ELn is connected to the pixels PX arranged in the same row, and each of the day lines DL1 to DLm is the pixels PX arranged in the same column. Can be connected to.

The pixel unit 110 may include inspection control lines CL1-CLn for applying an inspection control signal to the pixels PX. In addition, bias lines BL1 to BLn for applying a bias voltage to the pixels PX may be further disposed in the pixel unit 110. Each of the bias lines BL1 to BLn may be connected to the pixels PX arranged in the same row and may be spaced apart from the inspection control lines CL1 to CLn.

The driving unit is provided in a non-display area around the pixel unit 110 and may drive and control the pixel unit 110. The driving unit 120 may include a control unit 121, a scan driving unit 122, a data driving unit 123, a power supply unit 124, a test driving unit 125, an inspection unit 126, and a bias voltage supply unit 124. . The driving unit may operate according to the driving mode and the inspection mode.

In the driving mode, under the control of the controller 121, the scan driver 122 sequentially applies a scan signal to the scan lines SL1 to SLn, and the data driver 123 applies a data signal to each pixel PX. Can be approved. Under the control of the controller 121, the scan driver 122 may sequentially apply the emission control signal to the emission control lines EL1 to ELn. The pixels PX emit light with a brightness corresponding to a voltage level or a current level of a data signal received through the data lines DL1 to DLm in response to a scan signal received through the scan lines SL1 to SLn.

In the inspection mode, under the control of the controller 121, the scan driver 122 sequentially applies scan signals to the scan lines SL1 to SLn, and the data driver 123 applies the scan signals to each pixel PX. Can be approved. Under the control of the controller 121, the scan driver 122 may sequentially apply the emission control signal to the emission control lines EL1 to ELn. Under the control of the controller 121, the test driver 125 may apply a test control signal to each pixel PX.

The power supply unit 124 receives external power and/or internal power, converts the voltage into various levels required for operation of each component, and converts the corresponding voltage to the pixel unit according to a power control signal input from the controller 121. It can be supplied at (110).

Under the control of the controller 121, the power supply unit 124 may generate and apply the first power voltage VDD to the pixel unit 110. The power supply unit 124 may generate a driving voltage and apply it to the scan driver 122, the data driver 123, and the test driver 125.

In the test mode, under the control of the control unit 121, the power supply unit 124 may generate and apply the second power voltage VDD_L to the test unit 126. In this case, the second power voltage VDD_L may be a power voltage for applying a lower voltage than the first power voltage. For example, the first power voltage VDD may be 4 to 6 volts and the second power voltage VDD_L may be 1.5 to 1.8 volts, but the present invention is not limited thereto.

In this case, the first power voltage VDD may be applied through the first power line VL1, and the second power voltage VDD_L may be applied through the second power line VL2. The first power line VL1 and the second power line VL2 may be connected from the power supply unit 124 to the pixel unit 110 and the inspection unit 126, respectively.

In the test mode, the test unit 126 may measure a current flowing through the pixel circuit included in the pixel unit 110 by using the second power voltage VDD_L through the second power line. The inspection unit 126 may include a current measurement circuit for measuring current. The inspection unit 126 may measure the current in units of each row (line) of the pixel unit 110 and compare the measured current value with a reference current value corresponding to the inspection signal. If the difference between the measured current value and the reference current value is greater than or equal to the threshold value, the inspection unit 126 may determine that the pixel circuit of at least one pixel PX among the pixels PX in the corresponding row is defective.

The bias voltage supply unit 127 may supply a bias voltage for turning on a bias transistor that controls a drain voltage of the driving transistor of each pixel PX through the bias lines BL1-BLn. The bias lines BL1-BLn may be connected to the gate terminal of the bias transistor.

The control unit 121, the scan driver 122, the data driver 123, the power supply unit 124, the test driver 125, and the bias voltage supply unit 127 are each in the form of a separate integrated circuit chip or one integrated circuit chip. It may be directly mounted on the substrate on which the pixel portion 110 is formed, mounted on a flexible printed circuit film, attached to the substrate in the form of a tape carrier package (TCP), or formed directly on the substrate. .

4 is an example of a pixel of the display device illustrated in FIG. 3.

In the embodiment of FIG. 4, for convenience of description, the pixel PX1 in the n-th row and m-th column will be described as an example. The pixel PX1 is one of a plurality of pixels included in the n-th row, and is connected to the scan line SLn corresponding to the n-th row and the data line DLm corresponding to the m-th column.

The pixel PX1 crosses the scan line SLn for transmitting a scan signal, the data line DLm for transmitting a data signal, and transmits the first power voltage VDD and the second power voltage VDD_L. It can be connected to the power line (VL).

The pixel PX1 may include a light emitting diode (LED) and a pixel circuit connected to the light emitting diode (LED). The pixel circuit may include first to third transistors T1 to T3, a capacitor C, a test transistor TT, and a bias transistor BT. The first electrode or the first terminal of each of the first to third transistors T1 to T3, the test transistor TT, and the bias transistor BT may be a drain terminal, and the second electrode or the second terminal may be a source terminal. .

The first transistor T1 includes a gate electrode connected to the first electrode of the capacitor C, a first electrode connected to the light emitting diode LED through the third transistor T3, and a second electrode connected to the third power voltage VSS. It may include an electrode. The third power voltage VSS may be a ground voltage GND. The first transistor T1 serves as a driving transistor and may receive a data signal according to a switching operation of the second transistor T2 and supply current to the light emitting diode LED.

The first transistor T1 according to an embodiment of the present invention may operate in a low voltage region. For example, the first transistor T1 may operate in a triode region.

The second transistor T2 may include a gate electrode connected to the scan line SLn, a first electrode connected to the data line DLm, and a second electrode connected to the gate electrode of the first transistor T1. The second transistor T2 is turned on according to the scan signal transmitted through the scan line SLn and serves as a switching transistor that transmits the data signal transmitted to the data line DLm to the gate electrode of the first transistor T1. can do.

The second transistor T2 according to the exemplary embodiment of the present invention may operate in a low voltage region together with the first transistor T1. That is, the second transistor T2 may operate in a triode region. In this case, the data signal may be converted into a voltage range corresponding to the low voltage operation of the first transistor T1 and the second transistor T2.

The third transistor T3 includes a gate electrode connected to the emission control line ELn, a first electrode connected to the second electrode of the bias transistor BT, and a second electrode connected to the first electrode of the first transistor T1. can do. The third transistor T3 may be turned on according to the light emission control signal transmitted through the light emission control line ELn so that the driving current of the first transistor T1 flows through the light emitting diode LED. In the embodiment of FIG. 3, the emission control line ELn is connected to the scan driver 122 and may receive an emission control signal from the scan driver 122. In another embodiment, the emission control line ELn may be connected to the scan driver 122 and a separate emission control driver (not shown) to receive the emission control signal.

The bias transistor BT may include a gate terminal connected to the bias line BLn, a first electrode connected to the second electrode of the light emitting diode LED, and a second terminal connected to the first terminal of the third transistor T3. have. The bias transistor BT may be a voltage control transistor that maintains a turn-on state in a driving mode by a bias voltage applied to the gate terminal and controls a drain voltage of the first transistor T1.

According to an embodiment of the present invention, the drain voltage of the first transistor T1 is controlled by the bias transistor BT, so that the first to third transistors T1 to T3 can function as low voltage transistors. have. That is, the bias transistor BT may control the drain voltage of the first transistor T1 so that the first transistor T1 operates in the triode region.

The bias transistor BT may be turned on by a bias voltage applied through the bias line BLn. The bias voltage may be a direct current voltage DC of a predetermined level to keep the bias transistor BT always turned on. The node voltage Vx between the third transistor T3 and the bias transistor BT, that is, the drain voltage of the third transistor T3, may be controlled according to the turn-on state of the bias transistor BT. The channel resistance of the bias transistor BT may vary according to the bias voltage. That is, the bias transistor BT may operate as a variable linear resistance.

The node voltage Vx, that is, the drain voltage of the third transistor T3, may be determined according to the channel resistance of the bias transistor BT. Accordingly, by controlling the bias voltage, the drain voltage of the third transistor T3 can be controlled to a voltage that satisfies the condition that the third transistor T3 operates in the triode region.

The capacitor C may include a first electrode connected to the gate electrode of the first transistor T1 and a second electrode connected to the third power voltage VSS.

The first electrode of the light emitting diode LED may receive the first power voltage VDD from the first power line VL1. The second electrode of the light emitting diode LED may be connected to the first electrode of the bias transistor BT. A light-emitting diode (LED) can display an image by emitting light with a luminance corresponding to a data signal. In the inspection mode, the light emitting diode (LED) may not emit light.

The test transistor TT is connected to the gate electrode connected to the test control line CLn, the first electrode connected to the second power voltage VDD_L supplied from the second power line VL2, and the second electrode of the light emitting diode LED. It may include a connected second electrode. The test transistor TT may be turned on in the test mode and turned off in the driving mode.

In units of rows, a scan signal may be applied to the second transistor T2 through the scan line SLn, and a data signal may be applied to the data line DLm in response to the scan signal. Subsequently, the emission control signal may be applied to the third transistor T3 through the emission control line ELn. The test control signal may be applied to the test transistor TT through the test control line CLn. The test control signal may be applied to the test transistor TT while the scan signal is applied to the second transistor T2 through the scan line SLn. The test transistor TT is turned on by the test control signal, and the test transistor TT, the third transistor T3, and the first transistor T1 from the second power line VL2 connected to the power supply 124 Current can flow through. The current measuring circuit of the inspection unit 126 may measure the current flowing through the second power line VL2. That is, the first to third transistors T1 to T3 are included by applying the second power voltage VDD_L through the second power line VL2 to the pixel circuit in the test mode using the test transistor TT. It is possible to check whether or not the pixel circuit to be operated normally operates.

5 is a schematic diagram of a display device according to another exemplary embodiment of the present invention.

Referring to FIG. 5, a display device 30B according to an exemplary embodiment may include a pixel unit 210 and a driving unit.

The pixel unit 210 may be disposed in a display area displaying an image. The pixel unit 210 may include a plurality of pixels PX arranged in various patterns such as a predetermined pattern, for example, a matrix type, a zigzag type, or the like. The pixel PX emits one color and, for example, may emit one color of red, blue, green, and white. The pixel PX may emit colors other than red, blue, green, and white.

The pixel PX may include a light emitting device. The light emitting device may be a self-luminous device. For example, the light emitting device may be a light emitting diode (LED). The light emitting device may be a light emitting diode (LED) having a micro to nano unit size. The light emitting device may emit light with a single peak wavelength or may emit a plurality of peak wavelengths.

The pixel PX may further include a pixel circuit connected to the light emitting device. The pixel circuit may include at least one thin film transistor and at least one capacitor. The pixel circuit may be implemented by a semiconductor stacked structure on a substrate.

The pixel unit 210 may include pulse lines PL1-PLn for applying a PWM signal to the pixels PX and test control lines CL1-CLn for applying a test control signal to the pixels PX. . Each of the pulse lines PL1-PLn and the inspection control lines CL1-CLn is connected to the pixels PX arranged in the same row.

The driving unit is provided in a non-display area around the pixel unit 210 and may drive and control the pixel unit 210. The driving unit 220 may include a control unit 221, a PWM driving unit 222, a current supply unit 223, a power supply unit 224, a test driving unit 225, a test unit 226, and a bias voltage supply unit 227. . The driving unit may operate according to the driving mode and the inspection mode.

In the driving mode, under the control of the control unit 221, the PWM driver 222 sequentially applies a PWM signal to the pulse lines PL1-PLn, and the current supply unit 223 applies a current Iref to each pixel PX. ) Can be authorized. The pixels PX emit light with a brightness corresponding to the PWM signal received through the PWM driver 222.

In the test mode, under the control of the control unit 221, the PWM driver 222 sequentially applies a PWM signal of a predetermined bit to the pulse lines PL1-PLn, and the current supply unit 223 applies each pixel ( Current (Iref) can be applied to PX). Under the control of the controller 221, the test driver 225 may apply a test control signal to each pixel PX.

The current supply unit 223 may include a plurality of current sources supplying current to each column of the pixel unit 210.

The power supply unit 224 may generate and apply the first power voltage VDD to the pixel unit 210. The power supply unit 224 may generate a driving voltage and apply it to the PWM driving unit 222 and the test driving unit 225.

In the test mode, under the control of the control unit 221, the power supply unit 224 may generate and apply the second power voltage VDD_L to the test unit 226. In this case, the second power voltage VDD_L may be a power voltage for applying a lower voltage than the first power voltage.

In this case, the first power voltage VDD may be applied through the first power line, and the second power voltage VDD_L may be applied through the second power line. The first power line and the second power line may be connected from the power supply unit 124 to the pixel unit 110 and the inspection unit 126, respectively.

In the test mode, the test unit 226 may measure a current flowing through the pixel circuit included in the pixel unit 110 by using the second power voltage VDD_L through the second power line. The inspection unit 226 may be implemented as a current measurement circuit for measuring current. The inspection unit 226 may measure the current in units of each row (line) of the pixel unit 210 and compare the measured current value with a reference current value corresponding to the inspection signal. If the difference between the measured current value and the reference current value is greater than or equal to the threshold value, the inspection unit 226 may determine that the pixel circuit of at least one pixel PX among the pixels PX in the corresponding row is defective.

The bias voltage supply unit 227 may supply a bias voltage for turning on a bias transistor that controls a drain voltage of a driving transistor of each pixel PX through the bias lines BL1 to BLn. The bias lines BL1-BLn may be connected to the gate terminal of the bias transistor.

The control unit 221, the PWM driver 222, the current supply unit 223, the power supply unit 224, the test driver 225, and the bias voltage supply unit 127 are each in the form of a separate integrated circuit chip or one integrated circuit chip. It may be directly mounted on the substrate on which the pixel portion 110 is formed, mounted on a flexible printed circuit film, attached to the substrate in the form of a tape carrier package (TCP), or formed directly on the substrate. .

6 is an example of a pixel of the display device illustrated in FIG. 5.

In the embodiment of FIG. 6, for convenience of description, the pixels PX2 in the n-th row and m-th column will be described as an example. The pixel PX2 is one of a plurality of pixels included in the n-th row, and is connected to the pulse line PLn corresponding to the n-th row and the current source line CSLm corresponding to the m-th column.

The pixel PX2 may include a light emitting diode (LED) and a pixel circuit connected to the light emitting diode (LED). The pixel circuit may include a fourth transistor T4, a test transistor TT, and a bias transistor BT.

The fourth transistor T4 may include a gate electrode connected to the pulse line PLn, a first electrode connected to the second electrode of the bias transistor BT, and a second electrode connected to the current source line CSLm.

The fourth transistor T1 according to an embodiment of the present invention may operate in a low voltage region. For example, the fourth transistor T4 may operate in a triode region.

The first electrode of the light emitting diode LED may receive the first power voltage VDD from the first power line VL1. The second electrode of the light emitting diode LED may be connected to the first electrode of the bias transistor BT. The light-emitting diode (LED) can display an image by emitting light with a luminance corresponding to the PWM signal. In the inspection mode, the light emitting diode (LED) may not emit light.

The test transistor TT includes a gate electrode connected to the test control line CLn, a first electrode connected to the second power voltage VDD_L supplied from the second power line VL2, and a second electrode of the light emitting diode LED. It may include a connected second electrode. The test transistor TT may be turned on in the test mode and turned off in the driving mode.

In units of rows, the PWM signal may be applied to the fourth transistor T4 through the pulse line PLn. The test control signal may be applied to the test transistor TT through the test control line CLn. The test control signal may be applied to the test transistor TT while the PWM signal is applied to the fourth transistor T4 through the pulse line PLn. The test transistor TT is turned on by the test control signal, and the test transistor TT, the fourth transistor T4, and the current supply unit 223 are connected from the second power line VL2 connected to the power supply unit 124. Current may flow through it. The current measuring circuit of the inspection unit 126 may measure the current flowing through the second power line VL2.

That is, the pixel PX2 including the fourth transistor T4 is applied by applying the second power voltage VDD_L through the second power line VL2 to the pixel circuit in the test mode using the test transistor TT. You can check whether the circuit is operating normally.

The bias transistor BT may include a gate terminal connected to the bias line BLn, a first electrode connected to the second electrode of the light emitting diode LED, and a second terminal connected to the first terminal of the fourth transistor T4. have. The bias transistor BT maintains a turned-on state by a bias voltage applied to the gate terminal, and may be a voltage control transistor that controls a drain voltage of the fourth transistor T4.

According to an embodiment of the present invention, since the drain voltage of the fourth transistor T4 is controlled by the bias transistor BT, the fourth transistor T4 may function as a low voltage transistor. That is, the bias transistor BT may control the drain voltage of the fourth transistor T4 so that the fourth transistor T4 operates in the triode region.

The bias transistor BT may be turned on by a bias voltage applied through the bias line BLn. The bias voltage may be a direct current voltage DC of a predetermined level to keep the bias transistor BT always turned on. The node voltage Vy between the fourth transistor T4 and the bias transistor BT, that is, the drain voltage of the fourth transistor T4, may be controlled according to the turn-on state of the bias transistor BT. The channel resistance of the bias transistor BT may vary according to the bias voltage. That is, the bias transistor BT may operate as a variable linear resistance.

The node voltage Vy, that is, the drain voltage of the fourth transistor T4, may be determined according to the channel resistance of the bias transistor BT. Accordingly, by controlling the bias voltage, the drain voltage of the fourth transistor T4 can be controlled to a voltage that satisfies the condition that the fourth transistor T4 operates in the triode region.

According to the embodiments of FIGS. 3 to 6 as described above, the pixel circuit of the present invention can implement a plurality of transistors including a driving transistor, a test transistor, and the like as a low voltage transistor, thereby achieving high resolution. There is an advantage in that it is easy to implement a micro display device having a suitable minimum size.

In addition, since the pixel circuit of the present invention uses a low voltage transistor as a driving transistor, there is an advantage of securing an optimum mismatch characteristic in the same size.

7 is a diagram illustrating a safe operating area (SOA) of a bias transistor used according to an embodiment of the present invention.

In general, the gate terminal of the transistor needs to be limited in voltage to a low voltage. On the other hand, in the case of the drain terminal, a safe operating area (SOA) is configured to be widely used. Referring to FIG. 7, a gate terminal in an SOA region is limited to 1.5V or 1.8V, but an extended voltage greater than that of the drain terminal may be allowed.

Accordingly, in the pixel circuit according to the exemplary embodiment of the present invention, a bias limiting transistor connected to a cathode terminal of the light emitting device LED may be used as a low voltage transistor.

For example, the bias transistor BT of FIGS. 4 and 6 may be configured to apply a low voltage of 1.5V or 1.8V to the gate terminal even if a voltage of 6V is applied by being connected to the VDD power voltage to the drain terminal.

That is, in the pixel circuit according to the exemplary embodiment of the present invention, a low voltage may be applied to the bias transistor BT as well as the first to fourth transistors T1 to T4. Accordingly, the present invention has an advantage in that it is easy to implement a micro display device having a minimum size suitable for high resolution.

As described above, the present invention has been described with reference to the embodiments shown in the drawings, but these are only exemplary, and those of ordinary skill in the art will appreciate that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

10: light emitting element array
20: driver circuit board
30: display device
121: control unit
122: scan driver
123: data driver
124: power supply
125: inspection driving unit
126: inspection department
127: bias voltage driver
221: control unit
222: PWM driver
223: current supply
224: power supply
225: inspection driving unit
226: inspection unit
227: bias voltage driver

Claims (4)

In the micro display device,
A display area including a plurality of pixels; And
Includes; a power supply unit for applying power through a first power line and a second power line connected to the plurality of pixels,
Each of the plurality of pixels,
A light emitting device comprising a first electrode and a second electrode, the first electrode connected to the first power line;
A voltage control transistor having a drain terminal connected to the second electrode of the light emitting device, maintaining a turned-on state by a bias voltage applied to a gate terminal, and controlling a voltage applied to a source terminal;
A driving transistor having a drain terminal connected to a source terminal of the voltage control transistor, a source terminal connected to a current source line, and a gate terminal connected to a pulse line; And
A drain terminal is connected to the second power line, a source terminal is connected to a source terminal of the voltage control transistor, a test control signal is applied through a test control line connected to a gate terminal, and a test control signal is applied to the pixel by the test control signal. Including; inspection transistor for inspecting defects,
The driving transistor operates in a triode region as the drain voltage of the driving transistor is controlled by the voltage control transistor. The method of claim 1,
A micro-display device, wherein a power voltage applied through the first power line is higher than a power voltage applied through the second power line. delete The method of claim 1,
The voltage control transistor, the driving transistor, and the test transistor are transistors driven by a low voltage.

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