KR102224890B1 - Gate driving method and display device - Google Patents

Abstract

The present embodiments relate to a display device that provides efficient divisional driving using an optimized signal wiring structure, and provides partial driving for efficiently driving only a partial region under the signal wiring structure and divisional driving, and a gate driving method thereof. will be.

Description

Gate driving method and display device {GATE DRIVING METHOD AND DISPLAY DEVICE}

The present embodiments relate to a gate driving method and a display device.

As the information society develops, demands for display devices for displaying images are increasing in various forms, and in recent years, liquid crystal display devices, plasma display devices, and organic light-emitting display devices ( Organic Light Emitting Display Device).

Such a display device includes a display panel in which pixels are defined by forming data lines and gate lines, a data driver supplying data signals to data lines, a gate driver supplying scan signals to gate lines, and data And a timing controller that controls driving timing of the driving unit and the gate driving unit.

Meanwhile, in order to efficiently drive a display panel, a divided driving method for driving a display area (also referred to as an active area) divided into several areas has been proposed.

The conventional divided driving method requires separate control signals to control the divided driving. Therefore, separate signal wires for providing separate control signals to the driver must be added. This may cause difficulties in the display panel process, and may cause a problem in that the bezel of the display panel increases.

On the other hand, in a conventional display device, even if there is an image change compared to the previous frame in only a part of the display area, the gate driver does not take this into account and drives all the gate lines of the display panel sequentially, so driving time is unnecessary. There is a problem in that it may be lengthened or power consumption may be unnecessarily generated.

Against this background, it is an object of the embodiments to provide an efficient split driving method and a display device providing the same.

Another object of the present embodiments is to provide a display device having a signal wiring structure for efficient divisional driving.

Another object of the present embodiments is to provide a display device capable of minimizing the number of signal wires for efficient divisional driving.

Another object of the present embodiments is to provide a partial gate driving method and a display device providing the same.

Still another object of the present embodiments is to provide a gate driving method capable of reducing driving time or power consumption, and a display device providing the same.

In one aspect, the present embodiments include a display panel on which a plurality of data lines and a plurality of gate lines are disposed, a data driver for driving a plurality of data lines, a data driver for driving a plurality of gate lines, and a plurality of gate driving integrated circuits. A display device including a gate driver including a and a timing controller for controlling the data driver and the gate driver is provided.

In such a display device, a plurality of gate driving integrated circuits are divided by M (M is a natural number of 2 or more) and classified into N (N is a natural number of 2 or more) gate driving groups, and the display panel is divided into N gate driving groups. It corresponds to the N partial regions and can operate independently of each other by a group driving start signal and a group driving refresh signal.

In another aspect, the present embodiments include a gate driving unit including a plurality of gate driving integrated circuits, and a gate driving group selected for driving one frame from among at least two gate driving groups including a plurality of gate driving integrated circuits. It provides a display device including a timing controller that controls to sequentially output scan signals from two or more included gate driving integrated circuits.

In yet another aspect, the present embodiments include selecting some or all of the gate driving groups for driving one frame from among two or more gate driving groups dividing a plurality of gate driving integrated circuits, and the selected gate driving group. It provides a gate driving method comprising the step of controlling to sequentially output scan signals from two or more gate driving integrated circuits included in each.

In another aspect, in the present embodiments, scan signals are sequentially generated only in a gate driver including a plurality of gate driving integrated circuits and at least two gate driving integrated circuits selected for driving one frame among the plurality of gate driving integrated circuits. It provides a display device including a timing controller that controls to be output.

According to the exemplary embodiments described above, it is possible to provide an efficient split driving method and a display device providing the same.

According to the present embodiments, it is possible to provide a display device having a signal wiring structure for efficient divisional driving.

According to the present embodiments, it is possible to provide a display device capable of minimizing the number of signal wires for divided driving.

According to the present embodiments, a partial gate driving method and a display device providing the same can be provided.

According to the present embodiments, a gate driving method capable of reducing a driving time or power consumption and a display device providing the same can be provided.

1 is a schematic diagram of a display device according to exemplary embodiments.
2 is an exemplary diagram of a gate driver of a display device according to the present exemplary embodiments.
3 is a diagram illustrating an active area and its divided areas in a display panel of the display device according to the present exemplary embodiments.
4 is a diagram illustrating a grouping of gate driving integrated circuits for partial gate driving of a display device according to the present exemplary embodiments.
5 is a diagram illustrating control signal wiring for driving a partial gate of the display device according to the present exemplary embodiments.
6 is a detailed diagram illustrating a timing controller for driving a partial gate of a display device according to the present exemplary embodiments.
7 to 11 are exemplary diagrams of partial gate driving of the display device according to the present exemplary embodiments.
12 is an exemplary diagram for explaining the operation of gate driving integrated circuits in a gate driving group for partial gate driving of the display device according to the exemplary embodiments.
13A and 13B are views exemplarily showing an arrangement structure of gate driving integrated circuits according to the present embodiments.
14 is an exemplary view in which a display panel is divided into three partial regions to exemplarily describe a gate driving grouping structure and a signal wiring structure enabling divided driving according to the present exemplary embodiments, and a partial driving method based thereon; to be.
15A is a diagram illustrating a gate driving group for divided driving under the arrangement structure of the gate driving integrated circuits of FIG. 13A.
15B is a diagram illustrating a gate driving group for divisional driving under the arrangement structure of the gate driving integrated circuits of FIG. 13B.
16A is an exemplary diagram of a signal wiring structure for divided driving under the gate driving grouping structure of FIG. 15A.
16B is an exemplary diagram of a signal wiring structure for divided driving under the gate driving grouping structure of FIG. 15B.
Fig. 17A is a timing diagram of a group drive start signal and a group drive refresh signal under the signal wiring structure of Fig. 16A.
Fig. 17B is a timing diagram of a group drive start signal and a group drive refresh signal under the signal wiring structure of Fig. 16B.
18A is another exemplary diagram of a signal wiring structure for divided driving under the arrangement structure of the gate driving integrated circuits of FIG. 13A.
18B is another exemplary diagram of a signal wiring structure for divided driving under the arrangement structure of the gate driving integrated circuits of FIG. 13B.
18C is an exemplary diagram showing the configuration of a logic circuit when the number of gate driving groups N is 8 and the number of group control signals is 3.
Fig. 19A is a timing diagram of a group driving start signal and a group driving refresh signal for divided driving under the signal wiring structure of Fig. 18A.
Fig. 19B is a timing diagram of a group driving start signal and a group driving refresh signal for division driving under the signal wiring structure of Fig. 18B.
20 is a block diagram of a timing controller for driving a partial gate of a display device according to the present exemplary embodiments.
21 is a diagram illustrating a change in image data for each partial region between a previous frame and a current frame in the display device according to the exemplary embodiments.
22A and 22B are diagrams illustrating a state of outputting a scan signal for driving a partial gate under the image data change state of FIG. 21 in the display device according to the present exemplary embodiments.
23B is a group driving start signal for partial gate driving using a method of generating three group driving start signals using one group driving start reference signal and two group control signals, as shown in FIG. 19A. , Is a diagram showing a group driving refresh signal and a scan signal.
23B is a group driving start signal for partial gate driving by using a method of generating 6 group driving start signals using two group driving start reference signals and two group control signals, as shown in Fig. 19B. , Is a diagram showing a group driving refresh signal and a scan signal.
24A shows one group driving start reference signal GDS_REF and two group control signals using the method described with reference to FIG. 19A in order to partially drive only two partial regions PA #2 and PA #3. It is a diagram showing three group driving start signals (GDS #1, GDS #2, GDS #3) made using (C1, C2).
24B shows two group driving start reference signals GDSo_REF and GDSe_REF and two groups using the method described with reference to FIG. 19B in order to partially drive only two partial regions (PA #2 and PA #3). It is a diagram showing six group driving start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) made using the control signals (C1, C2).

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, the detailed description may be omitted.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a) and (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, the component may be directly connected or connected to that other component, but other components between each component It should be understood that "interposed" or that each component may be "connected", "coupled" or "connected" through other components.

1 is a schematic diagram of a display device 100 according to an exemplary embodiment.

Referring to FIG. 1, a display device 100 according to an exemplary embodiment includes a display panel 110, a data driver 120, a gate driver 130, a timing controller 140, and the like.

In the display panel 110, m data lines DL1 to DLm and n gate lines GL1 to GLn are formed, and the m data lines DL1 to DLm and n gate lines GL1 to GLn are formed. A plurality of pixels (P) are defined according to the intersection.

The data driver 120 supplies a data voltage to m data lines DL1 to DLm.

The data driver 120 may include a plurality of data driver ICs (also referred to as "source driving integrated circuits"), and the plurality of data driving integrated circuits include tape automated bonding (TAB: Tape Automated Bonding) or chip-on-glass (COG) is connected to the bonding pad of the display panel 110, or may be implemented in a GIP (Gate In Panel) type and directly formed on the display panel 110. In some cases, it may be integrated into the display panel 110.

The gate driver 130 is for sequentially supplying scan signals to n gate lines GL1 to GLn, and may include a plurality of gate driver ICs.

The gate driver 130 may be positioned on only one side of the display panel 110 as shown in FIG. 1, or may be divided into two and positioned on both sides of the display panel 110, depending on the driving method.

In addition, the gate driver 130 outputs one scan signal to one gate line in a single feeding method or two scans in one gate line in a double feeding method, depending on the driving method. You can also output a signal.

In addition, a plurality of gate driver ICs included in the gate driver 130 may be applied to the display panel 110 using a tape automated bonding (TAB) method or a chip-on-glass (COG) method. It may be connected to a bonding pad or implemented in a GIP (Gate In Panel) type to be directly formed on the display panel 110, or may be integrated into the display panel 110 in some cases.

However, in the following description, for convenience of explanation, it is assumed that a plurality of gate driver ICs included in the gate driver 130 are of the GIP (Gate In Panel) type, and the gate driving integrated circuit is " Also described as "Gate Driver IC In Panel (GIP)".

In this case, as illustrated in FIG. 2, which is an exemplary diagram of the gate driver 130, an image is displayed on the display panel 110 in an outer area (non-display area) of an active area (AA), which is a display area. A plurality of gate driving integrated circuits (GIP 1, GIP 2, ..., GIP n) may be disposed. In FIG. 2, it is shown that the gate driving integrated circuit is n equal to the number of gate lines (n). However, according to an implementation method such as a gate driving method (double feeding method), the number of gate driving integrated circuits is the number of gate lines (n ) And may be different (e.g. 2n).

The timing controller 140 controls driving timings of the data driver 120 and the gate driver 130 and outputs various control signals for this purpose.

Meanwhile, the display device 100 according to an exemplary embodiment may further include a system interface 150 for outputting an image signal (image data), various signals, and the like to the timing controller 140.

Meanwhile, the display device 100 according to an exemplary embodiment may scan all areas of the display panel 110 in order to display one frame, similar to the general gate driving method, that is, one In order to display a frame of, scan signals may be sequentially supplied to all n gate lines (GL1 to GLn), but in some cases, unlike the general gate driving method, "Partial Gate Drive" "You can do it.

Here, "Partial Gate Drive" means to scan only a partial area of the display panel 110 to display one frame, that is, to display one frame, n This means that scan signals are sequentially supplied to only some of the gate lines GL1 to GLn.

Conceptually, when the frame is changed, when the image change between the previous frame and the current frame occurs only in some areas, gate driving is performed on some areas where the image change occurs, and the area in which the image change does not occur. It means that gate driving is not performed.

For this partial gate driving, a screen division concept is proposed.

3 is a diagram illustrating an active area AA and divided areas PA of the display panel 110 of the display device 100 according to an exemplary embodiment.

Referring to FIG. 3, in relation to screen division for partial gate driving, an active area AA corresponding to a display area in which an image can be displayed on the display panel 110 is two or more partial areas PA. Partial Area; PA #1, PA #2, ..., PA #N, N≥2).

In each partial region, two or more gate lines are formed.

In order to drive such partial gates, a new concept of a virtual "Gate Driver IC Group (GDG)" is proposed as an aggregate (group) of gate driving integrated circuits that drive each partial region. This will be described with reference to FIG. 4.

4 is a diagram illustrating grouping of gate driving integrated circuits for partial gate driving of the display device 100 according to an exemplary embodiment.

Referring to FIG. 4, the gate driving group is a set or group of two or more gate driving integrated circuits.

One such gate driving group includes two or more gate driving integrated circuits, and corresponds to one partial area PA.

Accordingly, two or more gate driving integrated circuits included in one gate driving group output scan signals to two or more gate lines GL formed in the corresponding partial area PA.

Referring to FIG. 4, if n gate driving integrated circuits are grouped by k to form one gate driving group (GDG), N gate driving groups (GDG #1, GDG #2, ..., GDG #N) are Becomes (N<n, N*k=n).

4, k gate driving integrated circuits (GIP #i-1, GIP #i-2) included in each of the N gate driving groups (GDG #1, GDG #2, ..., GDG #N) , ..., GIP #ik, 1≤i≤N).

For example, if 270 of 1080 gate driving integrated circuits are grouped to form one gate driving group (GDG), there are 4 gate driving groups (GDG #1, GDG #2, GDG #3, GDG #4), Each gate driving group includes 270 gate driving integrated circuits (GIP #i-1, GIP #i-2, ..., GIP #i-270, 1≤i≤4).

4, N gate driving groups (GDG #1, GDG #2, ..., GDG #N) are N partial regions (PA #1, PA #2, ..., PA #N) Each corresponds to.

In addition, k gate driving integrated circuits (GIP #i-1, GIP #i-2, ...) included in each of the N gate driving groups (GDG #1, GDG #2, ..., GDG #N) , GIP #ik, 1≦i≦N) outputs a scan signal to a gate line formed in a corresponding partial region of the display panel 110.

For example, GDG #1 contains GIP #1-1, GIP #1-2, ..., GIP #1-k, and GIP #1-1, GIP #1-2, ..., GIP #1-k sequentially outputs scan signals to k gate lines (GL #1-1, GL #1-2, ..., GL #1-k) formed in PA #1 corresponding to GDG #1 do.

Meanwhile, for partial gate driving, it is necessary to know whether the gate driving integrated circuit included in each gate driving group should be operated (scan signal output) to drive this frame.

Therefore, whether each of the N gate driving groups (GDG #1, GDG #2, ..., GDG #N) operates, that is, the N gate driving groups (GDG #1, GDG #2, ..., GDG #N) N gate driving groups (GDG #1, GDG #2, ..., GDG #N) control signals to inform whether or not scan signals should be output from two or more gate driving integrated circuits included in each. Each of them must be input to the gate driving group to be operated.

5 is a diagram illustrating control signal wiring for driving a partial gate of the display device 100 according to an exemplary embodiment.

Referring to FIG. 5, a control signal for partial gate driving includes a group drive start signal (GDS: Group Drive Start) for indicating the start of the operation of the corresponding gate driving group, and a group drive start signal for indicating the end of the operation of the corresponding gate driving group. It includes a group drive refresh signal (GDR).

Referring to FIG. 5, in order for a corresponding gate driving group to receive control signals (GDS, GDR) for partial gate driving, a control signal wiring through which control signals (GDS, GDR) are input to each gate driving group is shown on the display panel. It may be formed in (110).

Referring to FIG. 5, of the control signals for partial gate driving, GDS may be input to a first gate driving integrated circuit among gate driving integrated circuits included in each gate driving group. In addition, of the control signals for partial gate driving, GDR may be input to the last gate driving integrated circuit among the gate driving integrated circuits included in each gate driving group.

Accordingly, as shown in FIG. 5, among the gate driving integrated circuits included in each gate driving group, the first gate driving integrated circuit is connected to the GDS signal line through which the GDS is transmitted. Among the gate driving integrated circuits included in each gate driving group, the last gate driving integrated circuit is connected to the GDR signal wiring through which the GDR is transmitted.

The timing and region control of the partial gate driving described above, i.e., control over which gate driving group should be operated (which partial region should be driven in one frame) and the operation timing of the gate driving group to be operated, etc. This can be done by the controller 140.

The timing controller 140 included in the display device 100 according to an exemplary embodiment is selected for driving one frame from among two or more gate driving groups GDG including a plurality of gate driving integrated circuits. Controls to sequentially output scan signals from two or more gate driving integrated circuits included in the gate driving group.

The timing controller 140 may output at least two scan signals for driving the current frame among a plurality of gate driving integrated circuits based on a result of comparing image data between the current frame to be displayed and the previous frame displayed previously. One or more gate driving groups including the gate driving integrated circuit may be selected from two or more gate driving groups, and a scan signal may be output only from two or more gate driving integrated circuits included in the selected gate driving group.

In more detail, the timing controller 140 outputs a scan signal to a gate line formed in an image change region among a plurality of gate driving integrated circuits based on a result of comparing image data between the current frame and the previous frame. One or more gate driving groups including the gate driving integrated circuit may be selected from two or more gate driving groups.

In relation to the output of the control signal for partial gate driving, the timing controller 140 supplies a group driving start signal GDS and a group driving refresh signal GDR to each of the gate driving groups selected from two or more gate driving groups. , At least one upper gate driving group in an ascending driving order among the selected gate driving groups (when all the gate driving groups operate, a gate driving group including a gate driving integrated circuit that first outputs a scan signal, and the following One more gate driving group may be included), a gate start signal VST is further supplied. Here, the gate start signal VST is a control signal applied to the first gate driving junction circuit(s) to indicate the start of a frame in general gate driving. In addition, the timing controller 140 may output at least one lower gate driving group according to a descending driving order among gate driving groups selected from two or more gate driving groups (when all the gate driving groups operate, the scan signal is last output. A gate and signal VEND may be further supplied to a gate driving group including the gate driving integrated circuit and one more gate driving group prior to the gate driving group. Here, the gate and signal VEND is a control signal applied to the last gate driving junction circuit(s) to indicate the end of the frame in general gate driving.

Accordingly, regardless of the gate start signal (VST) and the gate-and signal (VEND) for indicating the start and end of driving of one frame, a group driving start signal is selected from all gate driving groups and is applied to each gate driving group to be operated. (GDS) and a group driving refresh signal (GDR) are applied.

Meanwhile, the timing controller 140 supplies only one of a group driving start signal GDS and a gate start signal VST to at least one upper gate driving group in an ascending driving order among gate driving groups selected from all gate driving groups. do. In addition, the timing controller 140 supplies only one of a group driving refresh signal GDR and a gate AND signal VEND to at least one lower gate driving group in a descending driving order among the selected gate driving groups. In addition, the timing controller 140 may supply a group driving start signal GDS and a group driving refresh signal GDR to each of the intermediate gate driving groups excluding the upper gate driving group and the lower gate driving group among the selected gate driving groups. I can.

According to this, since the gate start signal VST and the gate AND signal VEND for indicating the start and end of driving of one frame are applied to the first gate driving group and the last gate driving group, respectively, for partial gate driving , When the first gate driving group is operated, the group driving start signal (GDS) does not need to be input to the first gate driving group, and the role of the group driving refresh signal (GDR) is replaced by the gate start signal (VST). can do. In addition, for partial gate driving, when the last gate driving group is operated, the group driving refresh signal GDR does not need to be input to the last gate driving group, and the gate and end play the role of the group driving refresh signal GDR. It can be replaced with a signal (VEND).

Meanwhile, at least one of the highest gate driving group among the upper gate driving groups and the lowest gate driving group among the lower gate groups may further include one or more dummy gate driving integrated circuits. The dummy gate driving integrated circuit may receive a gate start signal VST and a gate AND signal VEND.

Hereinafter, an internal configuration of the timing controller 140 capable of controlling partial gate driving will be described with reference to FIG. 6.

6 is a detailed diagram illustrating a timing controller 140 for driving a partial gate of the display device 100 according to an exemplary embodiment.

Referring to FIG. 6, the timing controller 140 includes a first frame buffer 620 that stores image data of a current frame input from the system interface 150 and a new current frame in the first frame buffer 620. When the image data RGB is input, the second frame buffer 630 receives and stores image data of the previous frame stored in the first frame buffer 620 and the previous frame stored in the second frame buffer 630. By comparing the image data with the image data of the current frame stored in the first frame buffer 620, a gate driving group including gate driving integrated circuits to be actually operated is selected from among the entire gate driving groups, and according to the result, a partial gate And a control unit 610 that outputs the control signals GDS and GDR for driving to the first gate driving integrated circuit and the last gate driving integrated circuit among the gate driving integrated circuits included in the selected gate driving group.

The control unit 610 of the timing controller 140 equally allocates the frame driving time to each of the two or more gate driving groups, and corresponds to each of the start points of the time allocated to each of the selected gate driving groups, so that the corresponding group driving start signal The timing can be controlled so that (GDS) is supplied.

In this case, the frame driving time is the same for every frame regardless of the number of selected gate driving groups, and the driving time and frame driving time allocated to each of the selected gate driving groups are allocated to each of the unselected gate driving groups. The rest time is the same.

Alternatively, the control unit 610 of the timing controller 140 allocates the frame driving time only to each of the selected gate driving groups, and corresponds to each start point of the time allotted to each of the selected gate driving groups, and the corresponding group driving start signal The timing can be controlled so that (GDS) is supplied.

In this case, the frame driving time is shortened as the number of selected gate driving groups decreases.

7 to 11 are exemplary diagrams of partial gate driving of the display device 100 according to an exemplary embodiment.

7 is a conceptual diagram exemplarily showing a previous frame and a current frame in which image data are compared when a gate driving group is selected to illustrate a partial gate driving method.

Referring to FIG. 7, compared to the previous frame, the current frame includes two parts including PA #2 and PA #3 among four partial areas (PA #1 to PA #4) in which the display area AA is divided. It can be seen that the image change occurred only in the area.

The timing controller 140 recognizes that there is an image change in PA #2 and PA #3, and that there is no image change in PA #1 and PA #4, through image data comparison, and the partial region with image change (PA # 2, A gate driving group including gate driving integrated circuits capable of outputting a scan signal to a gate line formed in PA #3) is selected.

Here, for partial gate driving, selecting a gate driving group to be actually operated (driving) from among all the gate driving groups is the same as selecting gate driving integrated circuits that actually output a scan signal from among all gate driving integrated circuits. .

Thereafter, the timing controller 140 selects a group driving start signal (GDS) and a group driving refresh signal (GDR), which are two control signals for partial gate driving, as a first gate driving integrated circuit included in each of the selected gate driving groups. And output to the last gate driving integrated circuit.

FIG. 8 is a diagram conceptually showing that only a part of the entire gate driving group is operated and gate line driving is performed only in a partial region.

Referring to FIG. 8, only the gate driving integrated circuits included in the gate driving group (GDG #2, GDG #3) selected from the entire gate driving group (GDG #1 to GDG #4) by the timing controller 140 The scan signals are sequentially output, and the scan signals are not output from the gate driving integrated circuits included in the remaining gate driving groups GDG #1 and GDG #4.

Accordingly, in the display area AA consisting of four partial areas (PA #1 to PA #4), driving is only possible in the two partial areas (PA #2, PA #3) identified as partial areas with image change. It happens.

9 is, as in FIG. 8, by the timing controller 140, the gate driving included in the gate driving group (GDG #2, GDG #3) selected from the entire gate driving group (GDG #1 to GDG #4) The timing controller 140 transmits a group driving start signal GDS and a group driving refresh signal GDR only to each of the selected gate driving groups (GDG #2 and GDG #3) so that scan signals are sequentially output only from the integrated circuits. Print it out.

10 and 11 are 2 showing timing when the timing controller 140 outputs a group driving start signal GDS and a group driving refresh signal GDR to each of the selected gate driving groups GDG #2 and GDG #3. It is a timing diagram.

Referring to FIG. 10, the timing controller 140 evenly allocates the frame driving time to each of the four gate driving groups GDG #1 to GDG #4. Accordingly, the time allotted to each of the four gate driving groups GDG #1 to GDG #4 is the same, and the frame driving time is the same for every frame.

Referring to FIG. 10, the timing controller 140 selects GDG #2 and GDG #3 for partial gate driving, if the previous example is applied as it is, so the time allocated to GDG #2 is GDG #2. It is the driving time, the time allotted to GDG #4 is the GDG #4 driving time, the time allotted to GDG #1 is the GDG #1 rest time (rest time), and the time allotted to GDG #4 is GDG #4 rest It is time (break time).

Referring to FIG. 10, by GDS #2 supplied to GDG #2, two or more gate driving integrated circuits (GIP #2-1, GIP #2-2, ...) included in GDG #2 are scanned signals. Is output in sequence. Subsequently, by GDR #2 supplied to GDG #2 and GDS #3 supplied to GDG #3, two or more gate driving integrated circuits included in GDG #3 (GIP #3-1, GIP #3-2,. ..) sequentially outputs scan signals.

According to the timing control method of the timing controller 140 as illustrated in FIG. 10, the frame driving time may be unnecessarily lengthened due to the GDG #1 pause time and the GDG #4 pause time.

11 shows a timing diagram according to the timing control method of the timing controller 140 for eliminating this point.

Referring to FIG. 11, unlike the timing control method of FIG. 10, the timing controller 140 does not evenly allocate the frame driving time to each of the entire gate driving groups (GDG #1 to GDG #4). It is assigned only to each of the gate driving groups (GDG #2 and GDG #3) selected from the driving groups (GDG #1 to GDG #4).

The timing controller 140 corresponds to each start point of the time allocated to each of the gate driving groups GDG #2 and GDG #3 selected from the entire gate driving group (GDG #1 to GDG #4), and starts driving the corresponding group. The timing can be controlled so that the signals GDS #2 and GDS #3 are supplied.

In this case, the frame driving time may be shortened as the number of selected gate driving groups decreases. Accordingly, as there are more partial areas with image change and no screen change, the time taken to drive one frame is shortened, thereby reducing unnecessary waste of time and power consumption accordingly.

The timing controller 140 corresponds to each start point of the time allocated to each of the gate driving groups GDG #2 and GDG #3 selected from the entire gate driving group (GDG #1 to GDG #4), and starts driving the corresponding group. The timing can be controlled so that the signals GDS #2 and GDS #3 are supplied.

12 illustrates gate driving integrated circuits GIP i-1, GIP i-2, ..., GIP i-Kk in a gate driving group GDG for partial gate driving of the display device 100 according to an exemplary embodiment. ) Is an exemplary diagram for explaining the operation.

As shown in (b) of FIG. 12, the (partial) gate driving may be performed in a four-phase driving method using four clock signals CLK 1 to CLK 4.

Referring to (a) of FIG. 12, GIP i-1 of the first stage of the i-th gate driving group (GDG #i) receives a group driving start signal (GDS #1) through GDS signal wiring. . Accordingly, the scan signal Vgout from the k gate driving integrated circuits (GIP #i-1, GIP #i-2, ..., GIP #ik) included in the i-th gate driving group (GDG #i) is It is output sequentially.

Referring to FIG. 12, according to the four-phase driving method, the scan signal Vgout output from the gate driving integrated circuit of the j-th stage is input as a driving start signal Vst to the gate driving integrated circuit of the j+2nd stage. At the same time, the reset signal Vnext is input to the gate driving integrated circuit of the j-2 th stage.

In addition to the four-phase driving method as shown in FIG. 12, it may be driven in a two-phase, six-phase, or eight-phase driving method.

The partial gate driving of the display device 100 according to the exemplary embodiment described above will be briefly summarized below.

If the concept of the gate driving group is not considered, the timing controller 140 controls scan signals to be sequentially output only from two or more gate driving integrated circuits selected for driving one frame among a plurality of gate driving integrated circuits.

The timing controller 140 includes two or more gate driving integrated circuits that output a scan signal to a gate line formed in an image change region among a plurality of gate driving integrated circuits through image data comparison between a current frame and a previous frame. You can choose.

In the above-described partial gate driving method, the timing controller 140 selects some or all of the gate driving groups for driving one frame from among two or more gate driving groups including a plurality of gate driving integrated circuits (STEP 1) and controlling the timing controller 140 to sequentially output scan signals from two or more gate driving integrated circuits included in each of the selected gate driving groups (STEP 2).

In addition, the display panel 110 for partial gate driving includes gate lines GL1 to GLn formed in a first direction, data lines DL1 to DLm formed in a second direction crossing the first direction, It includes a plurality of gate driver ICs arranged to supply scan signals to the gate lines GL1 to GLn. Here, only some of the plurality of gate driving integrated circuits may output a scan signal for driving one frame.

In the above, a divided driving method and a partial driving method for effective gate driving have been described. Hereinafter, a gate driving grouping structure and a signal wiring structure enabling divided driving for effective gate driving, and a partial driving method based on the gate driving grouping structure will be exemplarily described.

The display device 100 according to the present exemplary embodiments includes a display panel 110 on which m data lines DL1, ..., DLm and n gate lines GL1, ..., GLn are arranged, The data driver 120 drives m data lines DL1, ..., DLm, and drives n gate lines GL1, ..., GLn, and drives n gate driving integrated circuits (GIP #1). , ..., GIP #n), including a gate driver 130, a data driver 120 and a timing controller 140 for controlling the gate driver 130, and the like.

n gate driving integrated circuits (GIP #1, ..., GIP #n) are divided by M (M is a natural number of 2 or more) and N (N is a natural number of 2 or more) gate driving groups (GDG #1,. .., GDG #N) (n=N×M, n is the number of gate lines, N is the number of gate driving groups, M is the number of gate driving integrated circuits in one gate driving group).

The N gate driving groups GDG #1, ..., GDG #N correspond to the N partial regions PA #1, ..., PA #N in which the display panel 110 is divided.

In addition, the N gate driving groups GDG #1, ..., GDG #N operate independently of each other (gate driving operation such as scan signal output) by a group driving start signal and a group driving refresh signal.

As described above, by allowing the display panel 110 to be dividedly driven, the time for driving the entire display panel 110 can be shortened or the driving efficiency can be increased, or in some cases, the display panel 110 By driving only a part of ), the driving efficiency can be significantly increased and the driving time can be greatly shortened.

Below, n corresponding to the number of gate lines and the number of gate driving integrated circuits is 12, N corresponding to the number of partial regions and the number of gate driving groups is 3, and gate driving integrated included in one gate driving group (GDG). It is assumed that M corresponding to the number of circuits is 4.

13A and 13B are views exemplarily showing an arrangement structure of gate driving integrated circuits according to the present embodiments.

13A, 12 gate driving integrated circuits GIP #1, ..., GIP #12 driving 12 gate lines GL1, ..., GL12 are one side of the display panel 110 May be placed all in.

Unlike the one-side arrangement structure shown in FIG. 13A, as shown in FIG. 13B, the gate driver 130 is disposed on one side and is odd-numbered gate lines GL1, GL3, ..., GL11. ) And a gate driver 130e disposed on the other side and driving the even-numbered gate lines GL2, GL4, ..., GL2.

13B, among 12 gate driving integrated circuits (GIP #1, ..., GIP #12), odd-numbered gate lines GL1, GL3, among 12 gate lines GL1, ..., GL12, The odd-numbered gate driving integrated circuits (GIP #1, GIP #3, ..., GIP #11) driving the ..., GL11 are disposed on one side of the display panel 110.

13B, the even gate driving integrated circuit (GIP #2, GIP) driving the even gate lines GL2, GL4, ..., GL12 among 12 gate lines GL1, ..., GL12. #4, ..., GIP #12 may be disposed on the other side of the display panel 110.

In the present specification, as an example, the number of gate lines and the number of gate driving integrated circuits are illustrated as being the same, but in some cases, the number of gate lines may be greater than the number of gate driving integrated circuits.

Below, for each of the arrangement structure on one side of the gate driving unit 130 illustrated in FIG. 13A and the arrangement structure on both sides of the gate driving unit 130 illustrated in FIG. 13B, a gate enabling divisional driving for effective gate driving. A driving grouping structure and a signal wiring structure, and a partial driving method based thereon will be exemplarily described.

14 illustrates a gate driving grouping structure and a signal wiring structure enabling divisional driving according to the present embodiments, and a partial driving method based thereon, in which the display panel 110 is divided into three partial regions. This is an exemplary diagram (ie, N=3).

Referring to FIG. 14, an active area AA in which an image is displayed on the display panel 110 is divided into three partial areas PA #1, PA #2, and PA #3.

15A shows three gate driving groups for divided driving (GDG #1) under the arrangement structure (one-side arrangement structure) of 12 gate driving integrated circuits (GIP #1, ... GIP #12) in FIG. 13A. , GDG #2, GDG #3) is an exemplary diagram.

Referring to FIG. 15A, 12 gate driving integrated circuits (GIP #1, GIP #2, ..., GIP #12) are grouped by four and three gate driving groups (GDG #1, GDG #2, GDG #3). ).

Accordingly, GDG #1 is a gate driving group that drives PA #1, and includes GIP #1, GIP #2, GIP #3, and GIP #4. GDG #2 is a gate drive group for driving PA #2, and includes GIP #5, GIP #6, GIP #7, and GIP #8. GDG #3 is a gate drive group that drives PA #3, and includes GIP #9, GIP #10, GIP #11, and GIP #12.

Referring to FIG. 15A, for convenience of explanation, the shape of the GIP identifier appended to the "GIP" is changed from "# number" to "# number (GDG identifier)-number (GIP identifier in GDG)".

That is, GIP #1, GIP #2, GIP #3 and GIP #4 included in GDG #1 are described as GIP #1-1, GIP #1-2, GIP #1-3 and GIP #1-4, and , GIP #5, GIP #6, GIP #7 and GIP #8 included in GDG #2 are described as GIP #2-1, GIP #2-2, GIP #2-3 and GIP #2-4, GIP #9, GIP #10, GIP #11 and GIP #12 included in GDG #3 are described as GIP #3-1, GIP #3-2, GIP #3-3 and GIP #3-4.

15B shows three gate driving groups for divided driving (GDG #1, GDG) under the arrangement structure (both arrangement structure) of the 12 gate driving integrated circuits (GIP #1, ... GIP #12) of FIG. 13B. #2, GDG #3) is an exemplary diagram.

Referring to FIG. 15B, each of the three gate driving groups GDG #1, GDG #2, and GDG #3 includes an odd gate driving group including odd gate driving integrated circuits and an even gate driving integrated circuit. It includes an even gate driving group.

More specifically, GDG #1 is an odd-numbered gate driving integrated circuit (GIP #1-1, GIP #1-3) that drives the odd-numbered gate lines GL 1-1 and GL 1-3 in PA #1. ), and an even gate driving integrated circuit (GIP #1-2, GIP) that drives the even gate line (GL 1-2, GL 1-4) in PA #1 and the odd gate driving group GDG #1o. The odd gate driving group GDG #1e including #1-4) is included.

GDG #2 includes odd-numbered gate driving integrated circuits (GIP #2-1, GIP #2-3) that drive odd-numbered gate lines (GL 2-1, GL 2-3) in PA #2. Odd gate driving group GDG #2o and even gate driving integrated circuits (GIP #2-2, GIP #2-4) driving even gate lines (GL 2-2, GL 2-4) in PA #2 An odd gate driving group GDG #2e including) is included.

GDG #3 includes odd-numbered gate driving integrated circuits (GIP #3-1, GIP #3-3) that drive odd-numbered gate lines (GL 3-1, GL 3-3) in PA #3. Odd gate driving group GDG #3o and even gate driving integrated circuits (GIP #3-2, GIP #3-4) driving even gate lines (GL 3-2, GL 3-4) in PA #3 ) And an odd gate driving group GDG #3e.

16A is an exemplary diagram of a signal wiring structure for divided driving under the gate driving grouping structure of FIG. 15A.

Referring to FIG. 16A, in order to supply a group driving start signal (GDS #1, GDS #2, GDS #3) corresponding to each of three gate driving groups (GDG #1, GDG #2, GDG #3), Three group drive start signal wires (GDSL #1, GDSL #2, GDSL #3) are arranged in correspondence with three gate drive groups (GDG #1, GDG #2, GDG #3).

Referring to FIG. 16A, that is, GDS #1 is supplied to GDG #1 (eg, GIP #1-1 included in GDG #1) through GDSL #1. GDS #2 is supplied to GDG #2 (eg, GIP #2-1 included in GDG #2) through GDSL #2. GDS #3 is supplied as GDG #3 (eg, GIP #3-1 included in GDG #3) through GDSL #3.

Referring to FIG. 16A, in order to supply one group driving refresh signal GDR corresponding to three gate driving groups (GDG #1, GDG #2, GDG #3), one group driving refresh signal wiring (GDRL) can be deployed.

Unlike FIG. 16A, in order to supply three group driving refresh signals corresponding to each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), three group driving refresh signal lines are arranged. May be.

Using the above-described signal wiring structure, it is possible to accurately and independently control the driving start and end of each of the three gate driving groups (GDG #1, GDG #2, and GDG #3).

16B is an exemplary diagram of a signal wiring structure for divided driving under the gate driving grouping structure of FIG. 15B.

Referring to FIG. 16B, each of the three gate driving groups GDG #1, GDG #2, and GDG #3 includes an odd gate driving group including odd gate driving integrated circuits and an even gate driving integrated circuit. It includes an even gate driving group.

Referring to FIG. 16B, GDG #1 is an odd gate driving group GDG #1o including GIP #1-1 and GIP #1-3, and an odd gate including GIP #1-2 and GIP #1-4. Includes drive group GDG #1e. GDG #2 includes an odd gate driving group GDG #2o including GIP #2-1 and GIP #2-3, and an odd gate driving group GDG #2e including GIP #2-2 and GIP #2-4. Includes. GDG #3 includes an odd gate driving group GDG #3o including GIP #3-1 and GIP #3-3, and an odd gate driving group GDG #3e including GIP #3-2 and GIP #3-4. Includes.

Referring to FIG. 16B, for each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), a group driving corresponding to an odd gate driving group (GDG #1o, GDG #2o, GDG #3o) A start signal (GDS #1o, GDS #2o, GDS #3o) is supplied, and a group drive start signal (GDS #1e, GDS #) corresponding to an even gate drive group (GDG #1e, GDG #2e, GDG #3e) is supplied. 2e, GDS #3e), 2×3 group drive start signal wires (GDSL #1o, GDSL #2o, GDSL #3o, GDSL #1e, GDSL #2e, GDSL #3e) can be arranged. .

That is, GDS #1o is supplied to GDG #1o of GDG #1 through GDSL #1o, and GDS #1e is supplied to GDG #1e of GDG #1 through GDSL #1e. GDS #2o is supplied to GDG #2o of GDG #2 through GDSL #2o, and GDS #2e is supplied to GDG #2e of GDG #2 through GDSL #2e. GDS #3o is supplied to GDG #3o of GDG #3 through GDSL #3o, and GDS #3e is supplied to GDG #3e of GDG #3 through GDSL #3e. GDS #4o is supplied to GDG #4o of GDG #4 through GDSL #4o, and GDS #4e is supplied to GDG #4e of GDG #4 through GDSL #4e.

Referring to FIG. 16B, for each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), a group driving corresponding to an odd gate driving group (GDG #1o, GDG #2o, GDG #3o) To supply a refresh signal (GDRo) and a group driving refresh signal (GDRe) corresponding to an even gate driving group (GDG #1e, GDG #2e, GDG #3e), two group driving refresh signals Wirings GDRLo and GDRe may be arranged.

Unlike FIG. 16B, for each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), a group driving corresponding to each of the odd gate driving groups (GDG #1o, GDG #2o, and GDG #3o) In order to supply a refresh signal and supply a group drive refresh signal corresponding to each of the even gate drive groups (GDG #1e, GDG #2e, GDG #3e), 2x3 group drive refresh signal lines are arranged. It could be.

Using the signal wiring structure as described above, under the odd/even (Odd/Even) gate driving method, the driving start and end of each of the three gate driving groups (GDG #1, GDG #2, GDG #3) are accurately Can be controlled independently.

17A shows three group driving start signals (GDS #1, GDS #2, GDS #) supplied to each of three gate driving groups (GDG #1, GDG #2, and GDG #3) under the signal wiring structure of FIG. 16A. 3) and the timing diagram of the group drive refresh signal GDR.

Referring to FIG. 17A, in order to inform the start of gate driving of each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), three group driving start signals (GDS #1, GDS #2, and GDS #3) is supplied to each of the three gate driving groups (GDG #1, GDG #2, and GDG #3).

That is, GDS #1 is a control signal indicating the start of gate driving of GDG #1, and is supplied to GIP #1-1 of GDG #1. GDS #2 is a control signal indicating the start of gate driving of GDG #2, and is supplied to GIP #2-1 of GDG #2. GDS #3 is a control signal indicating the start of gate driving of GDG #3, and is supplied to GIP #3-1 of GDG #3.

Referring to FIG. 17A, a group driving refresh signal GDR is a control signal for indicating the end of gate driving of each of three gate driving groups (GDG #1, GDG #2, and GDG #3). The signal level (LOW->HGH or HIGH->LOW) changes at the end timing of the gate driving of each of the gate driving groups (GDG #1, GDG #2, and GDG #3).

In the case of the example of FIG. 17A, the group driving refresh signal GDR is maintained at a low level (LOW), then changed to a high level (HIGH) at the timing when the gate driving of GDG #1 is finished, and then changed to a low level (LOW). It is kept off, and it changes back to the high level (HIGH) at the timing when the gate driving of GDG #2 is finished, and then falls to the low level (LOW), and remains at a high level (HIGH) when the gate driving of GDG #3 ends. It changes back to and stays at a low level (LOW).

In the example of FIG. 17A, at the end timing of the gate driving of each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), the group driving refresh signal GDR represents a rising signal waveform. However, differently, each of the three gate driving groups (GDG #1, GDG #2, and GDG #3) may have a signal waveform falling at the end timing of the gate driving.

Referring to FIG. 17A, the polling timing (eg FT_G2_S) of the group driving start signal (eg GDG #2) corresponding to the i-th gate driving group (eg GDG #2) is the i-1th gate driving group ( Example: It corresponds to the rising timing (eg, RT_G1_E) of the group driving refresh signal GDR corresponding to GDG #1).

Unlike FIG. 17A, the rising timing of the group driving start signal (eg, GDG #2) corresponding to the i-th gate driving group (eg, GDG #2) is the i-1th gate driving group (eg, GDG #1). It may correspond to the polling timing of the group driving refresh signal GDR corresponding to.

Referring to FIG. 17A, the driving time of GDG #1 is a time from the polling timing (or rising timing) of GDS #1 to the rising timing (polling timing) corresponding to GDR #1. The driving time of GDG #2 is the time from the polling timing (or rising timing) of GDS #2 to the rising timing (polling timing) corresponding to GDR to GDG #2. The driving time of GDG #3 is the time from the polling timing (or rising timing) of GDS #3 to the rising timing (polling timing) corresponding to GDR to GDG #3.

17B shows six group drive start signals (GDS #1o, GDS #1e, and GDS #) supplied to each of three gate drive groups (GDG #1, GDG #2, and GDG #3) under the signal wiring structure of FIG. 16B. 2o, GDS #2e, GDS #3o, GDS #3e) and two group driving refresh signals (GDRo, GDRe) are timing diagrams.

Referring to FIG. 17B, in order to indicate the start of gate driving of each of the odd gate driving group and the even gate driving group included in each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), six Group drive start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) are connected to each of the three gate drive groups (GDG #1, GDG #2, GDG #3). It is supplied to each of the included odd-numbered gate driving groups and the even-numbered gate driving groups.

That is, GDS #1o is a control signal indicating the start of gate driving of GDG #1o included in GDG #1, and is supplied to GIP #1-1 of GDG #1o. GDS #1e is a control signal indicating the start of gate driving of GDG #1e included in GDG #1, and is supplied to GIP #1-2 of GDG #1e.

GDS #2o is a control signal indicating the start of gate driving of GDG #2o included in GDG #2, and is supplied to GIP #2-1 of GDG #2o. GDS #2e is a control signal indicating the start of gate driving of GDG #2e included in GDG #2, and is supplied to GIP #2-2 of GDG #2e.

GDS #3o is a control signal indicating the start of gate driving of GDG #3o included in GDG #3, and is supplied to GIP #3-1 of GDG #3o. GDS #3e is a control signal indicating the start of gate driving of GDG #3e included in GDG #3, and is supplied to GIP #3-2 of GDG #3e.

Referring to FIG. 17B, two group driving refresh signals GDRo and GDRe are an odd gate driving group and an even gate driving group included in each of three gate driving groups (GDG #1, GDG #2, and GDG #3). As a control signal to inform the end of gate driving of each group, the gate driving of each of the odd gate driving group and the even gate driving group included in each of the three gate driving groups (GDG #1, GDG #2, GDG #3) At the end timing of the signal level (LOW->HGH or HIGH->LOW) changes.

In the case of the example of FIG. 17B, of the two group driving refresh signals GDRo and GDRe, the odd gate driving groups GDG # included in each of the three gate driving groups GDG #1, GDG #2, and GDG #3. 1o, GDG #2o, GDG #3o) GDRo to indicate the end of gate driving is maintained at a low level (LOW), then changed to a high level (HIGH) when the gate driving of GDG #1o ends and then low. It is kept falling to the level (LOW), and it is changed back to the high level (HIGH) at the timing when the gate driving of GDG #2o is finished, and then it falls to the low level (LOW), and is maintained at the timing when the gate driving of GDG #3o ends. It changes back to the level (HIGH) and then falls back to the low level (LOW).

In addition, of the two group driving refresh signals (GDRo, GDRe), even gate driving groups (GDG #1e, GDG #2e) included in each of the three gate driving groups (GDG #1, GDG #2, GDG #3). , GDRe to indicate the end of gate driving of GDG #3e) is maintained at a low level (LOW), then changes to a high level (HIGH) when the gate driving of GDG #1e ends, and then goes to a low level (LOW). It is kept apart, and it changes back to high level (HIGH) at the timing when the gate driving of GDG #2e is finished, then remains off to a low level (LOW), and goes to high level (HIGH) when the gate driving of GDG #3e ends. It changes back and stays at a low level (LOW).

In the example of FIG. 17B, at the end timing of the gate driving of each of the odd gate driving group and the even gate driving group included in each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), the group driving refresh The signals GDRo and GDRe have a rising signal waveform, but differently, the odd gate driving group and the even gate included in each of the three gate driving groups (GDG #1, GDG #2, and GDG #3) Each of the driving groups may have a signal waveform falling at the end timing of driving the gate.

Referring to FIG. 17B, a rising timing of a group driving start signal (eg GDS #2o) corresponding to an odd gate driving group (eg GDG #2o) included in the i-th gate driving group (eg GDG #2) ( Example: RT_G2O_S) is the polling timing of the group driving refresh signal (GDR) corresponding to the even gate driving group (eg GDG #1e) included in the i-1th gate driving group (eg GDG #1). : May correspond to FT_G1E_E).

Unlike this, the polling timing of the group driving start signal (eg GDS #2o) corresponding to the odd gate driving group (eg GDG #2o) included in the i-th gate driving group (eg GDG #2) is i- It may correspond to the rising timing of the group driving refresh signal GDR corresponding to the even gate driving group (eg, GDG #1e) included in the first gate driving group (eg, GDG #1).

Referring to FIG. 17B, the driving time of GDG #1 is a time from the polling timing (or rising timing) of GDS #1o to the rising timing (polling timing) corresponding to GDR #1e. The driving time of GDG #2 is the time from the polling timing (or rising timing) of GDS #2o to the rising timing (polling timing) corresponding to GDR to GDG #2e. The driving time of GDG #3 is the time from the polling timing (or rising timing) of GDS #3o to the rising timing (polling timing) corresponding to the GDR to GDG #3e.

As described above, the rising timing of the group driving start signal (eg GDS #2o) corresponding to the odd gate driving group (eg GDG #2o) included in the i-th gate driving group (eg GDG #2) : RT_G2O_S) is the polling timing of the group driving refresh signal (GDR) corresponding to the even gate driving group (eg GDG #1e) included in the i-1th gate driving group (eg GDG #1). FT_G1E_E), as shown in FIG. 17B, a pause time may exist between driving times of each of the three gate driving groups (GDG #1, GDG #2, and GDG #3).

To avoid such a pause time, the polling timing of the group drive start signal (e.g. GDS #2o) corresponding to the odd gate drive group (e.g. GDG #2o) included in the i-th gate drive group (e.g. GDG #2). In order to correspond to the rising timing of the group driving refresh signal (GDR) corresponding to the even gate driving group (eg GDG #1e) included in the i-1th gate driving group (eg GDG #1), the signal waveform You can adjust it.

In order to drive the divided gate under the one-side arrangement structure, to supply the group driving start signals (GDS #1, GDS #2, GDS #3) as shown in FIG. 17A, the number of gate driving groups as shown in FIG. 16A It requires N group drive start signal wires (GDSL #1, GDSL #2, GDSL #3).

In addition, in order to supply the group driving start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) as shown in FIG. , As shown in FIG. 16B, group drive start signal wirings (GDSL #1o, GDSL #1e, GDSL #2o, GDSL #2e, GDSL #3o, GDSL #3e) as much as twice the number of gate drive groups N. need.

Hereinafter, in order to reduce the number of such group driving start wirings, a new signal wiring structure and a group driving start signal generation method will be described.

18A is another exemplary diagram of a signal wiring structure for divided driving under the arrangement structure of one side of the gate driving integrated circuits of FIG. 13A. 19A is a timing diagram of a group driving start signal and a group driving refresh signal GDR for divided driving under the signal wiring structure of FIG. 18A.

Referring to FIG. 18A, in order to supply three group driving start signals (GDS #1, GDS #2, GDS #3) in correspondence with three gate driving groups (GDG #1, GDG #2, GDG #3). , 1 group drive start signal wiring (GDSL), and L group control signal wirings (CL #1, CL #2, ..., CL #L, L are natural numbers of 2 or more, in Fig. 18A, L = 2) Is disposed, and N logic circuits (in the case of N=3, LC #1, LC #2, and LC #3) equal to the number of gate driving groups (eg, N=3) are disposed.

Each of the N logic circuits (LC #1, LC #2, and LC #3 when N=3) has one group drive start reference signal (GDS_REF) and L group control signals (C1 when L=2). , C2) is received, and a group driving start signal to be supplied to the corresponding gate driving group is output.

For example, LC #1 receives GDS_REF and outputs GDS #1 using two group drive control signals (C1, C2), and LC #2 receives GDS_REF and receives two group drive control signals (C1, C2). C2) is used to output GDS #2, and LC #3 receives GDS_REF and outputs GDS #3 using two group drive control signals (C1, C2).

Further, referring to FIG. 18A, in order to supply a group driving refresh signal GDR to three gate driving groups (GDG #1, GDG #2, GDG #3), one group driving refresh signal line GDRL ) Or N (e.g., N=3) group drive refresh signal lines are arranged.

In the case of using the signal wiring structure of FIG. 18A, compared to the signal wiring structure of FIG. 16A, three group driving start signals GDS #1 and GDS It is possible to reduce the number of group drive start signal wires required to supply #2 and GDS #3) in correspondence.

Of course, although more L group control signal wires are added, the larger the value of the number of gate drive groups N increases, the greater the effect of reducing the group drive start signal than the number of group control signal wires added. If the signal wiring structure is used, the total number of signal wirings can be significantly reduced.

Accordingly, in the display panel 110, the width (size) of the outer area of the active area AA in which an image is displayed can be reduced, thereby obtaining an effect of reducing a bezel.

Referring to FIG. 18A, L corresponding to the number of group control signals or the number of group control signal wires ^{may be a minimum value among natural numbers satisfying "2 L} ≥N (number of gate driving groups)".

For example, as shown in FIG. 18A, when the number of gate driving groups N is 3, L becomes 2. When the number of gate driving groups N is 4, L becomes 2. When the number of gate driving groups N is 8, L becomes 3. When the number of gate driving groups N is 9, L becomes 4. When the number of gate driving groups N is 32, L becomes 5.

As such, L, which corresponds to the number of group control signals or the number of group control signal wires, is a value smaller than the number of gate driving groups N. Also, as the number of gate driving groups N increases, the difference between N and L increases.

Therefore, when the signal wiring structure of Fig. 18A is used, compared to the case of using the signal wiring structure of Fig. 16A, L group control signal wirings are added, but the group driving start signal wirings are N to 1+L N-1. Since the number is reduced by -L, the benefit of reducing the total number of signal wires is large. The larger the number of gate driving groups N is, the greater the benefit of reducing the total number of signal lines.

As described above, the total number of signal wires can be reduced by using the group control signal and group control signal wires having a smaller number (L) than the number of gate driving groups N.

In the following, since N corresponding to the number of partial regions or the number of gate driving groups is 3, it is assumed that L is 2 as an example. That is, in order to supply three group drive start signals (GDS #1, GDS #2, GDS #3) to three gate drive groups (GDG #1, GDG #2, GDG #3), three logic circuits ( It is assumed that LC #1, LC #2, LC #3) and two group control signals C1 and C2 are used, and two group control signal wires CL #1 and CL #2 are arranged.

18A and 19A, each of the two logic circuits LC #1 and LC #2 receives one group driving start reference signal GDS_REF and two group control signals C1 and C2, Among the three gate driving groups (GDG #1, GDG #2, and GDG #3), a group driving start signal corresponding to the corresponding gate driving group is output.

18A and 19A, LC #1 receives GDS_REF, C1, and C2, and outputs GDS #1 to GDG #1. LC #2 receives GDS_REF, C1 and C2, and outputs GDS #2 to GDG #2. LC #3 receives GDS_REF, C1 and C2, and outputs GDS #3 to GDG #3.

According to the above, three gate driving groups (GDG #1, GDG #2, GDG #3) using the same group driving start reference signal (GDS_REF) and two group control signals (C1, C2). Three group drive start signals (GDS #1, GDS #2, and GDS #3) can be generated to be supplied to the device.

Referring to FIG. 18A, each of the three logic circuits LC #1, LC #2, and LC #3 has one AND gate (AG) and 0 to L NOT gates (NG: NOT Gate). ).

Referring to FIG. 18A, LC #1 includes one AND gate AG #1 and two NOT gates (NG_C1, NG C2) connected to two driving control signal input terminals (C1 input terminal, C2 input terminal) of AG #1. do. LC #2 includes one AND gate AG #2 and one NOT gate (NG C2) connected to the C2 input of the two driving control signal inputs (C1 input and C2 input) of AG #2. LC #3 includes one AND gate AG #3 and one NOT gate (NG C1) connected to the C1 input of the two driving control signal inputs (C1 input and C2 input) of AG #3.

The location and number of the input terminals of the AND gate to which the NOT gate is connected can be better understood with reference to FIG. 18C.

18C is an exemplary diagram showing the configuration of a logic circuit when the number of gate driving groups N is 8 and the number of group control signals (number of group control signal wires) L is 3. FIG.

18C, for example, when C1, C2, and C3 are 1, 1, and 1, C1', C2', and C3' finally input to the AND gate are displayed.

Referring to FIG. 18C, C1' will be 0 when C1(=1) passes through the NOT gate, and C1' will be 1 when C1(=1) does not pass through the NOT gate. If C2(=1) passes through the NOT gate, C2' will be 0, and if C2(=1) does not pass through the NOT gate, C2' will be 1. If C3(=1) passes through the NOT gate, C3' will be 0, and if C3(=1) does not pass through the NOT gate, C3' will be 1.

Referring to FIG. 18C, in the above-described manner, a group control signal (C1'/C2'/C3') finally input to each of the eight AND gates (AG #1, ..., AG #8) is, 000 , 001, 010, 011, 100, 101, 110, 111. When these are expressed as decimal numbers, they are 0, 1, 2, 3, 4, 5, 6, 7, and 8 gate driving groups or 8 group driving start signals can be distinguished.

18A and 19A, AND gates (AG #1, AG #2, AG #3) included in each of three logic circuits (LC #1, LC #2, and LC #3) are one group. A driving start reference signal GDS_REF is input, two group control signals C1 and C2 are input through 0 to L NOT gates, and a group driving start signal corresponding to a corresponding gate driving group is output.

In other words, each of the three AND gates (AG #1, AG #2, AG #3) receives one group drive start reference signal (GDS_REF) and directly inputs two group control signals (C1, C2). Or receive two group control signals through two NOT gates (NG_C1, NG_C2), or some of the two group control signals (C1 or C2) are input through NOT gates (NG_C1 or NG_C2) and the rest (C2 or C2) is immediately input and outputs a group driving start signal corresponding to the corresponding gate driving group.

For example, referring to FIGS. 18A and 19A, AG #1 receives GDS_REF, C1 receives C1' through NG_C1, C2 receives C2' through NG_C2, and outputs GDS #1. . AG #2 receives GDS_REF, C1 is directly input as C1', C2 receives C2' through NG_C2, and outputs GDS #2. AG #3 receives GDS_REF, C1 receives C1' through NG_C1, C2 is directly input as C2', and GDS #3 is output.

GDS #1, GDS #2, and GDS #3 output in this manner are the same as GDS #1, GDS #2, and GDS #3 in FIG. 17A.

Through the above-described logic circuit configuration, the same three signals, that is, one group drive start reference signal GDS_REF supplied through one group drive start signal line (GDSL), and two group control signals C1 , C2), it is possible to generate three other group drive start signals (GDS #1, GDS #2, GDS #3) to be supplied to three gate drive groups (GDG #1, GDG #2, GDG #3). I can.

Meanwhile, referring to FIG. 18A, each of the three logic circuits LC #1, LC #2, and LC #3 is a corresponding gate among three gate driving groups (GDG #1, GDG #2, and GDG #3). It may be included in one of the M gate driving integrated circuits included in the driving group.

Referring to FIG. 18A, LC #1 may be included in GIP #1-1 included in GDG #1. LC #2 may be included in GIP #2-1 included in GDG #2. LC #3 may be included in GIP #3-1 included in GDG #3.

As described above, since the logic circuit configuration does not need to be disposed on the display panel 110, the width of the inactive area of the display panel 110 can be reduced.

18B is another exemplary diagram of a signal wiring structure for divided driving under the arrangement structure of both sides of the gate driving integrated circuits of FIG. 13B. 19B is a timing diagram of a group driving start signal and a group driving refresh signal GDR for divided driving under the signal wiring structure of FIG. 18B.

18B and 19B, each of the three gate driving groups GDG #1, GDG #2, and GDG #3 is an odd gate driving group including odd gate driving integrated circuits and an even gate driving integrated circuit. And an even gate driving group including

18B and 19B, GDG #1 includes an odd gate driving group GDG #1o including GIP #1-1 and GIP #1-3, and GIP #1-2 and GIP #1-4. The odd gate driving group GDG #1e is included. GDG #2 includes an odd gate driving group GDG #2o including GIP #2-1 and GIP #2-3, and an odd gate driving group GDG #2e including GIP #2-2 and GIP #2-4. Includes. GDG #3 includes an odd gate driving group GDG #3o including GIP #3-1 and GIP #3-3, and an odd gate driving group GDG #3e including GIP #3-2 and GIP #3-4. Includes.

18B and 19B, for each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), a group is divided into an odd gate driving group (GDG #1o, GDG #2o, and GDG #3o). Supply the drive start signal (GDS #1o, GDS #2o, GDS #3o), and use the even gate drive group (GDG #1e, GDG #2e, GDG #3e) to the group drive start signal (GDS #1e, GDS #2e). , GDS #3e), two group drive start signal wires (GDSLo, GDSLe) and two group control signal wires (CL #1, CL #2, ..., CL #L, L are 2) The above natural number, L=2 in Fig. 18B, is arranged, and 2x3 logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, and LC #3e) are arranged.

In addition, referring to FIG. 18B, for each of the three gate driving groups (GDG #1, GDG #2, and GDG #3), the corresponding group is an odd gate driving group (GDG #1o, GDG #2o, GDG #3o). To supply the driving refresh signal (GDRo) and supply the corresponding group driving refresh signal (GDRe) to the even gate driving group (GDG #1e, GDG #2e, GDG #3e), two group driving refresh signals Wires GDRLo and GDRLe or 2N group driving refresh signal wires may be disposed.

In the case of using the signal wiring structure of FIG. 18B, compared to the signal wiring structure of FIG. 16B, three odd gate driving groups (GDG #1o, GDG #2o, GDG #3o) and three even gate driving groups (GDG #1e, GDG #2e, GDG #3e) for a total of 6 group drive start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) to correspond and supply the necessary group drive The number of start signal wires can be reduced from six to two.

Of course, L (e.g., L=2) group control signal wires (CL #1, CL #2) are added, but as the value of the number of gate driving groups N increases, the number of group control signal wires is added. Since the effect of reducing the group driving start signal is greater than that, using the signal wiring structure of Fig. 18B can significantly reduce the total number of signal wirings.

Accordingly, in the display panel 110, the width (size) of the outer area of the active area AA in which an image is displayed can be reduced, thereby obtaining an effect of reducing a bezel.

Referring to FIG. 18B, L corresponding to the number of group control signals or the number of group control signal wires ^{may be a minimum value among natural numbers satisfying "2 L} ≥N (number of gate driving groups)".

For example, as shown in FIG. 18B, when the number of gate driving groups N is 3, L becomes 2. When the number of gate driving groups N is 4, L becomes 2. When the number of gate driving groups N is 8, L becomes 3. When the number of gate driving groups N is 9, L becomes 4. When the number of gate driving groups N is 32, L becomes 5.

As such, L, which corresponds to the number of group control signals or the number of group control signal wires, is a value smaller than the number of gate driving groups N. Also, as the number of gate driving groups N increases, the difference between N and L increases.

Therefore, when the signal wiring structure of Fig. 18B is used, compared to the case of using the signal wiring structure of Fig. 16B, L group control signal wirings are added, but the group drive start signal wirings are 2N to 2+L. Since it is reduced by -L, the benefit of reducing the total number of signal wires is large. The larger the number of gate driving groups N is, the greater the benefit of reducing the total number of signal lines.

As described above, the total number of signal wires can be reduced by using the group control signal and group control signal wires having a smaller number (L) than the number of gate driving groups N.

In the following, since N corresponding to the number of partial regions or the number of gate driving groups is 3, it is assumed that L is 2 as an example. That is, 3 odd gate driving groups (GDG #1o, GDG #2o, GDG #3o) and 3 even gate driving groups (GDG #1, GDG #2, GDG #3) included in the 3 gate driving groups (GDG #1, GDG #2, GDG #3) In order to supply 6 group drive start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) with GDG #1e, GDG #2e, GDG #3e), 6 Two logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, LC #3e) and two group control signals (C1, C2) are used, and two group control signal wires ( It is assumed that CL #1 and CL #2) are arranged.

18B and 19B, each of 2×N (for example, N=3) logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, and LC #3e), Receives two group drive start reference signals (GDSo_REF, GDSe_REF) and two group control signals (C1, C2), and the corresponding gate drive group among three gate drive groups (GDG #1, GDG #2, GDG #3) A group driving start signal corresponding to the odd gate driving group or the even gate driving group included in is output.

For example, LC #1o receives GDSo_REF, C1, C2, and outputs GDS #1o to GDG #1o of GDG #1. LC #1e receives GDSe_REF, C1, C2, and outputs GDS #1e to GDG #1e of GDG #1. LC #2o receives GDSo_REF, C1, C2, and outputs GDS #2o to GDG #2o of GDG #2. LC #2e receives GDSe_REF, C1, C2, and outputs GDS #2e to GDG #2e of GDG #2. LC #3o receives GDSo_REF, C1, C2, and outputs GDS #3o to GDG #3o of GDG #3. LC #3e receives GDSe_REF, C1, C2, and outputs GDS #3e to GDG #3e of GDG #3.

According to the above, the two group driving start reference signals GDSo_REF and GDSe_REF and the two group control signals C1 and C2 are used in the same manner, and the three gate driving groups GDG #1, GDG #2, and GDG # Start driving 6 groups to supply to 3 odd gate driving groups (GDG #1o, GDG #2o, GDG #3o) and 3 even gate driving groups (GDG #1e, GDG #2e, GDG #3e) belonging to 3) It can generate signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e).

Meanwhile, referring to FIG. 18B, each of 2×3 logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, and LC #3e) has one AND gate (AG) and , May include 0 to L NOT gates NG.

18B, 6 AND gates (AG #1o, AG #1o, AG) included in 2x3 logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, LC #3e) #1e, AG #2o, AG #2e, AG #3o, AG #3e) each receives two group drive start reference signals (GDS_REF), and receives two groups through 0 to L NOT gates (NG). The group control signals C1 and C2 are received, and a group driving start signal corresponding to an odd gate driving group or an even gate driving group included in the corresponding gate driving group is output.

For example, referring to FIGS. 18B and 19B, AG #1o receives GDSo_REF, C1 receives C1' through NG_C1, C2 receives C2' through NG_C2, and GDS #1o is GDG Print with #1o. AG #1e receives GDSe_REF, C1 receives C1' through NG_C1, C2 receives C2' through NG_C2, and outputs GDS #1e to GDG #1e. AG #2o receives GDSo_REF, C1 is directly input as C1', C2 receives C2' through NG_C2, and outputs GDS #2o to GDG #2o. AG #2e receives GDSe_REF, C1 is directly input as C1', C2 receives C2' through NG_C2, and outputs GDS #2e to GDG #2e. AG #3o receives GDSo_REF, C1 receives C1' through NG_C1, receives C2 directly as C2', and outputs GDS #3o to GDG #3o. AG #3oe receives GDSe_REF, C1 receives C1' through NG_C1, receives C2 directly as C2', and outputs GDS #3e to GDG #3e.

GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, and GDS #3e output in this way are GDS #1o, GDS #1e, GDS #2o, and GDS #2e in FIG. 17B. , GDS #3o, same as GDS #3e.

Through the above-described logic circuit configuration, even if the same four signals, that is, two group driving start reference signals GDSo_REF and GDSe_REF and two group control signals C1 and C2 are used, three gate driving groups ( It can generate 6 different group drive start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) to be supplied to GDG #1, GDG #2, GDG #3). I can.

Meanwhile, referring to FIG. 18B, each of 2×3 logic circuits (LC #1o, LC #1e, LC #2o, LC #2e, LC #3o, and LC #3e) has three gate driving groups (GDG # 1, GDG #2, GDG #3) may be included in one of the odd gate driving group included in the corresponding gate driving group or M/2 gate driving integrated circuits included in the even gate driving group.

Here, M is the number of gate driving integrated circuits included in one gate driving group. Accordingly, the number of gate driving integrated circuits included in one odd gate driving group or one even gate driving group is M/2.

As described above, since the logic circuit configuration does not need to be disposed on the display panel 110, the width of the inactive area of the display panel 110 can be reduced.

In FIG. 19A, the above timing diagram shows one group driving start reference signal GDS_REF, two group control signals C1' and C2' finally input to each AND gate, and one group driving refresh signal GDR. ), and the timing diagram below is output from three logic circuits (LC #1, LC #2, LC #3) to three gate drive groups (GDG #1, GDG #2, GDG #3) It is a timing diagram of three group drive start signals (GDS #1, GDS #2, GDS #3) and one group drive refresh signal (GDR).

The timing diagram below in FIG. 19A is the same as that in FIG. 17A.

Referring to FIG. 19A, three AND gates (AG #1, AG #2, AG #3) included in three logic circuits (LC #1, LC #2, and LC #3) start driving one group. Using the reference signal (GDS_REF) and the two group control signals (C1', C2') that are finally input to each AND gate, three group drive start signals (GDS #1, GDS #2, GDS #3) are created. It outputs to three gate driving groups (GDG #1, GDG #2, GDG #3).

Referring to the timing diagram below in FIG. 19A, the rising of a group driving start signal (eg GDS #2) output from the i-th logic circuit (eg, LC #2) to the i-th gate driving group (eg, GDG #2) The timing corresponds to the polling timing of the group driving refresh signal GDR corresponding to the i-1 th gate driving group (eg, GDG #1).

Unlike the timing chart below in FIG. 19A, the polling timing of the group driving start signal (eg GDS #2) output from the i-th logic circuit (eg, LC #2) to the i-th gate driving group (eg, GDG #2) is , It may correspond to the rising timing of the group driving refresh signal GDR corresponding to the i-1 th gate driving group (eg, GDG #1).

According to the above, three gate driving groups (GDG #1, GDG #2, GDG #3) using the same group driving start reference signal (GDS_REF) and two group control signals (C1, C2). Three group drive start signals (GDS #1, GDS #2, and GDS #3) can be generated to be supplied to the device. In addition, as shown in the timing diagram below in FIG. 19A, by adjusting the timing so that there is a pause time, divided driving for each partial region can be provided more efficiently while minimizing the driving load.

In Fig. 19B, the above timing diagram shows two group driving start reference signals (GDSo_REF, GDSe_REF), two group control signals (C1', C2') finally inputted to each AND gate, and two group driving refresh signals. (GDRo, GDRe) is a timing diagram, and the timing diagram below is three gates each including an odd gate driving group and an even gate driving group in three logic circuits (LC #1, LC #2, LC #3). 6 group drive start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) output to the drive group (GDG #1, GDG #2, GDG #3) and It is a timing diagram of two group driving refresh signals (GDRo, GDRe).

The lower timing diagram of FIG. 19B is the same as that of FIG. 17B.

Referring to FIG. 19B, the rising timing of the group driving start signal GDSo #2 corresponding to the odd gate driving group (eg, GDGo #2) included in the i-th gate driving group (eg, GDG #2) is i -It may correspond to the polling timing of the group driving refresh signal GDRe corresponding to the even gate driving group (eg, GDGe #1) included in the first gate driving group (eg, GDG #1).

Unlike FIG. 19B, the polling timing of the group driving start signal (GDSo #2) corresponding to the odd gate driving group (eg, GDGo #2) included in the i-th gate driving group (eg, GDG #2) is i -It may correspond to the rising timing of the group driving refresh signal GDRe corresponding to the even gate driving group (eg, GDGe #1) included in the first gate driving group (eg, GDG #1).

According to the above, the two group driving start reference signals GDSo_REF and GDGe_REF and the two group control signals C1 and C2 are used in the same manner, and the three gate driving groups GDG #1, GDG #2, and GDG # Start driving 6 groups to supply to 3 odd gate driving groups (GDG #1o, GDG #2o, GDG #3o) and 3 even gate driving groups (GDG #1e, GDG #2e, GDG #3e) belonging to 3) It can generate signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e). In addition, as shown in the timing diagram below in FIG. 19B, by adjusting the timing so that there is a pause time, the divided driving for each partial region can be provided more efficiently while minimizing the driving load.

Hereinafter, a partial driving method will be described using the divided driving method described with reference to FIGS. 18A to 19B.

20 is a block diagram of a timing controller 140 for driving a partial gate of the display device 100 according to the present exemplary embodiments.

Referring to FIG. 20, the timing controller 140 includes a control unit 2010, a first frame buffer 2020, a second frame buffer 2030, and the like.

The first frame buffer 2020 stores image data of a current frame input from the system interface 150.

When the image data RGB of the new current frame is input to the first frame buffer 2020, the second frame buffer 2030 receives and stores the image data of the previous frame stored in the first frame buffer 2020. .

The control unit 2010 compares the image data of the previous frame stored in the second frame buffer 2030 with the image data of the current frame stored in the first frame buffer 2020, and integrates gate driving to be actually operated among all gate driving groups. A gate driving group including circuits is selected, and according to the result, control signals (GDS, GDR) for partial gate driving are selected from among the gate driving integrated circuits included in the selected gate driving group. It is controlled to be supplied to the gate driving integrated circuit.

The control unit 2010 corresponds to each start point of time allocated to each of the gate driving groups selected for partial gate driving, so that the corresponding group driving start signal is supplied to the corresponding gate driving integrated circuit. Outputs (GDS_REF) or two group drive start reference signals (GDSo_REF, GDSe_REF), outputs two group control signals (C1, C2), and outputs one group drive refresh signal (GDR) or two group drive reset signals. Flash signals (GDRo, GDRe) are output.

In this case, the frame driving time is the same for every frame regardless of the number of selected gate driving groups, and the driving time and frame driving time allocated to each of the selected gate driving groups are allocated to each of the unselected gate driving groups. The rest time is the same.

Alternatively, the control unit 2010 of the timing controller 140 allocates the frame driving time only to each of the selected gate driving groups, and corresponds to each start point of the time allocated to each of the selected gate driving groups, and the corresponding group driving start signal It is also possible to control the timing so that is supplied.

21 is a diagram illustrating a change in image data for each partial region between a previous frame and a current frame in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 21, compared to the previous frame, the current frame is only in PA #2 and PA #3 among three sub-areas (PA #1, PA #2, PA #3) in which the active area AA is divided. It can be seen that an image change has occurred.

The timing controller 140 recognizes that there is an image change in PA #2 and PA #3 and there is no image change in PA #1 through image data comparison, and the partial regions with image change (PA #2, PA # A gate driving group (GDG #2, GDG #3) including gate driving integrated circuits capable of outputting a scan signal to the gate line formed in 3) is selected.

Here, for partial gate driving, selecting the gate driving group (GDG #2, GDG #3) to be actually operated (driving) from all the gate driving groups (GDG #1, GDG #2, GDG #3) It is the same as selecting gate driving integrated circuits that actually output a scan signal from among the gate driving integrated circuits (GIP #1, ..., GIP #12).

Thereafter, the timing controller 140 selects one or two group driving start reference signals and a group driving refresh signal to drive the first gate driving integrated circuit and the last gate included in each of the selected gate driving groups for partial gate driving. Output to an integrated circuit. However, it is assumed that the logic circuit is included in the corresponding gate driving integrated circuit.

22A and 22B are diagrams illustrating a state of outputting a scan signal for driving a partial gate under the image data change state of FIG. 21 in the display device 100 according to the present exemplary embodiments.

22A and 22B, the timing controller 140 includes a gate driving group (GDG #2, GDG #3) selected from all gate driving groups (GDG #1, GDG #2, and GDG #3). Scan signals are sequentially output only to the gate driving integrated circuits, and the scan signals are not output from the gate driving integrated circuits included in the remaining gate driving group GDG #1.

Accordingly, in the active area AA consisting of three partial areas (PA #1, PA #2, PA #3), two partial areas (PA #2, PA #3) identified as partial areas with image change. ) Only.

23A shows three group drive start signals GDS #1 and GDS #2 using one group drive start reference signal GDS_REF and two group control signals C1 and C2, as shown in FIG. 19A. , GDS #3) is a diagram showing a group driving start signal, a group driving refresh signal (GDR), and a scan signal for partial gate driving.

Referring to FIG. 23A, a gate driving group (GDG #2, GDG #3) selected for partial driving among all gate driving groups (GDG #1, GDG #2, and GDG #3) is Scan signals are sequentially output only from the included gate driving integrated circuits, and the scan signals are not output from the gate driving integrated circuits included in the remaining gate driving group GDG #1.

Accordingly, in the active zero (AA) consisting of three partial regions (PA #1, PA #2, PA #3), two partial regions (PA #2, PA #3) identified as partial regions with image change. ) Only.

23B shows six group drive start signals GDS #1o and GDS using two group drive start reference signals GDSo_REF and GDSe_REF and two group control signals C1 and C2, as shown in FIG. 19B. #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e), a group drive start signal for partial gate drive, a group drive refresh signal (GDRo, GDRe), and scan signal. It is a figure shown.

Referring to FIG. 23B, a gate driving group (GDG #2, GDG #3) selected for partial driving among all gate driving groups (GDG #1, GDG #2, and GDG #3) is selected by the timing controller 140. Scan signals are sequentially output only from the included gate driving integrated circuits, and the scan signals are not output from the gate driving integrated circuits included in the remaining gate driving group GDG #1.

Accordingly, in the active zero (AA) consisting of three partial regions (PA #1, PA #2, PA #3), two partial regions (PA #2, PA #3) identified as partial regions with image change. ) Only.

24A shows one group driving start reference signal GDS_REF and two group control signals using the method described with reference to FIG. 19A in order to partially drive only two partial regions PA #2 and PA #3. It is a diagram showing three group driving start signals (GDS #1, GDS #2, GDS #3) made using (C1, C2).

Referring to FIG. 24A, only GDS #2 and GDS #2 have a high level section at the corresponding driving timing, and GDS #1 does not have a high level section.

In addition, referring to FIG. 24A, in the GDR, there is no high level section at the driving timing corresponding to GDG #1, and only the driving timing corresponding to GDG #2 and GDG #3 has a high level section.

24B shows two group driving start reference signals GDSo_REF and GDSe_REF and two groups using the method described with reference to FIG. 19B in order to partially drive only two partial areas PA #2 and PA #3. It is a diagram showing six group driving start signals (GDS #1o, GDS #1e, GDS #2o, GDS #2e, GDS #3o, GDS #3e) made using the control signals (C1, C2).

Referring to FIG. 24B, only GDS #2o, GDS #2e, GDS #3o, and GDS #3e have a high level section at their driving timing, and GDS #1o and GDS #1e have no high level section.

In addition, referring to FIG. 24B, in GDRo, there is no high level section at the driving timing corresponding to GDG #1o, and only the driving timing corresponding to GDG #2o and GDG #3o has a high level section. In GDRe, there is no high level section at the driving timing corresponding to GDG #1e, and only the driving timing corresponding to GDG #2e and GDG #3e has a high level section.

According to the exemplary embodiments described above, it is possible to provide an efficient split driving method and the display device 100 providing the same.

According to the present embodiments, it is possible to provide the display device 100 having a signal wiring structure for efficient divisional driving.

According to the present embodiments, it is possible to provide the display device 100 capable of minimizing the number of signal wires for divided driving.

According to the present embodiments, a partial gate driving method and a display device 100 providing the same can be provided.

According to the present embodiments, a gate driving method capable of reducing a driving time or power consumption and a display device 100 providing the same can be provided.

The description above and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the technical field to which the present invention pertains, combinations of configurations within the scope not departing from the essential characteristics of the present invention. Various modifications and variations, such as separation, substitution, and alteration, will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
120: data driver
130: gate driver
140: timing controller

Claims (18)

A display panel on which a plurality of data lines and a plurality of gate lines are disposed;
A data driver driving the plurality of data lines;
A gate driver driving the plurality of gate lines and including a plurality of gate driving integrated circuits; And
A timing controller that controls the data driver and the gate driver,
The plurality of gate driving integrated circuits are divided by M (M is a natural number of 2 or more) and classified into N (N is a natural number of 2 or more) gate driving groups,
The N gate driving groups correspond to the N partial regions in which the display panel is divided and operate independently of each other by a group driving start signal and a group driving refresh signal,
In order to correspond and supply N group driving start signals to the N gate driving groups, one group driving start signal wiring and L group control signal wiring are arranged, and N logic circuits are arranged,
In order to supply a group driving refresh signal corresponding to each of the N gate driving groups, one or N group driving refresh signal lines are arranged, and
Each of the N logic circuits,
It receives 1 group drive start reference signal and L group control signals,
And outputting a group driving start signal corresponding to a corresponding gate driving group among the N gate driving groups. delete The method of claim 1,
L is,
2 A display device, characterized in that it is a natural number main minimum value satisfying ^{L ≥N.} delete The method of claim 1,
Each of the N logic circuits,
A display device comprising: one AND gate and 0 (Zero) to L NOT gates. The method of claim 5,
One AND gate included in each of the N logic circuits,
Receives one group drive start reference signal,
L group control signals are directly input, L group control signals are input through L NOT gates, or some of the L group control signals are input through NOT gates and the rest are directly input.
A display device comprising: outputting a group driving start signal corresponding to a corresponding gate driving group. The method of claim 1,
The rising timing of the group driving start signal corresponding to the i-th gate driving group corresponds to the polling timing of the group driving refresh signal corresponding to the i-1th gate driving group, or
The display device, wherein the polling timing of the group driving start signal corresponding to the i-th gate driving group corresponds to a rising timing of the group driving refresh signal corresponding to the i-1 th gate driving group. A display panel on which a plurality of data lines and a plurality of gate lines are disposed;
A data driver driving the plurality of data lines;
A gate driver driving the plurality of gate lines and including a plurality of gate driving integrated circuits; And
A timing controller that controls the data driver and the gate driver,
The plurality of gate driving integrated circuits are divided by M (M is a natural number of 2 or more) and classified into N (N is a natural number of 2 or more) gate driving groups,
The N gate driving groups correspond to the N partial regions in which the display panel is divided and operate independently of each other by a group driving start signal and a group driving refresh signal,
In order to correspond and supply N group driving start signals to the N gate driving groups, one group driving start signal wiring and L group control signal wiring are arranged, and N logic circuits are arranged,
In order to supply a group driving refresh signal corresponding to each of the N gate driving groups, one or N group driving refresh signal lines are arranged,
Each of the N logic circuits,
And one of M gate driving integrated circuits included in a corresponding gate driving group among the N gate driving groups. A display panel on which a plurality of data lines and a plurality of gate lines are disposed;
A data driver driving the plurality of data lines;
A gate driver driving the plurality of gate lines and including a plurality of gate driving integrated circuits; And
A timing controller that controls the data driver and the gate driver,
The plurality of gate driving integrated circuits are divided by M (M is a natural number of 2 or more) and classified into N (N is a natural number of 2 or more) gate driving groups,
The N gate driving groups correspond to the N partial regions in which the display panel is divided and operate independently of each other by a group driving start signal and a group driving refresh signal,
Each of the N gate driving groups,
An odd gate driving group including odd gate driving integrated circuits and an even gate driving group including even gate driving integrated circuits,
In order to supply a group driving start signal corresponding to an odd gate driving group and an even gate driving group included in each of the N gate driving groups, two group driving start signal wires and L group control signal wires are disposed, and 2N Two logic circuits are placed,
In order to supply a group driving refresh signal corresponding to an odd gate driving group and an even gate driving group included in each of the N gate driving groups, two or 2N group driving refresh signal lines are arranged,
Each of the 2N logic circuits,
It receives two group drive start reference signals and L group control signals,
And outputting a group driving start signal corresponding to an odd gate driving group or an even gate driving group included in a corresponding gate driving group among the N gate driving groups. The method of claim 9,
L is,
2 A display device, characterized in that it is a natural number main minimum value satisfying ^{L ≥N.} delete The method of claim 9,
Each of the 2N logic circuits,
A display device comprising: one AND gate and 0 to L NOT gates. The method of claim 12,
One AND gate included in each of the 2N logic circuits,
Two group drive start reference signals are received,
L group control signals are directly input, L group control signals are input through L NOT gates, or some of the L group control signals are input through NOT gates and the rest are directly input.
A display device comprising: outputting a group driving start signal corresponding to an odd gate driving group or an even gate driving group included in a corresponding gate driving group. The method of claim 9,
The rising timing of the group driving start signal corresponding to the odd gate driving group included in the i-th gate driving group is the polling timing of the group driving refresh signal corresponding to the even gate driving group included in the i-1 th gate driving group. Corresponds to, or
The polling timing of the group driving start signal corresponding to the odd gate driving group included in the i-th gate driving group is the rising timing of the group driving refresh signal corresponding to the even gate driving group included in the i-1 th gate driving group. A display device, characterized in that corresponding. The method of claim 9,
Each of the 2N logic circuits,
And one of M/2 gate driving integrated circuits included in an odd gate driving group or an even gate driving group among the N gate driving groups. delete delete delete

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